128M GDDR SDRAM K4D263238K 128Mbit GDDR SDRAM Revision 1.1 July 2007 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. - 1/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K Revision History Revision Month Year History 1.0 January 2007 - Release revision 1.0 SPEC - Corrected Package Outline 1.1 July 2007 - Revised comment about voltage of power up sequence - Revised ICC2P current to 20mA - 2/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES * 2.5V 5% power supply for device operation * Data I/O transactions on both edges of Data strobe * 2.5V 5% power supply for I/O interface * DLL aligns DQ and DQS transitions with Clock transition * SSTL_2 compatible inputs/outputs * Edge aligned data & data strobe output * 4 banks operation * Center aligned data & data strobe input * MRS cycle with address key programs * DM for write masking only -. Read latency 3 (clock) * Auto & Self refresh -. Burst length (2, 4, 8 and Full page) * 32ms refresh period (4K cycle) -. Burst type (sequential & interleave) * 144pin FBGA package * Full page burst length for sequential burst type only * Maximum clock frequency up to 250MHz * Start address of the full page burst should be even * Maximum data rate up to 500Mbps/pin * All inputs except data & DM are sampled at the positive going edge of the system clock * Differential clock input * Write Interrupted by Read function ORDERING INFORMATION Part NO. Max Freq. Max Data Rate K4D263238K-VC40 250MHz 500Mbps/pin K4D263238K-VC50 200MHz 400Mbps/pin Interface Package SSTL_2 144FBGA K4D263238K-GC is the Leaded package part number. GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank DDR SDRAM The K4D263238K is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 2.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. - 3/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K PIN CONFIGURATION (Top View) 2 3 4 5 6 7 8 9 10 11 12 13 B DQS0 DM0 VSSQ DQ3 DQ2 DQ0 DQ31 DQ29 DQ28 VSSQ DM3 DQS3 C DQ4 VDDQ NC VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ NC VDDQ DQ27 D DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25 E DQ7 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ24 F DQ17 DQ16 VDDQ VSSQ VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSSQ VDDQ DQ15 DQ14 G DQ19 DQ18 VDDQ VSSQ VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSSQ VDDQ DQ13 DQ12 H DQS2 DM2 NC VSSQ VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSSQ NC DM1 DQS1 J DQ21 DQ20 VDDQ VSSQ VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSSQ VDDQ DQ11 DQ10 K DQ22 DQ23 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ8 L CAS WE VDD VSS A10 VDD VDD RFU1 VSS VDD NC NC M RAS NC NC BA1 A2 A11 A9 A5 RFU2 CK CK NC N CS NC BA0 A0 A1 A3 A4 A6 A7 A8/AP CKE VREF NOTE: 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. VSS Thermal balls are optional PIN DESCRIPTION CK,CK Differential Clock Input BA0, BA1 Bank Select Address CKE Clock Enable A0 ~A11 Address Input CS Chip Select DQ0 ~ DQ31 Data Input/Output RAS Row Address Strobe VDD Power CAS Column Address Strobe VSS Ground WE Write Enable VDDQ Power for DQ's DQS Data Strobe VSSQ Ground for DQ's DM Data Mask NC No Connection RFU Reserved for Future Use - 4/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function Input The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQs and DMs that are sampled on both edges of the DQS. CKE Input Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS Input CS enables the command decoder when low and disabled the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. CAS Input Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. WE Input Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQS Input/Output Data input and output are synchronized with both edge of DQS. DM0 ~ DM3 Input Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. DQ0 ~ DQ31 Input/Output Data inputs/Outputs are multiplexed on the same pins. Input Selects which bank is to be active. A0 ~ A11 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7. Column address CA8 is used for auto precharge. VDD/VSS Power Supply Power and ground for the input buffers and core logic. VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Power Supply Reference voltage for inputs, used for SSTL interface. CK, CK*1 BA0, BA1 *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin. - 5/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank) 32 Intput Buffer I/O Control CK, CK Data Input Register Serial to parallel Bank Select LWE LDMi 64 1Mx32 32 Output Buffer 2-bit prefetch Sense AMP 1Mx32 64 x32 DQi 1Mx32 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length Programming Register LRAS LCBR DLL Strobe Gen. LCKE Row Decoder Refresh Counter Row Buffer ADDR Address Register CK,CK 1Mx32 Data Strobe LWE LCAS LWCBR CK,CK LDMi Timing Register CK,CK CKE CS RAS CAS WE - 6/19 - DMi Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K FUNCTIONAL DESCRIPTION * Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before or with VDDQ . - Apply VDDQ before or with VREF & VTT - The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min and the power voltage ramps are without any slope reversal. 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high. 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. Power up & Initialization Sequence 0 1 2 3 4 tRP 5 6 2 Clock min. EMRS 8 2 Clock min. Command precharge ALL Banks 7 MRS DLL Reset 9 10 11 12 1st Auto Refresh 200 Clock min. Inputs must be stable for 200us 14 tRFC tRP precharge ALL Banks 13 15 16 17 18 tRFC 2nd Auto Refresh 19 2 Clock min. Mode Register Set Any Command CK CK * When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL. - 7/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 RFU 0 A11 A10 A9 RFU A8 A7 DLL TM A6 A5 A4 A3 CAS Latency A2 BT A1 A0 Address Bus Mode Register Burst Length Burst Type Test Mode DLL A8 DLL Reset A3 Type A7 mode 0 Sequential 1 Interleave 0 No 0 Normal 1 Yes 1 Test Burst Length CAS Latency BA0 An ~ A 0 A6 A5 A4 Latency Burst Type A2 A1 A0 Sequential Interleave 0 0 Reserve Reserve 0 MRS 0 0 0 Reserved 0 1 EMRS 0 0 1 Reserved 0 0 1 2 2 0 1 0 Reserved 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserve Reserve 1 0 1 Reserved 1 0 1 Reserve Reserve 1 1 0 Reserved 1 1 0 Reserve Reserve 1 1 1 Reserved 1 1 1 Full page Reserve * RFU(Reserved for future use) should stay "0" during MRS cycle. MRS Cycle 0 1 2 3 4 5 6 7 8 CK, CK Command NOP Precharge All Banks NOP NOP MRS NOP Any Command NOP NOP tMRD=2 tCK tRP *1: MRS can be issued only at all banks precharge state. *2: Minimum tRP is required to issue MRS command. - 8/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extend mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA0 RFU 1 BA0 A11 A10 A9 A8 A7 RFU A6 A5 D.I.C An ~ A0 A6 A1 0 MRS 0 0 Full 1 EMRS 0 1 1 1 * RFU(Reserved for future use) should stay "0" during EMRS cycle. A4 A3 A2 RFU A1 A0 D.I.C DLL Address Bus Extended Mode Register A0 DLL Enable 100% 0 Enable Weak 60% 1 Disable 0 N/A Do not use 1 Matched 30% Output Driver Impedance Control Figure 7. Extend Mode Register set - 9/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDD supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 C Power dissipation PD 1.8 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65C) Parameter Symbol Min Typ Max Unit Note Device Supply voltage VDD 2.375 2.50 2.625 V 1 Output Supply voltage VDDQ 2.375 2.50 2.625 V 1 Reference voltage VREF 0.49*VDDQ - 0.51*VDDQ V 2 Termination voltage Vtt VREF-0.04 VREF VREF+0.04 V 3 Input logic high voltage VIH VREF+0.15 - VDDQ+0.30 V 4 Input logic low voltage VIL -0.30 - VREF-0.15 V 5 Output logic high voltage VOH Vtt+0.76 - - V IOH=-15.2mA Output logic low voltage VOL - - Vtt-0.76 V IOL=+15.2mA Input leakage current IIL -5 - 5 uA 6 Output leakage current IOL -5 - 5 uA 6 Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. VIL(min.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V VIN VDD is acceptable. For all other pins that are not under test VIN=0V. - 10/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, TA=0 to 65C) Parameter Symbol Version Test Condition -40 -50 Unit Note 1 Operating Current (One Bank Active) ICC1 Burst Lenth=2 tRC tRC(min) IOL=0mA, tCC= tCC(min) 189 170 mA Precharge Standby Current in Power-down mode ICC2P CKE VIL(max), tCC= tCC(min) 20 20 mA Precharge Standby Current in Non Power-down mode ICC2N 48 43 mA Active Standby Current power-down mode ICC3P 78 67 mA Active Standby Current in in Non Power-down mode ICC3N 153 134 mA CKE VIH(min), CS VIH(min), tCC= tCC(min). CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min), tCC= tCC(min) . Operating Current ( Burst Mode) ICC4 IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated. 402 344 mA Refresh Current ICC5 tRC tRFC(min) 159 135 mA Self Refresh Current ICC6 CKE 0.2V 10 2 mA Note: 1. Measured with outputs open. 2. Refresh period is 32ms. AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to VSS=0V, VDD/ VDDQ=2.5V+ 5%, TA=0 to 65C) Parameter Symbol Min Typ Max Unit Note Input High (Logic 1) Voltage; DQ VIH VREF+0.35 - - V Input Low (Logic 0) Voltage; DQ VIL - - VREF-0.35 V Clock Input Differential Voltage; CK and CK VID 0.7 - VDDQ+0.6 V 1 Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2 - 0.5*VDDQ+0.2 V 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same - 11/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K AC OPERATING TEST CONDITIONS (VDD/ VDDQ=2.5V+ 5% , TA= 0 to 65C) Parameter Value Unit Input reference voltage for CK(for single ended) 0.50*VDDQ V CK and CK signal maximum peak swing 1.5 V CK signal minimum slew rate 1.0 V/ns VREF+0.35/VREF-0.35 V VREF V Vtt V Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Note See Fig.1 Vtt=0.5*VDDQ RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ (Fig. 1) Output Load Circuit CAPACITANCE (VDD=2.5V, TA= 25C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance( CK, CK ) CIN1 1.0 5.0 pF Input capacitance(A0~A11, BA0~BA1) CIN2 1.0 4.0 pF Input capacitance ( CKE, CS, RAS,CAS, WE ) CIN3 1.0 4.0 pF Data & DQS input/output capacitance(DQ0~DQ31) COUT 1.0 6.0 pF Input capacitance(DM0 ~ DM3) CIN4 1.0 6.0 pF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Symbol Value Unit Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01 uF Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF Note : 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip. - 12/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K AC CHARACTERISTICS Parameter -40 Symbol CK cycle time CL=3 CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble DQS-In high level width DQS-In low level width Address and Control input setup Address and Control input hold DQ and DM setup time to DQS DQ and DM hold time to DQS tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH Clock half period tHP Data output hold time from DQS tQH -50 Min 4.0 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLmin or tCHmin tHP-0.4 Max 10 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 - Min 5.0 0.45 0.45 -0.7 -0.7 0.9 0.4 0.8 0 0.25 0.4 0.4 0.4 1.0 1.0 0.45 0.45 tCLmin or tCHmin tHP-0.45 - Unit Max 10 0.55 0.55 +0.7 +0.7 +0.45 1.1 0.6 1.2 0.6 0.6 0.6 - Note ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns - ns - ns Simplified Timing @ BL=2, CL=3 tCH 0 1 tCL tCK 2 3 4 6 5 7 8 CK, CK tIS CS tIH tDQSCK tDQSS DQS tRPST tRPRE tWPRES tDQSQ tAC DQ Da1 tDQSH tWPST tWPREH tDS tDH Db0 Da2 Hi-Z Db1 Hi-Z DM WRITEB COMMAND READA - 13/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output valid window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax tQH Timing (CL3, BL2) tHP 0 1 2 3 4 5 CK, CK CS DQS tDQSQ(max) tQH tDQSQ(max) Da0 DQ COMMAND Da1 READA - 14/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K AC CHARACTERISTICS (I) Parameter Symbol -40 -50 Min Max Min Max Unit Note Row cycle time tRC 48 - 50 - ns 2,5 Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge Last data in to Row precharge @Auto Precharge Auto precharge write recovery + Precharge Last data in to Read command Col. address to Col. address Mode register set cycle time Exit self refresh to read command Power down exit time Refresh interval time tRFC tRAS tRCDRD tRCDWR tRP tRRD tWR 56 32 16 8 16 10 15 100K - 100K - - 55 35 15 10 15 10 15 - ns ns ns ns ns ns ns 5 5 5 4 5 5 5 tWR_A 3 - 3 - tCK 3 tDAL 7 - 6 - tCK 3,5 2 1 2 200 3tCK+tIS - 7.8 2 1 2 200 3tCK+tIS - 7.8 tCK tCK tCK tCK ns us 1 tCDLR tCCD tMRD tXSR tPDEX tREF Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM 2. The number of clock of tRP is restricted by the number of clock of tRAS and tRP 3. The number of clock of tWR_A is fixed. It can't be changed by tCK 4. tRCDWR is equal to tRCDRD-2tCK and the number of clock can not be lower than 2tCK. 5. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer unconditionally. AC CHARACTERISTICS (II) K4D263238K-VC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 tRC 12 10 9 tRFC 14 11 9 tRAS 8 7 6 tRCDRD tRCDWR 4 2 3 2 3 2 tRP 4 3 3 tRRD 3 2 2 tDAL 7 6 6 Unit K4D263238K-VC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 tRC 10 9 tRFC 11 9 tRAS 7 6 tRCDRD tRCDWR 3 2 3 2 tRP 3 3 tRRD 2 2 tDAL 6 6 Unit tCK tCK tCK tCK tCK * 200/166MHz are supported in K4D263238K-VC40 * 166MHz is supported in K4D263238K-VC50 - 15/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K Simplified Timing(2) @ BL=4, CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CK, CK BA[1:0] BAa A8/AP Ra ADDR (A0~A7, A9~,A11) Ra BAa BAa Ca BAa BAb Ra Rb Ra Rb BAa BAb Ca Cb WE DQS Da0 Da1 Da2 Da3 DQ Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 DM COMMANDACTIVEA WRITEA PRECH ACTIVEA ACTIVEB WRITEA WRITEB tRCD tRAS tRP tRC Normal Write Burst (@ BL=4) tRRD Multi Bank Interleaving Write Burst (@ BL=4) - 16/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K PACKAGE DIMENSIONS (144-Ball FBGA) A1 INDEX MARK 12.0 12.0 <Top View> 0.8x11=8.8 0.10 Max 0.8 0.8 0.40 13 12 11 10 9 8 7 6 5 4 3 2 0.35 0.05 1.40 Max 0.8x11=8.8 0.45 0.05 B C D E F G H J K L M N A1 INDEX MARK 0.40 <Bottom View> Unit : mm - 17/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K IBIS :I/V Characteristics for Input and Output Buffers Voltage(V) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Pulldown Current(mA) Minimum Maximum 0 0 4.2 5.24 9.92 11.36 15.28 17.24 20.56 23.12 25.6 28.76 30.36 34.24 34.88 39.48 38.96 44.64 42.64 49.48 45.76 53.92 48.4 57.92 50.48 61.56 52.04 64.72 53.24 67.28 54.16 69.44 54.8 71.2 55.32 72.52 55.76 73.48 56.16 74.28 56.48 74.92 56.8 75.4 57.08 75.84 57.36 76.24 57.64 76.56 57.84 76.8 58.08 77.12 58.28 77.36 Pullup Current(mA) Minimum Maximum 0 0 1.84 2.44 -2.88 -2.88 -7.44 -8.16 -11.84 -13.16 -16 -18.24 -20.04 -23.08 -23.92 -27.84 -27.52 -32.4 -30.8 -36.84 -33.88 -41.04 -36.6 -45.04 -39 -48.84 -41.08 -52.48 -42.84 -55.76 -44.24 -58.84 -45.44 -61.56 -46.44 -64.04 -47.28 -66.16 -47.96 -68.04 -48.68 -69.64 -49.28 -71.04 -49.84 -72.24 -50.36 -73.36 -50.48 -74.24 -50.52 -75.08 -50.55 -75.84 -50.58 -76.56 Full Strength Driver Characteristics - 18/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K Voltage(V) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Pulldown Current(mA) Minimum Maximum 0 0 3.48 4.32 7.96 9.2 12.24 14 16.44 18.76 20.36 23.2 24.08 27.6 27.36 31.8 30.48 35.68 33.12 39.36 35.32 42.6 37.08 45.6 38.4 48.08 39.44 50.2 40.16 51.92 40.72 53.28 41.12 54.32 41.52 55.08 41.84 55.68 42.08 56.2 42.32 56.56 42.56 56.92 42.76 57.24 42.96 57.44 43.16 57.72 43.32 57.92 43.52 58.12 43.68 58.32 Pullup Current(mA) Minimum Maximum 0 0 0.96 -2.68 -2.92 -7.4 -6.56 -11.96 -10.12 -16.4 -13.64 -20.68 -16.8 -24.84 -19.88 -28.88 -22.72 -32.8 -25.32 -36.48 -27.64 -40.08 -29.72 -43.44 -31.52 -46.44 -33.04 -49.36 -34.28 -51.96 -35.36 -54.4 -36.2 -56.48 -36.92 -58.36 -37.6 -60 -38.12 -61.48 -38.6 -62.72 -39.08 -63.8 -39.48 -64.8 -39.92 -65.64 -40.12 -66.4 -40.15 -67.12 -40.18 -67.72 -40.2 -68.32 Weak Strength Driver Characteristics - 19/19 - Rev. 1.1 July 2007 128M GDDR SDRAM K4D263238K Voltage(V) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Pulldown Current(mA) Minimum Maximum 0 0 3.08 0.84 6.76 4.84 10.28 8.56 13.72 12.32 16.84 15.92 19.84 19.36 22.48 22.64 24.88 25.72 26.8 28.56 28.44 31.16 29.6 33.44 30.52 35.36 31.24 36.96 31.8 38.16 32.12 39.12 32.44 39.84 32.68 40.4 32.92 40.84 33.16 41.2 33.28 41.44 33.48 41.72 33.64 41.88 33.8 42.08 33.92 42.24 34.12 42.44 34.24 42.56 34.36 42.68 Pullup Current(mA) Minimum Maximum 0 0 0.24 -2.36 -2.76 -5.88 -5.68 -9.36 -8.44 -12.8 -11.08 -16.16 -13.56 -19.24 -15.8 -22.32 -17.96 -25.16 -19.88 -27.92 -21.56 -30.52 -23.04 -32.92 -24.36 -35.12 -25.36 -37.12 -26.24 -38.88 -26.96 -40.52 -27.56 -41.96 -28.04 -43.12 -28.56 -44.24 -28.92 -45.12 -29.28 -45.96 -29.6 -46.6 -29.96 -47.28 -30.24 -47.84 -30.34 -48.36 -30.38 -48.84 -30.41 -49.28 -30.42 -49.68 Matched Strength Driver Characteristics - 20/19 - Rev. 1.1 July 2007