LTC2633 Dual 12-/10-/8-Bit I2C VOUT DACs with 10ppm/C Reference Description Features n n n n n n n n n n Integrated Precision Reference 2.5V Full-Scale 10ppm/C (LTC2633-L) 4.096V Full-Scale 10ppm/C (LTC2633-H) Maximum INL Error: 1LSB (LTC2633A-12) Low Noise: 0.75mVP-P 0.1Hz to 200kHz Guaranteed Monotonic Over -40C to 125C Temperature Range Selectable Internal or External Reference 2.7V to 5.5V Supply Range (LTC2633-L) Low Power: 0.4mA at 3V Power-on-Reset to Zero-Scale/Mid-Scale/Hi-Z Double-Buffered Data Latches 8-Lead ThinSOTTM Package The LTC(R)2633 is a family of dual 12-, 10-, and 8-bit voltage-output DACs with an integrated, high accuracy, low drift reference in an 8-lead TSOT-23 package. It has rail-to-rail output buffers and is guaranteed monotonic. The LTC2633-L has a full-scale output of 2.5V, and operates from a single 2.7V to 5.5V supply. The LTC2633-H has a full-scale output of 4.096V, and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the full-scale output to the external reference voltage. These DACs communicate via a 2-wire I2C-compatible serial interface. The LTC2633 operates in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz). The LTC2633 incorporates a power-on reset circuit. Options are available for reset to zero-scale, reset to mid-scale in internal reference mode, reset to mid-scale in external reference mode, or reset with all DAC outputs in a high impedance state after power-up. Applications n n n n n Mobile Communications Process Control and Industrial Automation Power Supply Margining Portable Equipment Automotive L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433, 6937178, 7414561. Block Diagram INTERNAL REFERENCE GND SWITCH REF Integral Nonlinearity (LTC2633A-LZ12) INL Curve VREF 2 POWER-ON RESET DAC B CONTROL DECODE LOGIC VCC = 3V INTERNAL REF. 1 VOUTB INL (LSB) REGISTER REGISTER DAC A REGISTER VOUTA REGISTER VCC 0 -1 SCL CA0 I2C ADDRESS DECODE -2 I2C INTERFACE SDA 0 1024 2048 CODE 3072 4095 2633 TA01 2633 BD 2633fb 1 LTC2633 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) Supply Voltage (VCC).................................... -0.3V to 6V SCL, SDA...................................................... -0.3V to 6V VOUTA , VOUTB....................-0.3V to Min(VCC + 0.3V, 6V) CA0....................................-0.3V to Min(VCC + 0.3V, 6V) REF....................................-0.3V to Min(VCC + 0.3V, 6V) Operating Temperature Range LTC2633C................................................. 0C to 70C LTC2633H (Note 3)............................. -40C to 125C Maximum Junction Temperature........................... 150C Storage Temperature Range.................... -65C to 150C Lead Temperature (Soldering, 10 sec)................... 300C TOP VIEW SCL CA0 REF GND 1 2 3 4 8 7 6 5 SDA VCC VOUTB VOUTA TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 150C (NOTE 6), JA = 195C/W Order Information LTC2633 A C TS8 -L Z 12 #TRM PBF LEAD FREE DESIGNATOR TAPE AND REEL TR = 2,500-Piece Tape and Reel TRM = 500-Piece Tape and Reel RESOLUTION 12 = 12-Bit 10 = 10-Bit 8 = 8-Bit POWER-ON RESET I = Reset to Mid-Scale in Internal Reference Mode X = Reset to Mid-Scale in External Reference Mode (2.5V Full-Scale Voltage, Internal Reference Mode Option Only) O = Reset to Mid-Scale in Internal Reference Mode, DACs High Z (2.5V Full-Scale Voltage, Internal Reference Mode Option Only) Z = Reset to Zero-Scale in Internal Reference Mode FULL-SCALE VOLTAGE INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE TS8 = 8-Lead Plastic TSOT-23 TEMPERATURE GRADE C = Commercial Temperature Range (0C to 70C) H = Automotive Temperature Range (-40C to 125C) ELECTRICAL GRADE (OPTIONAL) A = 1LSB Maximum INL (12-Bit) PRODUCT PART NUMBER Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2633fb 2 LTC2633 Product Selection Guide PART MARKING** VFS WITH INTERNAL REFERENCE POWER-ON RESET TO CODE POWER-ON REFERENCE MODE RESOLUTION VCC LTC2633A-LI12 LTC2633A-LX12 LTC2633A-LZ12 LTC2633A-LO12* LTC2633A-HI12 LTC2633A-HZ12 LTFTC LTFTB LTFSZ LTFTV LTFTF LTFTD 2.5V * (4095/4096) 2.5V * (4095/4096) 2.5V * (4095/4096) 2.5V * (4095/4096) 4.096V * (4095/4096) 4.096V * (4095/4096) Mid-Scale Mid-Scale Zero-Scale High Impedance Mid-Scale Zero-Scale Internal External Internal Internal Internal Internal 12-Bit 12-Bit 12-Bit 12-Bit 12-Bit 12-Bit 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 1LSB 1LSB 1LSB 1LSB 1LSB 1LSB LTC2633-LI12 LTC2633-LI10 LTC2633-LI8 LTFTC LTFTJ LTFTQ 2.5V * (4095/4096) 2.5V * (1023/1024) 2.5V * (255/256) Mid-Scale Mid-Scale Mid-Scale Internal Internal Internal 12-Bit 10-Bit 8-Bit 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.5LSB 1LSB 0.5LSB LTC2633-LX12 LTC2633-LX10 LTC2633-LX8 LTFTB LTFTH LTFTP 2.5V * (4095/4096) 2.5V * (1023/1024) 2.5V * (255/256) Mid-Scale Mid-Scale Mid-Scale External External External 12-Bit 10-Bit 8-Bit 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.5LSB 1LSB 0.5LSB LTC2633-LZ12 LTC2633-LZ10 LTC2633-LZ8 LTFSZ LTFTG LTFTN 2.5V * (4095/4096) 2.5V * (1023/1024) 2.5V * (255/256) Zero-Scale Zero-Scale Zero-Scale Internal Internal Internal 12-Bit 10-Bit 8-Bit 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.5LSB 1LSB 0.5LSB LTC2633-LO12* LTC2633-LO10* LTC2633-LO8* LTFTV LTFTW LTFTX 2.5V * (4095/4096) 2.5V * (1023/1024) 2.5V * (255/256) High Impedance High Impedance High Impedance Internal Internal Internal 12-Bit 10-Bit 8-Bit 2.7V to 5.5V 2.7V to 5.5V 2.7V to 5.5V 2.5LSB 1LSB 0.5LSB LTC2633-HI12 LTC2633-HI10 LTC2633-HI8 LTFTF LTFTM LTFTS 4.096V * (4095/4096) 4.096V * (1023/1024) 4.096V * (255/256) Mid-Scale Mid-Scale Mid-Scale Internal Internal Internal 12-Bit 10-Bit 8-Bit 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 2.5LSB 1LSB 0.5LSB LTC2633-HZ12 LTC2633-HZ10 LTC2633-HZ8 LTFTD LTFTK LTFTR 4.096V * (4095/4096) 4.096V * (1023/1024) 4.096V * (255/256) Zero-Scale Zero-Scale Zero-Scale Internal Internal Internal 12-Bit 10-Bit 8-Bit 4.5V to 5.5V 4.5V to 5.5V 4.5V to 5.5V 2.5LSB 1LSB 0.5LSB PART NUMBER MAXIMUM INL * Contact Linear Technology for other Hi-Z options. **The temperature grade is identified by a label on the shipping container. Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2633-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8/-LO12/-LO10/-LO8/LTC2633A-LI12/-LX12/-LZ12/-LO12 (VFS = 2.5V) LTC2633-8 SYMBOL PARAMETER CONDITIONS LTC2633-10 LTC2633-12 LTC2633A-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS DC Performance l 8 10 12 12 Bits Monotonicity VCC = 3V, Internal Ref. (Note 4) l 8 10 12 12 Bits DNL Differential Nonlinearity VCC = 3V, Internal Ref. (Note 4) l 0.5 INL Integral Nonlinearity VCC = 3V, Internal Ref. (Note 4) l 0.05 0.5 ZSE Zero Scale Error VCC = 3V, Internal Ref., Code = 0 l 0.5 VOS Offset Error VCC = 3V, Internal Ref. (Note 5) 0.5 VOSTC VOS Temperature Coefficient VCC = 3V, Internal Ref. GE Gain Error VCC = 3V, Internal Ref. Resolution l l 0.5 1 1 LSB 0.2 1 1 2.5 0.5 1 LSB 5 0.5 5 0.5 5 0.5 5 mV 5 0.5 5 0.5 5 0.5 5 mV 10 10 10 10 V/C 0.2 0.8 0.2 0.8 0.2 0.8 0.2 0.8 %FSR 2633fb 3 LTC2633 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2633-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8/-LO12/-LO10/-LO8/LTC2633A-LI12/-LX12/-LZ12/-LO12 (VFS = 2.5V) LTC2633-8 SYMBOL PARAMETER GETC ROUT CONDITIONS VCC = 3V, Internal Ref. (Note 10) C-Grade H-Grade Load Regulation Internal Ref., Mid-Scale, VCC = 3V 10%, -5mA IOUT 5mA VCC = 5V 10%, -10mA IOUT 10mA Internal Ref., Mid-Scale, VCC = 3V 10%, -5mA IOUT 5mA VCC = 5V 10%, -10mA IOUT 10mA SYMBOL PARAMETER LTC2633-12 LTC2633A-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Gain Temperature Coefficient DC Output Impedance LTC2633-10 10 10 10 10 10 10 10 10 UNITS ppm/C ppm/C l 0.009 0.016 0.035 0.064 0.14 0.256 0.14 0.256 LSB/mA l 0.009 0.016 0.035 0.064 0.14 0.256 0.14 0.256 LSB/mA l 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 l 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 CONDITIONS MIN TYP MAX UNITS VOUT DAC Output Span External Reference Internal Reference PSR Power Supply Rejection VCC = 3V 10% or 5V 10% ISC Short Circuit Output Current (Note 6) Sinking Sourcing VFS = VCC = 5.5V Zero Scale; VOUT shorted to VCC Full Scale; VOUT shorted to GND l l 27 -28 48 -48 mA mA DAC Output Current in High Impedance Mode LO Options Only l 0.01 0.5 A 5.5 V DAC ISD 0 to VREF 0 to 2.5 V V -80 dB Power Supply VCC Positive Supply Voltage For Specified Performance l 2.7 ICC Supply Current (Note 7) VCC = 3V, VREF = 2.5V, External Reference VCC = 3V, Internal Reference VCC = 5V VREF = 2.5V, External Reference VCC = 5V, Internal Reference l l l l 0.3 0.4 0.3 0.4 0.5 0.6 0.5 0.6 mA mA mA mA ISD Supply Current in Power-Down Mode (Note 7) VCC = 5V l 0.5 2 A VCC V 160 200 k Reference Input Input Voltage Range l 1 Resistance l 120 Capacitance IREF Reference Current, Power Down Mode 12 DAC Powered Down l pF 0.005 5 1.25 1.26 A Reference Output Output Voltage l 1.24 V Reference Temperature Coefficient 10 ppm/C Output Impedance 0.5 k Capacitive Load Driving 10 F 2.5 mA Short Circuit Current VCC = 5.5V, REF Shorted to GND 2633fb 4 LTC2633 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2633-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8/-LO12/-LO10/-LO8/LTC2633A-LI12/-LX12/-LZ12/-LO12 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital I/O VIL Low Level Input Voltage (SDA and SCL) (Note 14) l -0.5 0.3VCC V VIH High Level Input Voltage (SDA and SCL) (Note 11) l 0.7VCC VIL(CA0) Low Level Input Voltage on CA0 See Test Circuit 1 l VIH(CA0) High Level Input Voltage on CA0 See Test Circuit 1 l RINH Resistance from CA0 to VCC to Set CA0 = VCC See Test Circuit 2 l 10 k RINL Resistance from CA0 to GND to Set CA0 = GND See Test Circuit 2 l 10 k RINF Resistance from CA0 to VCC or GND to Set CA0 = Float See Test Circuit 2 l 2 VOL Low Level Output Voltage Sink Current = 3mA l 0 0.4 V tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 12) l 20 + 0.1CB 250 ns tSP Pulse Width of Spikes Suppressed by Input Filter l 0 50 ns IIN Input Leakage 0.1VCC VIN 0.9VCC l 1 A CIN I/O Pin Capacitance (Note 8) l 8 pF CB Capacitive Load for Each Bus Line l 400 pF CCA0 External Capacitive Load on Address Pin CA0 l 10 pF V 0.15VCC 0.85VCC V V M AC Performance ts en Settling Time VCC = 3V (Note 9) 0.39% (1LSB at 8 Bits) 0.098% (1LSB at 10 Bits) 0.024% (1LSB at 12 Bits) 3.4 4.0 4.5 s s s Voltage Output Slew Rate 1.0 V/s Capacitive Load Driving 500 pF Glitch Impulse At Mid-Scale Transition 2.8 nV*s DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switch 0-FS 5.2 nV*s Multiplying Bandwidth External Reference 320 kHz Output Voltage Noise Density At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 180 160 200 180 nV/Hz nV/Hz nV/Hz nV/Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1F 30 35 680 730 VP-P VP-P VP-P VP-P 2633fb 5 LTC2633 Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 13) LTC2633-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8/-LO12/-LO10/-LO8/LTC2633A-LI12/-LX12/-LZ12/-LO12 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 400 kHz fSCL SCL Clock Frequency l 0 tHD(STA) Hold Time (Repeated) Start Condition l 0.6 s tLOW Low Period of the SCL Clock Pin l 1.3 s tHIGH High Period of the SCL Clock Pin l 0.6 s tSU(STA) Set-Up Time for a Repeated Start Condition l 0.6 s tHD(DAT) Data Hold Time l 0 tSU(DAT) Data Set-Up Time l 100 tr Rise Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1CB 300 ns tf Fall Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1CB 300 ns tSU(STO) Set-Up Time for Stop Condition l 0.6 s tBUF Bus Free Time Between a Stop and Start Condition l 1.3 s 0.9 s ns Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2633-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8/LTC2633A-HI12/-HZ12 (VFS = 4.096V) LTC2633-8 SYMBOL PARAMETER CONDITIONS LTC2633-10 LTC2633-12 LTC2633A-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS DC Performance Resolution l 8 8 10 12 Monotonicity VCC = 5V, Internal Ref. (Note 4) l Differential Nonlinearity VCC = 5V, Internal Ref. (Note 4) l 0.5 INL Integral Nonlinearity VCC = 5V, Internal Ref. (Note 4) l 0.05 0.5 0.2 1 1 2.5 ZSE Zero Scale Error VCC = 5V, Internal Ref., Code = 0 l 0.5 5 0.5 5 0.5 5 VOS Offset Error VCC = 5V, Internal Ref. (Note 5) l 0.5 5 0.5 5 0.5 5 VOSTC VOS Temperature Coefficient VCC = 5V, Internal Ref. GE Gain Error VCC = 5V, Internal Ref. GETC Gain Temperature Coefficient VCC = 5V, Internal Ref. (Note 10) C-Grade H-Grade Load Regulation l VCC = 5V 10%, Internal Ref. Mid-Scale, -10mA IOUT 10mA 0.006 0.01 0.022 0.04 0.09 0.16 0.09 0.16 LSB/mA DC Output Impedance l VCC = 5V 10%, Internal Ref. Mid-Scale, -10mA IOUT 10mA 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 ROUT 12 Bits DNL l 10 12 12 0.5 Bits 1 1 LSB 0.5 1 LSB 0.5 5 mV 0.5 5 mV 10 10 10 10 V/C 0.2 0.8 0.2 0.8 0.2 0.8 0.2 0.8 %FSR 10 10 10 10 10 10 10 10 ppm/C ppm/C 2633fb 6 LTC2633 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2633-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8/LTC2633A-HI12/-HZ12 (VFS = 4.096V) SYMBOL PARAMETER CONDITIONS MIN VOUT DAC Output Span External Reference Internal Reference PSR Power Supply Rejection VCC = 5V 10% ISC Short Circuit Output Current (Note 6) Sinking Sourcing VFS = VCC = 5.5V Zero Scale; VOUT shorted to VCC Full Scale; VOUT shorted to GND l l TYP MAX UNITS 0 to VREF 0 to 4.096 V V -80 dB 27 -28 48 -48 mA mA 5.5 V Power Supply VCC Positive Supply Voltage For Specified Performance l 4.5 ICC Supply Current (Note 7) VCC = 5V, VREF =4.096V, External Reference VCC = 5V, Internal Reference l l 0.4 0.5 0.6 0.7 mA mA ISD Supply Current in Power-Down Mode (Note 7) VCC = 5V l 0.5 2 A VCC V 200 k Reference Input Input Voltage Range l 1 Resistance l 120 Capacitance IREF Reference Current, Power Down Mode 160 12 DAC Powered Down l pF 0.005 5 A 2.048 2.064 V Reference Output Output Voltage l 2.032 Reference Temperature Coefficient 10 ppm/C Output Impedance 0.5 k Capacitive Load Driving 10 F 4 mA Short Circuit Current VCC = 5.5V, REF Shorted to GND VIL Low Level Input Voltage (SDA and SCL) (Note 14) l -0.5 VIH High Level Input Voltage (SDA and SCL) (Note 11) l 0.7VCC VIL(CA0) Low Level Input Voltage on CA0 See Test Circuit 1 l VIH(CA0) High Level Input Voltage on CA0 See Test Circuit 1 l RINH Resistance from CA0 to VCC to Set CA0 = VCC See Test Circuit 2 l 10 k RINL Resistance from CA0 to GND to Set CA0 = GND See Test Circuit 2 l 10 k RINF Resistance from CA0 to VCC or GND to Set CA0 = Float See Test Circuit 2 l 2 VOL Low Level Output Voltage Sink Current = 3mA l 0 0.4 V tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 12) l 20 + 0.1CB 250 ns tSP Pulse Width of Spikes Suppressed by Input Filter l 0 50 ns IIN Input Leakage 1 A Digital I/O 0.1VCC VIN 0.9VCC l 0.3VCC V V 0.15VCC 0.85VCC V V M 2633fb 7 LTC2633 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2633-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8/LTC2633A-HI12/-HZ12 (VFS = 4.096V) SYMBOL PARAMETER CONDITIONS (Note 8) MIN TYP MAX UNITS CIN I/O Pin Capacitance l 8 pF CB Capacitive Load for Each Bus Line l 400 pF CCA0 External Capacitive Load on Address Pin CA0 l 10 pF AC Performance ts en Settling Time VCC = 5V (Note 9) 0.39% (1LSB at 8 Bits) 0.098% (1LSB at 10 Bits) 0.024% (1LSB at 12 Bits) 3.7 4.0 4.7 s s s Voltage Output Slew Rate 1.0 V/s Capacitive Load Driving 500 pF Glitch Impulse At Mid-Scale Transition 3.0 nV*s DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switch 0-FS 6.7 nV*s Multiplying Bandwidth External Reference 320 kHz Output Voltage Noise Density At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 180 160 250 230 nV/Hz nV/Hz nV/Hz nV/Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1F 30 40 680 750 VP-P VP-P VP-P VP-P 2633fb 8 LTC2633 Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 13) LTC2633-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8/LTC2633A-HI12/-HZ12 (VFS = 4.096V) SYMBOL PARAMETER CONDITIONS MIN MAX UNITS 400 kHz fSCL SCL Clock Frequency tHD(STA) Hold Time (Repeated) Start Condition l 0.6 s tLOW Low Period of the SCL Clock Pin l 1.3 s tHIGH High Period of the SCL Clock Pin l 0.6 s tSU(STA) Set-Up Time for a Repeated Start Condition l 0.6 s tHD(DAT) Data Hold Time l 0 tSU(DAT) Data Set-Up Time l 100 tr Rise Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1CB 300 ns tf Fall Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1CB 300 ns tSU(STO) Set-Up Time for Stop Condition l 0.6 s tBUF Bus Free Time Between a Stop and Start Condition l 1.3 s Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltages are with respect to GND Note 3. High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105C. Note 4. Linearity and monotonicity are defined from code kL to code 2N-1, where N is the resolution and kL is given by kL = 0.016 * (2N/ VFS), rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity is defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = 16 and linearity is defined from code 16 to code 4,095. Note 5. Inferred from measurement at code 16 (LTC2633-12), code 4 (LTC2633-10) or code 1 (LTC2633-8), and at full scale. Note 6. This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can 0 TYP l 0.9 s ns exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 7. Digital inputs at 0V or VCC. Note 8. Guaranteed by design and not production tested. Note 9. Internal reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2k in parallel with 100pF to GND. Note 10. Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 11. Maximum VIH = VCC(MAX) + 0.5V Note 12. CB = capacitance of one bus line in pF Note 13. All values refer to VIH = VIH(MIN) and VIL = VIL(MAX) levels. Note 14. Minimum VIL exceeds the absolute maximum rating. This condition won't damage the IC, but could degrade performance. 2633fb 9 LTC2633 Typical Performance Characteristics TA = 25C unless otherwise noted. LTC2633-L12 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL) 1.0 VCC = 3V 1.0 VCC = 3V -0.5 INL (LSB) 0 0 1024 3072 2048 CODE 4095 -1.0 0 1024 3072 2048 CODE 2633 G01 4095 -1.0 -50 -25 INL (NEG) 0 25 50 75 100 125 150 TEMPERATURE (C) 2633 G03 Reference Output Voltage vs Temperature 1.260 VCC = 3V 0.5 VCC = 3V 1.255 DNL (POS) VREF (V) DNL (LSB) 0 2633 G02 DNL vs Temperature 1.0 INL (POS) -0.5 -0.5 0 VCC = 3V 0.5 0.5 DNL (LSB) INL (LSB) 0.5 -1.0 INL vs Temperature Differential Nonlinearity (DNL) 1.0 0 DNL (NEG) -0.5 1.250 1.245 -1.0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 1.240 -50 -25 0 2633 G04 2633 G05 Settling to 1LSB Rising Settling to 1LSB Falling 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV 3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS VOUT 1LSB/DIV 3.6s VOUT 1LSB/DIV 25 50 75 100 125 150 TEMPERATURE (C) 4.5s 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2s/DIV SCL 5V/DIV 9TH CLOCK OF 3RD DATA BYTE 2s/DIV 2633 G06 2633 G07 2633fb 10 LTC2633 Typical Performance Characteristics TA = 25C unless otherwise noted. LTC2633-H12 (Internal Reference, VFS = 4.096V) Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 5V -0.5 0 1024 3072 2048 CODE 4095 -1.0 0 1024 3072 2048 CODE 2633 G08 0 INL (NEG) -1.0 -50 -25 4095 0 25 50 75 100 125 150 TEMPERATURE (C) 2633 G10 2633 G09 Reference Output Voltage vs Temperature DNL vs Temperature 1.0 INL (POS) -0.5 -0.5 2.068 VCC = 5V 0.5 VCC = 5V 2.058 DNL (POS) VREF (V) 0 VCC = 5V 0.5 INL (LSB) DNL (LSB) 0 -1.0 VCC = 5V 0.5 DNL (LSB) INL (LSB) 0.5 INL vs Temperature 1.0 0 DNL (NEG) -0.5 2.048 2.038 -1.0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 2.028 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 2633 G11 2633 G12 Settling to 1LSB Rising Settling to 1LSB Falling SCL 5V/DIV VOUT 1LSB/DIV 4.7s 3.8s VOUT 1LSB/DIV 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 9TH CLOCK OF 3RD DATA BYTE 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2s/DIV SCL 5V/DIV 9TH CLOCK OF 3RD DATA BYTE 2s/DIV 2633 G13 2633 G14 2633fb 11 LTC2633 Typical Performance Characteristics TA = 25C unless otherwise noted. LTC2633-10 Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 3V VFS = 2.5V INTERNAL REF 0.5 DNL (LSB) INL (LSB) 0.5 0 -0.5 -1.0 VCC = 3V VFS = 2.5V INTERNAL REF 0 -0.5 256 0 768 512 CODE -1.0 1023 256 0 512 CODE 768 2633 G15 1023 2633 G16 LTC2633-8 Integral Nonlinearity (INL) 0.50 Differential Nonlinearity (DNL) 0.50 VCC = 3V VFS = 2.5V INTERNAL REF 0.25 DNL (LSB) INL (LSB) 0.25 0 0 -0.25 -0.25 -0.50 VCC = 3V VFS = 2.5V INTERNAL REF 64 0 192 128 CODE -0.50 255 64 0 128 CODE 192 255 2633 G18 2633 G17 LTC2633 Load Regulation 8 6 Current Limiting 0.20 VCC = 5V (LTC2633-H) VCC = 5V (LTC2633-L) VCC = 3V (LTC2633-L) 0.15 2 VOUT (V) VOUT (mV) VCC = 5V (LTC2633-H) VCC = 5V (LTC2633-L) VCC = 3V (LTC2633-L) 2 0.10 4 0 -2 0.05 0 -0.05 -4 -0.10 -6 INTERNAL REFERENCE CODE = MID-SCALE -8 -10 -30 Offset Error vs Temperature 3 OFFSET ERROR (mV) 10 -20 -10 0 10 IOUT (mA) 20 30 2633 G19 0 -1 -2 -0.15 -0.20 -30 1 INTERNAL REFERENCE CODE = MID-SCALE -20 -10 0 10 IOUT (mA) 20 30 2633 G20 -3 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 2633 G21 2633fb 12 LTC2633 Typical Performance Characteristics TA = 25C unless otherwise noted. LTC2633 Large-Signal Response Mid-Scale-Glitch Impulse Power-On Reset Glitch LTC2633-L 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV LTC2633-H12, VCC = 5V 3nV*s TYPICAL VCC 2V/DIV VOUT 0.5V/DIV VOUT 2mV/DIV ZERO-SCALE VOUT 10mV/DIV LTC2633-L12, VCC = 3V 2.8nV*s TYPICAL VFS = VCC = 5V 1/4 SCALE to 3/4 SCALE 2s/DIV 2s/DIV 2633 G24 200s/DIV 2633 G22 2633 G23 Headroom at Rails vs Output Current Exiting Power-Down to Mid-Scale Power-On Reset to Mid-Scale 5.0 5V SOURCING 4.5 9TH CLOCK OF 3RD DATA BYTE 4.0 3V (LTC2633-L) SOURCING LTC2633-H 2.5 2.0 1.5 DAC B IN POWER-DOWN MODE VOUTA 0.5V/DIV 5V SINKING LTC2633-H VCC = 5V INTERNAL REF. 1.0 3V (LTC2633-L) SINKING 0.5 0 0 1 2 4 5 6 IOUT (mA) 3 7 8 9 1.2 200s/DIV 2633 G27 2633 G26 2633 G25 Exiting Power-Down for Hi-Z Option SWEEP SDA, SCL BETWEEN ON AND VCC 1.0 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV VCC = 5V 0.8 0.6 0.4 0.2 VOUT 500mV/DIV VCC = 3V (LTC2633-L) 0 1 LTC2633-L VOUT 0.5V/DIV 5s/DIV 10 Supply Current vs Logic Voltage ICC (mA) VOUT (V) 3.5 3.0 VCC 2V/DIV SCL 5V/DIV 2 3 LOGIC VOLTAGE (V) 4 5 2633 G28 LTC2633-LO, VCC = 3V DAC OUTPUT DRIVEN BY 1V SOURCE THROUGH 15k RESISTOR DAC OUTPUT SET TO MID-SCALE HIGH-IMPEDANCE (POWER-DOWN) MODE 5s/DIV 2633 G29 2633fb 13 LTC2633 Typical Performance Characteristics TA = 25C unless otherwise noted. LTC2633 Noise Voltage vs Frequency 500 0 NOISE VOLTAGE (nV/Hz) -2 -4 -8 -10 -12 VCC = 5V VREF(DC) = 2V VREF(AC) = 0.2VP-P CODE = FULL-SCALE -14 -16 -18 1k 10k 100k FREQUENCY (Hz) VCC = 5V CODE = MID-SCALE INTERNAL REFERENCE 300 LTC2633-H 200 LTC2633-L 100 0.4 0.2 0 -0.2 -0.4 -0.6 1M 0 100 1k 100k 10k FREQUENCY (Hz) -0.8 1M 1 1.5 2633 G32 2633 G31 0.1Hz to 10Hz Voltage Noise 2 2.5 3 3.5 4 4.5 REFERENCE VOLTAGE (V) 5 5.5 2633 G33 Gain Error vs Temperature DAC to DAC Crosstalk (Dynamic) 1.0 VCC = 5V, VFS = 2.5V CODE = MID-SCALE INTERNAL REFERENCE SCL 5V/DIV 9TH CLOCK OF 3RD DATA BYTE 1 DAC SWITCH 0-FS 2V/DIV 10V/DIV VOUT 2mV/DIV 1s/DIV VCC = 5.5V GAIN ERROR OF 2 CHANNELS 0.6 2632 G34 LTC2633-H12, VCC = 5V 6.7nV*s TYP GAIN ERROR (%FSR) dB -6 400 Gain Error vs Reference Input 0.8 GAIN ERROR (%FSR) Multiplying Bandwidth 2 0.5 0 -0.5 -1.0 -50 -25 2s/DIV 2633 G35 0 25 50 75 100 125 150 TEMPERATURE (C) 2633 G36 Pin Functions SCL (Pin 1): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to VCC. (0.1F is recommended) and must be buffered when driving external DC load current. CA0 (Pin 2): Chip Address Bit 0. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (see Table 1). VOUTA, VOUTB (Pins 5,6): DAC Analog Voltage Output. REF (Pin 3): Reference Voltage Input or Output. When external reference mode is selected, REF is an input (1V VREF VCC) where the voltage supplied sets the full-scale DAC output voltage. When internal reference is selected, the 10ppm/C 1.25V (LTC2633-L) or 2.048V (LTC2633-H) internal reference (half full-scale) is available at the pin. This output may be bypassed to GND with up to 10F GND (Pin 4): Ground. VCC (Pin 7): Supply Voltage Input. 2.7V VCC 5.5V (LTC2633-L) or 4.5V VCC 5.5V (LTC2633-H). Bypass to GND with a 0.1F capacitor. SDA (Pin 8): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This pin is high impedance while data is shifted in. Open drain N-channel output during acknowledgement. SDA requires a pull-up resistor or current source to VCC. 2633fb 14 LTC2633 Block Diagram INTERNAL REFERENCE GND REF SWITCH VREF REGISTER REGISTER DAC A REGISTER VOUTA REGISTER VCC VOUTB DAC B CONTROL DECODE LOGIC POWER-ON RESET SCL I2C ADDRESS DECODE CA0 SDA I2C INTERFACE 2633 BD Test Circuit Test circuits for I2C digital I/O (see Electrical Characteristics) Test Circuit 1 Test Circuit 2 VDD 100 CA0 RINH/RINL/RINF VIH(CA0)/VIL(CA0) 2633 TC01 CA0 GND 2633 TC02 Timing Diagram SDA tLOW tf tf tSU(DAT) tr tHD(STA) tSP tBUF tr SCL tHD(STA) tHD(DAT) tSU(STA) S tHIGH S tSU(STO) P S 2633 F01 ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS Figure 1. I2C Timing SLAVE ADDRESS 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE START SDA A6 A5 A4 A3 A2 A1 A0 W SCL 1 2 3 4 5 6 7 8 ACK C3 9 1 C2 C1 C0 A3 A2 A1 A0 ACK 2 3 4 5 6 7 8 9 ACK 1 2 3 4 5 6 7 8 9 1 2 3 4 X X X X ACK 5 6 7 8 9 2633 F02 Figure 2. Typical LTC2633 Write Transaction 2633fb 15 LTC2633 Operation The LTC2633 is a family of dual voltage output DACs in an 8-lead TSOT package. Each DAC can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. Eighteen combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zeroscale, mid-scale in internal reference mode, or mid-scale in external reference mode), DAC power-down output load (high impedance or 200k), and full-scale voltage (2.5V or 4.096V) are available. The LTC2633 is controlled using a 2-wire I2C interface. Power-On Reset The LTC2633-HZ/LTC2633-LZ clear the output to zero-scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2633 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 10mV above zero scale during power-on. In general, the glitch amplitude decreases as the power supply ramp time is increased. See power-on reset glitch in the Typical Performance Characteristics section. The LTC2633-HI/LTC2633-LI/LTC2633-LX provide an alternative reset, setting the output to mid-scale when power is first applied. The LTC2633-LI/ and LTC2633-HI power up in internal reference mode, with the output set to a mid-scale voltage of 1.25V and 2.048V respectively. The LTC2633-LX power-up in external reference mode, with the output set to mid-scale of the external reference. The LTC2633-LO powers up in internal reference mode with all the DAC channels placed in the high impedance state (powered down). Input and DAC registers are set to the mid-scale code, and only the internal reference is powered up, causing supply current to be typically 180A upon power up. Default reference mode selection is described in the Reference Modes section. Power Supply Sequencing The voltage at REF (Pin 3) must be kept within the range -0.3V VREF VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC is in transition. Transfer Function The digital-to-analog transfer function is: VOUT(IDEAL) = k 2N VREF where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is either 2.5V (LTC2633-LI/ LTC2633-LX/LTC2633-LO/LTC2633-LZ) or 4.096V (LTC2633-HI/LTC2633-HZ) when in internal reference mode, and the voltage at REF when in external reference mode. I2C Serial Interface The LTC2633 communicates with a host using the standard 2-wire I2C interface. The Timing Diagram (Figures 1 and 2) show the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifications. For an I2C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF. The LTC2633 is a receive-only (slave) device. The master can write to the LTC2633. The LTC2633 will not acknowledge (NAK) a read request from the master. 2633fb 16 LTC2633 Operation START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. Acknowledge The acknowledge (ACK) signal is used for handshaking between the master and the slave. An ACK generated by the slave lets the master know that the latest byte of information was properly received. The ACK related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the ACK clock pulse. The slave-receiver must pull down the SDA bus line during the ACK clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2633 responds to a write by a master in this manner but does not acknowledge a read operation; in that case, SDA is retained HIGH during the period of the ACK clock pulse. Chip Address In addition to the address selected by the address pin, the part also responds to a global address. This address allows a common write to all LTC2633 parts to be accomplished using one 3-byte write transaction on the I2C bus. The global address, listed at the end of Tables 1, is a 7-bit hardwired address not selectable by CA0. If another address is required, please consult the factory. The maximum capacitive load allowed on the address pin (CA0) is 10pF, as these pins are driven during address detection to determine if they are floating. Write Word Protocol The master initiates communication with the LTC2633 with a START condition and a 7-bit slave address followed by the write bit (W) = 0. The LTC2633 acknowledges by pulling the SDA pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by CA0) or the global address. The master then transmits three bytes of data. The LTC2633 acknowledges each byte of data by pulling the SDA line low at the 9th clock of each data byte transmission. After receiving three complete bytes of data, the LTC2633 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2633 does not acknowledge the extra bytes of data (SDA is high during the 9th clock). The state of pin CA0 determines the slave address of the part. This pin can be set to any one of three states: VCC, GND or float. This results in 3 selectable addresses for the part. The slave address assignments is shown in Table 1. Table 1. Slave Address Map CA0 A6 A5 A4 A3 A2 A1 A0 GND 0 0 1 0 0 0 0 FLOAT 0 0 1 0 0 0 1 VCC 0 0 1 0 0 1 0 GLOBAL ADDR 1 1 1 0 0 1 1 2633fb 17 LTC2633 Operation The format of the three data bytes is shown in Figure 3. The first byte of the input word consists of the 4-bit command, followed by the 4-bit DAC address. The next two bytes contain the 16-bit data word, which consists of the 12-, 10- or 8-bit input code, MSB to LSB, followed by 4, 6 or 8 don't-care bits (LTC2633-12, LTC2633-10 and LTC2633-8 respectively). A typical LTC2633 write transaction is shown in Figure 4. Table 3. Command Codes COMMAND* The command bit assignments (C3-C0) and address (A3A0) assignments are shown in Tables 3 and 4. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register. In an update operation, the data word is copied from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 12-, 10-, or 8-bit input code, and is converted to an analog voltage at the DAC output. Write to and update combines the first two commands. The update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. C3 C2 C1 C0 0 0 0 0 Write to Input Register n 0 0 0 1 Update (Power-Up) DAC Register n 0 0 1 0 Write to Input Register n, Update (Power-Up) All 0 0 1 1 Write to and Update (Power-Up) DAC Register n 0 1 0 0 Power-Down n 0 1 0 1 Power-Down Chip (All DAC's and Reference) 0 1 1 0 Select Internal Reference (Power-Up Reference) 0 1 1 1 Select External Reference (Power-Down Internal Reference) 1 1 1 1 No Operation *Command codes not shown are reserved and should not be used. Table 4. Address Codes ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 DAC A 0 0 0 1 DAC B 1 1 1 1 All DACs * Address codes not shown are reserved and should not be used. WRITE WORD PROTOCOL LTC2633 S W SLAVE ADDRESS A 1ST DATA BYTE A 2ND DATA BYTE A 3RD DATA BYTE A P D5 D4 D1 D0 INPUT WORD INPUT WORD (LTC2633-12) C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 1ST DATA BYTE D8 D7 D6 D3 D2 X X X X X X X X X X 3RD DATA BYTE 2ND DATA BYTE INPUT WORD (LTC2633-10) C3 C2 C1 C0 A3 A2 A1 A0 D9 D8 D7 1ST DATA BYTE D6 D5 D4 D3 D2 D1 D0 X 2ND DATA BYTE X X 3RD DATA BYTE INPUT WORD (LTC2633-8) C3 C2 C1 C0 A3 1ST DATA BYTE A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 2ND DATA BYTE X X X X X 3RD DATA BYTE 2633 F03 Figure 3. Command and Data Input Format 2633fb 18 X = DON'T CARE 2 1 SCL VOUT A5 A6 A5 SDA START A6 3 A4 4 A3 A3 5 A2 A2 6 A1 A1 SLAVE ADDRESS A4 7 A0 8 9 1 ACK C3 C3 2 C2 C2 3 C1 C1 4 C0 C0 5 A3 A3 COMMAND 6 A2 A2 7 A1 A1 8 A0 A0 9 ACK 1 2 3 D11 D10 D9 4 D8 5 D7 MS DATA 6 D6 7 D5 8 D4 9 ACK 1 D3 2 D2 3 D1 Figure 4. Typical LTC2633 Input Waveform--Programming DAC Output for Full Scale A0 WR 4 D0 5 X LS DATA 6 X 7 X 8 X 9 ACK 2633 F04 ZERO-SCALE VOLTAGE FULL-SCALE VOLTAGE STOP LTC2633 Operation 2633fb 19 LTC2633 Operation Reference Modes For applications where an accurate external reference is either not available, or not desirable due to limited space, the LTC2633 has a user-selectable, integrated reference. The integrated reference voltage is internally amplified by 2x to provide the full-scale DAC output voltage range. The LTC2633-LI/LTC2633-LX/LTC2633-LO/LTC2633-LZ provides a full-scale output of 2.5V. The LTC2633-HI/ LTC2633-HZ provides a full-scale output of 4.096V. The internal reference can be useful in applications where the supply voltage is poorly regulated. Internal reference mode can be selected by using command 0110b, and is the power-on default for LTC2633-HZ/LTC2633-LZ, as well as for LTC2633-HI/LTC2633-LI/LTC2633-LO. The 10ppm/C, 1.25V (LTC2633-LI/LTC2633-LX/LTC2633LO/LTC2633-LZ) or 2.048V (LTC2633-HI/LTC2633-HZ) internal reference is available at the REF pin. Adding bypass capacitance to the REF pin will improve noise performance; 0.1F is recommended and up to 10F can be driven without oscillation. This output must be buffered when driving an external DC load current. Alternatively, the DAC can operate in external reference mode using command 0111b. In this mode, an input voltage supplied externally to the REF pin provides the reference (1V VREF VCC) and the supply current is reduced. The external reference voltage supplied sets the full-scale DAC output voltage. External reference mode is the power-on default for LTC2633-LX. The reference mode of LTC2633-HZ/LTC2633-LZ/ LTC2633-HI/LTC2633-LI/LTC2633-LO (internal reference power-on default), can be changed by software command after power up. The same is true for LTC2633-LX (external reference power-on default). Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than two DAC outputs are needed. When in power-down, the buffer amplifiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. The DAC outputs are put into a high impedance state, and the output pins are passively pulled to ground through individual 200k resistors (LTC2633-LI/LTC2633-LX/ LTC2633-LO/LTC2633-LZ/LTC2633-HI/LTC2633-HZ). For the LTC2633-LO options, the output pins are not passively pulled to ground, but are also placed in a high impedance state (open-circuited state) during power-down, typically drawing less than 0.1A. The LTC2633-LO options powerup with all DAC outputs in this high impedance state. They remain that way until given a software update command. For all LTC2633 options, Input- and DAC-register contents are not disturbed during power-down. Any channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The supply current is reduced approximately 30% for each DAC powered down. The integrated reference is automatically powered down when external reference is selected using command 0111b. In addition, all the DAC channels and the integrated reference together can be put into power-down mode using Power Down Chip command 0101b. When the integrated reference is in power-down mode, the REF pin becomes high impedance (typically > 1G). For all power-down commands the 16-bit data word is ignored. Normal operation resumes after executing any command that includes a DAC update, (as shown in Table 1). The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than two DACs are in a powered-down state prior to the update command, the power-up delay time is 10s. However, if both DACs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the DAC amplifiers and reference buffers. In this case, the power up delay time is 12s. The power-up of the integrated reference depends on the command that powered it down. If the reference is powered down using the select external reference command (0111b), then it can only be powered back up using select internal reference command (0110b). However, if the reference was powered down using power down chip command (0101b), then in addition to select 2633fb 20 LTC2633 Operation internal reference command (0110b), any command in software that powers up the DACs will also power up the integrated reference. 50 * 1mA, or 50mV). See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. Voltage Output The amplifier is stable driving capacitive loads of up to 500pF. The LTC2633's integrated rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Load regulation is a measure of the amplifier's ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA. Since the analog output of the DAC cannot go below ground, it may limit for the lowest codes as shown in Figure 5b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 5c. No full-scale limiting can occur if VREF is less than VCC-FSE. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to . The amplifier's DC output impedance is 0.1 when driving a load well away from the rails. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50 typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0V NEGATIVE OFFSET 0 2,048 INPUT CODE 2633 F05 4,095 (a) 0V INPUT CODE (b) Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12 Bits). (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full Scale 2633fb 21 LTC2633 Operation Board Layout The PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. The resistance from the LTC2633 GND pin to the ground plane should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.1). Note that the LTC2633 is no more susceptible to this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Another technique for minimizing errors is to use a separate power ground return trace on another board layer. The trace should run between the point where the power supply is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for analog ground, digital ground, and power ground. When the LTC2633 is sinking large currents, this current flows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. It is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. Package Description TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 0.40 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 - 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 - 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 - 0.90 0.20 BSC 0.01 - 0.10 1.00 MAX DATUM `A' 0.30 - 0.50 REF 0.09 - 0.20 (NOTE 3) 1.95 BSC TS8 TSOT-23 0710 REV A NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 2633fb 22 LTC2633 Revision History REV DATE DESCRIPTION PAGE NUMBER A 3/11 Revised part numbering. 2 to 9, 13, 16, 20, 26 B 3/11 Revised title of Typical Application. 24 2633fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC2633 Typical Application Voltage Margining Application with LTC3850 (1.2V 5%) LTC2633-LO Option Only 0.1F 4.7F 5V 3 REF 0.1F TO I2C BUS 1 8 2.2k 0.1F DAC A DAC B 6 10k ILM 15k FREQ 0.1F 2.2H 0.008k VOUT 1.2V 5% SW1 4 1nF RJK0305DPB TG1 BOOST1 CA0 GND PGOOD INTVCC LTC3850EUF 10k 0.22F SCL VIN CMDSH-3 100k 7 LTC2633CTS8-L012 5 2 VCC VIN 6.5V TO 14V RJK0301DPB BG1 3.32k PGND SDA 1nF 10k 500kHz 100pF 10k SENSE1+ ITH1 MODE/PLLIN TKSS1 RUN1 SENSE1 10nF 1nF - 10k VFB1 SGND 15pF 63.4k 2633 TA02 20k Related Parts PART NUMBER DESCRIPTION COMMENTS LTC2632 Dual 12-/10-/8-Bit, SPI VOUT DACs with Internal Reference 2.7V to 5.5V Supply Range, 10ppm/C Reference, External REF Mode, Rail-to-Rail Output, 8-Pin ThinSOTTM Package LTC2607/LTC2617/ Dual 16-/14-/12-Bit, I2C VOUT DACs with External Reference LTC2627 260A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, 16-Lead SSOP Package LTC2602/LTC2612/ Dual 16-/14-/12-Bit SPI VOUT DACs with External Reference LTC2622 300A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead MSOP Package LTC1662 Dual 10-Bit, SPI VOUT DAC with External Reference 1.5A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead MSOP Package LTC2630/LTC2631 Single 12-/10-/8-Bit, SPI/ I2C VOUT DACs with 10ppm/C Reference 180A per DAC, 2.7V to 5.5V Supply Range, 10ppm/C Reference, Rail-to-Rail Output, in SC70 (LTC2630)/ ThinSOT (LTC2631) LTC2640 Single 12-/10-/8-Bit, SPI VOUT DACs with 10ppm/C Reference 180A per DAC, 2.7V to 5.5V Supply Range, 10ppm/C Reference, External REF Mode, Rail-to-Rail Output, in ThinSOT LTC2634/LTC2635 Quad 12-/10-/8-Bit SPI/I2C VOUT DACs with 2.5LSB INL, 2.7V to 5.5V Supply Range, 10ppm/C Reference, External REF Mode, 10ppm/C Reference 16-Pin 3mm x 3mm QFN and 10-Lead MSOP Packages LTC2636/LTC2637 Octal 12-/10-/8-Bit, SPI/I2C VOUT DACs with 125A per DAC, 2.7V to 5.5V Supply Range, 10ppm/C Reference, External REF Mode, 10ppm/C Reference Rail-to-Rail Output, 14-Lead 4mm x 3mm DFN and 16-Lead MSOP Packages LTC2654/LTC2655 Quad 16-/12 Bit, SPI/I2C VOUT DACs with 10ppm/C Max Reference 4LSB INL Max at 16-Bits and 2mV Offset Error, Rail-to-Rail Output, 20-Lead 4mm x 4mm QFN and 16-Lead Narrow SSOP Packages LTC2656/LTC2657 Octal 16-/12 Bit, SPI/I2C VOUT DACs with 10ppm/C Max Reference 4LSB INL Max at 16-Bits and 2mV Offset Error, Rail-to-Rail Output, 20-Lead 4mm x 5mm QFN and 16-Lead TSSOP Packages 2633fb 24 Linear Technology Corporation LT 0311 REV B * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2011