© Semiconductor Components Industries, LLC, 2011
November, 2011 − Rev. 5
1Publication Order Number:
MMBFJ309LT1/D
MMBFJ309L, MMBFJ310L,
SMMBFJ310L
JFET - VHF/UHF Amplifier
Transistor
N−Channel
Features
•AEC−Q101 Qualified and PPAP Capable
•S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain−Source Voltage VDS 25 Vdc
Gate−Source Voltage VGS 25 Vdc
Gate Current IG10 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR−5 Board,
(Note 1) TA = 25°C
Derate above 25°C
PD225
1.8
mW
mW/°C
Thermal Resistance, Junction−to−Ambient RqJA 556 °C/W
Junction and Storage Temperature TJ, Tstg −55 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−5 = 1.0 x 0.75 x 0.062 in.
http://onsemi.com
SOT−23 (TO−236)
CASE 318
STYLE 10
Device Package Shipping†
ORDERING INFORMATION
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
MMBFJ309LT1G SOT−23
(Pb−Free)
3,000 / Tape &
Reel
1
2
3
MMBFJ310LT1G SOT−23
(Pb−Free)
3,000 / Tape &
Reel
*Date Code orientation and/or overbar may
vary depending upon manufacturing location.
1
6x M G
G
6x = Device Code
x = U for MMBFJ309L
x = T for MMBFJ310L, SMMBFJ310L
M = Date Code*
G= Pb−Free Package
(Note: Microdot may be in either location)
MARKING DIAGRAM
2 SOURCE
3
GATE
1 DRAIN
SMMBFJ310LT1G SOT−23
(Pb−Free)
3,000 / Tape &
Reel
SMMBFJ310LT3G SOT−23
(Pb−Free)
10,000 / Tape &
Reel
MMBFJ309L, MMBFJ310L, SMMBFJ310L
http://onsemi.com
2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Gate−Source Breakdown Voltage
(IG = −1.0 mAdc, VDS = 0)
V(BR)GSS −25 − − Vdc
Gate Reverse Current (VGS = −15 Vdc)
Gate Reverse Current (VGS = −15 Vdc, TA = 125°C)
IGSS −
−
−
−
−1.0
−1.0
nAdc
mAdc
Gate Source Cutoff Voltage MMBFJ309
(VDS = 10 Vdc, ID = 1.0 nAdc) MMBFJ310, SMMBFJ310
VGS(off) −1.0
−2.0
−
−
−4.0
−6.5
Vdc
ON CHARACTERISTICS
Zero−Gate−Voltage Drain Current MMBFJ309
(VDS = 10 Vdc, VGS = 0) MMBFJ310, SMMBFJ310
IDSS 12
24
−
−
30
60
mAdc
Gate−Source Forward Voltage
(IG = 1.0 mAdc, VDS = 0)
VGS(f) − − 1.0 Vdc
SMALL−SIGNAL CHARACTERISTICS
Forward Transfer Admittance
(VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz)
|Yfs| 8.0 −18 mmhos
Output Admittance
(VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz)
|yos|− − 250 mmhos
Input Capacitance
(VGS = −10 Vdc, VDS = 0 Vdc, f = 1.0 MHz)
Ciss − − 5.0 pF
Reverse Transfer Capacitance
(VGS = −10 Vdc, VDS = 0 Vdc, f = 1.0 MHz)
Crss − − 2.5 pF
Equivalent Short−Circuit Input Noise Voltage
(VDS = 10 Vdc, ID = 10 mAdc, f = 100 Hz)
en−10 −nVńHz
Ǹ
MMBFJ309L, MMBFJ310L, SMMBFJ310L
http://onsemi.com
3
70
60
50
40
30
20
, SATURATION DRAIN CURRENT (mA)
-5.0 -4.0 -3.0 -2.0 -1.0 0
ID - VGS, GATE-SOURCE VOLTAGE (VOLTS)
IDSS
10
0
70
60
50
40
30
20
10
, DRAIN CURRENT (mA)ID
IDSS - VGS, GATE-SOURCE CUTOFF VOLTAGE (VOLTS)
Figure 1. Drain Current and Transfer
Characteristics versus Gate−Source Voltage
VDS = 10 V
IDSS
+25°C
TA = -55°C
+25°C
+25°C
-55°C
+150°C
+150°C
ID, DRAIN CURRENT (mA)
100 k
10 k
1.0 k
100
1.0 k
100
10
1.0
0.01 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100
, FORWARD TRANSCONDUCTANCE ( mhos)Yfs μ
, OUTPUT ADMITTANCE ( mhos)Y
os μ
VGS(off) = -2.3 V =
VGS(off) = -5.7 V =
Figure 2. Common−Source Output
Admittance and Forward Transconductance
versus Drain Current
Yfs Yfs
Yos
VGS, GATE SOURCE VOLTAGE (VOLTS)
5.0 4.0 3.0 2.0 1.0 06.07.08.09.010
CAPACITANCE (pF)
10
7.0
4.0
1.0
0
120
96
72
48
24
0
, ON RESISTANCE (OHMS)RDS
RDS
Cgs
Cgd
Figure 3. On Resistance and Junction
Capacitance versus Gate−Source Voltage
MMBFJ309L, MMBFJ310L, SMMBFJ310L
http://onsemi.com
4
|Y11|, |Y21|, |Y22 | (mmhos)
Y12 (mmhos)
30
24
18
12
6.0
01000100 200 300 500 700
f, FREQUENCY (MHz)
3.0
2.4
1.8
1.2
0.6
|S21|, |S11|
0.45
0.39
0.33
0.27
0.21
0.15
0.85
0.79
0.73
0.67
0.61
0.55
|S12|, |S22|
0.060
0.048
0.036
0.024
0.012
1.00
0.98
0.96
0.94
0.92
0.90
1000100 200 300 500 700
f, FREQUENCY (MHz)
Figure 4. Common−Gate Y Parameter
Magnitude versus Frequency
Figure 5. Common−Gate S Parameter
Magnitude versus Frequency
VDS = 10 V
ID = 10 mA
TA = 25°CY11
Y21
Y22
Y12
S22
S21
S11
S12
VDS = 10 V
ID = 10 mA
TA = 25°C
f, FREQUENCY (MHz)
q21, q11
50°
40°
30°
20°
10°
0°
180°
170°
160°
150°
140°
130°
q12, q22
-20°
-40°
-80°
-120°
-160°
-200°
-20°
-60°
-100°
-140°
-180°
87°
86°
85°
84°
83°
82°
1000100 200 300 500 700
Figure 6. Common−Gate Y Parameter
Phase−Angle versus Frequency
f, FREQUENCY (MHz)
q11, q12
120°
100°
80°
60°
40°
20°
-20°
-40°
-60°
-80°
-100°
-120°
q21, q22
0
-40°
-80°
-20°
-60°
-100°
1000100 200 300 500 700
Figure 7. S Parameter Phase−Angle
versus Frequency
q22
q21
q12
q11 VDS = 10 V
ID = 10 mA
TA = 25°C
q11
q21 q22
q21
q11
q12
VDS = 10 V
ID = 10 mA
TA = 25°C
MMBFJ309L, MMBFJ310L, SMMBFJ310L
http://onsemi.com
5
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AP
D
A1
3
12
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
ǒmm
inchesǓ
SCALE 10:1
0.8
0.031
0.9
0.035
0.95
0.037
0.95
0.037
2.0
0.079
VIEW C
L
0.25
L1
q
e
EE
b
A
SEE VIEW C
DIM
A
MIN NOM MAX MIN
MILLIMETERS
0.89 1.00 1.11 0.035
INCHES
A1 0.01 0.06 0.10 0.001
b0.37 0.44 0.50 0.015
c0.09 0.13 0.18 0.003
D2.80 2.90 3.04 0.110
E1.20 1.30 1.40 0.047
e1.78 1.90 2.04 0.070
L0.10 0.20 0.30 0.004
0.040 0.044
0.002 0.004
0.018 0.020
0.005 0.007
0.114 0.120
0.051 0.055
0.075 0.081
0.008 0.012
NOM MAX
L1
H
2.10 2.40 2.64 0.083 0.094 0.104
HE
0.35 0.54 0.69 0.014 0.021 0.029
c
0−−− 10 0 −−− 10
q°°°°
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MMBFJ309LT1/D
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