M41T94MH6TR - STMicroelectronics, Inc.

August 2006 Rev 4 1/40

M41T94

Serial Real Time Clock with 44Bytes NVRAM and Reset

Feature summary

■Counters for tenths/hundredths of seconds,

seconds, minutes, hours, day, date, month,

year, and century

■32KHz crystal oscillator integrating load

capacitance (12.5pF) providing exceptional

oscillator stability and high crystal series

resistance operation

■Serial peripheral interface (2MHz SPI)

■Ultra-low battery supply current of 500nA (max)

■2.7 to 5.5V operating voltage

■2.5 to 5.5V oscillator operating voltage

■Battery low Flag

■Automatic switch-over and dese lect circuitry

■44 bytes of gen eral purpose RAM

■Programmable Alarm and interrupt function

(valid even during battery back-up mode)

■Accurate programmable Watchdog timer (from

62.5ms to 128s)

■Microprocessor power-on reset

■Choice of power-fail deselect voltages

(VCC = 2.7 to 5.5V):

–THS = V

SS; 2.55V ≤ VPFD ≤ 2.70V

–THS = V

CC; 4.20V ≤ VPFD ≤ 4.50V

■Packaging includes a 28-lead SOIC and

SNAPHAT® TOP (to be ordered separately) or

16-lead SOIC

■28-lead SOIC package provides direct

connection for a SNAPHAT TOP which

contains the battery and crystal

SO16 (MQ)

SOH28 (MH)

SNAPHAT (SH)

Battery & Crystal

www.st.com

Contents M41T94

2/40

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Serial data output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 SPI bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 READ and WRITE cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3 Setting Alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.5 Square Wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.6 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.7 Reset inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.8 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.9 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.10 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.11 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.12 tREC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.13 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

M41T94 Contents

3/40

8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

List of figures M41T94

4/40

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. 16-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. 28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. Data and clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 7. Input timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. Output timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

Figure 10. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11. Alarm interrupt reset Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Back-up mode Alarm Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13. RSTIN1 and RSTIN2 timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 15. Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 16. AC Testing input/output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 17. Power down/up mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 18. SO16 – 16-lead plastic small outline package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 19. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package outline . . . . . . . . . . . 35

Figure 20. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline . . . . . . . . . . 36

Figure 21. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 37

M41T94 List of tables

5/40

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4. Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. Alarm Repeat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 6. Square Wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 7. Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 8. tREC definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 9. Default values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 10. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 11. DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 13. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14. Crystal electrical characteristics (externally supplied) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 15. Power Down/Up AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 16. SO16 – 16-lead Plastic small outline package mechanical data . . . . . . . . . . . . . . . . . . . . 34

Table 17. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package mechanical data . . . 35

Table 18. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mechanical data . . 36

Table 19. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data. . . . . . 37

Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 21. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 22. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Summary description M41T94

6/40

1 Summary description

The M41T94 is a Serial Real Time Clock with 44 bytes of NVRAM and a RESET output. A

built-in 32,768Hz oscillator (external crystal controlled) and 8 bytes of the SRAM (see

Table 4 on page 19) are used for the clock/calendar function and are configu red in binary

coded decimal (BCD) format.

An additional 12 b ytes of RAM pro vide status/c ontrol of Alarm, W atc hdog and Squa re Wave

functions. Addresses and data are transferred serially via a serial SPI interface. The b uilt-in

address register is incremented automatically after each WRITE or READ data byte. The

M41T94 has a built-in power sense circuit which detects power failures and automatically

switches to the battery supply when a power failure occur s. The energy needed to sustain

the SRAM and clock ope rations can be supplied b y a small lithium butto n-cell supply when a

power failure occurs. Functions available to the user include a non-volatile, time-of-day

clock/calendar, Alarm interrupts, Watchdog timer and programmable Square Wave output.

Other features include a Power-On reset as well as two additional debounced inputs

(RSTIN1 and RSTIN2) which can also generate an output reset (RST). The eight clock

address locations contain the century, ye ar, month, date, day, hour, minute, second and

tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year -

valid until year 2100), 30 and 31 day months are made automatically. The ninth clock

address location controls user access to the clock information and also stores the clock

software calibration setting.

The M41T94 is supplied in eith er a 16-lead plastic SOIC (req uiring user supplied crystal and

battery) or a 28-lead SOIC SNAPHAT® package (which integrates both cryst al an d ba tt ery

in a single SNAPHAT top). The 28-pin, 330mil SOIC provides sockets with gold plated

contacts at both ends for direct connection to a separate SNAPHAT housing containing the

battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be

mounted on top of the SOIC package after the completio n of the surface mount process.

Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal

damage due to the high te mper atur es require d for de vice surface-mounting. The SNAPHAT

housing is also keyed to prevent reverse insertion.

The SOIC and battery/crystal pack ages are shipped separ ately in p lastic anti-static tu bes or

in Tape & Reel form. For the 28-lead SOIC, the battery /crystal package (e.g., SNAPHAT)

part number is “M4TXX-BR12SH” (see Table 21 on page 38).

Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the

lithium button-cell battery.

M41T94 Summary description

7/40

Figure 1. Logic diagram

1. For SO16 package only.

Figure 2. 16-pin SOIC connections

AI03683

SCL

VCC

M41T94

VSS

RSTIN1

IRQ/FT/OUT

SQW

WDI

THS

RST

SDO

VBAT (1)

XI (1)

XO (1)

SDI

RSTIN2

AI03684

RSTIN1

WDI IRQ/FT/OUT

SDO

VBAT

SDI

SQW

SCL

THS

RSTIN2

VSS

RST

XI VCC

M41T94

Summary description M41T94

8/40

Figure 3. 28-pin SOIC connections

Table 1. Signal names

EChip Enable

IRQ/FT/OUT Interrupt/frequency te st/out

output (open drain)

RST Reset output (open drain)

RSTIN1 Reset 1 input

RSTIN2 Reset 2 input

SCL Serial Clock input

SDI Serial data input

SDO Serial data output

SQW Square W ave output

THS Threshold select pin

WDI Watchdog input

XI (1)

1. For SO16 package only.

Oscillator input

XO (1) Oscillator output

VBAT (1) Battery supply voltage

VCC Supply voltage

VSS Ground

AI03685

RSTIN1

WDI

IRQ/FT/OUT

THS

SCL

SDINC

VSS SDO

RST

SQW VCC

M41T94

RSTIN2

M41T94 Summary description

9/40

Figure 4. Block diagram

1. Open drain output

Figure 5. Hardware hookup

1. CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI Control register of the MCU.

AI04785

COMPARE

VPFD = 4.4V

VCC

COMPARE

VSO = 2.5V

VBL= 2.5V BL

COMPARE

Crystal

SPI

INTERFACE

REAL TIME CLOCK

CALENDAR

44 BYTES

USER RAM

RTC w/ALARM

& CALIBRATION

WATCHDOG

SQU ARE W AVE

SDO

SDI

SCL

RSTIN1

POR

SQW

RST(1)

WDI

WDF

IRQ/FT/OUT(1)

VBAT

32KHz

OSCILLATOR

RSTIN2

(2.65V if THS = VSS)

AI03686

Master

(ST6, ST7, ST9,

ST10, Others)

SPI Interface with

(CPOL, CPHA)(1) =

('0','0') or ('1','1')

CS3 CS2 CS1

M41T94

XXXXX

CQD

XXXXX

CQD

E E

CQD

Summary description M41T94

10/40

Figure 6. Data and clock timing

Table 2. Function table

Mode E SCL SDI SDO

Disable reset H Input disabled Input disabled High Z

WRITE L Data bit latch High Z

READ L X Ne xt data bit shift (1)

1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.

AI04630

AI04631

AI04632

MSB LSB

CPHA

SDI

CPOL

MSB LSB

SDO

M41T94 Signal description

11/40

2 Signal description

2.1 Serial data output (SDO)

The output pin is used to transfer data serially out of the Memory. Data is shifted out on t he

falling edge of the serial clock.

2.2 Serial data input (SDI)

The input pin is used to transfer data serially into the device. Instructions, addresses, and

the data to be written, are each received this way. Input is latched on the rising edge of the

serial clock.

2.3 Serial clock (SCL)

The serial cloc k provide s the timing f o r the serial interf ace ( as shown in Figure 7 on page 13

and Figure 8 on page 14). The W/R bit, addresses, or data are latched, from the input pin,

on the rising edge of the cloc k input. The ou tput data on the SDO pin changes state afte r the

falling edge of the clock input.

The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of

the two follo wing modes:

●(CPOL, CPHA) = ('0', '0') or

●(CPOL, CPHA) = ('1', '1').

For these two modes, input data (SDI) is latched in by the low-to-high transition of clock

SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2

on page 10 and Figure 6 on page 10).

2.4 Chip Enable (E)

When E is high, the memory device is de selected, and t he SDO outp ut pin is held in it s high

impedance state. After power-on, a high-to-low transition on E is required prior to the st art of

any operation.

Operation M41T94

12/40

3 Operation

The M41T94 cloc k oper ates as a sla v e de vice on the SPI serial b us. Each memory device is

accessed by a simple serial interface that is SPI bus compat ible. The bus signals are SCL,

SDI and SDO (see Tab le 1 on page 8 and Figure 5 on page 9). The device is selected when

the Chip Enable input (E) is held low. All instructions, addresses and data are shifted se rially

in and out of the chip. The most significant bit is presented first, with the data input (SDI)

sampled on the first rising edge of th e clock (SCL) after the Chip Enable (E) goes low. The

64 bytes contained in the device can then be accessed sequentially in the following order:

●1st Byte: tenths/hundredths of a second register

●2nd Byte: seconds register

●3rd Byte: minutes register

●4th Byte: century/hours register

●5th Byte: day register

●6th Byte: date register

●7th Byte: month register

●8th Byte: year register

●9th Byte: Control register

●10th Byte: Watc hd og reg ist er

●11th - 16th Bytes: Alarm registers

●17th - 19th Bytes: reserved

●20th Byte: Square Wave register

●21st - 64th Bytes: user RAM

The M41T94 clock continually monitors VCC for an out-of tolerance condition. Should VCC

f all below VPFD, the device terminates an access in progress and resets the device address

counter. Inputs to the device will not be recognized at this time to prevent erroneous data

from being written to the device from a an out-of-tole rance system. When VCC falls below

VSO, the de vice automatically s witches o ver to the battery and pow ers down into an ultra low

current mode of operation to conserve battery life. As system power returns and VCC rises

above VSO, the battery is disconnected, and the power supply is switched to external VCC.

Write protection continues until VCC reaches VPFD (min) plus tREC (min). For more

information on Battery Storage Life refer to Application Note AN1012.

M41T94 Operation

13/40

3.1 SPI bus characteristics

The Serial Peripheral interface (SPI) bus is intended for synchronous communication between different

ICs. It consists of four signal lines: Serial data input (SDI), Serial data output (SDO), Serial clock (SCL)

and a Chip Enable (E).

By definition a device that gives out a message is called “transmitter,” the receiving de vice that gets the

message is called “receiver.” The device that controls the message is called “master.” The devices that

are controlled by the master are called “slaves.”

The E input is used to initiate and terminate a data transfer. The SCL input is used to synchronize data

transfer between the master (micro) and the slave (M41T94) devices.

The SCL input, which is genera ted b y the microcon troller, is active only during address and data tran sfer

to any device on the SPI bus (see Figure 5 on page 9).

The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of the two

fo llowing modes:

●(CPOL, CPHA) = ('0', '0') or

●(CPOL, CPHA) = ('1', '1').

F o r th ese two modes, input dat a ( SDI) is latc he d in by the low-to- hig h transition of clock SCL , and o utpu t

data (SDO) is shifted out on the high-to-low transition of SCL (see Table2 on page10 and Figure 6 on

page 10).

There is one clock for each bit transferred. Address and data bit s are transferred in groups of eight bits.

Due to memory size the second most significant address bit is a Don’t Care (address bit 6).

Figure 7. Input timing requirements

AI04633

SCL

SDI

MSB IN

SDO

tDVCH

HIGH IMPEDANCE

LSB IN

tELCH

tCHDX

tDLDH

tDHDL

tCHCL

tCLCH

tEHCH

tEHEL

tCHEH

Operation M41T94

14/40

Figure 8. Output timing requirements

AI04634

SCL

SDO

LSB OUT

SDIADDR. LSB IN

tEHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

MSB OUT

M41T94 Operation

15/40

Table 3. AC characteristics

Symbol Parameter(1)

1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).

Min Max Unit

fSCL Serial clock input frequency DC 2 MHz

tCH(2)

2. tCH + tCL ≥ 1/fSCL

Clock high 200 ns

tCHCL(3)

3. Value guaranteed by design, not 100% tested in production.

Clock transition (fall time) 1 µs

tCHDX Serial clock input high to input data transition 50 ns

tCHEH Serial clock input high to Chip Enable high 200 ns

tCL(2) Clock low 200 ns

tCLCH(3) Clock transition (rise time) 1 µs

tCLQV Serial clock input low to output valid 150 ns

tCLQX Serial clock input low to output data transition 0 ns

tDHDL(3) Input data transition (fall time) 1 µs

tDLDH(3) Input data transition (rise time) 1 µs

tDVCH Inpu t data to serial clock input high 40 ns

tEHCH Chip Enable high to serial clock input high 200 ns

tEHEL Chip Enable high to Chip Enable low 200 ns

tEHQZ(3) Chip Enable high to output high-z 250 ns

tELCH Chip Enable low to serial clock input high 200 ns

tQHQL(3) Output data transition (fall time) 100 ns

tQLQH(3) Output data transition (rise time) 100 ns

Operation M41T94

16/40

3.2 READ and WRITE cycles

Address and d ata ar e shif ted M SB f ir st int o t he Serial Data In put (SDI) a nd o ut of th e Serial

Data Output (SDO). Any data transfer considers the first bit to define whether a READ or

WRITE will occur. This is followed by seven bits defining the address to be read or written.

Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE

operation. The address is always the second through the eighth bit written after the Enable

(E) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a

'0,' one or more READ cycles will occur (see Figure Figure 9 on page 17 and Figure 10 on

page 17).

Data transfers can occur one byte at a time or in multiple byte burst mode, during which the

address pointer will be automatically incremented. For a single byte transfer, one byte is

read or written and then E is driven high. For a multiple byte transfer all that is required is

that E continue to remain low. Under this condition, the address pointer will continue to

increment as stated previously. Incrementing will continue until the device is deselected by

taking E high. The address will wrap to 00h after incrementing to 3Fh.

The system-to-user transfer of clock data will be halted whenever the address being read is

a cloc k addr ess (0 0h to 07 h) . Altho ug h the clock continues to maintain the co rr ect t ime, this

will prevent updates of time and date during either a READ or WRITE of these address

locations by the user. The update will resume either due to a deselect condition or when the

pointer increments to an non-clock or RAM address (08h to 3Fh).

Note: This is true both in READ and WRITE mode.

3.3 Data retention mode

With valid VCC applied, the M41T94 can be accessed as described above with READ or

WRITE cycles. Should the supply voltage decay, the M41T94 will automatically deselect,

write protecting itself when VCC falls between VPFD (max) and VPFD (min) (see Figure 17 on

page 32). At this time, the reset pin (RST) is driven active and will remain active until VCC

returns to nominal levels. When VCC falls below the switch-over voltage (VSO), power input

is switched from the VCC pin to the SNAPHAT battery (or external battery for SO16) at this

time, and the clock registers are maintained from the attached battery supply. All outputs

become high impedance. On power up, when VCC returns to a nominal value, write

protection continues for tREC by internally inhibiting E. The RST signal also remains active

during this time (see Figure 17 on page 32). Before the next active cycle, Chip Enable

should be taken high for at least tEHEL, then low.

For a further more detailed review of ba ttery lifetime calculations, please see Application

Note AN1012.

M41T94 Operation

17/40

Figure 9. READ mode sequence

Figure 10. WRITE mode sequence

SCL

SDI

SDO

HIGH IMPEDANCE

W/R BIT 7 BIT ADDRESS

MSB DATA OUT

MSB MSB

(BYTE 1) DATA OUT

(BYTE 2)

112 13 14 15 16 17 22

3456789

AI04635

SCL

SDI

SDO

HIGH IMPEDANCE

DATA BYTE

7 BIT ADDR

W/R BIT

10 15

MSB MSB

06543210

789

AI04636

Clock operations M41T94

18/40

4 Clock operations

The eight byte clock register (see Table 4 on page 19) is used to both set the clock and to

read the date and time from the cloc k, in a binary coded decimal f ormat. Tenths/Hu ndredths

of Seconds, Seconds, Minutes, and Hours ar e contained within the first four registers. Bits

D6 and D7 of cloc k registe r 03h (centu ry/hours register) contain the CENTURY ENABLE bit

(CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from

'0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is

set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the Day (day of

week). Register s 05h, 06h, an d 07h cont ain the Date (day of month), Month and Years . The

ninth clock register is the Control register (this is described in the clock calibration section).

Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the

oscillator to stop. If the device is ex pected to spend a significant amount of time on the shelf,

the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator

restarts within one second.

The eight clock registers may be read one byte at a time, or i n a sequential block. The

Control register (Address location 08h) ma y be accessed independently. Provision has been

made to assure that a clo ck update does not occur while any of the eight clock addresses

are being read. If a clock address is being read, an update of the clock registers will be

halted. This will prevent a transition of data during the READ.

4.1 Power-down time-stamp

When a power failure occurs, the Halt Update bit (HT) will automatically be set to a '1.' This

will prevent the clock from updating the clock registers, and will allow the user to read the

exact time of the power-down event. Resetting the HT bit to a '0' will allow the clock to

update the clock registers with the current time. For more information, see Application Note

AN1572.

4.2 Clock registers

The M41T94 offers 20 internal registers which contain clock, Alarm, Watchdog, Flag,

Square Wave and Control data (see Table4 on page19). These registers are me m ory

locations which contain external (user accessible) and internal copies of the data (usually

referred to as BiPORT™ cells). The external copies are in d ep e nd en t of intern al fu nct i ons

except that they are updated periodically by the simultaneous transfer of the incremente d

internal copy. The internal divider (or clock) chain will be reset upon the completion of a

WRITE to any clock address.

The system-to-user transfer of clock data will be halted whenever the clock addresses (00h

to 07h) are being written. The update will resume either due to a deselect condition or when

the pointer increments to a non-clock or RAM address.

Clock an d Alarm registers store data in BCD. Control, W atchd og and Square W av e regist ers

store data in Binary format.

M41T94 Clock operations

19/40

Table 4. Clock register map(1)

1. Keys:

S = Sign bit

FT = Frequency Test bit

ST = Stop bit

0 = Must be set to zero

BL = Battery low Flag (Read only)

BMB0-BMB4 = Watchdog Multiplier bits

CEB = Century Enable bit

CB = Century bit

OUT = Output level

AFE = Alarm Flag Enable Flag

RB0-RB1 = Watchdog Resolution bits

WDS = Watchdog Steering bit

ABE = Alarm in Battery Back-Up mode Enable bit

RPT1-RPT5 = Alarm Repeat mode bits

WDF = Watchdog Flag (Read only)

AF = Alarm Flag (Read only)

SQWE = Square Wave Enable

RS0-RS3 = SQW Frequency

HT = Halt Update bit

TR = tREC bit

Addr

Function/range

BCD format

D7 D6 D5 D4 D3 D2 D1 D0

00h 0.1 seconds 0.01 seconds Seconds 00-99

01h ST 10 seconds Seconds Seconds 00-59

02h 0 10 minutes Minutes Minutes 00-59

03h CEB CB 10 Hours Hours (24 hour format) Century/hours 0-1/00-23

04h TR 0 0 0 0 Day of week Day 01-7

05h 0 0 10 date Date: day of month Date 01-31

06h 0 0 0 10M Month Month 01-12

07h 10 Years Year Year 00-99

08h OUT FT S Calibration Control

09h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

0Ah AFE SQWE ABE Al 10M Alarm month Al month 01-12

0Bh RPT4 RPT5 AI 10 date Alarm date Al date 01-31

0Ch RPT3 HT AI 10 hour Alarm hour Al hour 00-23

0Dh RPT2 Alarm 10 minutes Alarm minutes Al min 00-59

0Eh RPT1 Alarm 10 seconds Alar m Seconds Al sec 00-59

0FhWDFAF0BL0000 Flags

10h 0 0 0 0 0 0 0 0 Reserved

11h 0 0 0 0 0 0 0 0 Reserved

12h 0 0 0 0 0 0 0 0 Reserved

13h RS3 RS2 RS1 RS0 0 0 0 0 SQW

Clock operations M41T94

20/40

4.3 Setting Alarm clock registers

Address locations 0Ah-0Eh contain the Alarm settings. The Alarm can be configured to go

off at a prescribed ti me on a specific month, date, hour, minute, or second, or repeat every

year, month, day, hour, minute, or second. It can also be programmed to go off while the

M41T94 is in the battery back-up to serve as a syste m wake-up call.

Bits RPT5-RPT1 put the Alarm in the Repeat mode of oper at ion. Table 5 on page 20 show s

the possible configurations. Codes not listed in the table default to the once per second

mode to quickly alert the user of an incorrect Alarm setting.

When the clock information matches the Alarm clock settings based on the match criteria

defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set,

the Alarm condition activates the IRQ/FT/OUT pin.

Note: If the address pointer is allowed to increment to the Flag register address, an Alarm

condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a

different address . It should also be noted that if the last address written is the “Alarm

Seconds,” the address pointer will increment to the Flag address, causing this situation to

occur.

To disable the Alarm, write '0' to the Alarm date register and to RPT1–5. The IRQ/FT/OUT

output is cleared by a READ to the Flags register. This READ of the Flags register will also

reset the Alarm Flag (D6; register 0Fh). See Figure 11 on page 21.

The IRQ/FT/OUT pin can also be activated in the Battery Back-up mode. The IRQ/FT/OUT

will go low if an Alarm occurs and both ABE (Alarm in Battery Back-up mode Enable) and

AFE are set. The ABE and AFE bits are reset during pow er-up, th erefore an Alarm

generated during power-up will only set AF. The user can read the Flag register at system

boot-up to de termine if an Alarm was generated whil e the M41T94 was in the deselect

mode during power-up. Figure 12 on page 21 illustrates the Back-up mode Alarm timing.

Table 5. Alarm Repeat mode

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting

11111Once per Second

11110Once per Minute

11100Once per Hour

11000Once per Day

10000Once per Month

0 0 0 0 0 Once per Year

M41T94 Clock operations

21/40

Figure 11. Alarm interrupt reset Waveforms

Figure 12. Bac k-up mode Alarm Waveforms

AI03664

IRQ/FT/OUT

ACTIVE FLAG

0Fh0Eh 10h

HIGH-Z

AI03920

VCC

IRQ/FT/OUT

VPFD

ABE, AFE Bits in Interrupt Register

AF bit in Flags Register

HIGH-Z

VSO

HIGH-Z

tREC

Clock operations M41T94

22/40

4.4 Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of time-out into the Watchdog

RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second,

and 11 = 4 seconds. The amou nt of time-out is then determined to be the multiplication of

the five-bit multiplier value with the resolution. (For example: writing 00001110 in the

Watchdog register = 3*1 or 3 seconds).

Note: Accuracy of timer is within ± the selected resolutio n.

If the processor does not reset the timer within the specified period, the M41T94 sets the

WDF (W atchd og Flag) and gener ate s a watc hdog interrupt or a microprocesso r reset. WDF

is reset by reading the Flags register (0Fh).

The most significant bit of the Watchdog registe r is the W atchdog Steering bit (WDS). When

set to a '0,' the watchdog will activate the IRQ/FT/OUT pin when timed-out. When WDS is

set to a '1,' the watchdog will output a negativ e pulse on the RST pin for tREC. The W atchdog

time-out when the WDS bit is set to a '1.'

The watchdog timer can be reset by two methods:

1. a tr ansition (high-to-lo w or low-to-h igh) can be applied to the W atchdog Input pin (WDI),

2. the microprocessor can perf orm a WRITE of the Watchdog register.

The time-out period the n starts ov er. The WDI pin shoul d be ti ed to VSS if not used . In orde r

to perf orm a softwa re reset of the w atchdog t imer , t he original time-out period can be written

into the Watchdog register, effectively restarting the count-down cycle.

Should the watchdog timer time-o ut , and t he WDS b it is pro grammed to output an in te rrupt,

a value of 00h needs to be written to the Watchdog register in orde r to clear the

IRQ/FT/OUT pin. This will also disable the watchdog function until it is again programmed

correctly. A READ of the Flags register will reset the Watchdog Flag (bit D7; register 0Fh).

The wa tchdog function is automatically disabled upon power- up and the Watchdog register

is cleared. If the watchdog function is set to output to the IRQ/FT/OUT pin and the

F re quency Test (FT) f unction is activ a ted, the w atchd og function prev ails and the Frequency

Test function is denied.

4.5 Square Wave output

The M41T94 offers the user a prog rammable Square Wave function which is output on the

SQW pin. RS3-RS0 bits located in 13h establish the Square Wav e out put fr eque ncy. These

frequencies are listed in Table Table 6 on page 23. Once the selection of the SQW

frequency has been completed, the SQW pin can be turned on and off under software

control with the Square Wav e Enable bit (SQWE) located in register 0A h.

M41T94 Clock operations

23/40

4.6 Power-on reset

The M41T94 cont inuously monitors VCC. When VCC falls to the power fail detect trip point,

the RST pulls low (open drain) and rem ains low on po wer-up f or tREC after VCC passes VPFD

(max). The RST pin is an open drain output and an appropriate pull-up resistor shou ld be

chosen to control rise time.

4.7 Reset inputs (RSTIN1 & RSTIN2)

The M41T94 provides two independent inputs which can generate an output reset. The

duration and function of these resets is identical to a reset generated by a power cycle.

Table 7 on page 24 and Figure 13 on page 24 illustrate the AC reset characteristics of this

function. Pulses shorter than tRLRH1 and tRLRH2 will not generate a reset condition. RSTIN1

and RSTIN2 are each inte rnally pulle d up to V CC thr ou g h a 10 0kΩ resistor.

Table 6. Square Wave output frequency

Square W ave bits Square W ave

RS3 RS2 RS1 RS0 Frequency Units

0000None–

000132.768kHz

00108.192kHz

00114.096kHz

01002.048kHz

01011.024kHz

0110512Hz

0111256Hz

1000128Hz

100164Hz

101032Hz

101116Hz

11008Hz

11014Hz

11102Hz

11111Hz

Clock operations M41T94

24/40

Figure 13. RSTIN1 and RSTIN2 timing Waveforms

4.8 Calibrating the clock

The M41T94 is driven by a quartz-controlled oscillator with a nominal frequency of

32,768Hz. Uncalibrated clock accuracy will not e xceed ±35 ppm (parts per million) oscillator

frequency er ro r at 25 ° C, which equates to about ±1.5 3 minute s pe r mo n th . Whe n the

Calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25°C.

The oscillation rate of crystals changes with temperature (see Figure 14 on page 26).

Therefore, the M41T94 de sign employs periodic counter correction. The calibration circuit

adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as

shown in Fig ure 15 on page 26. The number of times pulses are blanked (subtracted,

negativ e calibratio n) or split (added, positi ve calibr ation) depends upon the value loaded in to

the five Calibration bits found in the Control register. Adding counts spe eds the clock up,

subtracting counts slows the clock down.

The Calibration bits occupy the five lower order bits (D4-D0) in the Control register (8h).

These bits can be set to rep resent any value between 0 and 31 in binary form. Bit D5 is a

Sign bit; '1' indicates posi tive calibr ation, '0' indicates nega tive calib ration. Calibr ation occurs

within a 64 minute cycle. The first 62 minutes in the cycle ma y, once per minute, have one

second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is

loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a

binar y 6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator

cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of

Table 7. Reset AC characteristics(1)

1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).

Symbol Parameter Min Max Unit

tRLRH1(2)

2. Pulse width less than 50ns will result in no RESET (for noise immunity).

RSTIN1 low to RSTIN1 high 200 ns

tRLRH2(3)

3. Pulse width less than 20ms will result in no RESET (for noise immunity).

RSTIN2 low to RSTIN2 high 100 m s

tR1HRH(4)

4. Programmable (see Table on page 28).

RSTIN1 high to RST high 40 200 ms

tR2HRH(4) RSTIN2 high to RST high 40 200 ms

AI03665

RSTIN2

RST (1)

RSTIN1

tRLRH1

tRLRH2

tR1HRH tR2HRH

M41T94 Clock operations

25/40

adjustment per calibration step in the calibration register. Assuming that the oscillator is

running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would

represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –

2.75 minutes per month.

Two methods are available for ascertaining how much calibration a gi ven M41T94 may

require.

The first involves setting the clock, letting it run f or a month and comparing it to a known

accurat e reference and recording deviation over a fixed period of time. Calibration values,

including the n umber of seconds lost or g ained in a giv en period, can be f ound in Application

Note AN934: TIMEKEEPER CALIBRATION. This allows the designer to give the end user

the ability to calibrate the clock as the environment requires, even if the final product is

packaged in a non-user serviceable enclosure. The designer could provide a simple utility

that accesses the Calibration Byte.

The second app roach is bet ter su ited to a man ufacturing environment , and involves the use

of the IRQ/FT/OUT pin. The pin will toggle at 512Hz, when the Stop bit (ST, D7 of 1h) is '0,'

the Frequency Test bit (FT, D6 of 8h) is '1,' the Alarm Flag Enable bit (AFE, D7 of Ah) is '0,'

and the Watchdog Steering bit (WDS, D7 of 9h) is '1' or the Watchdog regist er (9h = 0) is

reset.

Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at

the test temperature. For example, a reading of 512.010124Hz would indicate a +20 ppm

oscillator frequency error , requiring a –10 (XX001010) to be loaded into the Calibration Byte

for correction.

Note: Setting or changin g the Calibration Byte does not affect the Frequency Test output

frequency.

The IRQ/FT/OUT pin is an open drain output which requires a pull-up resistor for proper

operation. A 500 to 10kΩ resistor is recommended in order to control the rise time. The FT

bit is cleared on power-down.

Clock operations M41T94

26/40

Figure 14. Crystal accuracy across temperature

Figure 15. Calibration Waveform

4.9 Century bit

Bits D7 and D6 of clock register 03h contain the CENTURY ENABLE bit (CEB) and the

CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or

from '1' to '0' at the turn of the century (depending upon its initial st ate). If CEB is set to a '0,'

CB will not toggle.

AI00999b

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

∆F= K x (T –TO)2

K = –0.036 ppm/°C2 ± 0.006 ppm/°C2

TO = 25°C ± 5°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M41T94 Clock operations

27/40

4.10 Output driver pin

When the FT bit, AFE bit and Watchdog regist er are not set, the IRQ/FT/OUT pin becomes

an output driv e r that re flects t he cont ents of D7 of t he Cont rol regist er. In other words , when

D7 (OUT bit) and D6 (FT bit ) of address loca tion 08h are a '0,' th en the IRQ /FT/OUT pin will

be driven low.

Note: The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor.

4.11 Battery low warning

The M41T94 autom atically performs battery voltage monitoring upon power-up and at

factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit

D4 of Flags register 0Fh, will be asserted if the battery voltage is found to be less than

approximately 2.5V. The BL bit will remain asserted until completion of battery replacement

and subsequent battery low monitoring tests, either during the next power-up sequence or

the next scheduled 24-hour inter val.

If a battery low is generated during a power-up sequence, this indicates that the battery is

below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM.

Data should be considered suspect and verified as correct. A fresh battery should be

installed.

If a battery low indication is generated during the 24-hour interval check, this indicates that

the battery is near end of life. However, data is not compromised due to the fact that a

nominal VCC is supplied. In order to insure data integrity during subsequent periods of

battery Back-up mode, the battery should be replaced. The SNAPHAT top may be replaced

while VCC is applied to the device.

Note: This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is

disconnected.

The M41T94 only monitors the battery when a nominal VCC is applied to the device. Thus

applications which require extensive durations in the battery Back-up mode should be

powered-up periodically (at least once every few months) in order for this technique to be

beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon

power-up via a checksum or other technique.

4.12 tREC bit

Bit D7 of clock register 04h contains the tREC bit (TR). tREC refers to the au to matic

continuation of the deselect time after VCC reaches VPFD. This allows for a voltage setting

time before WRITEs may again be performe d to th e device after a power-down condition.

The tREC bit will allow the user to set the length of this deselect time as defined by Table

Table on page 28.

Clock operations M41T94

28/40

4.13 Initial power-on defaults

Upon initial application of power to the de vice, the f ollowing r egister bits are set to a '0 ' state:

Watchdog register, TR, FT, AFE, ABE, and SQWE. The following bits are set to a '1' state:

ST, OUT, and HT (see Table 9: Default values).

Table 8. tREC definitions

tREC bit (TR) STOP bit (ST) tREC time Units

Min Max

009698ms

0140200

(1)

1. Default Setting

1 X 50 2000 µs

Table 9. Default values

Condition TR ST HT Out FT AFE ABE SQWE WATCHDOG

1. BMB0-BMB4, RB0, RB1.

Initial power-up

(battery attach for

SNAPHAT)(2)

2. State of other Control bits undefined.

0111000 0 0

Subsequent power-up

(with battery back-up)(3)

3. UC = Unchanged

UC UC 1 UC 0 0 0 0 0

M41T94 Maximum rating

29/40

5 Maximum rating

Stressing the device above the rating listed in the “Absolute maximum ratings” table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exp osur e to abso lute maximum rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

Caution: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up

mode.

Caution: Do NOT wav e solder SOIC to avoid damaging SNAPHAT sockets.

Table 10. Absolute maximum ratings

Symbol Parameter Value Unit

TSTG Storage temperature (VCC off, oscillator off) SNAPHAT –40 to 85 °C

SOIC –55 to 125 °C

VCC Supply voltage –0.3 to 7 V

TSLD(1)(2)

1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget

not to exceed 180°C for between 90 to 150 seconds).

2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal

budget not to exceed 245°C for greater than 30 seconds).

Lead solder temperature for 10 seconds 260 °C

VIO Input or output Voltage –0.3 to VCC+0.3 V

IOOutput current 20 mA

PDPower dissipation 1 W

DC and AC parameters M41T94

30/40

6 DC and AC parameters

This section summarizes the oper ating and mea surement conditions , as we ll as the DC and

AC characteristics of the device. The parameters in t he following DC and AC characteristic

tables are derived from tests performed under the Measurement Condit ions listed in the

rele va nt tables. Designers should check that the operating conditions in their projects match

the measurement conditions when using the quoted parameters.

Figure 16. AC Testing input/output Waveforms

Table 11. DC and AC measurement conditions(1)

1. Output Hi-Z is defined as the point where data is no longer driven.

Parameter M41T94

VCC supply voltage 2.7 to 5.5V

Ambient operating temperature –40 to 85°C

Load capacitance (CL) 100pF

Input rise and fall times ≤ 50ns

Input pulse voltages 0.2 to 0.8VCC

Input and output timing ref. voltages 0.3 to 0.7VCC

Table 12. Capacitance

Symbol Parameter(1)(2)

1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.

2. At 25°C, f = 1MHz.

Min Max Unit

CIN Input capacitance 7 pF

COUT(3)

3. Outputs are deselected.

Output capacitance 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 50 ns

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

M41T94 DC and AC parameters

31/40

Table 13. DC characteristics

Symb. Parameter Test condition(1)

1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).

Min Typ Max Unit

IBAT Battery current OSC on TA = 25°C, VCC =

0V, VBAT = 3V 400 500 nA

Battery current OSC off 50 nA

ICC1 Supply current f = 2 MHz 2 mA

ICC2 Supply current (standby) SCL, SDI =

VCC – 0.3V 1.4 mA

ILI(2)

2. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS

through 100KΩ resistor.

Input leakage current 0V ≤ VIN ≤ VCC ±1 µA

ILO(3)

3. Outputs deselected.

Output leakage current 0V ≤ VOUT ≤ VCC ±1 µA

VIH Input high voltage 0.7VCC VCC + 0.3 V

VIL Input low voltage –0.3 0.3VCC V

VBAT Battery voltage 2.5 3.5(4)

4. For rechargeable back-up, VBAT (max) may be considered VCC.

VOH Output high voltage(5)

5. For SQW pin (CMOS).

IOH = –1.0mA 2.4 V

VOL

Output low voltage(5) IOL = 3.0m A 0.4 V

Output low voltage

(open drain)(6)

6. For IRQ/FT/OUT, RST pins (open drain): if pulled-up to supply other than VCC, this supply must be equal

to, or less than 3.0V when VCC = 0V (during battery back-up mode).

IOL = 10mA 0.4

Pull-up supply voltage

(open drain) RST, IRQ/FT/OUT 5.5 V

VPFD Power fail desele ct (THS = VCC) 4.20 4.40 4.50 V

Power fail desele ct (THS = VSS) 2.55 2.60 2.70

VSO Battery back-up s witcho ver 2.5 V

Table 14. Crystal elect rical cha racteristics (externally supplied)

Symbol Parameter(1)(2)

1. Load capacitors are integrated within the M41T94. Circuit board layout considerations for the 32.768 kHz

crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.

These characteristics are externally supplied.

2. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the

DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be

contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type.

Typ Min Max Unit

f0Resonant frequency 32.768 kHz

RSSeries resistance 50 kΩ

CLLoad capacitance 12.5 pF

DC and AC parameters M41T94

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Figure 17. Power down/up mode AC Waveforms

Table 15. Power Down/Up AC Characteristics

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).

Min Typ Max Unit

tF(2)

2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring

until 200µs after VCC passes VPFD (min).

VPFD (max) to VPFD (min) VCC fall time 300 µs

tFB(3)

3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.

VPFD (min) to VSS VCC fall time 10 µs

tRVPFD (min) to VPFD (max) VCC rise time 10 µs

tRB VSS to VPFD (min) VCC rise time 1 µs

tREC(4)

4. Programmable (see Table 8 on page 28).

Power up deselect time 40 200 ms

tDR Expected data retention time 10(5)

5. At 25°C, VCC = 0V (when using SOH28 + M4T28-BR12SH SNAPHAT top).

YEARS

AI03687

VCC

INPUTS

(PER CONTROL INPUT)

OUTPUTS

DON'T CARE

HIGH-Z

tF tFB tR

tRB

tDR

VALID VALID

(PER CONTROL INPUT)

RECOGNIZEDRECOGNIZED

VPFD (max)

VPFD (min)

VSO

tREC

RST

M41T94 Package mechanical information

33/40

7 Package mechanical information

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect . The categor y of

second Level Interconnect is marked o n the package and on the inner box label, in

compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Package mechanical information M41T94

34/40

Figure 18. SO16 – 16-lead plastic small outline package outline

1. Drawing is not to scale.

Table 16. SO16 – 16-lead Plastic small outline package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.75 0.069

A1 0.10 0.25 0.004 0.010

A2 1.60 0.063

α0° 8° 0° 8°

B 0.35 0.46 0.014 0.018

C 0.19 0.25 0.007 0.010

CP 0.10 0.004

D 9.80 10.00 0.386 0.394

e1.27––0.050– –

E 3.80 4.00 0.150 0.157

L 0.40 1.27 0.016 0.050

N16 16

SO-b

LA1 α

M41T94 Package mechanical information

35/40

Figure 19. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package outline

1. Drawing is not to scale.

Table 17. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A – –3.05– –0.120

A1 – 0.05 0.36 – 0.002 0.014

A2 – 2.34 2.69 – 0.092 0.106

B – 0.36 0.51 – 0.014 0.020

C – 0.15 0.32 – 0.006 0.012

D – 17.71 18.49 – 0.697 0.728

E – 8.23 8.89 – 0.324 0.350

e1.27– –0.050– –

eB – 3.20 3.61 – 0.126 0.142

H – 11.51 12.70 – 0.453 0.500

L – 0.41 1.27 – 0.016 0.050

α– 0° 8° – 0° 8°

N28 28

CP – – 0.10 – – 0.004

SOH-A

LA1 α

Package mechanical information M41T94

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Figure 20. SH – 4-pin SNAPHAT housing for 48mAh bat tery & c rysta l, package outline

1. Drawing is not to scale.

Table 18. SH – 4-pin SNAPHAT housing for 48mAh battery & cryst al, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A – –9.78– –0.385

A1 – 6.73 7.24 – 0.265 0.285

A2 – 6.48 6.99 – 0.255 0.275

A3 – – 0.38 – – 0.015

B – 0.46 0.56 – 0.018 0.022

D – 21.21 21.84 – 0.835 0.8560

E – 14.22 14.99 – 0.556 0.590

eA – 15.55 15.95 – 0.612 0.628

eB – 3.20 3.61 – 0.126 0.142

L – 2.03 2.29 – 0.080 0.090

SHTK-A

A1 A

M41T94 Package mechanical information

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Figure 21. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package

outline

1. Drawing is not to scale.

Table 19. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech.

data

Symbol millimeters inches

Typ Min Max Typ Min Max

A – – 10.54 – – 0.415

A1 – 8.00 8.51 – 0.315 0.335

A2 – 7.24 8.00 – 0.285 0.315

A3 – – 0.38 – – 0.015

B – 0.46 0.56 – 0.018 0.022

D – 21.21 21.84 – 0.835 0.860

E – 17.27 18.03 – 0.680 0.710

eA – 15.55 15.95 – 0.612 0.628

eB – 3.20 3.61 – 0.126 0.142

L – 2.03 2.29 – 0.080 0.090

SHTK-A

A1 A

Part numbering M41T94

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8 Part numbering

Table 20. Ordering information scheme

Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductiv e foam as it will

drain the lithium button-cell battery.

For other options , or for more information on any aspect of this device, pl ease contact the

ST Sales Office nearest you.

Example: M41T 94 MH 6 E

Device type

M41T

Supply voltage and write protect voltage

94 = VCC = 2.7 to 5.5V

THS = VCC; 4.20V ≤ VPFD ≤ 4.50V

THS = VSS; 2.55V ≤ VPFD ≤ 2.70V

Package

MQ = SO16

MH(1)= SOH28

1. The 28-pin SOIC package (SOH28) requires the SNAPHAT® battery/crystal package which is ordered

separately under the part number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in Tape &

Reel form (see Table Table 21 on page 38).

Temperature range

6 = –40 to 85°C

Shipping method

Fo r SO16:

blank = tubes (not for new design - use E)

E = Lead-free package (ECOPA CK®), tubes

F = Lead-free package (ECOPACK®), Tape & Reel

TR = Tape & Reel (not for ne w design - use F)

Fo r SOH28:

blank = tubes (not for new design - use E)

E = Lead-free package (ECOPA CK®), tubes

F = Lead-free Package (ECOPACK®), Tape & Reel

TR = Tape & Reel (not for new design - use F)

Table 21. SNAPHAT Battery Table

Part number Description Package

M4T28-BR12SH Lithium battery (48mAh) and crystal SNAPHAT SH

M4T32-BR12SH Lithium battery (120mAh) and crystal SNAPHAT SH

M41T94 Revision history

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9 Revision history

Table 22. Document Revision History

Date Version Revision Details

April 2002 1.0 First edition

25-Apr-02 1.1 Adjust graphic (Figure 4 on pa ge 9); fix table text (Table 10 on page 29,

Table 20 on page 38); adjust characteristics (Table 13 on page 31,

Table 14 on page 31)

03-Jul-02 1.2 Modify DC, Crystal Electrica l Characteristics footnotes, Default Value

table (Table 13 on page 31, Table 14 on page 31, Table 9 on page 28)

06-Nov-02 1.3 Correct dimensions (Table 19 on page 37)

26-Mar-03 1.4 Update test condition (Table 15 on page 32)

28-Apr-03 2.0 New Si changes (Figure 4 on page 9; Table 15 on page 32, Table 7 on

page 24, Table 8 on page 28, Table 9 on page 28)

15-Jun-04 3.0 Re formatted ; added Lead-free information; update characteristics

(Figure 14 on page 26; Table 10 on page 29, Table 13 on page 31,

Table 20 on page 38)

29-Aug-2006 4

Changed document to new template; amalgamated diagrams in Feature

summar y on page 1; updated Package mechanical data in Section 7:

Package mechanical infor m ation; small text changes for entire

document, ECOPACK compliant

M41T94

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