WM8776SEFT/V - Wolfson Microelectronics

w WM8776

24-bit, 192kHz Stereo CODEC with 5 Channel I/P Multiplexer

WOLFSO N MICROELE CTRONICS plc

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Production Data, September 2008, Rev 4.1

DESCRIPTION

The WM8776 is a high performance, stereo audio

CODEC with five channel input selector. The W M8776 is

ideal for surround sound processing applications for

home hi-fi , DVD-RW and other audio visual equi pm ent .

A stereo 24-bit multi-bit sigma delta ADC is used with a

five stereo channel input mixer. Each ADC channel has

programmable gain control with automatic level control.

Digital audio output word lengths from 16-32 bits and

sampling rates from 32kHz to 96kHz are supported.

A stereo 24-bit multi-bit sigma delta DAC is used with

digital audio input word lengths from 16-32 bits and

sampling rates from 32kHz to 192kHz. The DAC has an

input mixer allowing an external analogue signal to be

mixed with the DAC signal. There are also Headphone

and line outputs, with volume controls for the

headphones.

The WM8776 supports fully independent sample rates

for the A DC and DAC. The audio data int erface supports

I2S, left justified, right justified and DSP formats.

The device is controlled in software via a 2 or 3 wire

serial interface, selected by the MODE pin, which

provides access to all features including channel

selection, volume controls, mutes, and de-emphasis

fa cilities.

The device is available in a 48-pin TQFP package.

FEATURES

• Audio Performance

− 108dB SNR (‘A’ weighted @ 48kHz) DAC

− 102dB SNR (‘A’ weighted @ 48kHz) ADC

• DAC Sampli ng Frequenc y: 32kHz – 192kHz

• ADC Sampli ng Frequenc y: 32kHz – 96kHz

• Five stereo ADC inputs with analogue gain adjust from

+24dB to –21dB in 0.5dB steps

• Programm abl e Limiter or Aut om at ic Level Control (ALC)

• Stereo DAC with independent analogue and digital

volume c ontr ols

• Stereo Headphone and Line Output

• 3-W ire S P I Com pati bl e or 2-W ir e Soft ware Serial

Control Interfac e

• Master or Slave Clocki ng Mode

• Programmable Audio Data Interface Modes

− I

2S, Left , Right J ustified or DSP

− 16/20/24/32 bit Word Lengths

• Analogue Bypass Path Feature

• Selectable AUX input to the volume controls

• 2.7V to 5.5V Analogue, 2.7V to 3.6V Digit al suppl y

Operation

APPLICATIONS

BLOCK DIAGRAM • Surround Sound AV Proc es sor s and Hi-Fi sys tems

• DVD-RW

WM8776 Production Data

w PD, Rev 4.1, September 2008

TABLE OF CONTENTS

DESCRIPTION .......................................................................................................1

FEATURES.............................................................................................................1

APPLICATIONS .....................................................................................................1

BLOCK DIAGRAM......... ... .... .... .... .... .... ............ .... .... .... .... .... .... .... .... .... .... .... .... ... ..1

TABLE OF CONTENTS .........................................................................................2

PIN CONFIGURATION....... ... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .3

ORDERING INFORMATION .......... ... .... .... .... .... .... ............ .... .... .... .... .... .... .... ... .... ..3

PIN DESCRIPTION ........ ... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... ... ..4

ABSOLUTE MAXIMUM RATINGS.........................................................................5

ELECTRICAL CHARACTERISTICS ......................................................................6

TERMINOLOGY............................................................................................................7

MASTER CLOCK TIMING......................................................................................9

DIGITAL AUDIO INTERFACE – MA STER MODE................................................. ......10

DIGITAL AUDIO INTERFACE – SLAVE MODE..........................................................11

3-WIRE MPU INTERFACE TIMING ............................................................................12

CONTROL INTERFACE TIMING – 2-WIRE MODE .......... ..........................................13

INTERNAL POWER ON RESE T CI RCUIT ....... .... .... .... .... .... .... .... ............ .... .... ...14

DEVICE DESCRIPTION.......................................................................................16

INTRODUCTION.........................................................................................................16

AUDIO DATA SAMPLING RATES........................ .......................... .............................17

ZERO DETECT...........................................................................................................18

POWERDOWN MODES .. ... .... ... ... ... .... ...... ... .... ... ... ... .... ...... ... .... ... ... .... ... ... ....... ... ... ...18

DIGITAL AUDIO INTERFACE.................................................. ...................................19

CONTROL INTERFACE OPERATION. ... ... ... .... ... ... ... ....... ... ... .... ... ... .... ...... ... .... ... ... ...23

CONTROL INTERFACE REGISTERS ....... ... .... ...... ... .... ... ... ... .... ... ....... ... ... ... .... ... ... ...25

LIMITER / AUTOMATIC LEVEL CONTROL (ALC)......... ... ... ....... ... ... ... .... ... ... ....... ... ...34

DIGITAL FILTER CHARACTERISTICS...............................................................49

DAC FILTER RESPONSES........ ... ... .... ...... ... .... ... ... ... .... ...... ... .... ... ... ... .... ...... ... .... ... ...49

ADC FILTER RESPONSES........... ... .... ... ... ... .... ...... ... .... ... ... ... .... ... ...... .... ... ... ... .... ... ...50

ADC HIGH PASS FILTER....... ... ... ... ....... ... ... .... ... ... ... ....... ... ... .... ... ... ... ....... ... .... ... ... ...51

DIGITAL DE-EMPHASIS CHARACTERISTICS...........................................................52

APPLICATIONS INFORMATION.........................................................................53

EXTERNAL CIRCUIT CONFIGURATION ............ .......................... .............................53

RECOMMENDED EXTERNAL C OMPONE NTS... .... .... .... ............ .... .... .... ...........54

PACKAGE DIMENSIONS ....................................................................................56

IMPORTANT NOTICE..........................................................................................57

ADDRESS:..................................................................................................................57

Product ion Data WM8776

w PD, Rev 4.1, September 2008

PIN CONFIGURATION

ORDERING INFORMATION

DEVICE TEMPERATURE

RANGE PACKAGE MOISTURE

SENSITIVITY LEVEL PEAK SOLDERING

TEMPERATURE

WM8776SEFT/V -25 to +85oC 48-pin TQFP

(Pb-free) MSL2

(drybagged) 260°C

WM8776SEFT/RV -25 to +85oC 48-pin TQFP

(Pb-free, tape and reel) MSL2

(drybagged) 260°C

Note:

Reel quantity = 2,200

WM8776 Production Data

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PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1 AIN2L Analogue Input

Channel 2 left input multiplexor virtual ground

2 AIN1R Analogue Input

Channel 1 right input multiplexor virtual ground

3 AIN1L Analogue Input

Channel 1 left input multiplexor virtual ground

4 DACBCLK Digital input/output

DAC audio interfac e bit cl ock

5 DACMCLK Digital input

Master DAC clock ; 256, 384, 512 or 768fs (fs = word clock fr equency)

6 DIN Digital Input

DAC data input

7 DACLRC Digital input/output

DAC left/right word clock

8 ZFLAG R Open Drain output DAC Right Zero Flag output (external pull-up resistor required)

9 ZFLAG L Open Drain output DAC Left Zero Flag output (external pull-up resistor required)

10 ADCBCLK Digital input/output

ADC audio interfac e bit cl ock

11 ADCMCLK Digital input

ADC audio interfac e m as t er cloc k

12 DOUT Digital output

ADC data output

13 ADCLRC Digital input/output

ADC left/right word clock

14 DGND Supply

Digital negati ve supply

15 DVDD Supply

Digital pos it ive s uppl y

16 MODE Digital input

Control interface mode select

17 CE Digital input

Serial interf ac e Latch s ignal

18 DI Digital input

Serial interf ac e data

19 CL Digital input

Serial interf ac e c lock

20 HPOUTL Analogue Output

Headphone left channel output

21 HPGND Supply

Headphone negative supply

22 HPVDD Supply

Headphone positive supply

23 HPOUTR Analogue Output

Headphone right channel output

24 NC Not bonded

25 NC Not bonded

26 VOUTL Analogue output

DAC channel left output

27 VOUTR Analogue output

DAC channel right output

28 VMIDDAC Analogue output

DAC midrai l decoupl ing pin ; 10uF external decoupling

29 DACREFN Analogue input

DAC negative reference input

30 DACREFP Analogue input

DAC positive reference input

31 AUXR Analogue input

DAC mixer right channel input

32 AUXL Analogue input

DAC mixer left channel input

33 VMIDADC Analogue Output

ADC midrail divider decoupling pin; 10uF external decoupling

34 ADCREFGND Supply ADC negative supply and subs tra te connec ti on

35 ADCREFP Analogue Output

ADC positive reference decoupling pin; 10uF external decoupling

36 AVDD Supply

Analogue posi ti ve sup ply

37 AGND Supply

Analogue negative supply and subVs tr ate c onnecti on

38 AINVGR Analogue Input

Right channel multiplexor virtual ground

39 AINOPR Analogue Output

Right channel multiplexor output

40 AINVGL Analogue Input

Left channel m ul ti pl exor virtual ground

41 AINOPL Analogue Output

Left channel m ul ti pl exor output

42 AIN5R Analogue Input

Channel 5 right input multiplexor virtual ground

43 AIN5L Analogue Input

Channel 5 left input multiplexor virtual ground

44 AIN4R Analogue Input

Channel 4 right input multiplexor virtual ground

45 AIN4L Analogue Input Channel 4 left input m ultiplexor virtual ground

46 AIN3R

Analogue Input Channel 3 right input mu lt ipl exor virtual ground

47 AIN3L

Analogue Input Channel 3 left input m ultiplexor virtual ground

48 AIN2R

Analogue Input Channel 2 right input mu lt ipl exor virtual ground

Note : Digital input pins have Schmitt trigger input buffers.

Product ion Data WM8776

w PD, Rev 4.1, September 2008

ABSOLUTE MAXIMUM RATINGS

Absolut e Maxim um Rati ngs ar e s t ress rat ings only. P erm ane nt da m age to the dev ice may be c aused by c ontinuous l y operati ng at

or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified.

ESD S ensitive Device. This device is manuf actured on a CMOS process . It is theref ore generically susc eptible

to damage fr om excessive st atic voltages . Proper ESD precautions must be taken during handling and storage

of this devic e.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage

conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Suppl i ed in m oisture barrier bag.

MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidi ty . Suppli ed in m ois t ure barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION MIN MAX

Digital supply voltage -0.3V +3.63V

Analogue supply voltage -0.3V +7V

Voltage range digit al inputs (MCLK, DIN, ADCLRC, DACLRC,

ADCBCLK, DACBCLK, DI, CL, CE and MODE) DGND -0.3V DVDD + 0.3V

Voltage range analogue inputs AGND -0.3V AVDD +0.3V

Master Clock Frequenc y 37MHz

Operating temperature range, TA -25°C +85°C

Storage temperature -65°C +150°C

Notes:

1. Analogue and digital grounds must always be within 0.3V of each other.

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digita l supply range DVDD 2.7 3.6 V

Analogue supply range AVDD, HPVDD,

DACREFP 2.7 5.5 V

Ground AGND, DGND,

DACREFN,

ADCREFGND

0 V

Differenc e DGND to AGND -0.3 0 +0.3 V

Note: digital supply DVDD m us t never be more than 0.3V great er than AVDD.

WM8776 Production Data

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ELECTRICAL CHARACTERISTICS

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +2 5oC, fs = 48kHz, MCLK = 256fs unless otherwise stat ed.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital Logic Levels (TTL Levels)

Input LOW level VIL 0.8 V

Input HIGH level VIH 2.0 V

Output LOW VOL IOL=1mA 0.1 x DVDD V

Output HIGH VOH IOH=1mA 0.9 x DVDD V

An alogue Reference Levels

Reference voltage VVMID AVDD/2 V

Potenti al divi der resistance RVMID 50k Ω

DAC Performance (Load = 10k Ω, 50pF)

0dBFs Full scale output voltage 1.0 x

AVDD/5 Vrms

SNR (Note 1,2) A-weighted,

@ fs = 48kHz 102 108 dB

SNR (Note 1,2) A-weighted

@ fs = 96kHz 108 dB

Dynamic Range (Note 2) DNR A-weighted, -60dB

full scal e input 108 dB

Total Harm onic Dis tor tion (THD) 1kHz, 0dBFs -97 -90 dB

DAC channel separati on 100 dB

1kHz 100mVpp 50 dB

Power Supply Reject ion Rati o PSRR 20Hz to 20kHz

100mVpp 45 dB

Headphone Buffer

Maximum Output voltage 0.9 Vrms

RL = 32 Ω 25 mW

Max Output Power (Note 4) Po RL = 16 Ω 50 mW

SNR (Note 1,2) A-weighted 85 92 dB

Headphone analogue Volume

Gain Step Size 0.5 1 1.5 dB

Headphone analogue Volume

Gain Range 1kHz Input -73 +6 dB

Headphone analogue Volume

Mute Attenuati on 1kHz Input, 0dB gain 100 dB

1kHz, RL = 32Ω @ Po=

10mW rm s -80

0.01 -60

0.1 dB

Total Harm onic Dis tor tion THD

1kHz, RL = 32Ω @ Po=

20mW rm s -77

0.014 -55

1.0 dB

Power Supply Rejection Rati o P SRR 20Hz to 20kHz, without

supply decoupli ng -40 dB

ADC Performance

Input Signal Level (0dB) 1.0 x

AVDD/5 Vrms

SNR (Note 1,2) A-weighted, 0dB gain

@ fs = 48kHz 97 102 dB

SNR (Note 1,2) A-weighted, 0dB gain

@ fs = 96kHz

64 x OSR

100 dB

Dynamic Range (note 2) A-weighted, -60dB

full scal e input 102 dB

Total Harm oni c Dis tor ti on (THD) 1kHz, 0dBFs -92 dB

Product ion Data WM8776

w PD, Rev 4.1, September 2008

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +2 5oC, fs = 48kHz, MCLK = 256fs unless otherwise stat ed.

1kHz, -1dBFs -95 -85 dB

ADC Channel Separation 1kHz Input 90 dB

Programmable Gain Step Size 0.25 0.5 0.75 dB

Programmable Gain Range

(Analogue) 1kHz Input -21 +24 dB

Programmable Gain Range

(Digital) 1kHz Input -103 -21.5 dB

Analogue Mute Attenuation

(Note 6) 1kHz Input, 0dB gain 76 dB

1kHz 100mVpp 50 dB

Power Supply Reject ion Rati o PSRR 20Hz to 20kHz

100mVpp 45 dB

Analogue Input (AIN) to Analogue output (VOUT) (Load=10kΩ, 50pF, gain = 0dB) Bypass Mode

0dB Full scale output voltage 1.0 x

AVDD/5 Vrms

SNR (Note 1) 99 103 dB

1kHz, 0dB -93 dB

THD

1kHz, -3dB -95 dB

1kHz 100mVpp 50 dB

Power Supply Reject ion Rati o PSRR 20Hz to 20kHz

100mVpp 45 dB

Mute Attenuati on 1kHz, 0dB 100 dB

Supply Current

Analogue supply current AVDD = 5V 48 m A

Digita l supply cur rent DVDD = 3.3V 8 mA

Aux Input (AUX/L/R) to Analogue output (VOUT L/R)( Load=10kΩ, 50pF, gain = 0dB)

SNR 108 dB

THD -95 dB

Notes:

1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’

weighted.

2. All performance m eas ur em ent s done with 20kHz low pass filter, and where noted an A-weight filter. F ail ure to use

such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical

Characteris ti c s. T he low pass fil ter rem oves out of band noise; alt hough it is not audible it m ay aff ec t dynamic

specification values.

3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).

4. Harmonic dist ort ion on the headphone output dec reases with output power.

5. All performance measurem ent done using c ertai n t im ings c ondi ti ons (P lease ref er to sec ti on ‘Digi tal Audi o Inter face’).

6. A full digital MUTE can be achieved if the ADC gain (LAG/RAG) is set to minimum.

TERM INOLOGY

1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output

with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).

2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.

Normall y a T HD+N meas urem ent at 60dB below full scal e. The m eas ured si gnal is then c orrected by adding the 60dB

to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).

3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

4. Stop band attenuation (dB) - Is the degree to which the frequency spec tr um is att enuated (out side audi o band).

WM8776 Production Data

w PD, Rev 4.1, September 2008

5. Channel Separati on (dB) - Al so known as Cross-Talk . This is a measure of the amount one channel is isolat ed from

the other. Normally measured by sending a full scale signal down one channel and measuring the other.

6. P as s -Band Ripple - Any variation of the frequency respons e in the pas s- band region.

Product ion Data WM8776

w PD, Rev 4.1, September 2008

MASTER CLOCK TIMI NG

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, ADC/DACMCLK = 256fs unless

otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

System Clock Timing Information

ADC/DACMCLK System clock

pulse width high tMCLKH 11 ns

ADC/DACMCLK System clock

pulse width low tMCLKL 11 ns

ADC/DACMCLK System clock

cycle time tMCLKY 28 1000 ns

AD C/DA C M CL K Duty c y cle 40:60 60:40

Power-saving mode act ivat ed After MCLK stopped 2 10 µs

Normal m ode resumed After MCLK re-started 0.5 1 MCLK

cycle

Table 1 Master Clock Timing Requirements

Note:

If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with

internal digital audio filters being reset. In this power-saving mode, all registers will retain their values and can be accessed

in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically powered up, but a

write to the volume update regis t er bit is requi red to rest ore the correc t volume setti ngs .

WM8776 Production Data

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DIGITAL AUDIO INTERFACE – MASTER MODE

ADCBCLK

DOUT

ADCLRC

DIN

DACLRC

WM8776

CODEC

DVD

Controller

DACBCLK

Figure 2 Audio Interface - Mast er M o de

ADCBCLK/

DACBCLK

(Output)

DOUT

ADCLRC/

DACLRC

(Outputs)

DIN

DDA

DHT

DST

Figure 3 Digital Audio Data Timing – Master Mode

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless

otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Audio Data Input Timing Information

ADC/DACLRC propagation

delay from ADC/DACBCLK

fall ing edge

tDL 0 10 ns

DOUT propagation delay

from ADCBCLK falling edge tDDA 0 10 ns

DIN setup time to

DACBCLK rising edge tDST 10 ns

DIN hold time from

DACBCLK rising edge tDHT 10 ns

Table 2 Digital Audi o Data Timing – Master Mode

Product ion Data WM8776

w PD, Rev 4.1, September 2008

DIGITAL AUDIO IN TERFACE – SLAVE MODE

ADCBCLK

DOUT

ADCLRC

DIN

DACLRC

WM8776

CODEC DVD

Controller

DACBCLK

Figure 4 Audio Interface – Slave M o de

ADCBCLK/

DACBCLK

DACLRC/

ADCLRC

BCH

BCL

BCY

DIN

DOUT

LRSU

LRH

Figure 5 Digital Audio Data Timing – Slave M ode

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +2 5oC, Slave Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless

otherwise stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Audio Data Input Timing Information

ADC/DACBCLK cycl e tim e tBCY 50 ns

ADC/DACBCLK pul s e width

high tBCH 20 ns

ADC/DACBCLK pul s e width

low tBCL 20 ns

DACLRC/ADCLRC set-up

time to ADC/DACBCLK

rising edge

tLRSU 10 ns

DACLRC/ADCLRC hold

time from ADC/DACBCLK

rising edge

tLRH 10 ns

DIN set-up time to

DACBCLK rising edge tDS 10 ns

DIN hold time from

DACBCLK rising edge tDH 10 ns

DOUT propagation delay

from ADCBCLK falling edge tDD 0 10 ns

Table 3 Digital Audio Data Timing – Slave Mode

Note: ADCLRC and DACLRC should be synchronous with MCLK, although the WM8776 interfac e is tol erant of phase

variations or jitt er on thes e signal s .

WM8776 Production Data

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3-WIRE MPU I NTERFACE TIMING

CSL

DHO

DSU

CSH

SCY

SCH

SCL

SCS

LSB

CSS

Figure 6 SPI Compatible (3-wire) Control Interface Input Timing (MODE=1)

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated

PARAMETER SYMBOL MIN TYP MAX UNIT

CL rising edge to CE rising edge tSCS 60 ns

CL pulse cycle time tSCY 80 ns

CL pulse width low tSCL 30 ns

CL pulse width high tSCH 30 ns

DI to CL set-up time tDSU 20 ns

CL to DI hold time tDHO 20 ns

CE pulse width low tCSL 20 ns

CE pulse width high tCSH 20 ns

CE rising to CL rising tCSS 20 ns

Table 4 3-wire SPI Compatible Control Interface Input Timing Information

Product ion Data WM8776

w PD, Rev 4.1, September 2008

CONTROL INTERFACE TIMING – 2-WIRE MODE

Figure 7 Control Interface Timing – 2-Wire Serial Control Mode (MODE=0)

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated

PARAMETER SYMBOL MIN TYP MAX UNIT

Program Register Input Information

CL Frequency 0 526 kHz

CL Low Pulse-Width t1 1.3 us

CL High Pulse-Width t2 600 ns

Hold Time (Start Condition) t3 600 ns

Setup Tim e (Star t Conditi on) t4 600 ns

Data Setup Time t5 100 ns

DI, CL Rise Time t6 300 ns

DI, CL Fall Time t7 300 ns

Setup Tim e (S top Condit ion) t8 600 ns

Data Hold Time t9 900 ns

Pulse width of spikes that will be suppressed tps 0 5 ns

Table 5 2-wire Control Interf ace Timing In for mat ion

WM8776 Production Data

w PD, Rev 4.1, September 2008

INTERNAL POWER ON RESET CIRCUIT

Figur e 8 Internal Pow er o n Reset Circui t Schematic

The W M8776 includes an internal Po wer on Reset Cir cuit which i s used reset the digital logic into a

default state after power up.

Figure 8 shows a s c hematic of the i nter nal P OR ci rc uit . The POR c ir cuit is powered from AV DD. The

circuit monitors DVDD and VMID and asserts PORB low if DVDD or VMID are below the minimum

threshold Vpor_off.

On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until

AVDD and DVDD and VMID are established. When AVDD, DVDD, and VMID have been

established, PORB is released high, all registers are in their default state and writes to the digital

interface m ay tak e plac e.

On power down, P ORB is as ser ted low whenever DV DD or V MID drop bel ow t he minim um threshol d

Vpor_off.

If AV DD is removed at any time, the int ernal Power on Reset circ uit is powered down and PORB will

follo w AVDD.

In m ost applications the tim e required for the device to release PORB hig h will be determined by the

charge time of the VMID node.

Figure 9 Typical Power up Sequence where DVDD is Powered before AVDD

Product ion Data WM8776

w PD, Rev 4.1, September 2008

Figure 10 Typical Power up Sequence where AVDD is Powered before DVDD

Typi cal PO R Operati on (typical values, not tested)

SYMBOL MIN TYP MAX UNIT

Vpora 0.5 0.7 1.0 V

Vporr 0.5 0.7 1.1 V

Vpora_off 1.0 1.4 2.0 V

Vpord_off 0.6 0.8 1.0 V

In a real application the designer is unlikely to have control of the relative power up sequence of

AVDD and DVDD. Using the POR circuit to monitor VMID ensures a reasonable delay between

applying power to the device and Device Ready.

Figure 9 and Figure 10 show typical power up scenarios in a real system. Both AVDD and DVDD

must be established and VMID must have reached the threshold Vporr before the device is ready

and can be written to. Any writes to the device before Device Ready will be ignored.

Figure 9 shows DVDD powering up before AVDD. Figure 10 shows AVDD powering up before

DVDD. In both cases, the time from applying power to Device Ready is dominated by the charge

time of VMID.

A 10uF cap is recommended for decoupling on VMID. The charge time for VMID will dominate the

time required for the device to become ready after power is applied. The time required for VMID to

reach the threshold is a function of the VMID resistor string and the decoupling capacitor. The

Resistor string has an typical equivalent resistance of 50kΩ (+/-20%). Assuming a 10uF capacitor,

the time required for VMID to reach threshold of 1V is approx 110ms.

WM8776 Production Data

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DEVICE DESCRIPTION

INTRODUCTION

W M8776 is a com plet e 2-c hannel DAC, 2-channel A DC audio CODEC, with flexible input mult iplexor

including digital interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched

capacitor multi-bit sigma delta DACs with analogue volume controls on each channel and output

smoothing filters. It is available in a single package and controlled by either a 3-wire or 2-wire

software interf ac e. The 3-wire interfac e is c ompatible with the SP I s tandar d.

An analogue bypass path option is available, to allow stereo analogue signals from any of the 5

stereo inputs to be sent to the stereo outputs via the main volume controls. This allows a purely

analogue input to analogue output high quali ty signal path to be implem ented if required.

The DAC and ADC have separate left/right clocks, bit clocks, master clocks and data I/Os. The

Audio Interface may be configured to operate in either master or slave mode. In Slave mode

ADCLRC, DACLRC, ADCBCLK and DACBCLK are all inputs. In Master mode ADCLRC, DACLRC,

ADCBCLK and DACBCLK are outputs .

The input multiplexor to the ADC is configured to allow large signal levels to be input to the ADC,

using external resis tors to reduce t he amplitude of lar ger signals to within the normal operating range

of the ADC. The ADC has an analogue input PGA and a digital gain control, accessed by one

regist er write. The i nput PGA allows input sig nals to be gained up to +24dB and attenuated down to

-21dB in 0.5dB steps. The digital gain control allows attenuation from -21.5dB to -103dB in 0.5dB

steps . This allows the user maximum fl exibilit y in the use of the ADC.

The DAC has it s own digital volum e cont rol, which is adjust able between 0dB and -127.5dB in 0.5dB

steps. There is also an analogue volume control on the headphone outputs, which is adjustable

between +6dB and -73dB in 1dB steps. The analogue and digital volume controls may be operated

independently. In additi on a zero cros s detect ci rcuit i s provided for bot h anal ogue and di git al vol um e

controls. When analogue volume zero-cross detection is enabled the attenuation values are only

updated when the input signal to the gain stage is close to the analogue ground level. The digital

volume control detects a transition through the zero point before updating the volume. This

mini m i s es audibl e cli c k s and ‘zipper’ noise as the gain values change.

The DA C out put incorporat es an input sel ector and mi xer allowing a si gnal t o be eit her switched into

the signal path in place of the DAC signal or mixed with the DAC signal before the volume control.

Use of external resistors allows larger input levels to be accepted by the device, giving maximum

user flexibility.

Internal functionality is controlled by CE, CL, DI and MODE input pins. The MODE pin determines

which of the two control interf ac e m odes is s el ec ted.

Operation using system clock of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided. In Slave

mode selection between clock rates is autom atically controlled. In master mode the master clock to

sam ple rat e rati o i s set by c ont rol bi ts A DCRATE and DA CRATE . ADC and DAC may run at d if ferent

rates and have their own bit clocks and master clock s .

The audio data int erf ac e s upports right, left and I2S i nterface form ats along with a highly flexible DSP

serial port interface.

Product ion Data WM8776

w PD, Rev 4.1, September 2008

AUDIO DATA SAMPLING RATES

In a t ypical digit al audio sys tem there is only one c entral cloc k sour ce produc ing a referenc e clock to

which al l audio data proces s i ng is synchroni s ed. T his c l oc k is oft en r eferred t o as the audi o s ystem’ s

Master Cloc k . The WM8776 uses separate m as t er cloc ks for the ADC and DAC. The external mas t er

system clocks can be applied directly through the ADCMCLK and DACMCLK input pins with no

software configurati on necess ary. In a s ystem where there are a number of poss ible sourc es for the

reference c lock it is recom m ended that t he c lock source with the lowest jitt er be used to optim ise the

performanc e of the ADC and DAC.

The master clock for WM8776 supports DAC and ADC audio sampling rates from 256fs to 768fs,

where fs is the audio sam pling frequency (DACLRC or ADCLRC) typically 32kHz, 44.1kHz, 48kHz or

96kHz (the DAC also supports operation at 128fs and 192fs and 192kHz sample rate). The master

cloc k is us ed to operate the digita l fi lt ers and the noise s haping c irc ui ts .

In Slave mode the WM8776 has a master detection circuit that automatically determines the

relationship between the master clock frequency and the sampling rate (to within +/- 32 system

clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output

level at the las t sampl e. The m aster cl ock sh ould be synchronis ed with ADCLRC/DACLRC for optical

performance, although the WM8776 is tolerant of phase variations or jitter on this clock. Table 6

shows the typical m aster cloc k frequency inputs for the WM8776.

The signal processing for the WM8776 typically operates at an oversampling rate of 128fs for both

ADC and DAC. T he exception to this for the DAC is for operation with a 128/192fs system cloc k, e.g.

for 192kHz operation where the oversampling rate is 64fs. For ADC operation at 96kHz it is

recommended that the user set the ADCOSR bit. This changes the ADC signal processing

oversampl e rate to 64fs.

System Clock Frequency (MHz)

128fs 192fs

SAM PLING

RATE

(DACLRC/

ADCLRC) DAC ONLY

256fs 384fs 512fs 768fs

32kHz 4.096 6.144 8.192 12.288 16.384 24.576

44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688

48kHz 6.144 9.216 12.288 18.432 24.576 36.864

96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable

192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable

Table 6 System Clock Frequencies Versus Sampling Rate

In Master mode DACB CLK, ADCBCLK, DACLRC and ADCLRC are generated by the W M8776. The

frequencies of A DCLRC and DACLRC are s et by sett ing the required ratio of DACMCLK to DACLRC

and ADCMCLK to ADCLRC using the DACRATE and ADCRATE control bits (Table 7).

ADCRATE[2:0]/

DACRATE[2:0] ADCMCLK/DACMCLK:

ADCLRC/DACLRC

RATIO

000 128fs (DAC Only)

001 192fs (DAC Only)

010 256fs

011 384fs

100 512fs

101 768fs

Table 7 Master Mode MCLK:ADCLRC/DACLRC Ratio Select

WM8776 Production Data

w PD, Rev 4.1, September 2008

Table 8 shows the settings for ADCRATE and DACRATE for common sample rates and

ADCMCLK/DACMCLK frequenc ies .

System Clock Frequency (MHz)

128fs 192fs 256fs 384fs 512fs 768fs

SAM PLING

RATE

(DACLRC/

ADCLRC) DACRATE

=000 DACRATE

=001 ADCRATE/

DACRATE

=010

ADCRATE/

DACRATE

=011

ADCRATE/

DACRATE

=100

ADCRATE/

DACRATE

=101

32kHz 4.096 6.144 8.192 12.288 16.384 24.576

44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688

48kHz 6.144 9.216 12.288 18.432 24.576 36.864

96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable

192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable

Table 8 Master Mode ADC/DACLRC Frequency Selection

ADCBCLK and DACBCLK are also generated by the WM8776. The frequency of ADCBCLK and

DACBCLK depends on the mode of operation.

In 128/192fs modes (DACRATE=000 or 001) BCLK = MCLK/2. In 256/384/512fs modes

(ADCRATE/DACRATE=010 or 011 or 100) BCLK = MCLK/4. However if DSP mode is selected as

the audio interface m ode then BCLK=MCLK. Note that DSP m ode cannot be used in 128fs mode for

word lengths greater than 16 bits or in 192fs m ode for word lengths greater than 24 bits .

ZERO DETECT

The W M8776 has a zero detect ci rcuit for each DAC channel, which detects when 1024 consecuti ve

zero samples have been input. The two zero flag outputs (ZFLAGL and ZFLAGR) may be

programmed to output the zero detect signals (see Table 9) that may then be used to control external

muting circuits. A ‘1’ on ZFLAGL or ZFLAGR indicates a zero detect. The zero detect may also be

used to autom atically enable the PGA m ute by setti ng IZD. The zero flag output may be disabled by

setti ng DZFM to 00. The zero flag signal for each DAC channel will only be enabled if it is enabled as

an input to the output summing stage.

DZFM[1:0] ZFLAGL ZFLAGR

00 Zero flag disabled Zero flag disabled

01 Left channel zero Right channel zero

10 Both channel zero Both channel zero

11 Either channels zero Eit her channel zero

Table 9 Zero Flag Output Select

POWERDOWN MODES

The W M8776 has powerdown control bits allowing specific parts of the WM8776 to be powered off

when not being used. The 5-channel input source selector and input buffer may be powered down

using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1l/R to AIN5L/R)

are switched to a buf fered VMIDADC. Control bit ADCPD powers off the ADC and also the ADC input

PGAs. The stereo DAC has a separate powerdown control bit, DACPD allowing the DAC and

analogue output m ixer to be powered off when not in use. This also switches the analogue outputs

VOUTL/R to VMIDDAC to maintain a dc level on the output.

Setting AINPD, ADCPD and DACPD will powerdown everything except the references VMIDADC,

ADCREF and VMIDDAC. These may be powered down by setting PDWN. Setting PDWN will

override all other powerdown control bits. It is recommended that AINPD, HPPD, ADCPD and

DACPD are set before setting PDWN. The default is for all blocks to be enabled other than HPPD.

Product ion Data WM8776

w PD, Rev 4.1, September 2008

DIGITAL AUDIO INTERFACE

MASTER AND SLAVE MODES

The audio int erface operates in either Sl ave or Master mode, s electable using the MS control bit. In

both Master and Sl ave m odes DIN i s al ways an input to the WM8776 and DOUT is always an output.

The default is S lave m ode.

In Slave mode (MS=0) ADCLRC, DACLRC, ADCBCLK and DACBCLK are inputs to the WM8776

(Figure 11). DIN and DACLRC are sampled by the WM8776 on the rising edge of DACBCLK,

ADCLRC is sam pl ed on the r ising edge of A DCBCLK. ADC data i s output on DOUT and changes on

the falling edge of ADCBCLK. By setting control bit BCLKINV the polarity of ADCBCLK and

DACBCLK may be reversed so that DIN and DACLRC are sampled on the falling edge of DACBCLK,

ADCLRC is sampled on the falling edge of ADCBCLK and DOUT changes on the rising edge of

ADCBCLK.

ADCBCLK

DOUT

ADCLRC

DIN

DACLRC

WM8776

CODEC DVD

Controller

DACBCLK

Figure 11 Slave Mode

In Master mode (MS=1) ADCLRC, DACLRC, ADCBCLK and DACBCLK are outputs from the

W M8776 ( Figur e 12). ADCLRC, DACLRC, ADCBCLK and DACBCLK are generated by the W M8776.

DIN is s ampled by the WM8776 on t he rising edge of DACBCLK s o the controller m ust output DAC

data that changes on the falling edge of DACBCLK. ADC data is output on DOUT and changes on

the falling edge of ADCBCLK. By setting control bit BCLKINV, the polarity of ADCBCLK and

DACBCLK may be reversed so that DIN is sampled on the falling edge of DACBCLK and DOUT

changes on the rising edge of ADCBCLK.

ADCBCLK

DOUT

ADCLRC

DIN

DACLRC

WM8776

CODEC

DVD

Controller

DACBCLK

Figure 12 Master Mode

WM8776 Production Data

w PD, Rev 4.1, September 2008

AUDIO INTERFACE FORMATS

Audio data is applied to the internal DAC filters or output from the ADC filt ers, via t he Digital Audio

Interface. 5 popular interface formats are supported:

• Left Jus ti fi ed m ode

• Right Justified mode

• I

2S mode

• DSP mode A

• DSP mode B

All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the

exception of 32 bit right justified mode, which is not supported.

In left justi fi ed, ri ght j us ti fi ed and I2S m odes, the di gi tal audi o i nt erfac e receives DAC data on the DIN

input and out puts ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with

ADCLRC/DACLRC indi cating whether t he left or right c hannel is present. ADCLRC/DACLRC is also

used as a timi ng referenc e to indi c ate the beginn ing or end of the data words.

In left justi fied, right justi fied and I2S modes ; the m inimum num ber of BCLKs per DACLRC/ADCLRC

period is 2 tim es the selected word length. ADCLRC/DACLRC m ust be high for a minimum of word

length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on

ADCLRC/DACLRC is acceptabl e provided the above requirements are met.

In DSP modes A or B, DACLRC is used as a fram e sync signal to ident ify the MSB of the first word.

The minimum number of DACBCLKs per DACLRC period is 2 times the selected word length. Any

mark to space ratio is acceptable on DACLRC provided the rising edge is correctly positioned. The

ADC data may also be output in DSP modes A or B, with ADCLRC used as a frame sync to identify

the MSB of the first word. The minimum number of ADCBCLKs per ADCLRC period is 2 times the

selec ted word length.

LEFT JUSTIFIED MODE

In left justified mode, the MSB of DIN is sampled by the WM8776 on the first rising edge of

DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and

changes on t he s ame fall i ng edge of ADCB CLK as A DCLRC and m ay be s am pl ed on the rising edge

of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right

sam ples (Fi gure 13).

LEFT CHANNEL RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN/

DOUT

1/fs

n321 n-2 n-1

LSBMSB

n321 n-2 n-1

LSBMSB

Figure 13 Left Justified Mode Timing Diagram

Product ion Data WM8776

w PD, Rev 4.1, September 2008

RIGHT JUS TIFIED MODE

In right justified mode, the LSB of DIN is sampled by the WM8776 on the rising edge of DACBCLK

preceding a DACLRC transition. The LSB of the ADC dat a is output on DOUT and changes on the

falling edge of ADCBCLK pr eceding a ADCLRC trans ition and m ay be s ampl ed on the ris ing edge of

ADCBCLK. ADCLRC and DA CLRC are hi gh during the left samples and l ow during the right s am pl es

(Figure 14).

LEFT CHANNEL RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN/

DOUT

1/fs

n321 n-2 n-1

LSBMSB

n321 n-2 n-1

LSBMSB

Figure 14 Right Justified Mode Timing Diagram

I2S MODE

In I2S mode, the MSB of DIN is sampled by the WM8776 on the second rising edge of DACBCLK

following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the

first falling edge of ADCBCLK following an ADCLRC transition and may be sampled on the rising

edge of ADCB CLK. ADCLRC and DACLRC are low during the lef t sampl es and high during the right

samples.

LEFT CHANNEL RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN/

DOUT

1/fs

n321 n-2 n-1

LSB

MSB

n321 n-2 n-1

LSB

MSB

1 BCLK

Figure 15 I2S Mode Timing Diagram

DSP MODE S

In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A)

rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data

imm ediately fol lows lef t channel dat a. Depending on word length, BCLK frequency and sample rat e,

there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

In devic e m aster m ode, the LRC output will resem ble the fram e pulse shown in Figure 16 and Figure

17. In device slave mode, Figure 18 and Figure 19, it is possible to use any length of frame pulse

less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period

before the rising edge of the next frame pulse.

WM8776 Production Data

w PD, Rev 4.1, September 2008

Figure 16 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)

Figure 17 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)

Figure 18 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)

Product ion Data WM8776

w PD, Rev 4.1, September 2008

Figure 19 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave)

CONTROL INTERFACE OPERATION

The WM8776 is controlled by writing to registers through a serial control interface. A control word

consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is

access ed. The remaining 9 bits (B8 to B0) are dat a bits, cor responding to the 9 bi ts in each c ontrol

regist er. The c ontrol interf ace c an operate as eit her a 3-wire or 2-wire MPU interface. T he MODE pin

select s the inter fac e form at , as shown in Table 10. .

MODE Control Mode

0 2 wire interface

1 3 wire interface

Table 10 Control Interface Selection via M ODE Pi n

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

In 3-wire mode, every rising edge of CL clocks in one dat a bit from the DI pin. A rising edge on CE

latches in a complete control word consisting of the last 16 bits. The 3-wire interface protocol is

shown in Figure 20.

Figure 20 3-wire SPI Compatible Interface

1. B[15:9] are Control Addres s Bi ts

2. B[8:0] are Control Data Bits

3. CE is edge sensitive – the data is latched on the rising edge of CE.

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

control register address control register data bits

latch

WM8776 Production Data

w PD, Rev 4.1, September 2008

2-WIRE SERIAL CONTROL MODE

The WM8776 supports software control via a 2-wire serial bus. Many devices can be controlled by

the sam e bus, and each device has a unique 7-bit address (t his is not the sam e as t he 7-bit address

of each register in the WM8776).

The W M8776 operates as a sl ave device only. The contr oller indic ates t he start of data tr ansfer with

a high to low transition on DI while CL remains high. This indi cates that a device address and data

will foll ow. All devices on the 2-wire bus respond to the start condit ion and shift in the next eight bits

on DI (7-bit address + Read/Write bit, MSB fi rst ). If the devic e address rec eived m at c hes the address

of t he WM8776 and the R/W bit is ‘0’ , indi c at ing a write, then the WM8776 responds by pulling DI low

on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’, the WM8776

returns to the idle condition and wait for a new start condition and valid address.

Once t he W M8776 h as ack nowledged a correc t address , t he cont roller sends the first byte of control

data (B15 to B8, i.e. the WM8776 register address plus the first bit of register data). The WM8776

then acknowledges t he first data byte by pulling DI low for one clock puls e. The contr oller then sends

the sec ond byte of c ontrol data (B 7 to B0, i . e. the remai ni ng 8 bit s of r egis t er data), and the WM8776

acknowledges again by pulling DI low.

The transfer of data is complete when there is a low to high transition on DI while CL is high. After

receiving a compl ete address and data s equence the W M8776 retur ns to the idle stat e and waits fo r

another start condition. If a start or stop condition is detected out of sequence at any point during

data transfer (i.e. DI changes while CL is high), the device jumps to the idle condition.

Figure 21 2-wire Serial Interface

1. B[15:9] are Control Addres s Bi ts

2. B[8:0] are Control Data Bits

The WM8776 has two possible device addresses, which can be selected using the CE pin.

CE STATE DEVICE ADDRESS

Low 0011010 (0 x 34h)

High 0011011 (0 x 36h)

Table 11 2-Wi re M P U Interface Address Selection

Product ion Data WM8776

w PD, Rev 4.1, September 2008

CONTRO L INTERFACE REGISTERS

DIG ITAL AUDIO I N TERFACE CO NTROL REGIST ER

Interface format is selected via the FMT[1:0] register bits:

R10 (0Ah)

0001010

DAC Interface Cont rol

1:0 DACFMT

[1:0] 10

R11 (0Bh)

0001011

ADC Interfac e Control

1:0 ADCFMT

[1:0] 10

Interface format Select

00 : right just if ied m ode

01: left justifi ed m ode

10: I2S mode

11: DSP (early or late) mode

In left justified, right justified or I2S modes, the LRP register bit controls the polarity of

ADCLRC/DACLRC. If this bit is set high, the expected polarity of ADCLRC/DACLRC will be the

opposite of that shown Figure 13, Figure 14, etc. Note that if this feature is used as a means of

swapping the l eft and right c hannels, a 1 s am ple phas e dif ference will be introduced. In DSP modes ,

the LRP register bit is used to select between early and late modes.

R10 (0Ah)

0001010

DAC Interface Cont rol

2 DACLRP 0

R11 (0Bh)

0001011

ADC Interfac e Control

2 ADCLRP 0

In left/right/ I2S modes:

ADCLRC/DACLRC Polarity (normal)

0 : normal ADCLRC/DACLRC

polarity

1: inverted ADCLRC/DACLRC

polarity

In DSP mode:

0 : Early DSP mode

1: Late DSP mode

By defaul t, ADCLRC, DACLRC and DIN are sampled on the rising edge of ADCBCLK and DACBCLK

and should ideal l y change on the fall i ng edge. Data s ource s t hat c hange ADCLRC/DACLRC and DIN

on the ris ing edge of A DCBCLK/DACBCLK can be supported by set ting t he BCP regist er bit . Set ting

BCP to 1 inverts the polarity of BCLK to the inverse of that shown in Figure 13, Figure 14, etc.

R10 (0Ah)

0001010

DAC Interface Cont rol

3 DACBCP 0

R11 (0Bh)

0001011

ADC Interfac e Control

3 ADCBCP 0

BCLK Polarity (DSP modes)

0 : normal B CLK polar it y

1: inverted BCLK polar it y

The WL[1:0] bits are used to control the input word length.

R10 (0Ah)

0001010

DAC Interface Cont rol

5:4 DACWL

[1:0] 10

R11 (0Bh)

0001011

ADC Interfac e Control

5:4 ADCWL

[1:0] 10

Word Length

00 : 16 bit data

01: 20 bit data

10: 24 bit data

11: 32 bit data

Note: If 32-bit mode is s elected in right just if i ed m ode, the WM8776 defaults to 24 bits .

In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the

DAC is programm ed to rec eive 16 or 20 bit data, t he W M8776 pads the unus ed LSBs with zeros. If

the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.

Note: In 24 bi t I2S mode, any width of 24 bits or less is supported provided that ADCLRC/DACLRC is

high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs.

WM8776 Production Data

w PD, Rev 4.1, September 2008

W hen operating the A DC digital interfac e in slave mode, to opti mi se the performanc e of the ADC it is

recomm ended that t he ADCMCLK and ADCBCLK input signals do not have coinciding r ising edges .

The ADCMCLK bit provides the option to internally inv ert the ADCMCLK input signal when the input

signals have coinciding rising edges.

R11(0Bh)

0001011

Interfac e Control

6 ADCMCLK 0 ADCMCLK Polarity

0 : non-inverted

1: inverted

A number of options are available to control how data from the Digital Audio Interface is applied to

the DAC.

MASTER MODES

Control bit ADCMS selects between audio interface Master and Slave Modes for ADC. In ADC

Master mode ADCLRC and ADCBCLK are outputs and are generated by the WM8776. In Slave

mode ADCLRC and ADCBCLK are inputs to WM8776.

R12 (0Ch)

0001100

Interfac e Control

9 ADCMS 0 Audio Interface Master/Slave Mode

select for ADC:

0 : Slave Mode

1: Master Mode

Control bit DACMS selects between audio interface Master and Slave Modes for the DAC. In DAC

Master mode DACLRC and DACBCLK are outputs and are generated by the WM8776. In Slave

mode DACLRC and DACBCLK are inputs to WM8776.

R12 (0Ch)

0001100

Interfac e Control

8 DACMS 0 Audio Interface Master/Slave Mode

select for DAC:

0 : Slave Mode

1: Master Mode

MASTER MO DE ADCL RC/DACLRC FR E QU ENCY SE L ECT

In ADC Master mode the WM8776 generates ADCLRC and ADCBCLK, in DAC master mode the

WM8776 generates DACLRC and DACBCLK. These clocks are derived from the master clock

(ADCMCLK or DACMCLK). The ratios of ADCMCLK to ADCLRC and DACMCLK to DACLRC are

set by ADCRATE and DACRATE respectively.

2:0 ADCRATE[2:0] 010 Master Mode MCLK:ADCLRC

ratio select:

010: 256fs

011: 384fs

100: 512fs

101: 768fs

R12 (0Ch)

0001100

ADCLRC and DACLRC

frequency select

6:4 DACRATE[2:0] 010 Master Mode MCLK:DACLRC

ratio select:

000: 128fs

001: 192fs

010: 256fs

011: 384fs

100: 512fs

101: 768fs

Product ion Data WM8776

w PD, Rev 4.1, September 2008

ADC OVERSAMPLING RATE SELECT

For ADC operation at 96kHz it is recomm ended that the user set the ADCOSR bit . This changes the

ADC signal proces s i ng oversample rate to 64fs .

R12 (0Ch)

0001100

ADC Oversam pli ng Rate

3 ADCOSR 0 ADC oversampl ing rate selec t

0: 128x oversampling

1: 64x oversampling

MUTE MODES

Setting MUTE for the DAC will apply a ‘soft’ mute to the input of the digital filters of the channel

muted.

R8 (08h)

0001000

DAC Mute

0 DMUTE 0 DAC Soft Mute select

0 : Normal Operation

1: Soft mut e enabled

Figure 22 Application and Release of Soft Mute

Figure 22 shows the application and release of DMUTE whilst a full amplitude sinusoid is being

played at 48kHz sampling rate. When DMUTE (lower trace) is asserted, the output (upper trace)

begins to decay exponentially from the DC level of the last input sample. The output will decay

towards VMID with a time constant of approximately 64 input samples. If DMUTE is applied to both

channels for 1024 or more i nput sampl es the DAC will be m uted if I ZD is set. W hen DMUTE is de-

asserted, the output will restart immediately from the current input sample.

Note that all other means of muting the DAC: setting the PL[3:0] bits to 0, setting the PDW N bit or

setting attenuation to 0 will cause much more abrupt muting of the output.

-2.5

-2

-1.5

-1

-0.5

0.5

1.5

0 0.001 0.002 0.003 0.004 0.005 0.006

Time(s)

WM8776 Production Data

w PD, Rev 4.1, September 2008

ADC MUTE

Each ADC channel also has an individual mute control bit, which m utes the input to the ADC PGA.

By setting the LRBOTH bit (reg22, bit 8) both channels can be muted simultaneously.

R21 (15h)

0010101

ADC Mute Left

7 MUTELA 0 ADC Mute select

0 : Normal Operation

1: mute ADC left

R21 (15h)

0001111

ADC Mute Right

6 MUTERA 0 ADC Mute select

0 : Normal Operation

1: mute ADC right

DE-EMPHASIS MODE

The De-emphasis filter for the DAC is enabled under the control of DEEMP.

R9 (09h)

0001001

DAC De-emphasis

Control

0 DEEMPH 0 De-emphasis mode select:

0 : Normal Mode

1: De-emphas is Mode

Refer to Figure 35, Figure 36, Figure 37, Figure 38, Figure 39 and Figure 40 for details of the De-

Emphasis m odes at dif fer ent s am pl e rates .

POWERDOWN MODE AND ADC/DAC DISABLE

Setting the PDWN register bit immediately powers down the WM8776, including the references,

overriding all other powerdown control bits. Al l trace of the previous input sampl es is removed, but all

control register sett ings are preserved. W hen PDW N is cleared, the digi tal filt ers will be re-init ialised.

It is recom m ended that t he 5-channel input mux and buff er, A DC and DAC ar e powered down before

setting PDWN.

R13 (0Dh)

0001101

Powerdown Control

0 PDWN 0 Power Down Mode Selec t:

0 : Normal Mode

1: Power Down Mode

The ADC, DAC and HEADPHONE PGA’S may also be powered down by setting the ADCD and

DACD disable bits. Setting ADCD will disable the ADC and select a low power mode. The ADC

digital filters will be reset and will reinitialise when ADCD is reset. The DAC has a separate disable

DACD. Setting DACD will disable the DAC, mixer and output PGAs. Resetting DACD will reinitialise

the digit al fi l ters .

1 ADCPD 0 ADC Powerdown:

0 : Normal Mode

1: Power Down Mode

2 DACPD 0 DAC Powerdown:

0 : Normal Mode

1: Power Down Mode

R13 (0Dh)

0001101

Powerdown Control

3 HPPD 1

Headphone output/PGA Power

down :

0 : HP out enabled

1 : HP out disabled

The analogue audio input s and outp uts c an al s o be indi viduall y powered down by set ti ng the relevant

bits in the powerdown register.

Product ion Data WM8776

w PD, Rev 4.1, September 2008

R13 (0Dh)

0001101

Powerdown Control

6 AINPD 0 Analogue input PGA disable:

0 : Normal Mode

1: Power Down Mode

DIGITAL ATTENUATOR CONTROL MODE

Settin g the A TC regis ter bit caus es the left c hannel attenuati on sett ings to be applied to both left and

right channel DACs from the next audio input sample. No update to the attenuation registers is

required for ATC to take effect.

R7 (07h)

0000111

DAC Channel Control

1 ATC 0 Attenuator Control Mode:

0 : Right channel use Right

attenuation

1: Right Channel use Left

Attenuation

INFINITE ZERO DETECT ENABLE

Settin g t he IZD register bit will enable the internal infinite zero detect func t ion:

R7 (07h)

0000111

DAC Channel Control

2 IZD 0 Infi ni te zero Mute Enable

0 : disable inf ini te zero mut e

1: enable infinite zero Mute

With IZD enabled, applying 1024 consecutive zero input samples to the DAC will cause both DAC

outputs to be m uted. Mute will be removed as soon as any channel recei ves a non-zero input.

DAC OUTPUT CONTROL

The DAC output control word determines how the left and right inputs to the audio Interface are

applied to the left and ri ght DACs:

PL[3:0] Left

Output Right

Output

0000 Mute Mute

0001 Left Mute

0010 Right Mute

0011 (L+R)/2 Mute

0100 Mute Left

0101 Left Left

0110 Right Left

0111 (L+R)/2 Left

1000 Mute Right

1001 Left Right

1010 Right Right

1011 (L+R)/2 Right

1100 Mute (L+R)/2

1101 Left (L+R)/2

1110 Right (L+R)/2

R7 (07h)

0000111

DAC Control

7:4 PL[3:0] 1001

1111 (L+R)/2 (L+R)/2

WM8776 Production Data

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ANALOGUE OUTPUT VOLUME CONTROLS

There are analogue volume controls for the headphone outputs which may be adjusted

independently using separate volume control registers.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

6:0 HPLA[6:0] 1111001

(0dB) Attenuation data for Headphone Left channel in 1dB steps. See

Table 13

7 HPLZCEN 0 Headphone left zero cros s det ect enable

0: zero cross disabled

1: zero cross enabled

R0 (00h)

0000000

Analogue

Attenuation

Headphone

Output Left 8 UPDATE Not latched Controls simultaneous update of Headphone Attenuation Latches

0: Store HPLA in intermediate latch (no change to output)

1: Store HPLA and update att enuati on on both channels .

6:0 HPLA[6:0] 1111001

(0dB) Attenuation data for Headphone Right channel in 1dB steps. See

Table 13

7 HPRZCEN 0 Headphone right zero cross detect enable

0: zero cross disabled

1: zero cross enabled

R1 (01h)

0000001

Analogue

Attenuation

Headphone

Output Right 8 UPDATE Not latched Controls simultaneous update of Headphone Attenuation Latches

0: Store HPRA in int erm ediate latc h (no change to output)

1: Store HPRA and update attenuation on both channels.

6:0 HPMASTA

[6:0] 1111001

(0dB) Attenuation data for both Headphone channels in 1dB steps. See

Table 13

7 MZCEN 0

Master zero cross detec t enable

0: zero cross disabled

1: zero cross enabled

R2 (02h)

0000010

Headphone

Mas te r

Analogue

Attenuation

(both channels) 8 UPDATEA Not latched Controls simultaneous update of Attenuation Latches

0: Store gain in intermediate latch (no change to output)

1: Store gain and update attenuati on on all channel s .

R13 (0Dh)

0001101

Power Down

3 HPPD 1

Headphone output/PG A Power Down

0 : HP out enabled

1 : HP out disabled

Table 12 Headphone Attenuation Register Map

Each analogue headphone output channel has a PGA which can be used to attenuate the output

from that channel. The PGA’s can be powered up or down using the HPPD bit. Attenuation is 0dB by

default but can be set between +6dB and –73dB in 1dB steps using the two Attenuation control

words. The attenuation regis ters are double latched all owing them to be updated in pairs. Setti ng the

UPDATE bi t on an att enuati on writ e t o one c hannel, for example HPO UTL, will c ause the pre-latched

value in HPOUTR to be applied t o the PGA. A master at tenuation register is also i ncluded, allowing

both volume levels to be set to the same value in a single write.

Note: The UPDATE bit is not latched. I f UPDATE=0, the Attenuat ion value will be written t o the pre-

latch but not appli ed t o t he P G A . If UP DAT E=1, pre- lat c hed values will be appl ied fr om the next input

sample. Writing to HPMASTA[6:0] overwrites any values previously sent to HPLA[6:0] and

HPRA[6:0].

HEADPHONE OUT P UT PGA ATTE NUATION

The analogue output PGAs are controlled by the HPLA and HPRA registers. Register bits MASTA

can be used to control att enuation of both channels .

Table 13 shows how the attenuat i on levels are sel ec ted from the 7-bi t words.

Product ion Data WM8776

w PD, Rev 4.1, September 2008

HPLA/ HPRA[6:0] ATTENUATION LEVEL

00(hex) -∞dB (mute)

: :

2F(hex) -∞dB (mute)

30(hex) -73dB

: :

79 (hex) 0dB (default )

: :

7D(hex) +4dB

7E(hex) +5dB

7F(hex) +6dB

Table 13 Headphone Volume Control Attenuation Levels

In additi on a zero c ross detec t c irc uit i s p rovided f or the output P GA volume under the c ontrol of bit 7

(ZCEN) in t he each attenuation r egister. W hen ZCEN is set the attenuation values are only updated

when the input signal to the gain s tage is c lose t o t he analogue ground l evel. T his m ini m ises audibl e

clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which will

generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of

12.288MHz). The timeout clock may be disabled by setting TOD.

R7 (07h)

0000111

Timeout Clock Disable

3 TOD 0

DAC and ADC Analogue Zero

cross detect timeout disable

0 : Tim eout enabled

1: Timeout disabled

DAC DIGITAL VOLUME CONTROL

The DAC volume may also be adjusted in the digital domain using independent digital attenuation

control registers

ADDRESS BIT LABEL DEFAULT DESCRIPTION

7:0 LDA[7:0] 11111111

(0dB) Digital Attenuation data for Left channel DACL in 0.5dB steps. See

Table 14

R3 (03h)

0000011

Digital

Attenuation

DACL

8 UPDATED Not latched Controls simultaneous update of Attenuation Latches

0: Store LDA in intermediate latch (no change to output)

1: Store LDA and update attenuation on both channel s

7:0 RDA[6:0] 11111111

(0dB) Digital Attenuation data for Right channel DACR in 0.5dB steps. See

Table 14

R4 (04h)

0000100

Digital

Attenuation

DACR

8 UPDATED Not latched Controls simultaneous update of Attenuation Latches

0: Store RDA in interm edi ate lat c h (no change to output)

1: Store RDA and update attenuation on both channels.

7:0 MASTDA[7:0] 11111111

(0dB) Digital Attenuation data for DAC channels in 0.5dB steps. See Table

R5 (05h)

0000101

Master

Digital

Attenuation

(both channels)

8 UPDATED Not latched Controls simultaneous update of Attenuation Latches

0: Store gain in intermediate latch (no change to output)

1: Store gain and update attenuati on on channels .

WM8776 Production Data

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L/RDA[7:0] ATTENUATION LEVEL

00(hex) -∞ dB (mute)

01(hex) -127dB

: :

FE(hex) -0.5dB

FF(hex) 0dB

Table 14 Digital Volume Control Attenuation Levels

The digital volume control also incorporates a zero cross detect circuit which detects a transition

through the zero point before updating the digital volume control with the new volume. This is

enabled by control bit DZCEN.

R7 (07h)

0000111

DAC Control

0 DZCEN 0 DAC Digital Volume Zero Cross

Enable:

0: Zero cross detect disabled

1: Zero cross detect enabled

DAC OUTPUT PHASE

The DAC Phase control word determi nes whether the output of the DAC is non-inverted or inverted

Bit DAC Phase

0 DACL 1 = invert

R6 (06h)

0000110

DAC Phase

1:0 PH[1:0] 00

1 DACR 1 = invert

ADC GAIN CONTROL

The ADC has an analogue input PGA and digital gain control for each stereo channel. Both the

analogue and digital gains are adjust ed by the same regis ter, LAG for the left and RAG for the right.

The analogue PGA has a range of +24dB to -21dB in 0.5dB steps. The digital gain control allows

further attenuation (after the ADC) from -21.5dB to -103dB in 0.5dB steps. Table 15 shows how the

regist er maps the analogue and digi tal gains.

LAG/RAG[7:0] ATTENUATION

LEVEL (AT

OUTPUT)

ANAL OGU E PGA DIGIT AL

A TTENUATION

00(hex) -∞ dB (mute) -21dB Digital mute

01(hex) -103dB -21dB -82dB

: : : :

A4(hex) -21.5dB -21dB -0.5dB

A5(hex) -21dB -21dB 0dB

: : : :

CF(hex) 0dB 0dB 0dB

: : : :

FE(hex) +23.5dB +23.5dB 0dB

FF(hex) +24dB +24dB 0dB

Table 15 Analogue and Digital Gain Mapping for ADC

In addition, a zero cross detect circuit is provided for the input PGA, controlled by bit 8 in each

attenuation register. This minimises audible clicks and ‘zipper’ noise by updating the gain when the

signal crosses the zero level.

Product ion Data WM8776

w PD, Rev 4.1, September 2008

In additi on a zero c ross det ect circuit is provided for the output PGA volume under t he c ont rol of bit 7

(ZCEN) in t he each attenuation r egister. W hen ZCEN is set the attenuation values are only updated

when the input signal to the gain s tage is c lose t o t he analogue ground l evel. T his m ini m ises audibl e

clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which will

generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of

12.288MHz). The timeout clock may be disabled by setting TOD.

Left and right inputs m ay also be independently muted. The LRBOTH control bit allows the user to

write the same attenuation value to both left and right volume control registers, saving on software

writes. The ADC volume and mute also applies to the bypass signal path.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

7:0 LAG[7:0] 11001111

(0dB) Attenuation data for Left channel ADC gain in 0.5dB steps. See

Table 15.

R14 (0Eh)

0001110

Attenuation

ADC L 8 ZCLA 0

Left channel ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

7:0 RAG[7:0] 11001111

(0dB) Attenuation data for right c hannel A DC gain in 0.5dB steps . See

Table 15.

R15 (0Fh)

0001111

Attenuation

ADCR 8 ZCRA 0

Right channel ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

R21 (15h)

0010101

ADC Input Mux

8 LRBOTH 0 Right channel input PGA controlled by left channel register

0 : Right channel uses RAG .

1 : Right channel uses LA G.

7 MUTELA 0 Mute for lef t c hannel ADC

0: Mute Off

1: Mute on

R21 (15h)

0010101

ADC Input Mux 6 MUTERA 0 Mute for right channel ADC

0: Mute Off

1: Mute on

ADC HIGHPASS FILTER DISABLE

The ADC digit al fi lters c ontain a di gital high pass f ilter. This def aults t o enabled and can be disabled

using software control bit ADCHPD.

R11 (0Bh)

0001011

ADC Control

8 ADCHPD 0 ADC High pass filter disable:

0: High pass filter enabled

1: High pass filter disabled

WM8776 Production Data

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LIMITER / AUTOMATIC LEVEL CONTROL (ALC)

The WM8776 has an automatic pga gai n control ci rcui t , which can func ti on as a peak l imiter or as an

automatic level control (ALC). In peak limiter mode, a digital peak detector detects when the input

signal goes above a predefined level and will ramp the pga gain down to prevent the signal becoming

too large f or the input range of t he ADC. W hen the signal returns to a level below the threshold, the

pga gain is s lowly returned to i ts star ting level . The peak l im iter c annot inc rease t he pga gain above

its static level.

Figure 23 Limiter Operation

In ALC mode, the circuit aims to keep a constant recording volume irrespective of the input signal

level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC

input rem ains cons tant. A di gital peak detector m onitors the ADC output and changes the PGA gain

if necess ary.

Figure 24 ALC Operation

hold

time decay

time attack

time

input

signal

after

ALC

PGA

gain

ALC

target

level

input

signal

after

PGA

gain

Limiter

threshold

attack

time decay

time

Product ion Data WM8776

w PD, Rev 4.1, September 2008

The gain control circuit is enabled by setting the LCEN control bit. The user can select between

Limiter mode and three different ALC modes using the LCSEL control bits.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R17 (11h)

0010001

ALC Control 2

8 LCE N 0 Enable the PGA gain co ntrol c irc uit .

0 = Disabled

1 = Enabled

R16 (10h)

0010000

ALC Control 1

8:7 LCSEL 00 LC function select

00 = Limiter

01 = ALC Right channel only

10 = ALC Left channel only

11 = ALC Stereo

The lim iter f unction only oper ates in s tereo, which m eans that the peak detect or takes the maxim um

of left and right c hannel peak values, and any new gain setting is applied to both left and right PGAs ,

so that the stereo image is preserved. However, the ALC function can also be enabled on one

channel only. In this case, only one PGA is controlled by the ALC mechanism, while the other

channel runs independently with its PGA gain set through the control register.

W hen enabled, t he threshol d for the limiter or target l evel for t he ALC is program med us ing the LCT

control bits. This allows the threshold/target level to be programmed between -1dB and -16dB in 1dB

steps .

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R16 (10h)

0010000

ALC Control 1

3:0 LCT[3:0] 1011

(-5dB) Li m i ter Thr eshold/ALC target level in

1dB steps .

0000: -16dB FS

0001: -15dB FS

…

1101: -3dB FS

1110: -2dB FS

1111: -1dB FS

ATTACK AND DECAY TIMES

The lim i ter and ALC have di ff erent at tac k and dec ay tim es which determ ine thei r operatio n. However,

the attack and decay times are defined slightly differently for the limiter and for the ALC. DCY and

ATK control the decay and attack times, respectively.

Decay time (Gain Ramp-Up). When in ALC mode, this is defined as the time that it takes for the

PGA gain to ram p up across 90% of it s range (e.g. from –21dB up to +20 dB). W hen in lim iter mode,

it is defined as the time it takes for the gain to ramp up by 6dB.

The decay time can be programmed in power-of-two (2n) steps. For the ALC this gives times from

33.6ms , 67. 2ms, 134. 4ms etc. to 34. 41s. For the lim it er this gives t im es from 1. 2m s, 2. 4m s et c., up

to 1.2288s.

Attack time (Gain Ramp-Down) W hen in A LC mode, thi s is defined as the tim e that it takes f or the

PGA gain to ramp down across 90% of its range (e.g. from +20dB down to -21dB gain). When in

limiter mode, it is defined as the time it takes for the gain to ramp down by 6dB.

The attac k tim e can be programm ed in power-of-two (2n) st eps, from 8.4ms , 16.8m s, 33 .6ms et c. to

8.6s for the ALC and from 250us, 500us, etc. up to 256ms.

The time it takes for the recording level to return to its target value or static gain value therefore

depends on bot h the attac k/decay ti m e and on the gain adjustment required. If the gain adjus t m ent is

small, it will be shorter than the attack/decay time.

WM8776 Production Data

w PD, Rev 4.1, September 2008

ADDRESS BIT LABEL DEFAULT DESCRIPTION

LC attack (gain ramp-down) time 3:0 ATK[3:0] 0010 ALC mode

0000: 8.4ms

0001: 16.8ms

0010: 33.6ms …

(time doubles with

every step)

1010 or higher:

8.6s

Limiter Mode

0000: 250us

0001: 500us… 0010:

1ms

(time doubles with

every step)

1010 or higher: 256ms

LC decay (gain ramp-up) time

R18 (12h)

0010010

ALC

Control 3

7:4 DCY [3:0] 0011 ALC mode

0000: 33.5ms

0001: 67.2ms

0010: 134.4ms

….(time doubles for

every step)

1010 or higher:

34.3ms

Limiter mode

0000: 1.2ms

0001: 2.4ms

0010: 4.8ms ….( ti m e

doubles for every

step)

1010 or higher:

1.2288s

TRANSIENT WINDOW (LIMITER ONLY)

To prevent the lim iter responding to to short durat ion high ampitude signal s (such as hand-claps in a

live performance), the limiter has a programmable transient window preventing it responding to

signals above the t hreshold unti l their duration exceeds the window period. The T ransient window is

set in register TRANWIN.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R20 (14h)

0010100

Limi ter Control

6:4 TRANWIN

[2:0] 010 Length of Transient Window

000: 0us (disabled)

001: 62.5us

010: 125us

…..

111: 4ms

ZERO CR OSS

The PGA has a zero c ross det ector to prevent g ain changes introducing noise to the signal. In ALC

mode the register bit ALCZC allows this to be turned off if desired.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R17 (11h)

0010001

ALC Control 2

7 ALCZC 0

(disabled) P G A zero cros s enable

0 : disabled

1: enabled

Product ion Data WM8776

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MAXIMUM GAIN (ALC ONLY) AND MAXIMUM ATTENUATION

To prevent low level signals being amplified too much by the ALC, the MAXGAIN register sets the

upper limit for the gain. This prevents low level noise being over-amplified. The MAXGAIN register

has no effect on the limiter operat ion.

The MAXATTEN register has different operation for the limiter and for the ALC. For the limiter it

defines the maximum attenuation below t he static (user programm ed) gain. For the ALC, it defines

the lower limit for the gain.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R16 (10h)

0010000

ALC Control 1

6:4 MAXGAIN 111

(+24dB) Set maximum gain for the PGA (ALC

only)

111 : +24dB

110 : +20dB

…..(-4dB s teps )

010 : +4dB

001 : 0dB

000 : 0dB

Maximum att enuat ion of PG A R20 (14h)

0010100

Limi ter Control

3:0 MAXATTEN 0110 Limiter

(attenuation

below static)

0011 or lower:

-3dB

0100: -4dB

…. (-1dB steps)

1100 or higher:

-12dB

ALC (lower PGA

gain limi t)

1010 or lower:

-1dB

1011 : -5dB

….. (-4dB steps)

1110 : -17dB

1111 : -21dB

HOLD TIME (ALC ONLY)

The A LC also has a hold ti me, which is the ti me del ay between the peak l evel detected being below

target and the P G A gai n beginni ng to ramp up. It c an be programmed in power-of-two (2n) steps, e.g.

2.67ms , 5.33m s , 10. 67m s etc . up to 43.7m s . A lt ernativel y, t he hol d t ime can al s o be s et to zero. T he

hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the

signal l evel is above tar get.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R17 (11h)

0010001

ALC Control 2

3:0 HLD[3:0] 0000 ALC hold time before gain is

increased.

0000: 0ms

0001: 2.67ms

0010: 5.33ms

… (time doubles with every step)

1111: 43.691s

OVERLOAD DETECTOR (ALC ON LY)

To prevent c l ippi ng when a l arge s ignal o c curs jus t af ter a period of quiet, t he A LC c i rc uit inc ludes an

overload detector. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is

ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below

87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.

(Note: If AT K = 0000, then the overload detector makes no diff erence to the operation of the ALC. It

is designed to prevent clippi ng when long attack ti m es are us ed).

WM8776 Production Data

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NOISE GATE (ALC ONLY)

When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise

pumping” , i.e. loud hiss ing nois e during si lence peri ods. The WM8776 has a nois e gate funct ion t hat

prevents noise pumping by comparing the signal level at the AINL1/2/3/4/5 and/or AINR1/2/3/4/5 pins

against a noise gate thr eshold, NGTH. The noise gate cuts in when:

• Signal level at ADC [dB] < NGTH [dB] + PG A gain [dB ] + Mic B oos t gain [dB ]

This is equivalent to:

• Signal level at input pin [dB] < NGTH [dB]

W hen the noise gate is trigger ed, the P GA gain is held cons tant (preventing it f rom ram ping up as it

would normally when the signal is quiet).

The table below summarises the noise gate control register. The NGTH control bits set the noise

gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps.

Levels at t he extrem es of t he r ange may c aus e inappropriate operation, s o c ar e sho uld be tak en with

set–up of the func tion. Note that the noise gate only works in conjuncti on with the ALC f unction, and

always operates on the same channel(s) as the ALC (left, right, both, or none).

ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 NGAT 0 Noise gate funct ion enable

1 = enable

0 = disable

R19 (13h)

0010011

Noi se Ga te

Control 4:2 NGTH[2:0] 000 Noise gate thres hold (with respec t to

ADC output level)

000: -78dBFS

001: -72dBfs

… 6 dB steps

110: -42dBFS

111: -36dBFS

Product ion Data WM8776

w PD, Rev 4.1, September 2008

ADC INP UT MIX ER AND POW E RDOWN CON TROL

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R21 (15h)

0010101

ADC Input Mux

4:0 AMX[4:0] 00001

ADC left channel input m i xer

control bits (see T able 16)

R13 (0Dh)

0001101

Powerdown Control

6 AINPD 0

Input mux and buffer powerdown

0: Input mux and buffer

enabled

1: Input mux and buffer

powered dow n

AIN1. One bit of AMX is alloc ated to each stereo input pair to allow the signals to be mixed before

being digitised by the ADC. For example, if AMX[4:0] is 00101, the input signal to the ADC will be

(AIN1L+AIN3L) on the left channel and (AIN1R+AIN3R) on the right channel.

However if the analogue input buffer is powered down, by setting AINPD, then all 5-channel mixer

inputs are switched to buffered VMIDADC.

AMX[4:0] LEFT ADC INPUT

RIGH T ADC INPU T

00001 AIN1L AIN1R

00010 AIN2L AIN2R

00100 AIN3L AIN3R

01000 AIN4L AIN4R

10000 AIN5L AIN5R

Table 16 ADC Input Mixer

AIN1L/R

AIN2L/R

AIN3L/R

AIN4L/R

AIN5L/R

AMX[0]

AMX[1]

AMX[2]

AMX[3]

AMX[4]

Figure 25 ADC Input Mixer

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OUTPUT SELECT AND ENABLE CONTROL

and an input select switch for each input allowing each signal to be output individually or summed

with other signals and output on the analogue output. The default for the output is DAC playback

only. VOUT may be selected to output DAC playback, AUX, analogue bypass or a sum of these

using t he out put s ele c t c ontr ols MX[2:0]. For exampl e, to s elec t s um of DAC and AUX, set MX[2:0] to

011.

The output mixer is powered down with DACD.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R22 (16h)

0010110

Output Mux

2:0 MX[2:0] 001

(DAC playback) VOUT Output select (see Figure 26)

Figur e 26 MX[2:0] Output Select

SOFTWARE REGISTER RESET

W riting any value to register 0010111 will caus e a regist er reset , resetti ng all register bi ts to

their default values.

Product ion Data WM8776

w PD, Rev 4.1, September 2008

REGI STER MAP

The c om plete register map i s s hown below. The det ai led des c ripti on can be found in the relevant text

of t he devic e des cription. The WM8776 can be configured using the Contr ol Int erf ac e. A ll unused bit s

should be set to ‘0’.

B8 B7 B6 B5 B4 B3 B2 B1 B0

DEFAULT

(HEX)

R0 (00h) 0 0 0 0 0 0 0 UPDATE HPLZCEN HPLA[6:0] 079

R1 (01h) 0 0 0 0 0 0 1 UPDATE HPRZCEN HPRA[6:0] 079

R2 (02h) 0 0 0 0 0 1 0 UPDATEA HPMZCEN HPMASTA[6:0] 079

R3 (03h) 0 0 0 0 0 1 1

PDATED LDA[7:0] 0FF

R4 (04h) 0 0 0 0 1 0 0

PDATED RDA[7:0] 0FF

R5 (05h) 0 0 0 0 1 0 1

PDATED MASTDA 0FF

R6 (06h) 0 0 0 0 1 1 0 0 0 0 0 0 0 0 PHASE[1:0] 000

R7 (07h) 0 0 0 0 1 1 1 0 PL[3:0] TOD IZD ATC DZCEN 090

R8 (08h) 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 DMUTE 000

R9 (09h) 0 0 0 1 0 0 1 0 0 0 0 0 0 DZFM [1:0] DEEMPH 000

R10 (0Ah) 0 0 0 1 0 1 0 0 0 0 DACWL[1:0] DACBCP

DACLRP DACFMT[1:0] 022

R11 (0Bh) 0 0 0 1 0 1 1 ADCHPD 0 ADCMCLK ADCWL[1:0] ADCBCP

ADCLRP ADCFMT[1:0] 022

R12 (0Ch) 0 0 0 1 1 0 0 ADCMS DACMS DACRATE[2:0] ADCOSR ADCRATE[2:0] 022

R13 (ODh)

0 0 0 1 1 0 1 0 0 AINPD 0 0 HPPD DACPD ADCPD PDWN 008

R14 (0Eh) 0 0 0 1 1 1 0 ZCLA LAG[7:0] 0CF

R15 (0 F h) 0 0 0 1 1 1 1 ZCRA RAG[7:0] 0CF

R16 (10h) 0 0 1 0 0 0 0 LCSEL[1:0] MAXGAIN[2:0] LCT[3:0] 07B

R17 (11h) 0 0 1 0 0 0 1 LCEN ALCZC 0 0 0 HLD[3:0] 000

R18 (12h) 0 0 1 0 0 1 0 FDECAY DCY[3:0] ATK[3:0] 032

R19 (13h) 0 0 1 0 0 1 1 0 0 0 0 NGTH[2:0] 0 NGAT 000

R20 (14h) 0 0 1 0 1 0 0 0 1 TRANWIN[2:0] MAXATTEN[3:0] 0A6

R21 (15h) 0 0 1 0 1 0 1 LRBOTH MUTELA MUTERA 0 AMX[4:0] 001

R22 (16h) 0 0 1 0 1 1 0 0 0 0 MX[2:0] 001

R23 (17h) 0 0 1 0 1 1 1 SOFTWARE RESET not reset

WM8776 Production Data

w PD, Rev 4.1, September 2008

ADDRESS BIT LABEL DEFAULT DESCRIPTION

6:0 HPLA[6:0] 1111001

(0dB) At tenuat ion data for HEADPHONE lef t c hannel in 1dB st eps .

7 HPLZCEN 0

Left HEADPHONE zero cross detect enable

0: zero cross disabled

1: zero cross enabled

R0 (00h)

0000000

Headphone

Analogue

Attenuation

Headphone

Left 8 UPDATE Not latched

Controls simultaneous update of all Attenuation Latches

0: Store HPLA in inter m ediate latch (no change to output)

1: Store HPLA and update attenuation on all channels.

6:0 HPRA[6:0] 1111001

(0dB) At tenuat ion data for Headphone right channel in 1dB st eps .

7 HPRZCEN 0

Right Headphone zero cross detect enable

0: zero cross disabled

1: zero cross enabled

R1 (01h)

0000001

Headphone

Analogue

Attenuation

Headphone

Right 8 UPDATE Not latched

Controls simultaneous update of all Attenuation Latches

0: Store HPRA in int erm ediate latch (no change to output )

1: Store HPRA and update attenuation on all channels.

6:0 HPMASTA[6:0] 1111001

(0dB) At tenuat ion data for all ANALO GUE gains (L and R channels) in

1dB steps .

7 MZCEN 0

Master zero cross detec t enable

0: zero cross disabled

1: zero cross enabled

R2 (02h)

0000010

Headphone

aster A nalogue

Attenuation

(All Channels)

8 UPDATEA Not latched

Controls simultaneous update of all Attenuation Latches

0: Store gains in intermediate latch (no change to output)

1: Store gains and update attenuati on on all c hannel s.

7:0 LDA1[7:0] 11111111

(0dB) Digital Attenuation data for Left channel DACL in 0.5dB steps.

R3 (03h)

0000011

Digital

Attenuation

DACL 8 UPDATED Not latched

Controls simultaneous update of all Attenuation Latches

0: Store LDA1 in intermediate latch (no change to output)

1: Store LDA1 and update attenuati on on all channels

7:0 RDA1[6:0] 11111111

(0dB) Digit al At t enuati on data for Right channel DACR in 0.5dB s teps.

R4 (04h)

0000100

Digital

Attenuation

DACR 8 UPDATED Not latched

Controls simultaneous update of all Attenuation Latches

0: Store RDA1 in interm edi ate lat c h (no change to output)

1: Store RDA1 and update attenuation on all channels.

7:0 MASTDA[7:0] 11111111

(0dB) Digit al A tt enuati on data for all DAC channels in 0.5dB st eps.

R5 (05h)

0000101

Master

Digital

Attenuation

(All Channels

8 UPDATED Not latched

Controls simultaneous update of all Attenuation Latches

0: Store gain in intermediate latch (no change to output)

1: Store gain and update attenuati on on all channels.

Product ion Data WM8776

w PD, Rev 4.1, September 2008

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R6 (06h)

0000110

Phase S waps

1:0 PHASE 00

Controls phase of DAC outputs (LEFT, RIGHT channel)

0: Sets non inverted output phas e

1: inverts phase of DAC output

0 DZCEN 0

DAC Digital Vol ume Zero Cross Enable:

0: Zero Cross detect disabl ed

1: Zero Cross detect enabled

1 ATC 0

Attenuator Control

0: All DACs use attenuations as programmed.

1: Right DAC uses left DAC attenuations

2 IZD 0

Infini te zero detect ion c irc ui t contr ol and autom ut e co ntrol

0: Infinite zero detect automute disabled

1: Infinit e zero detect automute enabled

3 TOD

DAC and ADC Analogue Zero cross detect timeout disable

0 : Tim eout enabled

1: Timeout disabled

DAC Output Control

PL[3:0] Left

Output Right

Output PL[3:0] Left

Output Right

Output

0000 Mute Mute 1000 Mute Right

0001 Left Mute 1001 Left Right

0010 Right Mute 1010 Right Right

0011 (L+R)/2 Mute 1011 (L+R)/2 Right

0100 Mute Left 1100 Mute (L+R)/2

0101 Left Left 1101 Left (L+R)/2

0110 Right Left 1110 Right (L+R)/2

R7 (07h)

0000111

DAC Control

7:4 PL[3:0] 1001

0111 (L+R)/2 Left 1111 (L+R)/2 (L+R)/2

R8 (08h)

0001000

DAC Mute

0 DMUTE 0

DAC channel soft mute enables:

0: mute disabled

1: mute enabled

0 DEEMPH 0 De-emphasis mode select:

0 : Normal Mode

1: De-emphasi s Mode

DZFM ZFLAG1 ZFLAG2

R9 (09h)

0001001

DA C Co ntr o l 2:1 DZFM 00

disabled

left chan nels zero

both channels zero

either channel zero

disabled

right channels zero

both channels zero

either channel zero

WM8776 Production Data

w PD, Rev 4.1, September 2008

ADDRESS BIT LABEL DEFAULT DESCRIPTION

1:0 DACFMT[1:0] 10 DAC Interface format select

00: right justified mode

01: left justified mode

10: I2S mode

11: DSP mode

DACLRC Polarity or DSP Early/Late m ode s elec t 2 DACLRP 0

Left Jus t ified / Right Justifi ed /

I2S

0: Standard DACLRC Polarit y

1: Inverted DACLRC Polarity

DSP Mode

0: Early Mode

1: Late Mode

3 DACBCP 0 DAC BITCLK Polarity

0: Normal – DIN and DACLRC sampled on rising edge of

DACBCLK.

1: Inverted - DIN and DACLRC sampled on falling edge of

DACBCLK.

R10 (0Ah)

0001010

DAC Interface

Control

5:4 DACW L[ 1:0] 10 DA C Input Word Length

00: 16-bit Mode

01: 20-bit Mode

10: 24-bit Mode

11: 32-bit Mode (not supported in right justi fi ed m ode)

1:0 ADCFMT[1:0] 10 ADC Interface format select

00: right justified mode

01: left justified mode

10: I2S mode

11: DSP mode

ADCLRC Polarity or DSP Early/Late m ode s el ect 2 ADCLRP 0

Left Jus t ified / Right Justifi ed /

I2S

0: Standard ADCLRC Polarit y

1: Inverted ADCLRC Polarity

DSP Mode

0: Early Mode

1: Late Mode

3 ADCBCP 0 ADC BITCLK Polarity

0: Normal - ADCLRC sampled on risi ng edge of

ADCBCLK; DOUT changes on fall ing edge of ADCBCLK.

1: Inverted - ADCLRC sampled on falling edge of

ADCBCLK; DOUT changes on rising edge of ADCBCLK.

5:4 ADCW L[ 1:0] 10 A DC Input Word Length

00: 16-bit Mode

01: 20-bit Mode

10: 24-bit Mode

11: 32-bit Mode (not supported in right justi fi ed m ode)

6 ADCMCLK 0 ADCMCLK Polarity:

0: non-inverted

1: inverted

R11 (0Bh)

0001011

ADC Interface

Control

8 ADCHPD 0 ADC Highpass Filter Disable:

0: Highpass Filter enabled

1: Highpass Filter disabled

Product ion Data WM8776

w PD, Rev 4.1, September 2008

ADDRESS BIT LABEL DEFAULT DESCRIPTION

2:0 ADCRATE[2:0] 010 Mast er Mode ADCMCLK:ADCLRC ratio select:

010: 256fs

011: 384fs

100: 512fs

3 ADCOSR 0 ADC oversample rate select

0: 128x oversampling

1: 64x oversapmling

6:4 DACRATE[2:0] 010 Mast er Mode DACMCLK:DACLRC ratio select:

000: 128fs

001: 192fs

010: 256fs

011: 384fs

100: 512fs

7 DACMS 0 DAC Maser/Slave interface mode select

0: Slave Mode – DACLRC and DACBCLK are inputs

1: Master Mode –DACLRC and DACBCLK are outputs

R12 (0Ch)

0001100

Master Mode

Control

8 ADCMS 0 ADC Maser/Slave interface mode select

0: Slave Mode – ADCLRC and ADCBCLK are inputs

1: Master Mode – ADCLRC and ADCBCLK are outputs

0 PDW N 0 Chip Powerdown Control (works in tandem with ADCD and

DACD): 0: All circ uits runni ng, output s are acti ve

1: All c i rcui ts in power save mode, outputs muted

1 ADCPD 0 ADC powerdown:

0: ADC enabled

1: ADC disabled

2 DACPD 0 DAC powerdown

0: DAC enabled

1: DAC disabled

3 HPP D 1 Headphone Output/ P GA ’s powerdown

0: Headphone out enabled

1: Headphone out disabled

R13 (0Dh)

0001101

PWR Down

Control

6 AINPD 0 AINPD powerdown

0: ANALOGUE INPUT enabled

1: ANALOGUE INPUT disabled

7:0 LAG[7:0] 11001111

(0dB) At tenuat ion data for left ch annel ADC gain in 0.5dB s teps.

00000000 : digital m ute

00000001 : -103dB

………..

11001111 : 0dB

…………

11111110 : +23.5dB

11111111 : +24dB

R14 (0Eh)

0001110

Attenuation

ADCL

8 ZCLA 0

Left ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

WM8776 Production Data

w PD, Rev 4.1, September 2008

ADDRESS BIT LABEL DEFAULT DESCRIPTION

7:0 RAG[7:0] 11001111

(0dB) Attenuation data for right channel ADC gain in 0.5dB steps.

00000000 : digital m ute

00000001 : -103dB

………..

11001111 : 0dB

…………

11111110 : +23.5dB

11111111 : +24dB

R15 (0Fh)

0001111

Attenuation

ADCR

8 ZCRA 0 Right ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

3:0 LCT[3:0] 1011

(-5dB) Lim i t er thres hold/ ALC tar get level in 1dB step s

0000: -16dB FS

0001: -15dB FS

…

1101: -3dB FS

1110: -2dB FS

1111: -1dB FS

6:4 MAXGAIN[2:0] 111

(+24dB) Set Maximum Gain of PGA

111 : +24dB

110 : +20dB

….(-4dB steps)

010 : +4dB

001 : 0dB

000 : 0dB

R16 (10h)

0010000

ALC Control 1

8:7 LCSEL[1:0] 00

(Limiter) ALC/Limiter func t ion select

00 = Limit er

01 = ALC Right channel only

10 = ALC Left channel only

11 = ALC Stereo (PGA register s unus ed)

3:0 HLD[3:0] 0000

(OFF) ALC hold time before gain is increased.

0000: OFF

0001: 2.67ms

0010: 5.33ms

… (time doubles with every step)

1111: 43.691s

7 ALCZC 0 (zero

cross off) ALC uses zero cross detection circuit.

R17 (11h)

0010001

ALC Control 2

8 LCEN 0 Enable Gain control circuit.

0 = Disable

1 = Enable

Product ion Data WM8776

w PD, Rev 4.1, September 2008

ADDRESS BIT LABEL DEFAULT DESCRIPTION

ALC/Limiter att ack (gain ram p-down) time 3:0 ATK[3:0] 0010

(33ms/1ms) ALC mode

0000: 8.4ms

0001: 16.8ms

0010: 33.6ms…

(time doubles with every step)

1010 or higher: 8.6s

Limiter Mode

0000: 250us

0001: 500us…

0010: 1ms

(time doubles with every step)

1010 or higher: 256ms

ALC/Limiter decay (gain ramp up) time

R18 (12h)

0011000

ALC Control 3

7:4 DCY[3:0] 0011

(268ms/

9.6ms) ALC mode

0000: 33.5ms

0001: 67.2ms

0010: 134.4ms ….(time

doubles for every step)

1010 or higher: 34.3ms

Limiter mode

0000: 1.2ms

0001: 2.4ms

0010: 4.8ms ….( ti m e doubles

for every step)

1010 or higher: 1.2288s

0 NGAT 0 Noise gate enable (ALC only)

0 : disabled

1 : enabled

R19 (13h)

0010011

Noise Gate

Control 4:2 NGTH [2:0] 000 Noise gate threshold

000: -78dBFS

001: -72dBfs

… 6 dB steps

110: -42dBFS

111: -36dBFS

Maximum attenuat ion of P GA 3:0 MAXATTEN

[3:0] 0110 Lim i t er (attenuati on below

static)

0011 or lower: -3dB

0100: -4dB

…. (-1dB steps )

1100 or higher: -12dB

ALC (lower PGA gain lim it )

1010 or lower: -1dB

1011 : -5dB

….. (-4dB steps )

1110 : -17dB

1111 : -21dB

R20 (14h)

0010100

Limiter

Control

6:4 TRANWIN [2:0] 010 Length of Transient Window

000: 0us (disabled)

001: 62.5us

010: 125us

…..

111: 4ms

4:0 AMX[4:0] 00001 ADC left channel input mixer control bit

AMX[4:0] A DC LEFT IN ADC RIGHT IN

00001 AIN1L AIN1R

00010 AIN2L AIN2L

00100 AIN3L AIN3R

01000 AIN4L AIN4R

10000 AIN5L AIN5R

6 MUTERA 0

Mute for right channel ADC

0: Mute off

1: Mute on

R21 (15h)

0010101

ADC Mux

Control

7 MUTELA 0

Mute for left channel ADC

0: Mute off

1: Mute on

WM8776 Production Data

w PD, Rev 4.1, September 2008

ADDRESS BIT LABEL DEFAULT DESCRIPTION

8 LRBOTH 0

Right channel i nput PGA cont roll ed by left c hannel regist er

0 : Right channel uses RAG and MUTERA.

1 : Right channel us es LAG and MUTELA.

R22 (16h)

0010110

Output Mux

2:0 MX[2:0] 001 VOUT Output sel ect (Anal ogue ByPas s Enabl e / Dis abl e)

001: DAC

010: AUX

100: BYPASS

R23 (17h)

0010111

Software

Reset

[8:0] RES ET Not res et Writing to this regis t er will apply a reset to the device regis t ers.

Product ion Data WM8776

w PD, Rev 4.1, September 2008

DIGITAL FILTER CHARACTERISTICS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC Fi lter

±0.01 dB 0 0.4535fs

Passband -6dB 0.5fs

Pass band ripple ±0.01 dB

Stopband 0.5465fs

Stopband Attenuation f > 0.5465fs - 65 dB

Group Delay 22 fs

DAC Filter

±0.05 dB 0.454fs

Passband -3dB 0.4892 fs

Pass band ripple ±0.05 dB

Stopband 0.546fs

Stopband Attenuation f > 0.546fs -60 dB

Group Delay 19 fs

Table 17 Digital Filter Characteristics

DAC FI LTER RESPONSES

-120

-100

-80

-60

-40

-20

0 0.5 1 1.5 2 2.5 3

Frequency (Fs )

Response (dB)

Figure 27 DAC Digital F ilter Frequency Response – 44.1, 48

and 96kHz

-80

-70

-60

-50

-40

-30

-20

-10

0.4 0.45 0.5 0.55 0.6

Frequency (Fs)

Response (dB)

Figure 28 DAC Digital Fi lter Transition Band – 44.1, 48 and

96kHz

WM8776 Production Data

w PD, Rev 4.1, September 2008

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

0 0.1 0.2 0.3 0.4 0.5

F requency (Fs)

Response (dB)

Figure 29 DAC Digital Filter Ripple – 44.1, 48 and 96kHz

-80

-60

-40

-20

0 0.2 0.4 0.6 0.8 1

Response (dB)

Frequency (Fs)

Figure 30 DAC Digital Filter Frequency Response –

192kHz

-1

-0.8

-0.6

-0.4

-0.2

0.2

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Response (dB)

Frequency (Fs)

Figure 31 DAC Digi tal filter Ripp le - 192kHz

ADC FI LTER RESPONSES

-80

-60

-40

-20

0 0.5 1 1.5 2 2.5 3

Response (dB)

Frequency (Fs)

Figure 32 ADC Digital Filter Frequency Response

-0.02

-0.015

-0.01

-0.005

0.005

0.01

0.015

0.02

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Response (dB)

Frequency (Fs)

Figure 33 ADC Digital Filter Ripple

Product ion Data WM8776

w PD, Rev 4.1, September 2008

ADC HIGH PASS FILTER

The WM8776 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the

following polynomial.

Figure 34 ADC Highpass Filter Response

1 - z

-1

1 - 0.9 995z

-1

H(z) =

-15

-10

-5

0 0.0005 0.001 0.0015 0.002

Response (dB)

Frequency (Fs)

WM8776 Production Data

w PD, Rev 4.1, September 2008

DIGITAL DE-EMPHASIS CHARACTERISTICS

-10

-8

-6

-4

-2

0 2 4 6 8 10 12 14 16

Response (dB)

Frequency (kHz)

Figure 35 De-Emphasis Frequency Response (32kHz)

-3

-2.5

-2

-1.5

-1

-0.5

0.5

0 2 4 6 8 10 12 14 16

Response (dB)

Frequency (kHz)

Figure 36 De-Emphasis Error (32KHz)

-10

-8

-6

-4

-2

0 5 10 15 20

Response (dB)

Frequency (kHz)

Figure 37 De-Emphasis Frequency Response (44.1KHz)

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0 5 10 15 20

Response (dB)

Frequency (kHz)

Figure 38 De-Emphasis Error (44.1KHz)

-10

-8

-6

-4

-2

0 5 10 15 20

Response (dB)

Frequency (kHz)

Figure 39 De-Emphasis Frequency Response (48kHz)

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 5 10 15 20

Response (dB)

Frequency (kHz)

Figure 40 De-Emphasis Error (48kHz)

Product ion Data WM8776

w PD, Rev 4.1, September 2008

APPLICATIONS INFORMATION

EXTERNAL CIRCUIT CONFIGURATION

In order t o allow the use of 2V rms and larger inputs to the A DC and AUX inputs, a struct ure is used

that uses external resistors to drop these larger voltages. This also increases the robus tness of the

circui t to external abus e s uch as ESD pul ses. Fi gure 41 shows t he ADC input mul tiplexor c ircuit with

external components allowing 2Vrms inputs to be applied.

AIN1L

10K10uF

AIN2L

10K10uF

AIN3L

10K10uF

AIN4L

10K10uF

AIN5L

10K10uF

AIN1R

10K10uF

AIN2R

10K10uF

AIN3R

10K10uF

AIN4R

10K10uF

AIN5R

10K10uF

SOURCE

SELECTOR

INPUTS

AINVGR

AINOPR

AINVGL

AINOPL

Figure 41 ADC Input Multiplexor Configuration

10K

MX[0]

MX[1]

MX[2]

10K

DACL/R

BYPASSL/R

AUXL/R

10uF

AUX input

Figure 42 5.1 Channel Input Multiplexor Configuration

WM8776 Production Data

w PD, Rev 4.1, September 2008

RECOMMENDED EXTERNAL COMPONENTS

Figure 43 External Component Diagram

Product ion Data WM8776

w PD, Rev 4.1, September 2008

It is recom mended that a low pass filter be applied to the output from the DAC for hi-fi applications.

Typically a second order filter is suitable and provides sufficient attenuation of high frequency

components (the unique low order, high bit count multi-bit sigma delta DAC structure used in

WM8776 produces much less high frequency output noise). This filter is typically also used to

provide the 2x gain needed to provide the standard 2Vrms output level from most consumer

equipment . F igure 44 sh ows a s uitable pos t DAC fil ter circui t, with 2x gain. A lternative inver ting filt er

architectures might also be used with as good results.

+VS

-VS

10uF 51

Ω

7.5K

Ω

680pF

1.8k

Ω

10k

Ω

4.7k

Ω

4.7k

Ω

1.0nF

Figure 44 Recommended Post DAC Filter Circuit

WM8776 Production Data

w PD, Rev 4.1, September 2008

PACKAGE DIMENSIONS

NOTES:

A. ALL LINEAR DIMENSIONS ARE IN M ILLIMETERS.

B. THI S DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

C. BODY DIM ENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSI O N, NOT TO EXCE ED 0.25 MM.

D. ME E TS JE DE C. 95 MS-026, VARIATION = ABC. REFE R TO THIS SPECI FICA TION FOR FURTHER DETA ILS.

DM004.C

FT: 48 PIN TQFP (7 x 7 x 1.0 mm)

Symbols Dimensions

(mm)

MIN NOM MAX

A----- ----- 1.20

A10.05 ----- 0.15

A20.95 1.00 1.05

b0.17 0.22 0.27

c0.09 ----- 0.20

D9.00 BSC

D17.00 BSC

E9.00 BSC

E17.00 BSC

e0.50 BSC

L0.45 0.60 0.75

Θ0o3.5o7o

Tolerances of Form and Position

ccc 0.08

REF: JEDEC.95 , MS- 0 26

2536

121

E1 E

2437

AA2 A1

SEA TING PLA NE

ccc C

-C-

Product ion Data WM8776

w PD, Rev 4.1, September 2008

IMPORTANT NOTI CE

W olfson Microel ectronics plc (“W olfson”) product s and services are sold s ubject to Wolf son’s term s and conditi ons of s ale,

delivery and payment supplied at the time of order acknowledgement.

W olfson warrants per formance of i ts products to the spec ifications in effect at the date of shipment. Wolf son reserves the

right to make changes to its products and specifi cat ions or to discon tinue any product or service without noti ce. Custom ers

should therefore obtain the l ates t version of relevant inform at ion fr om Wol fs on to verify that the info rmat i on is current .

Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.

Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.

In order to minimise risks associated with customer applications, the customer must use adequate design and operating

safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer

product desi gn. T he c ustom er is s olely respons ibl e for it s s elec tion and use of W olf son products . W ol fson i s not liable for

such selec t ion or us e nor for use of any circui tr y other than circ ui try entir ely embodi ed in a Wolfson product.

Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where

malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.

Any use of products by the customer for such purposes is at the customer’s own risk.

Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other

intellec tual property ri ght of W olfson cover ing or relating to any combinati on, machine, or process in which its products or

services might be or are used. Any provision or publication of any third party’s products or services does not constitute

Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document

belong to the respecti ve third party owner.

Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is

accom panied by al l ass ociated copyright, proprietary and other notices (incl uding this noti ce) and conditi ons. W olfson is

not liable for any unauthorised alteration of such information or for any reliance placed thereon.

Any representati ons made, warranties given, and/or liabili ties accepted by any person which differ from those contained in

this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or

accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any

reliance plac ed thereon by any person.

ADDRESS:

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W es t fi eld Hous e

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Edinburgh

EH11 2QB

United Kingdom

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Emai l :: sal es @wolfs onmicro.c om