Si4704/05-D50 B ROADCAST F M R ADIO R ECEIVER FOR C ON SUMER E LECTRONICS Features Worldwide FM band support (64-108 MHz) RDS/RBDS decoding engine (Si4705 only) Lowest power consumption Received signal quality indicators On-chip tuned resonance for embedded antenna support Multipath detection and mitigation FM Hi-cut control Advanced FM stereo-mono blend Advanced audio processing Not EN 55020 compliant* Automatic gain control (AGC) Integrated FM LNA Image-rejection mixer Frequency synthesizer with integrated VCO Low-IF direct conversion with no external ceramic filters 2.7 to 5.5 V supply voltage Dual 1.8 and 2.7 V power supplies Stereo audio out I2S Digital audio out 20-pin 3 x 3 mm QFN package Pb-free/RoHS compliant Ordering Information: See page 27. Pin Assignments Si4704/05-GM *Note: *For consumer electronics applications that require EN 55020 compliance, use Si4704/05-D60. NC 1 20 19 18 17 16 FMI 2 15 DOUT RFGND 3 Description Functional Block Diagram Si4704/05 FM Antenna ADC FMI PGA ADC RSSI AFC Rev. 1.0 12/10 DAC ROUT CONTROL INTERFACE XTAL OSC GPO 13 ROUT 7 8 9 SEN SDIO RCLK 12 GND 6 SCLK RST 5 10 11 VA This product, its features, and/or its architecture is covered by one or more of the following patents, as well as other patents, pending and issued, both foreign and domestic: 7,127,217; 7,272,373; 7,272,375; 7,321,324; 7,355,476; 7,426,376; 7,471,940; 7,339,503; 7,339,504. DCLK DOUT DFS VD 1.62-3.6 V REG RDS (Si4705) RST VA SEN 2.7-5.5 V 0/90 SDIO 32.768 kHz (TYP) RCLK LOUT AGC SCLK LPI DAC DSP DIGITAL INTERFACE RFGND LNA 14 LOUT GND PAD LPI 4 The Si4704/05-D50 FM/RDS/RDBS receivers provide the highest performance and lowest power consumption available for portable devices today. The 100% CMOS IC integrates the complete FM and data receiver function from antenna to analog or digital audio and data out in a single 3 x 3 mm 20-pin QFN. DFS Personal navigation devices (PND) GPS-enabled handsets and portable devices GPO3/DCLK Cellular handsets Portable media devices Dedicated data receiver GPO2/INT VD NC Applications GPO1 (Top View) Copyright (c) 2010 by Silicon Laboratories Si4704/05-D50 Si4704/05-D50 2 Rev. 1.0 Si4704/05-D50 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.3. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6. Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.8. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.9. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.10. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.11. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.12. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.13. Embedded Antenna Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.14. RDS Decoder (Si4705 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.15. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.16. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.17. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.18. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.19. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. Pin Descriptions: Si4704/05-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8. Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1. Si4704 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.2. Si4705 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9. Package Outline: Si4704/05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10. PCB Land Pattern: Si4704/05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document Change List: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Rev. 1.0 3 Si4704/05-D50 1. Electrical Specifications Table 1. Recommended Operating Conditions* Parameter Symbol Test Condition Min Typ Max Unit Analog Supply Voltage VA 2.7 -- 5.5 V Digital and Interface Supply Voltage VD 1.62 -- 3.6 V Analog Power Supply Powerup Rise Time VARISE 10 -- -- s Digital Power Supply Powerup Rise Time VDRISE 10 -- -- s TA -20 25 85 C Ambient Temperature *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at VA = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless otherwise stated. Table 2. Absolute Maximum Ratings1,2 Parameter Symbol Value Unit Analog Supply Voltage VA -0.5 to 5.8 V Digital and Interface Supply Voltage VD -0.5 to 3.9 V Current3 IIN 10 mA Input Voltage3 VIN -0.3 to (VIO + 0.3) V Operating Temperature TOP -40 to 95 C Storage Temperature TSTG -55 to 150 C 0.4 VpK Input RF Input Level4 Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si4704/05 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV HBM. Handling and assembly of these devices should only be done at ESD-protected workstations. 3. For input pins DFS, SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, GPO3, and DCLK. 4. At RF input pins FMI and LPI. 4 Rev. 1.0 Si4704/05-D50 Table 3. DC Characteristics (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = -20 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit -- 7.5 9.7 mA FM Receiver to Line Output VA Supply Current IFMVA VD Supply Current IFMVD Digital Output Mode1 -- 8.5 11.1 mA VD Supply Current IFMVD Analog Output Mode -- 8.4 11.1 mA -- 4 15 A -- 3 10 A Powerdown and Interface VA Powerdown Current IDDPD VD Powerdown Current IIOPD SCLK, RCLK inactive High Level Input Voltage2 VIH 0.7 x VD -- VD + 0.3 V 2 VIL -0.3 -- 0.3 x VD V High Level Input Current2 IIH VIN = VD = 3.6 V -10 -- 10 A 2 IIL VIN = 0 V, VD = 3.6 V -10 -- 10 A High Level Output Voltage3 VOH IOUT = 500 A 0.8 x VD -- -- V 3 VOL IOUT = -500 A -- -- 0.2 x VD V Low Level Input Voltage Low Level Input Current Low Level Output Voltage Notes: 1. Guaranteed by characterization. 2. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3. 3. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3. Rev. 1.0 5 Si4704/05-D50 Table 4. Reset Timing Characteristics1,2,3 (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = -20 to 85 C) Parameter Symbol Min Typ Max Unit RST Pulse Width and GPO1, GPO2/INT Setup to RST tSRST 100 -- -- s GPO1, GPO2/INT Hold from RST tHRST 30 -- -- ns Important Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. 4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is high impedance, then minimum tSRST is 100 s to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and GPO2 low. tSRST RST 70% GPO1 70% GPO2 70% tHRST 30% 30% 30% Figure 1. Reset Timing Parameters for Busmode Select Method 6 Rev. 1.0 Si4704/05-D50 Table 5. 2-Wire Control Interface Characteristics1,2,3 (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = -20 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fSCL 0 -- 400 kHz SCLK Low Time tLOW 1.3 -- -- s SCLK High Time tHIGH 0.6 -- -- s SCLK Input to SDIO Setup (START) tSU:STA 0.6 -- -- s SCLK Input to SDIO Hold (START) tHD:STA 0.6 -- -- s SDIO Input to SCLK Setup tSU:DAT 100 -- -- ns SDIO Input to SCLK Hold 4, 5 tHD:DAT 0 -- 900 ns SCLK Input to SDIO Setup (STOP) tSU:STO 0.6 -- -- s STOP to START Time tBUF 1.3 -- -- s SDIO Output Fall Time tf:OUT -- 250 ns -- 300 ns Cb 20 + 0.1 ----------1pF SDIO Input, SCLK Rise/Fall Time tf:IN tr:IN Cb 20 + 0.1 ----------1pF SCLK, SDIO Capacitive Loading Cb -- -- 50 pF Input Filter Pulse Suppression tSP -- -- 50 ns Notes: 1. When VD = 0 V, SCLK and SDIO are low impedance. 2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si4704/05 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum tHD:DAT specification. 5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 kHz, tHD:DAT may be violated as long as all other timing parameters are met. Rev. 1.0 7 Si4704/05-D50 SCLK 70% SDIO 70% tSU:STA tHD:STA tLOW START tr:IN tHIGH tr:IN tf:IN tSP tSU:STO tBUF 30% 30% tf:IN, tf:OUT tHD:DAT tSU:DAT STOP START Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, R/W SDIO START ADDRESS + R/W D7-D0 ACK DATA D7-D0 ACK DATA ACK Figure 3. 2-Wire Control Interface Read and Write Timing Diagram 8 Rev. 1.0 STOP Si4704/05-D50 Table 6. 3-Wire Control Interface Characteristics (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = -20 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fCLK 0 -- 2.5 MHz SCLK High Time tHIGH 25 -- -- ns SCLK Low Time tLOW 25 -- -- ns tS 20 -- -- ns SDIO Input to SCLK Hold tHSDIO 10 -- -- ns SEN Input to SCLK Hold tHSEN 10 -- -- ns SCLK to SDIO Output Valid tCDV Read 2 -- 25 ns SCLK to SDIO Output High Z tCDZ Read 2 -- 25 ns SCLK, SEN, SDIO, Rise/Fall Time tR, tF -- -- 10 ns SDIO Input, SEN to SCLK Setup SCLK 70% 30% tR tF tHSDIO tS SEN 70% SDIO 70% tHIGH tLOW tHSEN tS 30% A7 30% A6-A5, R/W, A4-A1 A0 D15 D14-D1 Address In D0 Data In Figure 4. 3-Wire Control Interface Write Timing Parameters SCLK 70% SEN 70% 30% tHSDIO tS tCDV tHSEN tCDZ tS 30% 70% SDIO A7 30% A6-A5, R/W, A4-A1 Address In A0 D15 1/2 Cycle Bus Turnaround D14-D1 D0 Data Out Figure 5. 3-Wire Control Interface Read Timing Parameters Rev. 1.0 9 Si4704/05-D50 Table 7. Digital Audio Interface Characteristics (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = -20 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit DCLK Cycle Time tDCT 26 -- 1000 ns DCLK Pulse Width High tDCH 10 -- -- ns DCLK Pulse Width Low tDCL 10 -- -- ns DFS Setup Time to DCLK Rising Edge tSU:DFS 5 -- -- ns DFS Hold Time from DCLK Rising Edge tHD:DFS 5 -- -- ns tPD:DOUT 0 -- 12 ns DOUT Propagation Delay from DCLK Falling Edge tDCH tDCL DCLK tDCT DFS tHD:DFS tSU:DFS DOUT tPD:OUT Figure 6. Digital Audio Interface Timing Parameters, I2S Mode 10 Rev. 1.0 Si4704/05-D50 Table 8. FM Receiver Characteristics1,2 (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = -20 to 85 C, 76-108 MHz) Parameter Symbol Min Typ Max Unit 76 -- 108 MHz (S+N)/N = 26 dB -- 2.2 3.5 V EMF f = 2 kHz, RDS BLER < 5% -- 11 -- V EMF 3 4 5 k 4 5 6 pF 100 105 -- dBV EMF m = 0.3 40 50 -- dB Adjacent Channel Selectivity 200 kHz 35 50 -- dB Alternate Channel Selectivity 400 kHz 60 70 -- dB In-band 35 -- -- dB 72 80 90 mVRMS -- -- 1 dB Input Frequency fRF Sensitivity3,4,5 RDS Test Condition Sensitivity6 LNA Input Resistance6,7 6,7 LNA Input Capacitance Input IP36,8 AM Suppression3,4,6,7 Spurious Response Rejection6 3,4,7 Audio Output Voltage 3,7,9 Audio Output L/R Imbalance Audio Frequency Response Low6 -3 dB -- -- 30 Hz Audio Frequency Response High6 -3 dB 15 -- -- kHz 35 42 -- dB 55 63 -- dB -- 58 -- dB -- 0.1 0.5 % FM_DEEMPHASIS = 2 70 75 80 s FM_DEEMPHASIS = 1 45 50 54 s f = 400 kHz -- 34 -- dBV f = 4 MHz -- 30 -- dBV Audio Stereo Separation Audio Mono 7,9 S/N3,4,5,7 Audio Stereo S/N4,5,6,7 Audio THD3,7,9 6 De-emphasis Time Constant 3,4,5,6,12,13 Blocking Sensitivity Notes: 1. Additional testing information is available in "AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure." Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in "AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines." Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 s de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 - f1| > 2 MHz, f0 = 2 x f1 - f2. AGC is disabled. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. Analog audio output mode. 12. Blocker Amplitude = 100 dBV 13. Sensitivity measured at (S+N)/N = 26 dB. 14. At temperature (25C). Rev. 1.0 11 Si4704/05-D50 Table 8. FM Receiver Characteristics1,2 (Continued) (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = -20 to 85 C, 76-108 MHz) Parameter Symbol Test Condition Min Typ Max Unit f = 400 kHz, 800 kHz -- 40 -- dBV f = 4 MHz, 8 MHz -- 35 -- dBV RL Single-ended 10 -- -- k CL Single-ended -- -- 50 pF RCLK tolerance = 100 ppm -- -- 60 ms/channel From powerdown -- -- 110 ms Input levels of 8 and 60 dBV at RF Input -3 -- 3 dB Intermod Sensitivity3,4,5,6,12,13 Audio Output Load Resistance6,10 Audio Output Load Capacitance6,10 Seek/Tune Time6 Powerup Time6 14 RSSI Offset Notes: 1. Additional testing information is available in "AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure." Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in "AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines." Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 s de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 - f1| > 2 MHz, f0 = 2 x f1 - f2. AGC is disabled. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. Analog audio output mode. 12. Blocker Amplitude = 100 dBV 13. Sensitivity measured at (S+N)/N = 26 dB. 14. At temperature (25C). 12 Rev. 1.0 Si4704/05-D50 Table 9. 64-75.9 MHz Input Frequency FM Receiver Characteristics1,2,6 (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = -20 to 85 C) Parameter Symbol Min Typ Max Unit 64 -- 75.9 MHz -- 3.5 -- V EMF 3 4 5 k 4 5 6 pF -- 105 -- dBV EMF m = 0.3 -- 50 -- dB Adjacent Channel Selectivity 200 kHz -- 50 -- dB Alternate Channel Selectivity 400 kHz -- 70 -- dB Audio Output Voltage3,4,7 72 80 90 mVRMS Audio Output L/R Imbalance3,7,9 -- -- 1 dB Input Frequency fRF Sensitivity3,4,5 LNA Input Test Condition (S+N)/N = 26 dB Resistance7 7 LNA Input Capacitance Input IP3 8 AM Suppression3,4,7 Audio Frequency Response Low -3 dB -- -- 30 Hz Audio Frequency Response High -3 dB 15 -- -- kHz Audio Mono S/N3,4,5,7,10 -- 63 -- dB Audio THD3,7,9 -- 0.1 -- % FM_DEEMPHASIS = 2 70 75 80 s FM_DEEMPHASIS = 1 45 50 54 s De-emphasis Time Constant Audio Output Load Resistance10 RL Single-ended 10 -- -- k Audio Output Load Capacitance10 CL Single-ended -- -- 50 pF RCLK tolerance = 100 ppm -- -- 60 ms/channel From powerdown -- -- 110 ms Input levels of 8 and 60 dBV EMF -3 -- 3 dB Seek/Tune Time Powerup Time 11 RSSI Offset Notes: 1. Additional testing information is available in "AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure." Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in "AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines." Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 s de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 - f1| > 2 MHz, f0 = 2 x f1 - f2. AGC is disabled. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. At temperature (25 C). Rev. 1.0 13 Si4704/05-D50 Table 10. Reference Clock and Crystal Characteristics (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = -20 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit 31.130 32.768 40,000 kHz -100 -- 100 ppm 1 -- 4095 31.130 32.768 34.406 kHz -- 32.768 -- kHz -100 -- 100 ppm -- -- 3.5 pF Reference Clock RCLK Supported Frequencies1,2 1,3 RCLK Frequency Tolerance REFCLK_PRESCALE1,2 REFCLK 1 Crystal Oscillator Crystal Oscillator Frequency 1 Crystal Frequency Tolerance1,3 Board Capacitance 1 ESR 40 k CL Single-ended 12 pF Notes: 1. Guaranteed by characterization. 2. The Si4704/05 divide the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. See "AN332: Si47xx Programming Guide," Table 6 for more details. 3. A frequency tolerance of 50 ppm is required for FM seek/tune using 50 kHz channel spacing. 14 Rev. 1.0 Si4704/05-D50 2. Typical Application Schematic Optional: Digital Audio Out OPMODE: 0xB0, 0xB5 C9 GPO1 GPO2/INT R3 GPO3/DCLK 16 17 GND D50 6 VA 15 14 LOUT 13 ROUT 12 2.7 to 5.5 V 11 VA VD C1 10 RSTB DOUT DFS 18 GPO3/DCLK 19 GPO2/INT Si4704/05 LPI SENB 5 LOUT ROUT RCLK 4 DFS R1 DOUT RFGND 9 Embedded Antenna FMI SDIO 3 NC 8 2 SCLK C2 7 1 FM Antenna GPO1 NC 20 R2 1.62 to 3.6 V C4 RSTB VD RCLK SDIO SCLK 1 2 SENB GPO3 RCLK X1 C5 C6 Optional: For Crystal OSC Notes: 1. Place C1 close to VA pin. 2. Pins 1 and 20 are no connects, leave floating. 3. Place C4 close to DFS pin. 4. To ensure proper operation and receiver performance, follow the guidelines in "AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines." Silicon Laboratories will evaluate schematics and layouts for qualified customers. 5. Pin 2 or Pin 4 connects to the FM antenna interface. Pin 2 is for a half-wave antenna. Pin 4 is for an embedded antenna. 6. Place Si4704/05 as close as possible to antenna jack and keep the FMI and LPI traces as short as possible. Rev. 1.0 15 Si4704/05-D50 3. Bill of Materials Table 11. Si4704/05-D50 Bill of Materials Component(s) Supplier C1 Supply bypass capacitor, 22 nF, 20%, Z5U/X7R Murata C2 Coupling capacitor, 1 nF, 20%, Z5U/X7R Murata C4 Supply bypass capacitor, 100 nF, 10%, Z5U/X7R Murata U1 Si4704/05 FM Radio Tuner Silicon Laboratories R1 Resistor, 600 (Optional for digital audio) Venkel R2 Resistor, 2 k (Optional for digital audio) Venkel R3 Resistor, 2 k (Optional for digital audio) Venkel Crystal load capacitors, 22 pF, 5%, COG (Optional for crystal oscillator option) Venkel C9 Noise mitigating capacitor, 2~5 pF (Optional for digital audio) Murata X1 32.768 kHz crystal (Optional for crystal oscillator option) Epson C5, C6 16 Value/Description Rev. 1.0 Si4704/05-D50 4. Functional Description 4.1. Overview Si4704/05 FM Antenna ADC FMI LNA PGA 0/90 RSSI AFC GPO DCLK DOUT DFS VD 1.62-3.6 V CONTROL INTERFACE XTAL OSC RST REG RDS (Si4705) SDIO VA SEN 2.7-5.5 V ROUT AGC SCLK 32.768 kHz (TYP) RCLK DAC DSP ADC LPI LOUT DIGITAL INTERFACE RFGND DAC Figure 7. Functional Block Diagram The Si4704/05-D50 offers advanced audio processing plus advanced RDS processing in a very small, 100% CMOS receiver integrated circuit. The device provides both analog and digital audio out, and a highly flexible RDS pre-processor and 100 block RDS buffer. It is an ideal product for handsets and portable devices seeking to optimize both sound and data receiver performance. For sound, the advanced audio processing is unprecedented in portable devices. For RDS data applications such as song-tagging, meta-data, traffic message channel, or other open data applications, the advanced and patented R(B)DS decoding engine offers outstanding data synchronization and integrity. The RDS engine includes demodulation, symbol decoding, advanced error correction, detailed visibility to blockerror rates (BLER), advanced decoder reliability, and synchronization status. The Si4704/05 provides complete, decoded and error-corrected RDS groups (100 blocks), up to 25 groups at a time. The Si4704/05 offers several modes of operation for various applications which require more or less visibility to the RDS status and group data. *Note: The term "RDS" will be used to mean "RDS/RBDS" throughout the document. The Si4704/05 receiver draws on Silicon Laboratories' broadcast audio expertise and patent portfolio, using a digital low intermediate frequency (low-IF) receiver architecture proven by hundreds of millions of Silicon Laboratories' broadcast audio receivers shipped worldwide. Silicon Labs has shipped 1/2 billion broadcast audio receivers worldwide using this architecture. The low-IF architecture allows the Si4704/05 to deliver superior performance while integrating the great majority of external components required by competing solutions. The Si4704/05 digital integration reduces the required external components of traditional offerings, resulting in a solution requiring only an external bypass capacitor and occupying board space of approximately 15 mm2. The Si4704/05 is the first FM radio receiver IC to support embedded antenna technology, allowing the FM antenna to be integrated into the enclosure or PCB of a portable device. Refer to "AN383: Si47xx Antenna, Schematic, Layout, And Design Guidelines" for antenna design guidelines. The Si4704/05 is feature-rich, providing highly automated performance with default settings and extensive programmability and flexibility for customized system performance. Rev. 1.0 17 Si4704/05-D50 The Si4704/05 performs much of the FM demodulation digitally to achieve high fidelity, optimal performance versus power consumption, and flexibility of design. The on-board DSP provides unmatched pilot rejection, selectivity, and optimum sound quality. The integrated micro-controller offers both the manufacturer and the end-user unmatched programmability and flexibility in the listening experience. 4.2. FM Receiver The Si4704/05 FM receiver is based on the proven Si4700/01/02/03/04/05 FM radio receiver. The part leverages Silicon Laboratories' proven and patented FM broadcast radio receiver digital architecture, delivering excellent RF performance and interference rejection. The proven digital techniques provide good sensitivity in weak signal environments while allowing superb selectivity and inter-modulation immunity in strong signal environments. The part supports the worldwide FM broadcast band (64 to 108 MHz) with channel spacings of 50-200 kHz. The low-IF architecture utilizes a single converter stage and digitizes the signal using a high-resolution analog-todigital converter. The audio output can be directed either to an external headphone amplifier via analog in/out or to other system ICs through digital audio interface (I2S) (Si4705 only). 4.3. Stereo Audio Processing Modulation Level The output of the FM demodulator is a stereo multiplexed (MPX) signal. The MPX standard was developed in 1961, and is used worldwide. Today's MPX signal format consists of left + right (L+R) audio, left - right (L-R) audio, a 19 kHz pilot tone, and RDS/RBDS data as shown in Figure 8. Mono Audio Left + Right 0 Stereo Pilot 15 19 23 Stereo Audio Left - Right 38 Frequency (kHz) Figure 8. MPX Signal Spectrum 18 RDS/ RBDS 53 57 4.3.1. Stereo Decoder The Si4704/05 integrated stereo decoder automatically decodes the MPX signal using DSP techniques. The 0 to 15 kHz (L+R) signal is the mono output of the FM tuner. Stereo is generated from the (L+R), (L-R), and a 19 kHz pilot tone. The pilot tone is used as a reference to recover the (L-R) signal. Output left and right channels are obtained by adding and subtracting the (L+R) and (L-R) signals, respectively. 4.3.2. Stereo-Mono Blending Adaptive noise suppression is employed to gradually combine the stereo left and right audio channels to a mono (L+R) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. Three metrics, received signal strength indicator (RSSI), signal-to-noise ratio (SNR), and multipath interference, are monitored simultaneously in forcing a blend from stereo to mono. The metric which reflects the minimum signal quality takes precedence and the signal is blended appropriately. All three metrics have programmable stereo/mono thresholds and attack/release rates detailed in "AN332: Si47xx Programming Guide." If a metric falls below its mono threshold, the signal is blended from stereo to full mono. If all metrics are above their respective stereo thresholds, then no action is taken to blend the signal. If a metric falls between its mono and stereo thresholds, then the signal is blended to the level proportional to the metric's value between its mono and stereo thresholds, with an associated attack and release rate. Stereo/mono status can be monitored with the FM_RSQ_STATUS command. 4.4. Received Signal Qualifiers The quality of a tuned signal can vary depending on many factors including environmental conditions, time of day, and position of the antenna. To adequately manage the audio output and avoid unpleasant audible effects to the end-user, the Si4704/05-D50 monitors and provides indicators of the signal quality, allowing the host processor to perform additional processing if required by the customer. The Si4704/05-D50 monitors signal quality metrics including RSSI, SNR, and multipath interference on FM signals. These metrics are used to optimize signal processing and are also reported to the host processor. The signal processing algorithms can use either Silicon Labs' optimized settings (recommended) or be customized to modify performance. Rev. 1.0 Si4704/05-D50 4.5. De-emphasis 4.10. Tuning Pre-emphasis and de-emphasis is a technique used by FM broadcasters to improve the signal-to-noise ratio of FM receivers by reducing the effects of high-frequency interference and noise. When the FM signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. The Si4704/05 incorporates a de-emphasis filter that attenuates high frequencies to restore a flat frequency response. Two time constants are used in various regions. The deemphasis time constant is programmable to 50 or 75 s and is set by the FM_DEEMPHASIS property. The frequency synthesizer uses Silicon Laboratories' proven technology, including a completely integrated VCO. The frequency synthesizer generates the quadrature local oscillator signal used to downconvert the RF input to a low intermediate frequency. The VCO frequency is locked to the reference clock and adjusted with an automatic frequency control (AFC) servo loop during reception. The tuning frequency can be directly programmed using the FM_TUNE_FREQ. The Si4704/05 supports channel spacing of 50, 100, or 200 kHz in FM mode. 4.6. Volume Control 4.11. Seek The audio output may be muted. Volume is adjusted digitally by the RX_VOLUME property. The Si4704/05 seek functionality is performed completely on-chip and will search up or down the selected frequency band for a valid channel. A valid channel is qualified according to a series of programmable signal indicators and thresholds. The seek function can be made to stop at the band edge and provide an interrupt, or wrap the band and continue seeking until arriving at the original departure frequency. The device sets interrupts with found valid stations or, if the seek results in zero found valid stations, the device indicates failure and again sets an interrupt.(Refer to "AN332: Si47xx Programming Guide". The Si4704/05-D50 uses RSSI, SNR, and AFC to qualify stations. Most of these variables have programmable thresholds for modifying the seek function according to customer needs. 4.7. Stereo DAC High-fidelity stereo digital-to-analog converters (DACs) drive analog audio signals onto the LOUT and ROUT pins. The audio output may be muted. Volume is adjusted digitally with the RX_VOLUME property. 4.8. Soft Mute The soft mute feature is available to attenuate the audio outputs and minimize audible noise in very weak signal conditions. The soft mute feature is triggered by the SNR metric. The SNR threshold for activating soft mute is programmable, as are soft mute attenuation levels and attack and release rates. 4.9. FM Hi-Cut Control Hi-cut control is employed on audio outputs with degradation of the signal due to low SNR and/or multipath interference. Two metrics, SNR and multipath interference, are monitored concurrently in forcing hi-cut of the audio outputs. Programmable minimum and maximum thresholds are available for both metrics. The transition frequency for hi-cut is also programmable with up to seven hi-cut filter settings. A single set of attack and release rates for hi-cut are programmable for both metrics from a range of 2 ms to 64 s. The level of hi-cut applied can be monitored with the FM_RSQ_STATUS command. Hi-cut can be disabled by setting the hi-cut filter to audio bandwidth of 15 kHz. RSSI is employed first to screen all possible candidate stations. SNR and AFC are subsequently used in screening the RSSI qualified stations. The more thresholds the system engages, the higher the confidence that any found stations will indeed be valid broadcast stations. The Si4704/05-D50 defaults set RSSI to a mid-level threshold and add an SNR threshold set to a level delivering acceptable audio performance. This trade-off will eliminate very low RSSI stations while keeping the seek time to acceptable levels. Generally, the time to auto-scan and store valid channels for an entire FM band with all thresholds engaged is very short depending on the band content. Seek is initiated using the FM_SEEK_START command. The RSSI, SNR, and AFC threshold settings are adjustable using properties. Rev. 1.0 19 Si4704/05-D50 4.12. Digital Audio Interface 4.12.2. Audio Sample Rates The digital audio interface operates in slave mode and supports a variety of MSB-first audio data formats including I2S and left-justified modes. The interface has three pins: digital data input (DIN), digital frame synchronization input (DFS), and a digital bit synchronization input clock (DCLK). The Si4705 supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 kHz. The digital audio interface enables low-power operation by eliminating the need for redundant DACs and ADCs on the audio baseband processor. The device supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 kHz. The digital audio interface enables low-power operation by eliminating the need for redundant DACs on the audio baseband processor. 4.12.1. Audio Data Formats The digital audio interface operates in slave mode and supports three different audio data formats: I2S Left-Justified DSP Mode In I2S mode, by default the MSB is captured on the second rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB. The left channel is transferred first when the DFS is low, and the right channel is transferred when the DFS is high. In left-justified mode, by default the MSB is captured on the first rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB. The left channel is transferred first when the DFS is high, and the right channel is transferred when the DFS is low. In DSP mode, the DFS becomes a pulse with a width of 1DCLK period. The left channel is transferred first, followed right away by the right channel. There are two options in transferring the digital audio data in DSP mode: the MSB of the left channel can be transferred on the first rising edge of DCLK following the DFS pulse or on the second rising edge. In all audio formats, depending on the word size, DCLK frequency, and sample rates, there may be unused DCLK cycles after the LSB of each word before the next DFS transition and MSB of the next word. In addition, if preferred, the user can configure the MSB to be captured on the falling edge of DCLK via properties. The number of audio bits can be configured for 8, 16, 20, or 24 bits. 20 Rev. 1.0 Si4704/05-D50 (OFALL = 1) INVERTED DCLK (OFALL = 0) DCLK LEFT CHANNEL DFS I2S (OMODE = 0000) RIGHT CHANNEL 1 DCLK 1 DCLK 1 DOUT 2 n-2 3 n-1 MSB n 1 LSB MSB 2 n-2 3 n-1 n LSB Figure 9. I2S Digital Audio Format (OFALL = 1) INVERTED DCLK (OFALL = 0) DCLK DFS LEFT CHANNEL RIGHT CHANNEL Left-Justified (OMODE = 0110) 1 DOUT 2 3 n-2 n-1 MSB n 1 LSB MSB 2 n-2 3 n-1 n LSB Figure 10. Left-Justified Digital Audio Format (OFALL = 0) DCLK DFS RIGHT CHANNEL LEFT CHANNEL (OMODE = 1100) DOUT (MSB at 1st rising edge) 1 2 3 n-2 n-1 MSB DOUT (MSB at 2nd rising edge) 1 LSB MSB n-1 n 1 LSB MSB 2 n-2 3 1 2 3 n-2 MSB n-1 n LSB LEFT CHANNEL 1 DCLK (OMODE = 1000) n RIGHT CHANNEL 2 3 n-2 n-1 n LSB Figure 11. DSP Digital Audio Format Rev. 1.0 21 Si4704/05-D50 4.13. Embedded Antenna Support 4.14. RDS Decoder (Si4705 Only) The Si4704/05 is the first FM receiver to support the fast growing trend to integrate the FM receiver antenna into the device enclosure. The chip is designed with this function in mind from the outset, with multiple international patents pending, thus it is superior to many other options in price, board space, and performance. The Si4705 implements an RDS processor for symbol decoding, block synchronization, error detection, and error correction. The Si4705 device is user configurable and provides an optional interrupt when RDS is synchronized, loses synchronization, and/or the user configurable RDS FIFO threshold has been met. The Si4705 reports RDS decoder synchronization status and detailed bit errors in the information word for each RDS block with the FM_RDS_STATUS command. The range of reportable block errors is 0, 1-2, 3-5, or 6+. More than six errors indicates that the corresponding block information word contains six or more non-correctable errors or that the block checkword contains errors. Testing indicates that, when using Silicon Laboratories' patented techniques, embedded antenna performance can be very similar in many key metrics to a standard half-wavelength antenna. Refer to "AN383: Si47XX Antenna, Schematic, Layout, And Design Guidelines" for additional details on the implementation of support for an embedded antenna. Figure 12 shows a conceptual block diagram of the Si4704/05 architecture used to support the embedded antenna. The half-wavelength FM receive antenna is therefore optional. Host software can detect the presence of an external antenna and switch between the embedded antenna if desired. Si4704/05 Half-wavelength antenna FMI Integrated antenna LNA LPI RFGND AGC Figure 12. Conceptual Block Diagram of the Si4704/05 Embedded Antenna Support 4.15. Reference Clock The Si4704/05 reference clock is programmable, supporting RCLK frequencies in Table 10. Refer to Table 3, "DC Characteristics" on page 5 for switching voltage levels and Table 10, "Reference Clock and Crystal Characteristics" on page 14 for frequency tolerance information. An onboard crystal oscillator is available to generate the 32.768 kHz reference when an external crystal and load capacitors are provided. Refer to "2. Typical Application Schematic" on page 15. This mode is enabled using the POWER_UP command. Refer to Refer to "AN332: Si47xx Programming Guide". The Si4704/05 performance may be affected by data activity on the SDIO bus when using the integrated internal oscillator. SDIO activity results from polling the tuner for status or communicating with other devices that share the SDIO bus. If there is SDIO bus activity while the Si4704/05 is performing the seek/tune function, the crystal oscillator may experience jitter, which may result in mistunes, false stops, and/or lower SNR. For best seek/tune results, Silicon Laboratories recommends that all SDIO data traffic be suspended during Si4704/05 seek and tune operations. This is achieved by keeping the bus quiet for all other devices on the bus, and delaying tuner polling until the tune or seek operation is complete. The seek/tune complete (STC) interrupt should be used instead of polling to determine when a seek/tune operation is complete. 22 Rev. 1.0 Si4704/05-D50 4.16. Control Interface A serial port slave interface is provided, which allows an external controller to send commands to the Si4704/05 and receive responses from the device. The serial port can operate in two bus modes: 2-wire mode and 3-wire mode. The Si4704/05 selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST. The GPO1 pin includes an internal pull-up resistor, which is connected while RST is low, and the GPO2 pin includes an internal pull-down resistor, which is connected while RST is low. Therefore, it is only necessary for the user to actively drive pins which differ from these states. See Table 12. Table 12. Bus Mode Select on Rising Edge of RST Bus Mode GPO1 GPO2 2-Wire 1 0 3-Wire 0 (must drive) 0 After the rising edge of RST, the pins GPO1 and GPO2 are used as general purpose output (O) pins as described in Section "4.17. GPO Outputs". In any bus mode, commands may only be sent after VIO and VDD supplies are applied. In any bus mode, before sending a command or reading a response, the user must first read the status byte to ensure that the device is ready (CTS bit is high). 4.16.1. 2-Wire Control Interface Mode When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. Also, a start condition must not occur within 300 ns before the rising edge of RST. The 2-wire bus mode uses only the SCLK and SDIO pins for signaling. A transaction begins with the START condition, which occurs when SDIO falls while SCLK is high. Next, the user drives an 8-bit control word serially on SDIO, which is captured by the device on rising edges of SCLK. The control word consists of a 7-bit device address, followed by a read/write bit (read = 1, write = 0). The Si4704/05 acknowledges the control word by driving SDIO low on the next falling edge of SCLK. Although the Si4704/05 will respond to only a single device address, this address can be changed with the SEN pin (note that the SEN pin is not used for signaling in 2-wire mode). When SEN = 0, the 7-bit device address is 0010001b. When SEN = 1, the address is 1100011b. For write operations, the user then sends an 8-bit data byte on SDIO, which is captured by the device on rising edges of SCLK. The Si4704/05 acknowledges each data byte by driving SDIO low for one cycle, on the next falling edge of SCLK. The user may write up to 8 data bytes in a single 2-wire transaction. The first byte is a command, and the next seven bytes are arguments. For read operations, after the Si4704/05 has acknowledged the control byte, it will drive an 8-bit data byte on SDIO, changing the state of SDIO on the falling edge of SCLK. The user acknowledges each data byte by driving SDIO low for one cycle, on the next falling edge of SCLK. If a data byte is not acknowledged, the transaction will end. The user may read up to 16 data bytes in a single 2-wire transaction. These bytes contain the response data from the Si4704/05. A 2-wire transaction ends with the STOP condition, which occurs when SDIO rises while SCLK is high. For details on timing specifications and diagrams, refer to Table 5, "2-Wire Control Interface Characteristics" on page 7; Figure 2, "2-Wire Control Interface Read and Write Timing Parameters," on page 8, and Figure 3, "2Wire Control Interface Read and Write Timing Diagram," on page 8. 4.16.2. 3-Wire Control Interface Mode When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. The 3-wire bus mode uses the SCLK, SDIO, and SEN_ pins. A transaction begins when the user drives SEN low. Next, the user drives a 9-bit control word on SDIO, which is captured by the device on rising edges of SCLK. The control word consists of a 3-bit device address (A7:A5 = 101b), a read/write bit (read = 1, write = 0), and a 5-bit register address (A4:A0). For write operations, the control word is followed by a 16-bit data word, which is captured by the device on rising edges of SCLK. For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-around. Next, the Si4704/05 will drive the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK. A transaction ends when the user sets SEN high, then pulses SCLK high and low one final time. SCLK may either stop or continue to toggle while SEN is high. In 3-wire mode, commands are sent by first writing each argument to register(s) 0xA1-0xA3, then writing the command word to register 0xA0. A response is retrieved by reading registers 0xA8-0xAF. Rev. 1.0 23 Si4704/05-D50 For details on timing specifications and diagrams, refer to Table 6, "3-Wire Control Interface Characteristics" on page 9; Figure 4, "3-Wire Control Interface Write Timing Parameters," on page 9, and Figure 5, "3-Wire Control Interface Read Timing Parameters," on page 9. 4.17. GPO Outputs The Si4704/05 provides three general-purpose output pins. The GPO pins can be configured to output a constant low, constant high, or high-Z. The GPO pins are multiplexed with the bus mode pins or DCLK, depending on the application schematic of the device. GPO2/INT can be configured to provide interrupts for seek and tune complete, receive signal quality, and RDS. 4.18. Reset, Powerup, and Powerdown Setting the RST pin low will disable analog and digital circuitry, reset the registers to their default settings, and disable the bus. Setting the RST pin high will bring the device out of reset. A powerdown mode is available to reduce power consumption when the part is idle. Putting the device in powerdown mode will disable analog and digital circuitry while keeping the bus active. 24 4.19. Programming with Commands To ease development time and offer maximum customization, the Si4704/05 provides a simple yet powerful software interface to program the receiver. The device is programmed using commands, arguments, properties, and responses. To perform an action, the user writes a command byte and associated arguments, causing the chip to execute the given command. Commands control an action such as powerup the device, shut down the device, or tune to a station. Arguments are specific to a given command and are used to modify the command. A complete list of commands is available in "AN332: Si47xx Programming Guide". Properties are a special command argument used to modify the default chip operation and are generally configured immediately after powerup. Examples of properties are de-emphasis level, RSSI seek threshold, and soft mute attenuation threshold. Responses provide the user information and are echoed after a command and associated arguments are issued. All commands provide a one-byte status update indicating interrupt and clear-to-send status information. For a detailed description of the commands and properties for the Si4704/05, see "AN332: Si47xx Programming Guide". Rev. 1.0 Si4704/05-D50 5. Commands and Properties Refer to "AN332: Si47xx Programming Guide". Rev. 1.0 25 Si4704/05-D50 NC 1 DFS GPO3/DCLK GPO2/INT GPO1 NC 6. Pin Descriptions: Si4704/05-GM 20 19 18 17 16 FMI 2 15 DOUT RFGND 3 14 LOUT GND PAD LPI 4 13 ROUT 7 8 9 SDIO RCLK 10 11 VA VD 6 SCLK 12 GND SEN RST 5 Pin Number(s) Name 1, 20 NC No connect. Leave floating. 2 FMI FM RF input. 3 RFGND 4 LPI Loop antenna RF input. 5 RST Device reset input (active low). 6 SEN Serial enable input (active low). 7 SCLK Serial clock input. 8 SDIO Serial data input/output. 9 RCLK External reference or crystal oscillator input. 10 VD Digital and I/O supply voltage. 11 VA Analog supply voltage. May be connected directly to battery. 13 ROUT Right audio analog line output. 14 LOUT Left audio analog line output. 15 DOUT Digital audio output data. 16 DFS 17 GPO3/DCLK 18 GPO2/INT 19 GPO1 General purpose output. 12, GND PAD GND Ground. Connect to ground plane on PCB. 26 Description RF ground. Connect to ground plane on PCB. Digital frame synchronization. General purpose output/digital bit synchronous clock or crystal oscillator input. General purpose output/interrupt. Rev. 1.0 Si4704/05-D50 7. Ordering Guide Part Number* Description Package Type Operating Temperature Si4704-D50-GM FM Broadcast Radio Receiver QFN Pb-free -20 to 85 C Si4705-D50-GM FM RDS Broadcast Radio Receiver QFN Pb-free -20 to 85 C *Note: Add an "(R)" at the end of the device part number to denote tape and reel option. Rev. 1.0 27 Si4704/05-D50 8. Package Markings 8.1. Si4704 Top Mark 0450 DTTT YWW Figure 13. Si4704 Top Mark 8.2. Si4705 Top Mark 0550 DTTT YWW Figure 14. Si4705 Top Mark 8.3. Top Mark Explanation Mark Method: YAG Laser Line 1 Marking: Part Number 04 = Si4704 05 = Si4705 Firmware Revision 50 = Firmware Revision 5.0 R = Die Revision D = Revision D Die. TTT = Internal Code Internal tracking code. Line 2 Marking: Line 3 Marking: Circle = 0.5 mm Diameter Pin 1 Identifier. (Bottom-Left Justified) Y = Year WW = Workweek 28 Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date. Rev. 1.0 Si4704/05-D50 9. Package Outline: Si4704/05 Figure 15 illustrates the package details for the Si4704/05. Table 13 lists the values for the dimensions shown in the illustration. Figure 15. 20-pin Quad Flat No-Lead (QFN) Table 13. Package Dimensions Symbol Millimeters Symbol Millimeters Min Nom Max A 0.50 0.55 0.60 f A1 0.00 0.02 0.05 L 0.35 0.40 0.45 b 0.18 0.25 0.30 L1 0.00 -- 0.10 c 0.27 0.32 0.37 D D2 3.00 BSC 1.60 e 1.70 1.80 0.50 BSC E E2 Min 3.00 BSC 1.60 1.70 Nom Max 2.53 BSC aaa -- -- 0.05 bbb -- -- 0.05 ccc -- -- 0.08 ddd -- -- 0.10 eee -- -- 0.10 1.80 Notes: 1. All dimensions are shown in millimeters unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. Rev. 1.0 29 Si4704/05-D50 10. PCB Land Pattern: Si4704/05 Figure 16 illustrates the PCB land pattern details for the Si4704/05-GM. Table 14 lists the values for the dimensions shown in the illustration. Figure 16. PCB Land Pattern 30 Rev. 1.0 Si4704/05-D50 Table 14. PCB Land Pattern Dimensions Symbol Millimeters Min D D2 Symbol Max 2.71 REF Max 2.10 -- W -- 0.34 0.50 BSC X -- 0.28 E 2.71 REF Y f GD 1.60 1.80 Min e E2 1.60 GE Millimeters 1.80 2.53 BSC 2.10 0.61 REF ZE -- 3.31 ZD -- 3.31 -- Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing is per the ANSI Y14.5M-1994 specification. 3. This land pattern design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at maximum material condition (MMC). Least material condition (LMC) is calculated based on a fabrication allowance of 0.05 mm. Notes: Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Notes: Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. Notes: Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small body components. Rev. 1.0 31 Si4704/05-D50 11. Additional Reference Resources 32 Customer Support Site: This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA is required for complete access. Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. AN332: Si47xx Programming Guide AN342: Quick Start Guide AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure Si47xx EVB User's Guide Rev. 1.0 Si4704/05-D50 DOCUMENT CHANGE LIST: Revision 0.2 to Revision 1.0 Updated functional block diagram Updated specification tables, removed TBDs Updated "2. Typical Application Schematic" Updated"3. Bill of Materials" Added support for FM for 64-75.9 MHz frequency range Added Section "4.6. Volume Control" Digital audio output now available in Si4704-D50 Removed references to "AN344: Si4706/07/4x Programming Guide" Rev. 1.0 33 Smart. Connected. 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