MAX3784UTE+T - Maxim Integrated Products, Inc.

General Description

The MAX3784/MAX3784A 5Gbps equalizers provide

compensation for transmission-medium losses in up to

40in of FR-4. They are optimized for short-run length

and balanced codes such as 8b10b, as found in multi-

plexed 1.25Gbps Ethernet systems and 4.25Gbps

Fibre Channel.

The equalizers use differential CML data inputs and

outputs. A standby mode reduces power consumption

when the parts are not in use. The MAX3784/

MAX3784A are available in a 4mm ×4mm, 16-pin QFN

package that consumes only 185mW at +3.3V.

Features

♦Spans 40in (1m) of FR-4 PCB

♦0.18UI Deterministic Jitter Up to 40in

♦Low Power Consumption: 185mW (MAX3784)

♦Equalization Reduces Intersymbol Interference

♦Single +3.3V Supply

♦Standby Mode

♦Small 4mm ×4mm, 16-Pin QFN Package

MAX3784/MAX3784A

5Gbps PCB Equalizer

________________________________________________________________

Maxim Integrated Products

Pin Configurations

LINE CARD

+3.3V

5Gbps

+3.3V

T/R 1

T/R 2

T/R 3

T/R 4

T/R 1

T/R 2

T/R 3

T/R 4

1.25Gbps

SWITCH

SWITCH CARD

PCB

BACKPLANE

MAX3784/

MAX3784A

EQUALIZER

IN OUT

MAX3784/

MAX3784A

EQUALIZER

OUT IN

Typical Application Circuit

19-2565; Rev 4; 10/07

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

PART TEMP

RANGE

PIN-

PACKAGE

PKG

CODE

MAX3784UGE 0°C to +85°C 16 QFN-EP* G1644-1

MAX3784UTE+ 0°C to +85°C 16 TQFN-EP* T1644-3

MAX3784AUGE 0°C to +85°C 16 QFN-EP* G1644-1

MAX3784AUTE+ 0°C to +85°C 16 TQFN-EP* T1644-3

Ordering Information

Applications

Chassis Life Extension

4.25Gbps Fibre Channel

4x Multiplexed 1.25Gbps Ethernet (5Gbps)

Denotes a lead-free package.

*Exposed pad.

1234

VCC

IN+

IN-

GND

N.C.

OUT+

OUT-

* THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND

FOR CORRECT THERMAL AND ELECTRICAL PERFORMANCE.

MAX3784/

MAX3784A

TOP VIEW

QFN

*EP

Pin Configurations continued at end of data sheet.

MAX3784/MAX3784A

5Gbps PCB Equalizer

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VCC = +3V to +3.6V, TA= 0°C to +85°C. Typical values are at VCC = +3.3V and TA= +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage, VCC.................................................-0.5V to +6V

Input Voltage............................................(-0.5V) to (VCC + 0.5V)

Continuous Output Current ...............................-25mA to +25mA

Continuous Power Dissipation (TA= +85°C)

16-Pin QFN (derate 25mW/°C above +85°C) ............1600mW

Operating Ambient Temperature Range ................0°C to +85°C

Storage Temperature Range .............................-55°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

EN = low 30

Supply Power EN = high 185 250 mW

10Hz < f < 100Hz 100

100Hz < f < 1MHz 40Supply-Noise Tolerance (Note 1)

1MHz < f < 2.5GHz 10

mVP-P

Latency From input to output 200 ps

CML RECEIVER INPUT

Input Voltage Swing VIN Measured differentially at point A in Figure 1 400 1000 mVP-P

Return Loss 100MHz to 2.5GHz 15 dB

Input Resistance Differential 80 100 120 Ω

EQUALIZATION

20in 0.13 0.21

Residual Deterministic Jitter,

5Gbps Table 1 (Notes 2–5) 40in 0.18 0.23 UIP-P

20in 0.08 0.14

Residual Deterministic Jitter,

2.5Gbps Table 1 (Notes 2–5) 40in 0.13 0.28 UIP-P

20in 0.04 0.07

Residual Deterministic Jitter,

1.25Gbps Table 1 (Notes 2–5) 40in 0.07 0.15 UIP-P

Random Jitter (Notes 5, 6) 1.3 1.9 psRMS

CML TRANSMITTER OUTPUT (into 100Ω ±1Ω)

MAX3784 400 600

Output Voltage Swing VODifferential swing, measured

differentially at point C in Figure 1 MAX3784A 550 750 mVP-P

Transition Time tf, tr20% to 80% (Notes 5, 8) 30 45 60 ps

Output Resistance Single ended 40 50 60 Ω

MAX3784/MAX3784A

5Gbps PCB Equalizer

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VCC = +3V to +3.6V, TA= 0°C to +85°C. Typical values are at VCC = +3.3V and TA= +25°C, unless otherwise noted.)

Note 1: Allowed supply noise during jitter tests.

Note 2: Test pattern. This is a combination of K28.5± characters running at the full bit rate and at one-quarter the bit rate. This simu-

lates the multiplexing of four each 1.25Gbps Ethernet data streams.

Pattern (hex) 100 bits

00 FFFF F0F0 FF 0000 0F0F (quarter rate K28.5+, quarter rate K28.5-)

3EB05 (K28.5± 00 1111 1010 11 0000 0101)

Note 3: Difference in deterministic jitter between reference points A and C in Figure 1.

Note 4: Signal source amplitude range is 400mVP-P to 1000mVP-P differential. Signal is applied differentially at point A as shown in

Figure 1. The deterministic jitter at point B must be from media-induced loss and not from clock-source modulation.

Deterministic jitter is measured at the 50% vertical level of the signal at point C.

Note 5: Guaranteed by design and characterization.

Note 6: Test pattern is K28.5 with 40in trace.

Note 7: On-chip pullup resistor of 40kΩ(typ). Negative current indicates equalizer sources current.

Note 8: Using 00 0001 1111 or equivalent pattern. Measured over entire input voltage range, max and min media loss and within 2in

of output pins.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ENABLE CONTROL PIN

Input High Voltage 1.5 V

Input Low Voltage 0.5 V

Input High Current (Note 7) -150 +10 µA

Input Low Current (Note 7) -150 +10 µA

SIGNAL

SOURCE

BACKPLANE PCB MAX3784/MAX3784A

EQUALIZER

IN OUT

L ≤ 40in

6mil LINE

SMA CONNECTOR SMA CONNECTOR

Figure 1. Test Conditions

PARAMETER CONDITIONS MIN TYP MAX UNITS

Transmission Line Edge-coupled stripline 6 mils

Relative Permittivity FR-4 or similar 4.4 4.5 —

Loss Tangent FR-4 or similar 0.02 0.022 —

Metal Thickness 0.7 mils (0.5oz copper) 0.7 mils

Impedance Differential 90 100 110 

Table 1. PCB Assumptions (PCB material is FR-4)

MAX3784/MAX3784A

5Gbps PCB Equalizer

4 _______________________________________________________________________________________

Typical Operating Characteristics

(VCC = +3.3V, measurements done at 5Gbps, 800mVP-P board input with 100-bit pattern from Note 2 of the

EC Table

A= +25°C,

unless otherwise noted.)

55mV/

div

EQUALIZER INPUT EYE DIAGRAM

BEFORE EQUALIZATION AT 5Gbps

(40in, FR-4, 6-mil STRIPLINE)

MAX3784/4A toc01

32ps/div

80mV/

div

EQUALIZER OUTPUT EYE DIAGRAM

AFTER EQUALIZATION AT 5Gbps

(40in, FR-4, 6-mil STRIPLINE, MAX3784)

MAX3784/4A toc02

35ps/div

80mV/

div

EQUALIZER OUTPUT EYE DIAGRAM

AFTER EQUALIZATION AT 5Gbps

(40in, FR-4, 6-mil STRIPLINE, MAX3784A)

MAX3784/4A toc03

35ps/div

DIFFERENTIAL RETURN LOSS

MAX3784/4A toc04

FREQUENCY (GHz)

RETURN LOSS (dB)

2134

100

02010 30 40 50 60

DETERMINISTIC JITTER

vs. LINE LENGTH

MAX3784/4A toc05

LINE LENGTH (in)

(FR-4 6-mil STRIPLINE)

DETERMINISTIC JITTER (ps)

1.25GHz

2.5GHz

5GHz

100

200 600400 800 1000 1200

DETERMINISTIC JITTER vs. AMPLITUDE

(20in FR-4 STRIPLINE)

MAX3784/4A toc06

INPUT AMPLITUDE (mVP-P)

(FIGURE 1, POINT A)

DETERMINISTIC JITTER (ps)

1.25GHz

2.5GHz

5GHz

100

200 600400 800 1000 1200

DETERMINISTIC JITTER vs. AMPLITUDE

(40in FR-4 STRIPLINE)

MAX3784/4A toc07

INPUT AMPLITUDE (mVP-P)

(FIGURE 1, POINT A)

DETERMINISTIC JITTER (ps)

1.25GHz

2.5GHz

5GHz

100

300

200

400

500

LATENCY vs. TEMPERATURE

MAX3784/4A toc08

TEMPERATURE (°C)

LATENCY (ps)

05025 75 100

0255075

SUPPLY CURRENT vs. TEMPERATURE

MAX3784/4A toc09

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

ICC MAX3784

ICC MAX3784A

ISHUTDOWN

Detailed Description

General Theory of Operation

The MAX3784/MAX3784A adaptive equalizers extend

the reach of transmission lines in high-frequency back-

plane interconnect applications. They can be used for

4.25Gbps Fibre Channel, 4x 1.25Gbps Ethernet (5Gbps)

and other NRZ, 8b10b or short (≤20 bits) CID data

types. Internally, the MAX3784/MAX3784A are com-

prised of an equalizer control loop and limiting output

driver. The equalizer block reduces intersymbol interfer-

ence (ISI), compensating for frequency-dependent

media-induced loss. The equalization control detects the

spectral contents of the input signal and provides a con-

trol voltage to the equalizer core, adapting it to different

media. The equalizer operation is optimized for short-run,

DC-balanced transmission codes.

Standby Mode

Standby saves power when the equalizer is not in use.

The EN logic input must be set high or open for normal

operation. Logic low at EN forces the equalizer into the

standby state.

CML Input and Output Buffers

The input and output buffers are implemented using cur-

rent-mode logic (CML). Equivalent circuits are shown in

Figures 3 and 4. For details on interfacing with CML,

refer to Maxim Application Note HFAN-01.0:

Introduction

to LVDS, PECL, and CML

. The common-mode voltage

of the input and output is above +2.5V. AC-coupling

capacitors are required when interfacing this part with

devices terminated in voltages such as +1.8V. Values of

0.10µF or greater are recommended.

MAX3784/MAX3784A

5Gbps PCB Equalizer

_______________________________________________________________________________________________________ 5

Pin Description

PIN NAME FUNCTION

1, 7, 12 VCC +3.3V Supply Voltage

2 IN+ Positive Input, CML

3 IN- Negative Input, CML

4, 6, 9 GND Supply Ground

5, 8, 14, 15,

16 N.C. No Connection. Leave unconnected.

10 OUT- Negative Output, CML

11 OUT+ Positive Output, CML

13 EN Enable Equalizer. A logic high or open selects normal operation. A logic low selects low-power

standby mode.

EP Exposed

Pad

Connect to Ground. The exposed pad must be soldered to the circuit board ground plane for proper

thermal and electrical performance.

IN+

IN-

LIMITER

5Gbps EQUALIZER

OUT+

OUT-

VCC

EQUALIZER

OFFSET

CANCELLATION

LOWPASS FILTER 50Ω

100Ω

40kΩ

50Ω

VCC

MAX3784/

MAX3784A

Figure 2. Functional Diagram

MAX3784/MAX3784A

Applications Information

Alternate Data Rates

The MAX3784/MAX3784A is optimized for automatic

operation at 5Gbps. Equalization at other data rates,

such as 1.25Gbps and 2.5Gbps, is possible. See the

Typical Operating Characteristics

for Deterministic Jitter

vs. Line Length and Deterministic Jitter vs. Amplitude

for typical performance at these data rates.

Layout Considerations

Circuit board layout and design can significantly affect

the MAX3784/MAX3784As’ performance. Use good

high-frequency design techniques, including minimiz-

ing ground inductance and connections and using con-

trolled-impedance transmission lines for the

high-frequency data signals. Route signals differentially

to reduce EMI susceptibility and crosstalk. Solder the

exposed pad to supply ground for proper thermal and

electrical operation.

Place power-supply decoupling capacitors as close as

possible to the VCC pins.

5Gbps PCB Equalizer

6 _______________________________________________________________________________________

50Ω

VCC

250μA

Figure 3. CML Input Equivalent Circuit

VCC

50Ω50Ω

OUT+

OUT-

Figure 4. CML Output Equivalent Circuit

IN+

GND

VCC

OUT+

GND

VCC

N.C.

12 11 9

N.C.

VCC

GND

N.C.

MAX3784

MAX3784A

IN- OUT-

TQFN

TOP VIEW

* THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND

FOR CORRECT THERMAL AND ELECTRICAL PERFORMANCE.

*EP

Pin Configurations (continued)

21-0139

MAX3784/MAX3784A

5Gbps PCB Equalizer

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________

Revision History

Pages changed at Rev 4: 1–7 (removed package draw-

ings, replaced with table)

Package Information

For the latest package outline information, go to

www.maxim-ic.com/packages.

PACKAGE TYPE DOCUMENT NO.

16 QFN 21-0106

16 TQFN