PRELIMINARY
Three PLL Programmable Clock Generator
with Spread Spectrum
CY25403
CY25423
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-12564 Rev. *A Revised March 02, 2007
Features
• Three fully integrated phase-locked loops (PLLs)
• Input Frequency range:
— External crystal: 8 to 48 MHz
— External reference: 8 to 166 MHz clock
• Wide operating output frequency range
— 3 to 166 MHz
• Programmable Spread Spectrum modulation frequency
range of 30 to 120 kHz with Lexmark profile
• Center Spread: ±0.125% to ±2.5%
• Down Spread: –0.25% to –5%
• Frequency select feature with option to select four different
frequencies
• Low-jitter, high-accuracy outputs
• Up to three clock outputs
• Programmable output drive strength
• Glitch-free outputs while frequency switching
• Four independent outpu t voltages: 3.3V, 3.0V, 2.5V, and
1.8V
• 8-pin SOIC package
• Commercial and Industrial temperature range
Benefits
• Multiple high-performance PLLs allow synthesis of
unrelated frequencies
• Nonvolatile programming for customized PLL frequencies,
spread spectrum characteristics, drive strength, crystal load
capacitance, and output frequencies
• Two Spread Spectrum capable PLLs with Lexmark profile
for maximum for EMI reduction
• Spread Spectrum PLLs can be disabled or enabled
separately
• PLLs can be programmed for system frequency margin
tests
• Meets critical timing requirements in complex system
designs
• Suitable for PC, consumer, and networking applications
• Ability to synthesize standard frequencies with ease
• Application compatibility in standard and low-power
systems
Block Diagram
OSC
MUX
and
Control
Logic
PLL1
PLL2
(SS)
PLL3
(SS)
Output
Dividers
and
Drive
Strength
Control CLK3
CLK2
CLK1
FS1
FS0
SSON
XOUT
XIN
3 of 4
Crossbar
Switch
PD#/OE
PRELIMINARY CY25403
CY25423
Document #: 001-12564 Rev. *A Page 2 of 8
General Description
Th CY25403 and CY25423 are three PLL programmable
S pread S pectrum Clock Generators used to reduce EMI found
in high-speed digital electronic systems. T wo of the three PLLs
have Spread Spectrum capability. The spread spectrum
feature are turned on or off using the control pin SSON.
The advantage of having three PLLs is that a single device can
generate up to three independent frequencies from a single
crystal or reference input frequency. Generally, a design
requires up to three oscillators to achieve the same result with
a single CY25403 or CY25423.
The device uses Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy significantly reduces the cost of complying with
regulatory agency (EMC) requirements and improves
time-to-market without degrading the system performance.
The CY25403 and CY25423 use a factory/field-programmable
configuration memory array to provide customization for
output frequencies, frequency select optio ns, spread charac-
teristics like spread percentage and modulation frequency,
output drive strength and crystal load capacitance. A
customized device can be configured using CyberclocksTM
software or by contacting the factory.
The spread percentage is programmed to either center spread
or down spread with various spread percentages. The range
for center spread is from ±0.125% to ±2.50%. The range for
down spread is from –0.25% to –5.0%. Contact the factory for
smaller or larger spread percentage amounts, if required.
The input to the CY25403 and CY25423 is eith er a crystal or
a clock signal. The input frequency range for crystals is 8 MHz
to 48 MHz, and for clock signals is 8 MHz to 166 MHz.
The CY25403 and CY25423 have up to three clock outputs
and each output has four possible input sources.There are two
frequency select lines FS(1:0) that provide an option to select
four different sets of frequencies among the each of the three
PLLs. Each output has programmable output di vider options.
Output 1 has eight possible divider values and outputs 2–3
have four possible divider values for maximum flexibility. The
2 bit or 3 bit output dividers are programmable providing a wide
output frequency range.
The outputs are glitch-free when frequency is switched using
output dividers. The outputs have a predictable phase
relationship, if the clock source is the same PLL and divider
values are 2, 3, 4, or 6.
The CY25403 and CY25423 are 3-PLL memory program-
mable spread spectrum clock generators with three clock
outputs.
Pin Configuration
8 L D S OIC
1
2
3
4
8
7
6
5
XOUT
GND
CLK3/SSON
PD#/OE/FS1
XIN
VDD
CLK1
CLK2/FS0
Pin Description - Memory Programmable 3-PLL device with 2 Spread Spectrum PLLs
Pin Number Name I/O Description
1 XIN Input Crystal or Clock Input
2 VDD Power Power Supply
3 CLK1 Output Programmable Clock Output
4 CLK2/FS0 Output/input Programmable Clock Output or FS0
5 PD#/OE/FS1 Input Power Down, Output Enable or FS1
6 CLK3/SSON Output/Input Programmable Clock Output or SSON
7 GND Power Power Supply Ground
8 XOUT Output Crystal Output
Table 1. Supply Voltage Options
Device VDD Supply Voltage
CY25403
CY25423 2.5V, 3.0V or 3.3V
1.8V
PRELIMINARY CY25403
CY25423
Document #: 001-12564 Rev. *A Page 3 of 8
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
VDD Supply Vo ltage –0.5 4.5 V
VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC
TSTemperature, Storage Non Functional –65 +150 °C
ESDHBM ESD P rot ecti on (H uman
Body Model) MIL-STD-883, Method 3015 2000 –Volts
UL-94 Flammability Rating @1/8 in. V-0
MSL Moisture Sensitivity Level SOIC package 1
Recommended Operating Conditions
Parameter Description Min. Typ. Max. Unit
VDD1 Operating Voltage, 3.3V 3.0 – 3.6 V
VDD2 Operating Voltage, 3.0V 2.7 – 3.3 V
VDD3 Operating Voltage, 2.5V 2.25 – 2.75 V
VDD4 Operating Voltage, 1.8V 1.65 – 1.95 V
TAC Commercial Ambient Temperature 0 – +70 °C
TAI Industrial Ambient Temperature –40 – +85 °C
CLOAD Max. Load Capacitance – – 15 pF
tPU Power-up time for all VDD pins to reach minimum specified volt age (power ramps must
be monotonic) 0.05 – 500 ms
DC Electrical Specifications
Parameter Description Conditions Min. Typ. Max. Unit
VOL Output Low Voltage, All CLK pins All VDD levels, IOL = 8 mA 0 – 0.4 V
VOH Output High Voltage, All CLK pins All VDD levels, IOH = –8 mA VDD – 0.4 – VDD V
VIL All Inputs except XIN All VDD levels –0.3 – 0.2 * VDD V
VIH All Inputs except XIN All VDD levels 0.8 * VDD –V
DD + 0.3 V
VILX Input Low Voltage, clock input to XIN pin All VDD levels –0.3 – 0.36 V
VIHX Input High Voltage, clock input to XIN pin All VDD levels 1.44 – 2.0 V
IILPDOE Input Low Current, PD#/OE and FS0,1 pins VIN = VSS
(Internal pull up = 100k typical) ––10μA
IIHPDOE Input High Current, PD#/OE and FS0,1 pins VIN = VDD
(Internal pull up = 100k typical) ––1μA
IILSR Input Low Current, SSON pin VIN = VSS
(Internal pull down = 100k typical) ––1μA
IIHSR Input High Current, SSON pin VIN = VDD
(Internal pull down = 100k typical) ––10μA
IDD[1] Supply Current All clocks ru nning, CL = 0 ––17mA
CIN Input Capacitance - All inputs except XIN SS ON, OE, PD# or FS inputs ––7pF
Note
1. Configuration dependent.
PRELIMINARY CY25403
CY25423
Document #: 001-12564 Rev. *A Page 4 of 8
AC Electrical Specifications
Parameter Description Conditions Min. Typ. Max. Unit
FIN (crystal) Crystal Frequency 8 –48 MHz
FIN (clock) Input Clock Frequency (XIN) 8 –166 MHz
FOUT Output Clock Frequency 3 –166 MHz
DC Output Duty Cycle All Clocks except Ref Out Duty Cycle is defined in Figure 2; t1/t2,
50% of VDD 45 50 55 %
DC Ref Out Duty Cycle Ref In Min 45%, Max 55% 40 60 %
ERCLK1-3 Rising Edge Rate VDD = All, 20% to 80% VDD 0.8 – – V/ns
EFCLK1-3 Falling Edge Rate VDD = All, 20% to 80% VDD 0.8 – – V/ns
TCCJ1 Cycle-to-cycle Jitter Configuration dependent. See Table 2 –-–ps
TLTJ Long Term Jitter Configuration dependent. See Table 2 –-–ns
T10 PLL Lock Time – – 3 ms
Table 2. Configuration Example for Jitter
Reference Description Max Jitter (ps) on
Output 1(48MHz) Max Jitter (ps) on Output 2
(27 MHz) Max Jitte r (ps) on
Output 3 (166 MHz)
27MHz TCCJ1 155 255 170
27MHz TLTJ 770 580 630
48 MHz TCCJ1 135 225 100
48 MHz TLTJ 535 575 520
Recommended Crystal Specification for SMD Package
Parameter Description Range 1 Range 2 Range 3 Unit
Fmin Minimum Frequency 8 14 28 MHz
Fmax Maximum Frequency 14 28 48 MHz
R1(max) Maximum Motional Resistance (ESR) 135 50 30 Ω
C0(max) Maximum Shunt Capacit ance 4 4 2 pF
CL(max) Maximum Parallel Load Capacitance 18 14 12 pF
DL(max) Maximum Crystal Drive Level 300 300 300 μW
Recommended Crystal Specification for Thru-Hole Package
Parameter Description Ra ng e 1 Range 2 Range 3 Unit
Fmin Minimum Frequency 8 14 24 MHz
Fmax Maximum Frequency 14 24 32 MHz
R1(max) Maximum Motional Resistance (ESR) 90 50 30 Ω
C0(max) MaximumShunt Capacitance 7 7 7 pF
CL(max) Maximum Parallel Load Capacitance 18 12 12 pF
DL(max) Maximum Crystal Drive Level 1000 1000 1000 μW
PRELIMINARY CY25403
CY25423
Document #: 001-12564 Rev. *A Page 5 of 8
Test and Measurement Setup
Figure 1. Test and Measurement Setup
Voltage and Timing Definitions
Figure 2. Duty Cycle Definition
Figure 3. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4
0.1 μF
VDDs Outputs
CLOAD
GND
DUT
Clock
Output
V
50% of V
0V
t
t
Clock
Output
t 3 t 4
V DD
80% of V
DD
20% of V
DD
0V
PRELIMINARY CY25403
CY25423
Document #: 001-12564 Rev. *A Page 6 of 8
Ordering Information
Part Number[2] Type VDD(V) Temperature Range
Lead-free
CY25403SXC-xxx 8-pin SOIC 3.3, 3.0 or 2.5 Commercial, 0°C to 70°C
CY25403SXC-xxxT 8-pin SOIC-Tape & Reel 3.3, 3.0 or 2.5 Commercial, 0°C to 70°C
CY25403FSXC 8-pin SOIC 3.3, 3.0 or 2.5 Commercial, 0°C to 70°C
CY25403FSXCT 8-pin SOIC-Tape & Reel 3.3, 3.0 or 2.5 Commercial, 0°C to 70°C
CY25423SXC-xxx 8-pin SOIC 1.8 Commercial, 0°C to 70°C
CY25423SXC-xxxT 8-pin SOIC-Tape & Reel 1.8 Commercial, 0°C to 70°C
CY25423FSXC 8-pin SOIC 1.8 Commercial, 0°C to 70°C
CY25423FSXCT 8-pin SOIC-Tape & Reel 1.8 Commercial, 0°C to 70°C
CY25403SXI-xxx 8-pin SOIC 3.3, 3.0 or 2.5 Industrial, -40°C to +85°C
CY25403SXI-xxxT 8-pin SOIC-Tape & Reel 3.3, 3.0 or 2.5 Industrial, -40°C to +85°C
CY25403FSXI 8-pin SOIC 3.3, 3.0 or 2.5 Industrial, -40°C to +85°C
CY25403FSXIT 8-pin SOIC-Tape & Reel 3.3, 3.0 or 2.5 Ind ustrial, -40°C to +85°C
CY25423SXI-xxx 8-pin SOIC 1.8 Industrial, -40°C to +85°C
CY25423SXI-xxxT 8-pin SOIC-Tape & Reel 1.8 Industrial, -40°C to +85°C
CY25423FSXI 8-pin SOIC 1.8 Industrial, -40°C to +85°C
CY25423FSXIT 8-pin SOIC-Tape & Reel 1.8 I ndustrial, -40°C to +85°C
Note
2. xxx Indicates Factory Programmable are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative.
F in the part number indicates field programmable using CyberClocks Online software.
PRELIMINARY CY25403
CY25423
Document #: 001-12564 Rev. *A Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corpor ation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursua nt to an express written agreement with Cypress. Furthermore, Cy press does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Package Drawing and Dimensions
All products and company names mentioned in this document may be the trademarks of their respective holders.
Figure 4. 8-lead (150-Mil) SOIC S8
SEATING PLANE
PIN1ID
0.230[5.842]
0.244[6.197]
0.157[3.987]
0.150[3.810]
0.189[4.800]
0.196[4.978]
0.050[1.270]
BSC
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
0°~8°
0.016[0.406]
0.010[0.254] X 45°
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.004[0.102]
14
58
3. REFERENCE JEDEC MS-012
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
4. PACKAGE WEIGHT 0.07gms
51-85066-*C
PRELIMINARY CY25403
CY25423
Document #: 001-12564 Rev. *A Page 8 of 8
Document History Page
Document Title: CY25403/CY25423 Three PLL Programmable Clock Generator
with Spread Spectrum
Document Number: 001-12564
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 690339 See ECN RGL New Data Sheet
*A 815816 See ECN RGL Minor Change: To Post on web