Advanced v0.6 ProASICPLUSTM Family Flash FPGAs Fe a t ur es an d B e ne f i ts I/O High C apaci t y * Schmitt Trigger option on Every Input * Mixed 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate * Bidirectional Global I/Os * Compliance with PCI Specification Revision 2.2 * Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant * Pin Compatible Packages across ProASICPLUS Family * 150,000 to 1 million System Gates * 36k to 198 kbits of Two-Port SRAM * 106 to 712 User I/Os P erf orm a nce * 3.3V, 32-bit PCI (up to 50 MHz) * Internal System Performance up to 350 MHz * External System Performance up to 150 MHz Uni que Cl ock Con dit io ning C ir cui tr y Rep ro gra m m able Fl as h T ech nol ogy * * * * * Two Integrated PLLs (1.5 to 240 MHz Input and Output Ranges) * PLL with Flexible Phase, Multiply/Divide and Delay Capabilities * Internal and/or External Dynamic PLL Configuration * Two LVPECL Differential Pairs for Clock or Data Inputs 0.22 4LM Flash-based CMOS Process Live at Power Up, Single-Chip Solution No Configuration Device Required Retains Programmed Design During Power-Down/ Power-Up Cycles S ecur e Pr og ram m i ng S ta ndar d FP GA and AS IC De si gn F low * The Industry's Most Effective Security Key Prevents Read Back of Programming Bit Stream * Flexibility with Choice of Industry-Standard Front-End Tools * Efficient Design through Front-End Timing and Gate Optimization Low P ower * Low Impedance Flash Switches * Segmented Hierarchical Routing Structure * Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells IS P S uppo rt * In-System Programming (ISP) via JTAG Port S RA Ms and FIFO s H ig h P er f o r m ance R out ing H i era rc hy * * * * Ultra Fast Local and Long Line Network High Speed Very Long Line Network High Performance, Low Skew, Splitable Global Network 100% Routability and Utilization * Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks * Synchronous and Asynchronous Operation of 24 RAM and FIFO Configurations (Up to 150 MHz) Pr oA S I C PL U S P r o du ct Pr o f i l e Device Maximum System Gates Maximum Registers Embedded RAM Bits Embedded RAM Blocks (256 X 9) LVPECL PLL Global Networks Maximum Clocks Maximum User I/Os JTAG PCI Package (by pin count) PQFP PBGA FBGA April 2002 (c) 2002 Actel Corporation APA150 150,000 6,144 36k 16 2 2 4 32 242 Yes Yes APA300 300,000 8,192 72k 32 2 2 4 32 304 Yes Yes APA450 450,000 12,288 108k 48 2 2 4 48 356 Yes Yes APA600 600,000 21,504 126k 56 2 2 4 56 456 Yes Yes APA750 750,000 32,768 144k 64 2 2 4 64 642 Yes Yes APA1000 1,000,000 56,320 198k 88 2 2 4 88 712 Yes Yes 208 456 144, 256 208 456 144, 256 208 456 144, 256 208 456 256, 676 208 456 676, 896 208 456 896, 1152 1 Pr o A S I C P L U S F a m ily F la s h F P GA s G en er al D e sc r i p t i on The ProASICPLUS family of devices offers enhanced performance over Actel's ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile Flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, the ProASICPLUS family offers a unique clock conditioning circuit based on two on-board phase lock loops (PLLs). The family offers up to 1 million system gates, supported with up to 198 kbits of 2-port SRAM and up to 712 user I/Os, all providing 50 MHz PCI performance. Advantages to the designer extend beyond performance. Four levels of routing hierarchy simplify routing, while the use of Flash technology allows all functionality to be live at power up, unlike SRAM-based FPGAs. No external Boot PROM is required to support device programming. While on-board security mechanisms prevent all access to the program information, reprogramming can be performed in-system to support future design iterations and field upgrades. The device's architecture mitigates the complexity of ASIC migration at higher user volume. This makes ProASICPLUS a cost-effective solution for applications in the networking, communications, computing, and avionics markets. The ProASICPLUS family achieves its nonvolatility and reprogrammability through an advanced Flash-based 0.22m LVCMOS process with four-layer metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs. The result is predictable performance fully compatible with gate arrays. The ProASICPLUS architecture provides granularity comparable to gate arrays. The device core consists of a Sea-of-TilesTM. Each tile can be configured as a flip-flop, latch, or 3-input/1-output logic function by programming the appropriate Flash switches. The combination of fine granularity, flexible routing resources, and abundant Flash switches allow 100% utilization and over 95% routability for highly congested designs. Tiles and larger functions are interconnected through a 4-level routing hierarchy. Embedded 2-port SRAM blocks with built-in FIFO/RAM control logic can have user-defined depth and width. Users can also select programming for synchronous or asynchronous operation, as well as parity generations or checking. The clock conditioning circuitry is unique. Devices contain two clock conditioning blocks, each with a PLL core, delay lines, phase shifts (0x, 90x, 180x, 270x), and clock multipliers/dividers. In short, this is all the circuitry needed to provide bidirectional access to the PLL, and operation up to 240 MHz. The PLL block contains four programmable 2 frequency dividers which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. The clock conditioning circuit also delays or advances the incoming reference clock up to 4ns (in increments of 0.25ns). The PLL can be configured internally or externally during operation without redesigning or reprogramming the part. In addition to the PLL, there are two LVPECL differential input pairs to accommodate high speed clock and data inputs. To support customers' needs for more comprehensive, lower cost board-level testing, Actel's ProASICPLUS devices are fully compatible with IEEE Standard 1149.1 for test access port and boundary-scan test architecture. For more details on the Flash FPGA implementation please refer to the "Boundary Scan" section on page 12. ProASICPLUS devices are available in a variety of high-performance plastic packages. Those packages, and the performance features discussed above, are described in more detail in the following sections of this document: * "Features and Benefits" section on page 1 * "ProASICPLUS Architecture" section on page 5 * "Routing Resources" section on page 6 * "Clock Trees" section on page 9 * "Input/Output Blocks" section on page 10 * "LVPECL Input Pads" section on page 11 * "Boundary Scan" section on page 12 * "User Security" section on page 14 * "Embedded Memory Floorplan" section on page 14 * "Design Environment" section on page 17 * "Package Thermal Characteristics" section on page 19 * "Operating Conditions" section on page 22 * "DC Electrical Specifications (VDDP = 2.5V +/-0.2V)" section on page 23 - page 25 * "AC Specifications (3.3V PCI Revision 2.2 Operation)" section on page 26 * "Clock Conditioning Circuit" section on page 27 * "Embedded Memory Specifications" section on page 35 * "Package Pin Assignments" section on page 55 - page 109 * For more information concerning In-System Programming with ProASICPLUS, refer to the application note, Performing Internal In-System Programming Using Actel's ProASICPLUS Devices. http://www.actel.com/appnotes/PAplusISPAN.pdf Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s O r d e r i n g I nf o r m a t i o n _ APA1000 FG 1152 ES Application (Ambient Temperature Range) Blank = Commercial (0 to +70 C) I = Industrial (-40 to +85 C) PP = Pre-production ES = Engineering Silicon (Room Temperature Only) Package Lead Count Package Type PQ = Plastic Quad Flat Pack FG = FineBall Grid Array PB = Plastic Ball Grid Array Speed Grade Blank = Standard Speed 1 = TBD Part Number APA150 APA300 APA450 APA600 APA750 APA1000 = = = = = = 150,000 Equivalent System Gates 300,000 Equivalent System Gates 450,000 Equivalent System Gates 600,000 Equivalent System Gates 750,000 Equivalent System Gates 1,000,000 Equivalent System Gates Pr od uc t P l a n Speed Grade APA150 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Ball Grid Array (FBGA) 256-Pin Fine Ball Grid Array (FBGA) APA300 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Ball Grid Array (FBGA) 256-Pin Fine Ball Grid Array (FBGA) APA450 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Ball Grid Array (FBGA) 256-Pin Fine Ball Grid Array (FBGA) APA600 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 256-Pin Fine Ball Grid Array (FBGA) 676-Pin Fine Ball Grid Array (FBGA) APA750 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Fine Ball Grid Array (PBGA) 676-Pin Fine Ball Grid Array (FBGA) 896-Pin Plastic Ball Grid Array (FBGA) APA1000 Device 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 896-Pin Plastic Ball Grid Array (FBGA) 1152-Pin Plastic Ball Grid Array (FBGA) Applications: C = Commercial I = Industrial Availability: Application Std -1 C I P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P = Planned = Limited Availability - Contact your Actel Sales representative for the latest availability information. Advanced v0.6 3 Pr o A S I C P L U S F a m ily F la s h F P GA s Pl a s t i c D e vi c e Re so u r ce s User I/Os Device PQFP 208-Pin PBGA 456-Pin FBGA 144-Pin FBGA 256-Pin APA150 158 242 100 186 APA300 158 290 100 186 APA450 158 344 100 186 APA600 158 356 APA750 158 356 APA1000 158 356 186 FBGA 676-Pin 454 562 642 Advanced v0.6 FBGA 1152-Pin 454 Package Definitions PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Ball Grid Array 4 FBGA 896-Pin 712 Pr o A SI C P L U S F a m ily F la s h F P GA s Pr oA S I C PL U S A r c hi t e c t u r e Fla sh S wit ch The proprietary ProASICPLUS architecture provides granularity comparable to gate arrays. Unlike SRAM FPGAs, ProASICPLUS uses a live on power-up ISP Flash switch as its programming element. The ProASICPLUS device core (Figure 1) consists of a Sea-of-TilesTM. Each tile can be configured as a 3-input logic function (e.g., NAND gate, D-Flip-Flop, etc.) by programming the appropriate Flash switch interconnections (Figure 2 on page 6 and Figure 3 on page 6). Tiles and larger functions are connected with any of the four levels of routing hierarchy. Flash cells are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Flash switches are programmed to connect signal lines to the appropriate logic cell inputs and outputs. Dedicated high-performance lines are connected as needed for fast, low-skew global signal distribution throughout the core. Maximum core utilization is possible for virtually any design. In the ProASICPLUS Flash switch, two transistors share the floating gate, which stores the programming information. One is the sensing transistor, which is only used for writing and verification of the floating gate voltage. The other is the switching transistor. It can be used in the architecture to connect/separate routing nets or to configure logic. It is also used to erase the floating gate (Figure 2 on page 6). ProASICPLUS devices also contain embedded two-port SRAM blocks with built-in FIFO/RAM control logic. Programming options include synchronous or asynchronous operation, two-port RAM configurations, user defined depth and width, and parity generation or checking. Table 3 on page 14 lists the 24 basic memory configurations. Logi c Ti le The logic tile cell (Figure 3 on page 6) has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra fast local and efficient long line routing resources). Any three-input one-output logic function, except a three input XOR, can be configured as one tile. The tile can be configured as a latch with clear or set or as a flip-flop with clear or set. Thus the tiles can flexibly map logic and sequential gates of a design. 256x9 Two-Port SRAM or FIFO Block Logic Tile Figure 1 * The ProASICPLUS Device Architecture Advanced v0.6 5 Pr o A S I C P L U S F a m ily F la s h F P GA s S Col D Col Floating Gate Sensing Switch In Switching Word Switch Out Figure 2 * Flash Switch Local Routing In 1 Efficient Long Line Routing In 2 (CLK) In 3 (Reset) Figure 3 * Core Logic Tile Rou ti ng Res our ces ProASICPLUS The routing structure of the devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra fast local resources, efficient long line resources, high speed very long line resources, and high performance global networks. The ultra fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles (Figure 4 on page 7). The efficient long line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASICPLUS device (Figure 5 on page 7). Each tile can drive signals onto the efficient long line resources, which can, in turn, access every input of every tile. Active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout. 6 The high speed very long line resources which span the entire device with minimal delay, are used to route very long or very high fanout nets. (Figure 6 on page 8). The high performance global networks are low skew, high fanout nets that are accessible from external pins or from internal logic (Figure 7 on page 9). These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically, with signals accessing every input on all tiles. Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s L Inputs L L L Ultra Fast Local Lines (connects a tile to the adjacent tile, I/O buffer, or memory block) Output L L L L L Figure 4 * Ultra Fast Local Resources Spans 4 Tile Spans 1 Tile Spans 2 Tiles Logic Tile L L L L L L L L L L L L L L L L L L L L L L L L Spans 1 Tile Spans 2 Tiles Spans 4 Tile Logic Cell L L L L L L Figure 5 * Efficient Long Line Resources Advanced v0.6 7 Pr o A S I C P L U S F a m ily F la s h F P GA s High Speed Very Long Line Resouces I/O RING I/O RING PAD RING PAD RING PAD RING Figure 6 * High Speed Very Long Line Resources 8 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s Cl ock Res our ce s PLUS The ProASIC family offers powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has two clock conditioning blocks, containing a 240 MHz phase lock loop (PLL) core, delay lines, phase shifter(0, 90, 180, 270), clock multiplier/dividers and all the circuitry needed for the selection and interconnection of inputs to the global network (thus providing bidirectional access to the PLL). This permits the PLL block to drive inputs and/or outputs via the two global lines on each side of the chip (four total lines). This circuitry is discussed in more detail later in the data sheet. Cl ock T re es One of the main architectural benefits of ProASICPLUS is the set of power and delay friendly global networks. ProASICPLUS offers 4 global trees. Each of these trees is based on a network of spines and ribs that reach all the tiles in their regions (Figure 7). This flexible clock tree architecture allows users to map up to 88 different internal/external clocks in an APA1000 device. Details on the clock spines and various numbers of the family are given in Table 1 on page 10. The flexible use of the ProASICPLUS clock spine allows the designer to cope with several design requirements. Users implementing clock resource intensive applications can easily route external or gated internal clocks using global routing spines. Users can also drastically reduce delay penalties and save buffering resources by mapping critical high-fanout nets to spines. For design hints on using these features, refer to Actel's Efficient Use of ProASIC Clock Trees application note. High Performace Global Network I/O RING PAD RING PAD RING Low Skew Global Networks Global Pads Global Pads Global Spine I/O RING Global Ribs Scope of Spine PAD RING Note: This figure shows routing for only one global path. Figure 7 * High Performance Global Network Advanced v0.6 9 Pr o A S I C P L U S F a m ily F la s h F P GA s Table 1 * Number of Clock Spines APA150 APA300 APA450 APA600 APA750 APA1000 Top Spine Height 24 32 32 48 64 80 Tiles in Each Top Spine 768 1,024 1,024 1,536 2,048 2,560 Bottom Spine Height 24 32 32 48 64 80 Tiles in Each Bottom Spine 768 1,024 1,024 1,536 2,048 2,560 Global Clock Networks (Trees) 4 4 4 4 4 4 Clock Spines/Tree 8 8 12 14 16 22 Total Spines 32 32 48 56 64 88 6,144 8,192 12,288 21,504 32,768 56,320 Total Tiles Inpu t/ Out put Blo cks To meet complex system demands, the ProASICPLUS family offers devices with a large number of user I/O pins, up to 712 on the APA1000. If the I/O pad is powered at 3.3V, each I/O can be selectively configured at the 2.5V and 3.3V threshold levels. Table 2 shows the available supply voltage configurations (the PLL block uses an independent 2.5V supply). Figure 8 illustrates I/O interfaces with global networks. All I/Os include ESD protection circuits. Each I/O has been tested to 2000V to the human body model (per MIL-STD-883, Method 3015). I/O PAD Standard I/O Pad Cell Global MUX Driver Six or seven standard I/O pads are grouped with a GND pad and either a VDD or VDDP pad. Two reference bias signals ring the chip. One protects the cascaded output drivers while the other creates a virtual VDD supply for the I/O ring. Table 2 * ProASICPLUS Power Supply Voltages VDDP 2.5V 3.3V Input Tolerance 2.5V 3.3V, 2.5V Output Drive 2.5V 3.3V, 2.5V Notes: 1. VDD is always 2.5V. 2. There is no requirement for power-supply sequencing for ProASICPLUS devices. PC<0:4> P<1,2> P<0> I/O Tile X PC<0:4> P<1,2> P<0> I/O Tile A HC<A> GL<A> PAD Standard I/O Pad Cell GL<B> PAD Standard I/O Pad Cell PC<0:4> P<1,2> P<0> PC<0:4> P<1,2> P<0> Global MUX Driver PC<0:4> P<1,2> P<0> I/O Tile GA I/O Tile GB I/O Tile B HC<B> GL<B> PPECL GL<B> NPECL PAD PECL Input Pad Cell PAD Figure 8 * ProASICPLUS Global I/O Scheme with Multiplexed Global Pads 10 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s I/O pads are fully configurable to provide the maximum flexibility and speed. Each pad can be configured as an input, an output, a tristate driver, or a bidirectional buffer (Figure 9). I/O pads configured as inputs have the following features: * Individually selectable 2.5V or 3.3V threshold levels1 * Optional pull-up resistor I/O pads configured as outputs have the following features: * Individually selectable 2.5V or 3.3V compliant output signals1 LV PE C L In put P ads In addition to standard I/O pads and power pads, ProASICPLUS devices have a PECL input pad at each end of each of the global MUX lines, along with AVDD and AGND pins to power the PLL block. The PECL input pad cell is different from the standard I/O cell. It is operated from VDD only. Since it is exclusively an input, it requires no output signal, output enable signal or output configuration bits. As a special high-speed differential input, it also does not require pull ups. The PECL pad cell (Figure 10) consists of an input buffer (containing a low voltage differential amplifier, whose power is enabled by the PC<0> and CL<1> signals, and a cascaded buffer), and a signal and its compliment (PPECL and NPECL). The PECL pad cell compares voltages on the PPECL pad and the NPECL pad and sends the results to the global MUX over the P<0> wire. This high speed, low skew output essentially controls the clock conditioning circuit. * 3.3V PCI compliant * Ability to drive LVTTL and LVCMOS levels * Selectable drive strengths * Selectable slew rates * Tristate I/O pads configured as bidirectional buffers have the following features: * Individually selectable 2.5V or 3.3V output signals and threshold levels1 CORE & GLOBAL MUX CL<1> * 3.3V PCI compliant * Optional pull-up resistor * Optionally configurable as Schmitt Trigger input2 * Selectable drive strengths * Selectable slew rates * Tristate 3.3V/2.5V Signal Control Pull-up Control P<0> PC<0> input buffer PPECL pad + ESD PPECL protection PAD + clamp NPECL PAD NPECL pad + ESD protection + clamp Figure 10 * High Speed PECL Pad Cell Block Diagram Y EN A Pad 3.3V/2.5V Signal Control Drive Strength and Slew Rate Control Figure 9 * I/O Block Schematic Representation 1. If pads are configured for 2.5V operation, they are compliant with 2.5V level signals as defined by JEDEC JESD 8-5. If pads are configured for 3.3V operation, they are compliant with the standard as defined by JEDEC JESD 8-A (LVTTL and LVCMOS). 2. The Schmitt Trigger input option can be configured as an input only, not a bidirectional buffer. This input type may be slower than a standard input under certain conditions and has typical hysteresis of about 0.3V. Advanced v0.6 11 Pr o A S I C P L U S F a m ily F la s h F P GA s Bou ndar y S can PLUS (test data input and output), TMS (test mode selector) and TRST (test reset input). TMS, TDI and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. These pins are dedicated for boundary-scan test usage. ProASIC devices are compatible with IEEE Standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. The basic ProASICPLUS boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers, and instruction register (Figure 11). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS), the optional IDCODE instructions and private instructions used for device programming and factory testing. The TAP controller is a four-bit state machine (16 states) that operates as shown in Figure 12 on page 13. The `1's and `0's represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI, and TDO I/O I/O I/O I/O I/O TDI Test Data Registers TAP Controller Instruction Register Device Logic TDO I/O TRST I/O TMS I/O TCK I/O Bypass Register I/O I/O I/O Figure 11 * ProASICPLUS JTAG Boundary Scan Test Logic Circuit 12 Advanced v0.6 I/O I/O Pr o A SI C P L U S F a m ily F la s h F P GA s The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. The TRST pin may also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. ProASICPLUS devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device 1 Test-Logic Reset 0 0 Run-Test/ Idle 1 identification register is a shift register with four fields (LSB, ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pins. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary scan register chain which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O. 1 Select-DRScan 0 Scan 0 Capture-DR 1 Capture-IR 1 0 0 0 Shift-DR 0 0 1 1 0 0 Pause-IR 1 1 Exit2-DR 0 Exit2-IR 1 Update-DR 0 1 1 Exit-IR Pause-DR 0 0 Shift-IR 1 Exit-DR 1 Select-IR- 1 Update-IR 1 0 Figure 12 * TAP Controller State Diagram Advanced v0.6 13 Pr o A S I C P L U S F a m ily F la s h F P GA s U se r S e c u r it y PLUS The ProASIC devices have read-protect bits that, once programmed, block the entire programmed contents from being read externally. If locked, the user can only reprogram the device using the security key. This protects it from being read back and duplicated. Since programmed data is stored in nonvolatile memory cells (which are actually very small capacitors), rather than in the wiring, physical deconstruction cannot be used to compromise data. This approach is further hampered by the placement of the memory cells, beneath the four metal layers (whose removal cannot be accomplished without disturbing the charge in the capacitor). This is the highest security provided in the industry. For more information, refer to Actel's Design Security in Nonvolatile Flash and Antifuse FPGAs white paper. E m bedde d M em or y Flo orp lan The embedded memory is located across the top of the device (see Figure 1 on page 5) in 256x9 blocks. Depending upon the device, up to 88 blocks are available to support a variety of memory configurations. Each block can be programmed as an independent memory or combined (using dedicated memory routing resources) to form larger, more complex memories. A single memory configuration cannot include blocks from both the top and bottom memory locations. E m bed ded Mem or y Co nfig ur ati ons PLUS The embedded memory in the ProASIC family provides great configuration flexibility. Other programmable vendors typically use single port memories that can only be transformed into two-port memories by sacrificing half the memory. Each ProASICPLUS block is designed and optimized as a two-port memory (1 read, 1 write). This provides 198k bits of total memory for two-port and single port usage in the APA1000 device. Each memory can be configured as FIFO or SRAM, with independent selection of synchronous or asynchronous read and write ports (Table 3). Additional characteristics include programmable flags as well as parity checking and generation. Figure 13 on page 15 and Figure 14 on page 16 show the block diagrams of the basic SRAM and FIFO blocks. These memories are designed to operate at up to 150 MHz when operated individually. Each block contains a 256 word, 9-bit wide (1 read, 1 write) memory. The memory blocks may be combined in parallel to form wider memories or stacked to form deeper memories (Figure 15 on page 16). This provides optimal bit widths of 9 (1 block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1024. Refer to the Actel's Macro Library Guide for more information. Figure 16 on page 17 gives an example of optimal memory usage. Ten blocks with 23,040 bits have been used to generate three memories of various widths and depths. Figure 17 on page 17 shows how memory can be used in parallel to create extra read ports. In this example, using only 10 of the 88 available blocks of the APA1000 yields an effective 6,912 bits of multiple port memories. The Actel ACTgen software facilitates building wider and deeper memories for optimal memory usage. Table 3 * Basic Memory Configurations Type Write Access Read Access Parity Library Cell Name RAM Asynchronous Asynchronous Checked RAM256x9AA RAM Asynchronous Asynchronous Generated RAM256x9AAP RAM Asynchronous Synchronous Transparent Checked RAM256x9AST RAM Asynchronous Synchronous Transparent Generated RAM256x9ASTP RAM Asynchronous Synchronous Pipelined Checked RAM256x9ASR RAM Asynchronous Synchronous Pipelined Generated RAM256x9ASRP RAM Synchronous Asynchronous Checked RAM256x9SA RAM Synchronous Asynchronous Generated RAM256xSAP RAM Synchronous Synchronous Transparent Checked RAM256x9SST RAM Synchronous Synchronous Transparent Generated RAM256x9SSTP RAM Synchronous Synchronous Pipelined Checked RAM256x9SSR RAM Synchronous Synchronous Pipelined Generated RAM256x9SSRP FIFO Asynchronous Asynchronous Checked FIFO256x9AA FIFO Asynchronous Asynchronous Generated FIFO256x9AAP FIFO Asynchronous Synchronous Transparent Checked FIFO256x9AST FIFO Asynchronous Synchronous Transparent Generated FIFO256x9ASTP 14 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s Table 3 * Basic Memory Configurations (Continued) Type Write Access Read Access Parity Library Cell Name FIFO Asynchronous Synchronous Pipelined Checked FIFO256x9ASR FIFO Asynchronous Synchronous Pipelined Generated FIFO256x9ASRP FIFO Synchronous Asynchronous Checked FIFO256x9SA FIFO Synchronous Asynchronous Generated FIFO256x9SAP FIFO Synchronous Synchronous Transparent Checked FIFO256x9SST FIFO Synchronous Synchronous Transparent Generated FIFO256x9SSTP FIFO Synchronous Synchronous Pipelined Checked FIFO256x9SSR FIFO Synchronous Synchronous Pipelined Generated FIFO256x9SSRP DI <0:8> WADDR <0:7> WRB WBLKB WCLKS SRAM (256 X 9) Sync Write & Sync Read Ports DO <0:8> RADDR <0:7> DI <0:8> WADDR <0:7> RDB WRB RBLKB RCLKS WBLKB PARODD DI <0:8> WADDR <0:7> WRB WBLKB WCLKS Sync Write & Async Read Ports RADDR <0:7> DI <0:8> WADDR <0:7> WRB RDB RBLKB WBLKB RPE WPE RBLKB DO <0:8> SRAM (256 X 9) Async Write & Sync Read Ports RADDR <0:7> RDB RBLKB RCLKS RPE WPE PARODD Note: RDB PARODD DO <0:8> SRAM (256 X 9) DO <0:8> RADDR <0:7> RPE WPE RPE WPE SRAM (256 X 9) Async Write & Async Read Ports PARODD For memory block interface signal definitions, see Table 4 on page 35 Figure 13 * Example SRAM Block Diagrams Advanced v0.6 15 Pr o A S I C P L U S F a m ily F la s h F P GA s DI<0:8> LEVEL<0:7> DI <0:8> LEVEL <0:7> DO <0:8> LGDEP<0:2> WRB WBLKB LGDEP<0:2> WRB WBLKB RDB WPE FIFO (256 X 9) Sync Write & Sync Read Ports DO <0:8> RPE FULL RDB EMPTY RBLKB RBLKB EQTH PARODD WPE FIFO (256 X 9) Sync Write & Async Read Ports RPE FULL EMPTY EQTH PARODD GEQTH GEQTH WCLKS WCLKS RESET RCLKS WRB WBLKB RDB RBLKB WRB WBLKB WPE FIFO (256 X 9) Async Write & Sync Read Ports DO <0:8> DI <0:8> LEVEL <0:7> LGDEP<0:2> DO <0:8> DI <0:8> LEVEL <0:7> LGDEP<0:2> RPE FULL EMPTY RDB EQTH PARODD WPE FIFO (256 X 9) Async Write & Async.Read Ports RPE FULL EMPTY EQTH RBLKB GEQTH GEQTH PARODD RCLKS Note: RESET For memory block FIFO signal definitions, see Table 5 on page 46. Figure 14 * Basic FIFO Block Diagrams 9 Word Width 9 9 9 9 9 9 9 Word Depth 256 256 256 256 256 88 blocks Figure 15 * APA1000 Memory Block Architecture 16 256 256 ... 256 256 9 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s Word Width 9 9 Word 256 Depth 256 256 256 9 9 9 256 256 words x 18 bits, 1 read, 1 write 512 words x 18 bits, 1 read, 1 write 256 256 1,024 words x 9 bits, 1 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 23,040 Figure 16 * Example Showing Memories with Different Widths and Depths Word Width 9 Write Port 9 9 Word Depth 9 Write Port 256 256 Read Ports 256 words x 9 bits, 2 read, 1 write Read Ports 1,024 words x 9 bits, 4 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 6,912 Figure 17 * Multiport Memory Usage D es i gn E nv i r on m e nt PLUS ProASIC devices are supported by Actel's Designer Series, as well as third party CAE tools. Unlike some FPGA vendors, no special HDL design techniques are needed when using the standard VHDL or Verilog HDL descriptions. As a result, designers may utilize technology independent of HDL code for ProASICPLUS devices. This feature and the ASIC-like design flow ensure a seamless transition to an ASIC implementation, if desired (Figure 18 on page 18). ACTgen, included in Actel's Designer Series, can be used to automatically generate memories based on user inputs. The design engineer can select the depth and width, usage of parity generation or check, and synchronous or asynchronous functionality of the ports. For a synchronous read port, the user can choose whether the output is pipelined or transparent. Designer allows any bit width up to 252. However, when an intermediate bit width, such as 16 bits, is chosen, the remaining two bits are not accessible for other memories. Actel's Designer also enables optimal memory stacking in 256 word increments. However, any word depth may be combined for up to 22,528 words. ACTgen also allows the user to generate distributed memory. Advanced v0.6 17 Pr o A S I C P L U S F a m ily F la s h F P GA s Place and route is also performed by Actel's Designer software. Available for UNIX workstations and PC platforms, Designer accepts standard netlists in Verilog, VHDL, and EDIF formats, performs place and route of the design into the selected device, and provides postlayout delay information for back-annotation simulation and static timing analysis. Actel's Designer can also generate the BSDL (boundary-scan description language) files required for documenting the IEEE 1149.1 components which can be used by automatic test equipment software. ACTgen provides all the software needed for configuration of the PLL clock conditioning circuit. While the PLL has no placement mobility, ACTgen allows users to use placement and routing floorplan constraints hierarchically, in order to more easily and efficiently explore floorplan alternatives. This allows the power of the PLL circuitry to be utilized with minimal top level timing loop iterations. Once the design is finalized, the programming bitstream is downloaded into the device programmer for programming the ProASICPLUS part. ProASICPLUS devices can be programmed with the Silicon Sculptor II and Flash Pro programmers. Additionally, in-system programming is available. For details on ProASICPLUS programming, refer to the application note, Performing Internal In-System Programming Using Actel's ProASICPLUS Devices. Design Creation/Verification Actel's Designer also contains the necessary information for the placing, routing, and configuration of the clock conditioning circuit. High-Level Design (Verilog or VHDL) Verilog or VHDL Simulator Synthesis Tool Synthesis Library Forward Constraints Structural Netlist Design Implementation P&R User Constraints Designer ACTgen (P&R Tool) Backannotation Programming Programming Data Silicon Sculptor II Flash Pro Timing and Simulation SDF Timing File Timing Libraries Verilog or VHDL Simulator Timing Analyzer Figure 18 * Design Flow 18 Simulation Library Advanced v0.6 Simulation Library Pr o A SI C P L U S F a m ily F la s h F P GA s Pa c ka ge T he r m a l C ha r a ct e r i s t i c s The ProASICPLUS family is available in several package types with a range of pin counts. Actel has selected packages based on high pin count, reliability factors, and superior thermal characteristics. Thermal resistance defines the ability of a package to conduct heat away from the silicon, through the package, to the surrounding air. Junction-to-ambient thermal resistance is measured in degrees Celsius/Watt and is represented as Theta ja (ja). The lower thermal resistance, the more efficiently a package will dissipate heat. A package's maximum allowed power (P) is a function of maximum junction temperature (TJ), maximum ambient operating temperature (TA), and junction-to-ambient thermal resistance ja. Maximum junction temperature is the maximum allowable temperature on the active surface of the IC and is 110 C. P is defined as: TJ - TA P = ---------------- ja ja is a function of the rate (in linear feet per minute - lfpm) of airflow in contact with the package. When the estimated power consumption exceeds the maximum allowed power, other means of cooling, such as increasing the airflow rate, must be used. Pin Count jc ja Still Air ja 300 ft./min Units Plastic Quad Flat Pack (PQFP) 208 8 30 23 C/W PQFP with Heatspreader 208 3.8 20 17 C/W Fine Ball Grid Array (FBGA) 144 3.8 38.8 26.7 C/W Fine Ball Grid Array (FBGA) 256 3.0 30 25 C/W Plastic Ball Grid Array (PBGA) 456 3 18 14.5 C/W Fine Ball Grid Array (FBGA) 676 3.2 15 11.5 C/W Fine Ball Grid Array (FBGA) 896 2.0 10.9 7.9 C/W Fine Ball Grid Array (FBGA) 1152 2.0 11.2 7.0 C/W Package Type Advanced v0.6 19 Pr o A S I C P L U S F a m ily F la s h F P GA s C al c ul a t i n g P o w er Di s si p a t i on * Pdc = 10 mW * Pac = Pclock + Pstorage + Plogic + Pios + Pmemory Plogic, the logic-tile component of AC power dissipation, is given by Plogic = P3 * mc * Fs where: * P3 = 3.0 uW/MHz, is the average power consumption of a logic-tile normalized per MHz of its output frequency * mc = the number of logic tiles switching during each Fs cycle * Fs = the clock frequency Pclock, the clock component of power dissipation, is given by Pclock = (P1 + P2 * s) * Fs where: * P1 = 2500 uW/MHz is the basic power consumption of the clock tree normalized per MHz of the clock. * P2 = 1.0 uW/MHz is the extra power consumption of the clock tree per storage tile - also normalized per MHz of the clock * s = the number of storage tiles clocked by this clock * Fs = the clock frequency Pios, the I/O component of AC power dissipation, is given by Pios = (P4 + Cload * Vddp^2) * p * Fp where: * P4 = 60.0 uW/MHz is the average power consumption of an output pad normalized per MHz of its output frequency (internal power-load is not included) * Cload = the output load * p = the number of outputs * Fp = the average output frequency Pstorage, the storage-tile component of AC power dissipation, is given by Pstorage = P5 * ms * Fs where: * P5 = 1.0 uW/MHz is the average power consumption of a storage-tile normalized per MHz of its output frequency * ms = the number of storage tiles switching during each Fs cycle * Fs = the clock frequency Finally, Pmemory, the memory component of AC power consumption, is given by Pmemory = P6 * Nmem * Fmem where: * P6 = 100.0 uW/MHz is the average power consumption of a memory block normalized per MHz of the clock * Nmem = the number of RAM/FIFO blocks (1 block = 256 words * 9 bits) * Fmem = the clock frequency of the memory ProASICPLUS device power is calculated with both a static and an active component. The active component is a function of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following formula: Ptotal = Pdc + Pac where: 20 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s The following is an APA750 example using a shift register design with 13,440 storage tiles and 0 logic tiles. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as follows: Pclock * Fs = 10 MHz * s = 13,440 => Pclock = (P1 + P2 * s) * Fs = 159.4 mW Pstorage * ms = 13,440 (in a shift register 100% of storage-tiles are toggling at each clock cycle and Fs = 10 MHz) * mc = 0 (no logic tile in this shift-register) => => => 347.9 mW Ptotal Pdc + Pac = 357.9mW P ower Cons um pt io n o f an A PA D evi ce Pstorage = P5 * ms * Fs = 134.4 mW 40 pF 3.3 V 24 Plogic = 0 mW Pmemory = 0 mW Pac 1000 Power Consumption (mW) => Plogic * Cload = * Vddp = * p = Pios * Fp = 5 MHz => Pios = (P4 + Cload * Vddp^2) * p * Fp = 54.1 mW Pmemory Nmem = 0 (no RAM/FIFO in this shift-register) ProASIC SRAM 900 800 700 600 500 400 300 200 110 instances of 16-bit binary counters 100 0 20 30 40 50 60 70 80 90 100 120 Frequency (MHz) Advanced v0.6 21 Pr o A S I C P L U S F a m ily F la s h F P GA s O pe r a t i ng C on d i t i on s Abs ol ut e M axim u m Ra ti ngs Parameter Condition Minimum Maximum Units Supply Voltage (VDD) -0.3 3.0 V Supply Voltage I/O Ring (VDDP) -0.3 4.0 V DC Input Voltage -0.3 VDDP + 0.3 V PCI DC Input Voltage -0.5 VDDP + 0.5 V -10 +10 mA 0 2.5 V DC Input Clamp Current VIN < 0 or VIN> VDDP PECL Input Voltage P rog ra m mi ng and S to ra ge T em p er atu re Li m it s Storage Temperature Product Grade Programming Cycles Program Retention Min. Max. Commercial 100 20 years -55C 110C Industrial 100 20 years -55C 110C S uppl y Vol t ages Mode VDD VDDP VPP VPN Single Voltage 2.5V 2.5V 0 VPP 16.5V -13.8V VPN 0V Mixed Voltage 2.5V 3.3V 0 VPP 16.5V -13.8V VPN 0V Rec om m ende d Op era ti ng Con dit io ns Parameter Symbol Limits VDD & VDDP VDDP VDD TA TJ fCLOCK fRAM 2.3V to 2.7V 3.0V to 3.6V 2.3V to 2.7V 0C to 70C 110C 240 MHz 150 MHz VDD & VDDP VDDP VDD TA TJ fCLOCK fRAM 2.3V to 2.7V 3.0V to 3.6V 2.3V to 2.7V -40C to 85C 110C 240 MHz 150 MHz Commercial DC Supply Voltage (2.5V I/Os) DC Supply Voltage (Mixed 2.5V, 3.3V I/Os) Operating Ambient Temperature Range Maximum Operating Junction Temperature Maximum Clock Frequency Maximum RAM Frequency Industrial DC Supply Voltage (2.5V I/Os) DC Supply Voltage (2.5V, 3.3V I/Os) Operating Ambient Temperature Range Maximum Operating Junction Temperature Maximum Clock Frequency Maximum RAM Frequency 22 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s DC E le ct ri cal S peci fic at ions ( V D D P = 2. 5V + / -0. 2V) Symbol Parameter Conditions Output High Voltage High Drive (OB25LPH) IOH = -6 mA IOH = -12 mA IOH = -24 mA 2.1 2.0 1.7 Low Drive (OB25LPL) IOH = -4 mA IOH = -6 mA IOH = -10 mA 2.1 2.0 1.7 VOH Min. Typ. Max. Units V Output Low Voltage High Drive (OB25LPH) VOL Low Drive (OB25LPL) IOL = 8 mA IOL = 15 mA IOL = 24 mA 0.2 0.4 0.7 IOL = 4 mA IOL = 8 mA IOL = 15 mA 0.2 0.4 0.7 V VIH Input High Voltage 1.7 VDDP + 0.3 V VIL Input Low Voltage -0.3 0.7 V RWEAKPULLUP Weak Pull-up Resistance (OTB25LPU) 10 30 k -250 - 80 A -10 10 A 10 mA 10 A VIN 1.25 with pull up (VIN = VSS) Input Current Input Current without pull up (VIN = VSS or VDD) IDDQ Quiescent Supply Current (standby) VIN = VSS2 or VDD IOZ 3-State Output Leakage Current VOH = VSS or VDD -10 High Drive (OB25LPH) VIN = VSS Low Drive (OB25LPL) VIN = VSS -120 -100 IIN 5.0 Output Short Circuit Current High IOSH mA Output Short Circuit Current Low IOSL High Drive (OB25LPH) VIN = VDDP 100 Low Drive (OB25LPL) VIN = VDDP 30 mA CI/O I/O Pad Capacitance 10 pF CCLK Clock Input Pad Capacitance 10 pF Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. No pull-up resistor. Advanced v0.6 23 Pr o A S I C P L U S F a m ily F la s h F P GA s DC E le ct ri cal S peci fic at ions ( V D D P = 3. 3V + / -0. 3V and V D D 2. 5+ / -0. 2V) Symbol Parameter Output High Voltage 3.3V I/O, High Drive (OB33P) Conditions Min. IOH = -15 mA IOH = -30 mA 0.9VDDP 2.4 IOH = -7 mA IOH = -14 mA 0.9VDDP 2.4 IOH = -0.1 mA IOH = -0.5 mA IOH = -4 mA 2.1 2.0 1.7 IOH = -0.1 mA IOH = -0.5 mA IOH = -2.5 mA 2.1 2.0 1.7 Typ. Max. Units V 3.3V I/O, Low Drive (OB33L) VOH Output High Voltage 2.5V I/O, High Drive (OB25H) V 2.5V I/O, Low Drive (OB25L) Output Low Voltage 3.3V I/O, High Drive (OB33P) IOL = 15 mA IOL = 20 mA 0.1VDDP 0.4 IOL = 7 mA IOL = 10 mA 0.1VDDP 0.4 IOL = 7 mA IOL = 14 mA IOL = 28 mA 0.2 0.4 0.7 IOL = 5 mA IOL = 10 mA IOL = 15 mA 0.2 0.4 0.7 V 3.3V I/O, Low Drive (OB33L) VOL Output Low Voltage 2.5V I/O, High Drive (OB25H) V 2.5V I/O, Low Drive (OB25L) Input High Voltage 3.3V LVTTL/LVCMOS 2.5V Mode Input Low Voltage VIL 3.3V LVTTL/LVCMOS 2.5V Mode Weak Pull-up Resistance RWEAKPULLUP (OTB33U) Weak Pull-up Resistance RWEAKPULLUP (OTB25U) VIH Input Current IIN IDDQ IOZ IOSH VDDP + 0.3 VDDP + 0.3 0.3 0.3 0.8 0.7 V VIN 1.5 15k 25k k VIN 1.5 10k 20k k -300 --10 -80 10 A A 10 mA 10 A with pull up (VIN = VSS) without pull up (VIN = VSS or VDD) Quiescent Supply Current (standby) 3-State Output Leakage Current Output Short Circuit Current High 3.3V High Drive (OB33P) 3.3V Low Drive (OB33L) VIN = VSS VIN = VSS 200 100 2.5V High Drive (OB25H) 2.5V Low Drive (OB25L) VIN = VSS VIN = VSS 20 10 VIN = VSS2 or VDD VOH = VSS or VDD Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. No pull-up resistor. 24 V 2 1.7 Advanced v0.6 5.0 --10 mA Pr o A SI C P L U S F a m ily F la s h F P GA s DC E le ct ri cal S peci fic at ions ( V D D P = 3. 3V + / -0. 3V and V D D 2. 5+ / -0. 2V) (C ont inu ed) Symbol IOSL Parameter Conditions Output Short Circuit Current Low 3.3V High Drive 3.3V Low Drive VIN = VDD VIN = VDD 2.5V High Drive 2.5V Low Drive I/O Pad Capacitance Clock Input Pad Capacitance Min. Typ. Max. Units 2 00 100 mA VIN = VDD VIN = VDD 2 00 100 10 10 CI/O CCLK Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. No pull-up resistor. pF pF DC S pec if i cat ion s (3.3 V P C I Op era ti on) Symbol Parameter VDD Min. Max. Units Supply Voltage for Core 2.3 2.7 V VDDP Supply Voltage for I/O Ring 3.0 3.6 V VIH Input High Voltage 0.5VDPP VDPP + 0.5 V VIL Input Low Voltage -0.5 0.3VDDP V IIPU Input Pull-up Condition Voltage1 IIL Input Leakage VOH VOL Current2 0.7VDDP 0 < VIN < VCCI -10 Output High Voltage IOUT = -500 A 0.9VDPP Output Low Voltage IOUT = 1500 A Capacitance3 CIN Input Pin CCLK CLK Pin Capacitance 5 V +10 A V 0.1VDPP V 10 pF 12 pF Notes: 1. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this input voltage. 2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). Advanced v0.6 25 Pr o A S I C P L U S F a m ily F la s h F P GA s AC Specifications (3.3V PCI Revision 2.2 Operation) Symbol Parameter Condition Min. 0 < VOUT 0.3VCCI * Switching Current High IOH(AC) 0.3VCCI VOUT < 0.9VCCI * -12VCCI mA (-17.1 + (VDDP - VOUT)) mA VOUT = 0.7VCC * -32VCCI VCCI > VOUT 0.6VCCI * 0.6VCCI > VOUT > 0.1VCCI 1 mA (26.7VOUT) mA See page 21, equation B of PCI rev. 2.2 spec 0.18VCCI > VOUT > 0 * (Test Point) VOUT = 0.18VCC * ICL Low Clamp Current -3 < VIN -1 ICH High Clamp Current slewR 38VCCI mA -25 + (VIN + 1)/0.015 mA VCCI + 4 > VIN VCCI + 1 25 + (VIN - VDDP - 1)/0.015 mA Output Rise Slew Rate 0.2VCCI to 0.6VCCI load * 1 4 V/ns Output Fall Slew Rate 0.6VCCI to 0.2VCCI load * 1 4 V/ns * Refer to the PCI Specification document rev. 2.2. pin 1/2 in. max. output buffer 10 pF 1k pin output buffer 26 mA 16VDDP Switching Current Low IOL(AC) Note: Units 0.7VCCI < VOUT < VCCI * (Test Point) slewF Max. 1k 10 pF Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s Ti m i ng C on t r o l an d Ch a r ac t e r i s t i cs Cl ock Con dit io nin g C ir cui t PLUS ProASIC devices provide designers with very flexible clocking capabilities. Each side of the chip contains a clock conditioning circuit based upon a 240 MHz phase-locked loop (PLL) block (Figure 19 on page 28). Two global multiplexed lines extend along each side of the chip to provide bidirectional access to the PLL on that side (neither MUX can be connected to the opposite side's PLL). Each global line has optional PECL input pads (described below). The global lines may be driven by either the PECL global input pad or the outputs from the PLL block or both. Each can be driven by a different output from the PLL. The 2 signals available to drive the global networks are as follows: Global A: * Output from Global MUX A * Conditioned version of PLL output (fOUT) - Delayed or advanced - 0, 90, 180, and 270 phase shift (with optional time advance) * Divided version of either of the above * Delayed version of either of the above (0.25ns, 0.50ns, or 4.00ns delay).3 Global B: * Output from Global MUX B * Delayed or advanced version of fOUT * Divided version of either of the above * Delayed version of either of the above (0.25ns, 0.50ns, or 4.00ns delay).3 Each PLL block contains four programmable dividers as shown in Figure 20 on page 28. The first (n) provides all integer divisors from 1 to 16. The second and third (u and v) permit the signal applied to the global network to be further divided by factors of 2, 3 or 4. The fourth divider (m, located in the direct feedback path) is controlled by 6 bits, allowing the incoming clock signal to be multiplied by integer factors from 1 to 64. The implementations m/(n*u) and m/(n*v) enable the user to define a wide range of multipliers and divisors factors. The clock conditioning circuit can advance or delay the clock up to 4ns (in increments of 0.25ns) relative to the positive edge of the incoming reference clock. The system also allows for the selection of output frequency clock phases of 0, 90, 180, and 270. A "lock" signal is provided to indicate that the PLL has locked to the incoming signal, and a "standby" signal switches the PLL block off when it is not locked to a signal. That allows pre-selected signals to be passed directly through, at least to the corresponding rib drivers. Prior to the application of signals to the rib drivers, they pass through programmable delay units, one per global network. These units permit the delaying of global signals relative to other signals to assist in the control of input set-up times. Not all possible combinations of input and output mode can be used. The degrees of freedom available in the bidirectional global pad system and in the clock conditioning circuit have been restricted. This avoids unnecessary and unwieldy design kit and software work. The PLL can be configured internally during design (via Flash-configuration bits set in the programming bitstream) or externally during operation. This is done through a simple, dynamically accessible asynchronous interface - a dedicated register file, which allows user signals to initiate parameter changes, such as PLL divide/multiply ratios. For information on the clock conditioning circuit, refer to the, Using ProASICPLUS Clock Conditioning Circuits application note. 3. This mode is available through the delay feature of the Global MUX driver. Advanced v0.6 27 Pr o A S I C P L U S F a m ily F la s h F P GA s AVDD AGND VDD GND + LVPECL Output A - Global MUX A OUT Output B PLL Block Clock from Core Global MUX B OUT External Feedback Signal 8 24 4 To/From Mask Programmable Delay Dynamic Configuration Bits Flash Configuration Bits Dynamic Configuration Bit Inputs Dynamic Configuration Bit Outputs Stand-by mode of Core Data In Shift Clock Shift Enable Update NVM/Register Mode (Other three bits used for flash configuration) Lock Detect Data Out GND ( Spare 1) GND (Spare 2) Figure 19 * PLL Block - Top-Level View Global MUX A OUT /n 270 180 90 0 PLL Core /m /u D Output A D D External Feedback /v Global MUX B OUT Figure 20 * PLL Block - Detailed Block Diagram 28 Advanced v0.6 D Output B Pr o A SI C P L U S F a m ily F la s h F P GA s Logi c Ti le T im i ng C har act er is t ics PLUS Hig h S pee d V er y Long Li nes Timing characteristics for ProASIC devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all ProASICPLUS family members. Internal routing delays are device dependent. Design dependency means that actual delays are not determined until after placement and routing of the user's design are complete. Delay values may then be determined by using the Timer utility or performing simulation with post-layout delays. Cr it ic al Net s and T ypi cal Ne ts Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6 percent of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. Refer to the Actel Designer User's Guide for details on using constraints. Some nets in the design are very long lines, which are special routing resources that span multiple rows, columns or modules. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6 percent of nets in a fully utilized device require very long lines. Very long lines contribute from 4ns to 8.4ns routing delay. This additional delay is represented statistically in higher fanout routing delays. T im in g D er at ing Since ProASICPLUS devices are manufactured with a CMOS process, device performance will vary with temperature, voltage, and process. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and optimal process variations. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case process variations (within process specifications). Advanced v0.6 29 Pr o A S I C P L U S F a m ily F la s h F P GA s Tr i s t a t e B uf f e r D e l a y s EN A PAD OTBx A 50% PAD VOL 50% VOH EN 50% 50% 50% PAD EN 50% 50% VCC PAD GND 10% VOL tDLH tDHL 50% tENZL 50% VOH 90% 50% tENZH Tr i s t a t e B uf f e r D e l a y s ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , 35 p F l oad, T J = 70 C) Max tDLH Max tDHL Max tENZH Max tENZL Units 3.3V, PCI Output Current, High Slew Rate 2.4 2.2 4.4 3.7 ns OTB33PN 3.3V, PCI Output Current, Nominal Slew Rate 2.9 2.7 5.0 5.5 ns OTB33PL 3.3V, PCI Output Current, Low Slew Rate 3.5 3.4 5.5 6.9 ns OTB33LH 3.3V, Low Output Current, High Slew Rate 3.4 3.8 6.2 6.1 ns OTB33LN 3.3V, Low Output Current, Nominal Slew Rate 4.3 4.5 7.0 9.3 ns OTB33LL 3.3V, Low Output Current, Low Slew Rate 4.9 6.3 7.8 12.3 ns OTB25HH 2.5V, High Output Current, High Slew Rate 2.7 2.2 7.2 3.5 ns OTB25HN 2.5V, High Output Current, Nominal Slew Rate 3.5 3.2 7.5 5.1 ns OTB25HL 2.5V, High Output Current, Low Slew Rate 4.2 3.6 8.5 6.4 ns OTB25LH 2.5V, Low Output Current, High Slew Rate 3.9 4.9 10.8 5.4 ns OTB25LN 2.5V, Low Output Current, Nominal Slew Rate 5.7 4.6 11.5 8.4 ns OTB25LL 2.5V, Low Output Current, Low Slew Rate 7.1 6.0 12.4 11.1 ns OTB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate 6.0 1.9 5.3 4.6 ns OTB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate 5.9 2.8 6.2 7.7 ns OTB25LPHL 2.5V, Low Power, High Output Current, Low Slew Rate 5.9 4.3 7.1 9.7 ns OTB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate 9.2 2.7 7.7 8.1 ns OTB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew Rate 9.2 3.8 8.9 12.8 ns OTB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate 9.2 5.4 10.2 17.4 ns Macro Type Description OTB33PH Notes: 1. tDLH = Data-to-Pad HIGH 2. tDHL = Data-to-Pad LOW 3. tENZH = Enable-to-Pad, Z to HIGH 4. tENZL = Enable-to-Pad, Z to LOW 30 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s O ut p u t B uf f e r D e l ay s A A PAD 50% PAD VOL OBx 50% VOH 50% 50% tDLH tDHL O ut p u t B uf f e r D e l ay s ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , 35 p F l oad, T J = 70 C) Max tDLH Max tDHL Max tENZH Max tENZL Units 2.4 2.2 2.6 2.7 ns 3.3V, PCI Output Current, Nominal Slew Rate 2.9 2.7 3.1 3.3 ns OTB33PL 3.3V, PCI Output Current, Low Slew Rate 3.5 3.4 3.7 3.9 ns OTB33LH 3.3V, Low Output Current, High Slew Rate 3.4 3.8 3.6 4.3 ns OTB33LN 3.3V, Low Output Current, Nominal Slew Rate 4.3 4.5 4.5 5.1 ns OTB33LL 3.3V, Low Output Current, Low Slew Rate 4.9 6.3 5.1 6.8 ns OTB25HH 2.5V, High Output Current, High Slew Rate 2.7 2.2 2.9 2.8 ns OTB25HN 2.5V, High Output Current, Nominal Slew Rate 3.5 3.2 3.7 3.8 ns OTB25HL 2.5V, High Output Current, Low Slew Rate 4.2 3.6 4.4 4.1 ns OTB25LH 2.5V, Low Output Current, High Slew Rate 3.9 4.9 4.1 5.4 ns OTB25LN 2.5V, Low Output Current, Nominal Slew Rate 5.7 4.6 5.9 5.2 ns OTB25LL 2.5V, Low Output Current, Low Slew Rate 7.1 6.0 7.4 6.5 ns OTB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate 6.0 1.9 6.2 2.4 ns OTB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate 5.9 2.8 6.1 3.4 ns OTB25LPHL 2.5V, Low Power, High Output Current, Low Slew Rate 5.9 4.3 6.1 4.9 ns OTB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate 9.2 2.7 9.4 3.2 ns OTB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew Rate 9.2 3.8 9.4 4.3 ns OTB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate 9.2 5.4 9.4 5.9 ns Macro Type Description OTB33PH 3.3V, PCI Output Current, High Slew Rate OTB33PN Notes: 1. tDLH = Data-to-Pad HIGH 2. tDHL = Data-to-Pad LOW 3. tENZH = Enable-to-Pad, Z to HIGH 4. tENZL = Enable-to-Pad, Z to LOW Advanced v0.6 31 Pr o A S I C P L U S F a m ily F la s h F P GA s I n pu t B uf f er D e l ay s VCC PAD Y PAD IBx 50% 50% VCC Y GND 0V 50% 50% tINYH tINYL I n pu t B uf f er D e l ay s ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , T J = 70 C , f C L O C K = 2 5 0 M H z ) Macro Type Description IB25 2.5V, CMOS Input Levels, No Pull-up Resistor IB25 2.5V, CMOS Input Levels, No Pull-up Resistor IB25LP 2.5V, CMOS Input Levels, Low Power IB25LPS 2.5V, CMOS Input Levels, Low Power IB33 3.3V, CMOS Input Levels, No Pull-up Resistor IB33S 3.3V, CMOS Input Levels, No Pull-up Resistor Notes: 1. tINYH = Input Pad-to-Y HIGH 2. tINYL = Input Pad-to-Y LOW Max. tINYH Max. tINYL Units 0.5 0.8 1.1 0.9 0.9 1.2 0.8 0.8 0.7 0.9 0.6 0.5 ns ns ns ns ns ns G l ob al I np ut Bu f f e r D e l ay s ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , T J = 70 , f C L O C K = 2 5 0 M H z ) Macro Type Description GL25 GL25S GL25LP GL25LPS GL33 GL33S 2.5V, CMOS Input Levels 2.5V, CMOS Input Levels 2.5V, CMOS Input Levels 2.5V, CMOS Input Levels 3.3V, CMOS Input Levels 3.3V, CMOS Input Levels Max. tINYH Max. tINYL Units 1.9 1.8 1.7 1.9 1.9 2.2 1.6 1.8 2.2 1.9 1.6 1.5 ns ns ns ns ns ns Pr ed i ct ed G l ob a l Ro u t i ng D el a y* ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , T J = 70 C , f C L O C K = 2 5 0 M H z ) Parameter Description tRCKH Input Low to High (fully loaded row--32 inputs) tRCKL Input High to Low (fully loaded row--32 inputs) tRCKH Input Low to High (minimally loaded row--1 input) tRCKL Input High to Low (minimally loaded row--1 input) * The timing delay difference between tile locations is less than 15ps. Max. Units 1.2 1.1 0.9 0.9 ns ns ns ns G l ob al R o ut i ng S ke w ( W or st -C as e C om m er cia l Cond it ion s, V D D P = 3.0 V, V D D = 2 .3V , T J = 70 C , f C L O C K = 2 5 0 M H z ) Parameter Description tRCKSWH tRCKSHH Maximum Skew Low to High Maximum Skew High to Low 32 Advanced v0.6 Max. Units 0.3 0.3 ns ns Pr o A SI C P L U S F a m ily F la s h F P GA s M od u l e D e l ay s A B C A Y 50% 50% B 50% 50% C 50% 50% Y 50% 50% tDAHL 50% tDCLH tDBLH tDALH 50% 50% 50% tDCHL tDBHL Sa m p l e M a c r oc e l l Li b r a r y L i s t i ng ( W or st -C as e C om m er cia l Cond it ion s, V D D = 2.3V , T J = 7 0 C) Maximum Intrinsic Delay Minimum Setup/Hold Cell Name Description NAND2 2-Input NAND 0.4 ns AND2 2-Input AND 0.4 ns NOR3 3-Input NOR 0.4 ns MUX2L 2-1 Mux with Active Low Select 0.4 ns OA21 2-Input OR into a 2-Input AND 0.4 ns XOR2 2-Input Exclusive OR 0.3 ns LDL Active Low Latch (LH/HL) DFFL Negative Edge-Triggered D-type Flip-Flop (LH/HL) Note: Units D: 0.3/0.2 tsetup 0.5 thold 0.2 ns CLK-Q: 0.4/0.4 tsetup 0.4 thold 0.2 ns Assumes fanout of two. Advanced v0.6 33 Pr o A S I C P L U S F a m ily F la s h F P GA s Slew Rates Measured at C = 10pF, Nominal Power Supplies and 25C Type 34 Trig. Lev. Rising Edge Slew Rate Falling Edge Slew Rate pS V/nS pS V/nS OB33PH 20%-60% 397 3.33 390 -3.38 OB33PN 20%-60% 463 2.85 450 -2.93 OB33PL 20%-60% 567 2.33 527 -2.51 OB33LH 20%-60% 467 2.83 700 -1.89 OB33LN 20%-60% 620 2.13 767 -1.72 OB33LL 20%-60% 813 1.62 1100 -1.20 OB25HH 20%-60% 750 1.33 310 -3.23 OB25HN 20%-60% 850 1.18 390 -2.56 OB25HL 20%-60% 1310 0.76 510 -1.96 OB25LH 20%-60% 793 1.26 430 -2.33 OB25LN 20%-60% 870 1.15 730 -1.37 OB25LL 20%-60% 1287 0.78 1037 -0.96 OB25LPHH 20%-60% 470 2.13 433 -2.31 OB25LPHN 20%-60% 533 1.81 527 -1.90 OB25LPHL 20%-60% 770 1.30 753 -1.33 OB25LPLH 20%-60% 597 1.68 707 -1.42 OB25LPLN 20%-60% 873 1.15 760 -1.32 OB25LPLL 20%-60% 1153 0.87 1563 -0.54 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s Em b e dd ed M e m or y S pe ci f i ca t i o ns This section discusses ProASICPLUS SRAM/FIFO embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks (Table 4). Table 3 on page 14 shows basic RAM and FIFO configurations. Simultaneous Read and Write to the same location must be done with care. On such accesses the DI bus is output to the DO bus. Note: Enclosed Timing Diagrams--SRAM Mode: * Synchronous RAM Read, Access Timed Output Strobe (Synchronous Transparent) * Synchronous RAM Read, Pipeline Mode Outputs (Synchronous Pipelined) * Asynchronous RAM Write * Asynchronous RAM Read, Address Controlled, RDB=0 * Asynchronous RAM Read, RDB Controlled * Synchronous RAM Write * Embedded Memory Specifications The difference between synchronous transparent and pipeline modes is the timing of all the output signals from the memory. In transparent mode, the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. If clock cycles are short (high clock speed), the data requires most of the clock cycle to change to valid values (stable signals). Processing of this data in the same clock cycle is thus nearly impossible. Most designers add registers at all outputs of the memory to push the data processing into the next clock cycle. An entire clock cycle can then be used to process the data. To simplify use of this memory setup, suitable registers have been implemented as part of the memory primitive and are available to the user in the synchronous pipeline mode. In this mode, the output signals will change shortly after the second rising edge, following the initiation of the read access. Table 4 * Memory Block SRAM Interface Signals SRAM Signal Bits In/Out WCLKS 1 IN Write clock used on synchronization on write side RCLKS 1 IN Read clock used on synchronization on read side RADDR<0:7> 8 IN Read address RBLKB 1 IN Negative true read block select RDB 1 IN Negative true read pulse WADDR<0:7> 8 IN Write address WBLKB 1 IN Negative true write block select DI<0:8> 9 IN Input data bits <0:8>, <8> can be used for parity in WRB 1 IN Negative true write pulse DO<0:8> 9 OUT Output data bits <0:8>, <8> can be used for parity out RPE 1 OUT Read parity error WPE 1 OUT Write parity error PARODD 1 IN Note: Description Selects odd parity generation/detect when high, even when low Not all signals shown are used in all modes. Advanced v0.6 35 Pr o A S I C P L U S F a m ily F la s h F P GA s Synchronous RAM Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS Cycle Start RBD, RBLKB New Valid Address RADDR Old Data Out DO New Valid Data Out RPE tRACS tRDCS tRDCH tRACH tOCH tRPCH tCMH tCML tOCA tRPCA tCCYC Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns OCA New DO access from RCLKS 7.5 ns OCH Old DO valid from RCLKS RACH RADDR hold from RCLKS 0.5 ns RACS RADDR setup to RCLKS 1.0 ns RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 9.5 ns RPCH Old RPE valid from RCLKS 36 Max. 3.0 3.0 Advanced v0.6 Units ns ns Notes Pr o A SI C P L U S F a m ily F la s h F P GA s Synchronous RAM Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS Cycle Start RDB, RBLKB RADDR New Valid Address DO New Valid Data Out Old Data Out RPE Old RPE Out New RPE Out tRACS tOCA tRACH tRPCH tRDCH tOCH tRDCS tRPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. Max. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns OCA New DO access from RCLKS 2.0 ns OCH Old DO valid from RCLKS RACH RADDR hold from RCLKS 0.5 ns RACS RADDR setup to RCLKS 1.0 ns RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 4.0 ns RPCH Old RPE valid from RCLKS 0.75 1.0 Advanced v0.6 Units Notes ns ns 37 Pr o A S I C P L U S F a m ily F la s h F P GA s Asynchronous RAM Write WADDR WRB, WBLKB DI WPE tAWRS tAWRH tDWRH tWPDA tWPDH tDWRS tWRML tWRMH tWRCYC Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. AWRH WADDR hold from WB 1.0 ns AWRS WADDR setup to WB 0.5 ns DWRH DI hold from WB 1.5 ns DWRS DI setup to WB 0.5 ns PARGEN is inactive DWRS DI setup to WB 2.5 ns PARGEN is active WPDA WPE access from DI 3.0 ns WPE is invalid while WPDH WPE hold from DI ns PARGEN is active WRCYC Cycle time 7.5 ns WRMH WB high phase 3.0 ns Inactive WRML WB low phase 3.0 ns Active 38 Max. 1.0 Advanced v0.6 Units Notes Pr o A SI C P L U S F a m ily F la s h F P GA s Asynchronous RAM Read, Address Controlled, RDB=0 RADDR DO RPE tOAH tRPAH tOAA tRPAA tACYC Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description ACYC Min. Max. Units Read cycle time 7.5 ns OAA New DO access from RADDR stable 7.5 ns OAH Old DO hold from RADDR stable RPAA New RPE access from RADDR stable RPAH Old RPE hold from RADDR stable 3.0 10.0 ns ns 3.0 Advanced v0.6 Notes ns 39 Pr o A S I C P L U S F a m ily F la s h F P GA s Asynchronous RAM Read, RDB Controlled RB=(RDB+RBLKB) DO RPE tORDH tRPRDH tORDA tRPRDA tRDML tRDMH tRDCYC Note: The plot shows the normal operation status. T J = 0 C t o 1 10 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. ORDA New DO access from RB 7.5 ORDH Old DO valid from RB RDCYC Read cycle time 7.5 ns RDMH RB high phase 3.0 ns Inactive setup to new cycle RDML RB low phase 3.0 ns Active RPRDA New RPE access from RB 9.5 ns RPRDH Old RPE valid from RB 40 Max. Notes ns 3.0 3.0 Advanced v0.6 Units ns ns Pr o A SI C P L U S F a m ily F la s h F P GA s Synchronous RAM Write WCLKS Cycle Start WRB, WBLKB WADDR, DI WPE tWRCH, tWBCH tWRCS, tWBCS tDCS, tWDCS tWPCH tDCH, tWACH tWPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns DCH DI hold from WCLKS 0.5 ns DCS DI setup to WCLKS 1.0 ns WACH WADDR hold from WCLKS 0.5 ns WDCS WADDR setup to WCLKS 1.0 ns WPCA New WPE access from WCLKS 3.0 ns WPE is invalid while WPCH Old WPE valid from WCLKS ns PARGEN is active WRCH, WBCH WRB & WBLKB hold from WCLKS 0.5 ns WRCS, WBCS WRB & WBLKB setup to WCLKS 1.0 ns Note: Max. 0.5 Units Notes On simultaneous read and write accesses to the same location DI is output to DO. Advanced v0.6 41 Pr o A S I C P L U S F a m ily F la s h F P GA s Synchronous Write and Read to the Same Location RCLKS DO New Data* Last Cycle Data WCLKS t WCLKRCLKH t WCLKRCLKS t OCH t OCA * New data is read if WCLKS occurs before setup time. The data stored is read if WCLKS occurs after hold time. Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WCLKRCLKS WCLKS to RCLKS setup time - 0.1 ns WCLKRCLKH WCLKS to RCLKS hold time 7.0 ns OCH Old DO valid from RCLKS 3.0 ns OCA New DO valid from RCLKS 7.5 Max. Units ns Notes OCA/OCH displayed for Access Timed Output Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS and RCLKS driven by the same design signal. 3. If WCLKS changes after the hold time, the data will be read. 4. A setup or hold time violation will result in unknown output data. 42 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s Asynchronous Write and Synchronous Read to the Same Location RCLKS New Data* DO Last Cycle Data WB = {WRB + WBLKB} DI t WCLKRCLKS t WCLKRCLKH t OCH t OCA t DWRRCLKS t DWRH * New data is read if WB occurs before setup time. The stored data is read if WB occurs after hold time. Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WBRCLKS WB to RCLKS setup time -0.1 ns WBRCLKH WB to RCLKS hold time 7.0 ns OCH Old DO valid from RCLKS 3.0 ns OCA New DO valid from RCLKS DWRRCLKS DI to RCLKS setup time DWRH DI to WB hold time 7.5 ns 0 ns 1.5 Notes OCA/OCH displayed for Access Timed Output ns Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be read. 3. A setup or hold time violation will result in unknown output data. Advanced v0.6 43 Pr o A S I C P L U S F a m ily F la s h F P GA s Asynchronous Write and Read to the Same Location RB, RADDR DO NEW OLD NEWER WB = {WRB+WBLKB} t ORDA t RAWRH t ORDH t RAWRS t OWRA t OWRH Note: The plot shows the normal operation status. T J = 0 C to 11 0 C ; V D D = 2. 3V t o 2 .7V Symbol txxx Description Min. Max. ORDA New DO access from RB ORDH Old DO valid from RB OWRA New DO access from WB OWRH Old DO valid from WB RAWRS RB or RADDR from WB 5.0 ns RAWRH RB or RADDR from WB 5.0 ns 7.5 Units Notes ns 3.0 3.0 ns ns 0.5 ns Notes: 1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. Violation or RAWRS will disturb access to the OLD data. 3. Violation of RAWRH will disturb access to the NEWER data. 44 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s Synchronous Write and Asynchronous Read to the Same Location RB, RADDR DO NEW OLD NEWER WCLKS t ORDA t RAWCLKH t ORDH t OWRA t OWRH t RAWCLKS Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. Max. ORDA New DO access from RB ORDH Old DO valid from RB OWRA New DO access from WCLKS OWRH Old DO valid from WCLKS RAWCLKS RB or RADDR from WCLKS 5.0 ns RAWCLKH RB or RADDR from WCLKS 5.0 ns 7.5 Units Notes ns 3.0 3.0 ns ns 0.5 ns Notes: 1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. Violation of RAWCLKS will disturb access to OLD data. 3. Violation of RAWCLKH will disturb access to NEWER data. Advanced v0.6 45 Pr o A S I C P L U S F a m ily F la s h F P GA s Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem is created if the FIFO is written during the transition out of full to not full or read during the transition out of empty to not empty. The exact time at which the write (read) operation changes from inhibited to accepted after the read (write) signal which causes the transition from full (empty) to not full (empty) is indeterminate. This indeterminate period starts 1 ns after the RB (WB) transition, which deactivates full (not empty) and ends 3 ns after the RB (WB) transition for slow cycles. For fast cycles, the indeterminate period ends 3 ns (7.5 ns - RDL (WRL)) after the RB (WB) transition, whichever is later (Table 5). The timing diagram for write is shown in Figure 21 on page 47. The timing diagram for read is shown in Figure 22 on page 47. For basic RAM configurations, see Table 3 on page 14. Enclosed Timing Diagrams - FIFO Mode: * Asynchronous FIFO Read * Asynchronous FIFO Write * Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) * Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) * Synchronous FIFO Write * FIFO Reset Table 5 * Memory Block FIFO Interface Signals FIFO Signal Bits In/Out Description WCLKS 1 IN Write clock used for synchronization on write side RCLKS 1 IN Read clock used for synchronization on read side LEVEL <0:7> 8 IN Direct configuration implements static flag logic RBLKB 1 IN Negative true read block select RDB 1 IN Negative true read pulse RESET 1 IN Negative true reset for FIFO pointers WBLKB 1 IN Negative true write block select DI<0:8> 9 IN Input data bits <0:8>, <8> will be generated if PARGEN is true WRB 1 IN Negative true write pulse FULL, EMPTY 2 OUT FIFO flags. FULL prevents write and EMPTY prevents read EQTH, GEQTH 2 OUT EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more DO<0:8> 9 OUT Output data bits <0:8> RPE 1 OUT Read parity error WPE 1 OUT Write parity error LGDEP <0:2> 3 IN Configures DEPTH of the FIFO to 2 (LGDEP+1) PARODD 1 IN Selects odd parity generation/detect when high, even when low 46 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s FULL RB Write cycle Write inhibited Write accepted 1ns 3ns WB Figure 21 * Write Timing Diagram EMPTY WB Read cycle Read inhibited Read accepted 1ns 3ns RB Figure 22 * Read Timing Diagram Advanced v0.6 47 Pr o A S I C P L U S F a m ily F la s h F P GA s Asynchronous FIFO Read Cycle Start RB=(RDB+RBLKB) (Empty inhibits read) RDATA RPE WB EMPTY FULL EQTH, GETH tRDWRS tERDH, tFRDH tORDH tERDA, tFRDA tRPRDH tTHRDH tORDA Note: tTHRDA The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description ERDH, FRDH, THRDH Old EMPTY, FULL, EQTH, & GETH valid hold time from RB ERDA New EMPTY access from RB 3.01 ns FRDA FULL access from RB 3.01 ns ORDA New DO access from RB 7.5 ORDH Old DO valid from RB Min. Max. Units 0.5 ns Notes Empty/full/thresh are invalid from the end of hold until the new access is complete ns 3.0 ns RDCYC Read cycle time 7.5 ns RDWRS WB , clearing EMPTY, setup to 3.02 ns Enabling the read operation ns Inhibiting the read operation RB 1.0 RDH RB high phase 3.0 ns Inactive RDL RB low phase 3.0 ns Active RPRDA New RPE access from RB 9.5 ns RPRDH Old RPE valid from RB 4.0 THRDA EQTH or GETH access from RB 4.5 Notes: 1. At fast cycles, ERDA & FRDA = MAX (7.5 ns - RDL), 3.0 ns 2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns - WRL), 3.0 ns 48 Advanced v0.6 ns ns Pr o A SI C P L U S F a m ily F la s h F P GA s Asynchronous FIFO Write Cycle Start WB=(WRB+WBLKB) WDATA (Full inhibits write) WPE RB FULL EMPTY EQTH, GETH tWRRDS tDWRH tWPDH tWPDA tDWRS tEWRH, tFWRH tEWRA, tFWRA tTHWRH tTHWRA tWRL tWRH tWRCYC Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. DWRH DI hold from WB 1.5 ns DWRS DI setup to WB 0.5 ns PARGEN is inactive DWRS DI setup to WB 2.5 ns PARGEN is active EWRH, FWRH, THWRH Old EMPTY, FULL, EQTH, & GETH valid hold time after WB ns Empty/full/thresh are invalid from the end of hold until the new access is complete EWRA EMPTY access from WB 3.01 ns FWRA New FULL access from WB 3.01 ns THWRA EQTH or GETH access from WB 4.5 ns WPDA WPE access from DI 3.0 ns 0.5 WPDH WPE hold from DI WRCYC Cycle time 7.5 RB , clearing FULL, setup to 3.02 WRRDS 1.0 WB WRH WB high phase Max. Units ns 3.0 Advanced v0.6 WPE is invalid while PARGEN is active ns ns 1.0 WRL WB low phase 3.0 Notes: 1. At fast cycles, EWRA, FWRA = MAX (7.5 ns - WRL), 3.0 ns 2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns - RDL), 3.0 ns Notes Enabling the write operation Inhibiting the write operation ns Inactive ns Active 49 Pr o A S I C P L U S F a m ily F la s h F P GA s Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) RCLK Cycle Start RDB RDATA Old Data Out New Valid Data Out (Empty Inhibits Read) RPE EMPTY FULL EQTH, GETH tRDCH tECBH, tFCBH tECBA, tFCBA tRDCS tTHCBH tOCH tRPCH tHCBA tOCA tRPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. Max. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns ECBA New EMPTY access from RCLKS 3.01 ns FCBA FULL access from RCLKS 3.01 ns ECBH, FCBH, THCBH Old EMPTY, FULL, EQTH, & GETH valid hold time from RCLKS 1.0 Units ns OCA New DO access from RCLKS OCH Old DO valid from RCLKS RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 9.5 ns RPCH Old RPE valid from RCLKS 7.5 3.0 HCBA EQTH or GETH access from RCLKS Note: 1. At fast cycles, ECBA & FCBA = MAX (7.5 ns - CMH), 3.0 ns 50 ns 3.0 4.5 Advanced v0.6 ns ns ns Notes Empty/full/thresh are invalid from the end of hold until the new access is complete Pr o A SI C P L U S F a m ily F la s h F P GA s Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLK Cycle Start RDB RDATA Old Data Out RPE New Valid Data Out Old RPE Out New RPE Out EMPTY FULL EQTH, GETH tECBH, tFCBH tOCA tRDCH tECBA, tFCBA tTHCBH tRDCS tRPCH tOCH tHCBA tRPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. CCYC CMH CML ECBA FCBA Cycle time Clock high phase Clock low phase New EMPTY access from RCLKS FULL access from RCLKS 7.5 3.0 3.0 3.01 3.01 ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid THCBH hold time from RCLKS OCA New DO access from RCLKS OCH Old DO valid from RCLKS RDCH RDB hold from RCLKS RDCS RDB setup to RCLKS RPCA New RPE access from RCLKS RPCH Old RPE valid from RCLKS HCBA EQTH or GETH access from RCLKS Note: 1. At fast cycles, ECBA & FCBA = MAX (7.5 ns - CMS), 3.0 ns Max. 2.0 0.75 0.5 1.0 4.0 1.0 Advanced v0.6 Notes ns ns ns ns ns 1.0 4.5 Units ns Empty/full/thresh are invalid from the end of hold until the new access is complete ns ns ns ns ns ns ns 51 Pr o A S I C P L U S F a m ily F la s h F P GA s Synchronous FIFO Write WCLKS Cycle Start WRB, WBLKB (Full Inhibits Write) DI WPE FULL EMPTY EQTH, GETH tWRCH, tWBCH tECBH, tFCBH tWRCS, tWBCS tECBA, tFCBA tDCS tHCBH tHCBA tWPCH tDCH tWPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. T J = 0C to 110C; V DD = 2.3V to 2.7V Symbol txxx Description Min. CCYC Cycle time CMH Clock high phase CML Clock low phase DCH DI hold from WCLKS DCS DI setup to WCLKS FCBA New FULL access from WCLKS ECBA EMPTY access from WCLKS ECBH, Old EMPTY, FULL, EQTH, & GETH valid FCBH, hold time from WCLKS THCBH HCBA EQTH or GETH access from WCLKS WPCA New WPE access from WCLKS WPCH Old WPE valid from WCLKS WRCH, WRB & WBLKB hold from WCLKS WBCH WRCS, WRB & WBLKB setup to WCLKS WBCS Note: 1. At fast cycles, ECBA & FCBA = MAX (7.5 ns - CMH), 3.0 ns 52 Max. Units 1.0 ns ns ns ns ns ns ns ns 7.5 3.0 3.0 0.5 1.0 3.01 3.01 4.5 3.0 0.5 ns ns ns ns 1.0 ns 0.5 Advanced v0.6 Notes Empty/full/thresh are invalid from the end of hold until the new access is complete WPE is invalid while PARGEN is active Pr o A SI C P L U S F a m ily F la s h F P GA s FIFO Reset RESETB Cycle Start WB* WCLKS, RCLKS Cycle Start FULL EMPTY EQTH, GETH tCBRSS tERSA, tFRSA tCBRSH tTHRSA tWBRSH *WB = WRB tRSL + WBLRB tWBRSS Note: The plot shows the normal operation status. T J = 0 C t o 11 0 C; V D D = 2 .3V t o 2.7V Symbol txxx Description Min. CBRSH WCLKS or RCLKS hold from RESETB CBRSS Units Notes 1.5 ns Synchronous mode only WCLKS or RCLKS setup to RESETB 1.5 ns Synchronous mode only ERSA New EMPTY access from RESETB 3.0 ns FRSA FULL access from RESETB 3.0 ns RSL RESETB low phase 7.5 ns THRSA EQTH or GETH access from RESETB 4.5 ns WBRSH WB hold from RESETB 1.5 ns Asynchronous mode only WBRSS WB setup to RESETB 1.5 ns Asynchronous mode only Advanced v0.6 Max. 53 Pr o A S I C P L U S F a m ily F la s h F P GA s Pi n D es c r i pt i on I/O User Input/Output VPN The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with standard LVTTL and LVCMOS specifications. Unused I/O pins are configured as inputs with pull-up resistors. NC No Connect Programming Supply Pin This pin may be connected to any voltage between GND and 13.8V during normal operation, or it can be left unconnected. For information on using this pin during programming, see the Performing Internal In-System Programming Using Actel's ProASICPLUS Devices application note. To maintain compatibility with other Actel ProASIC products it is recommended that this pin not be connected to the circuitry on the board. TMS GL Clock input pin for boundary scan. Global Input Pin Low skew input pin for clock or other global signals. Input only. This pin can be configured with a pull-up resistor. GND Ground V DD Logic Array Power Supply Pin Test Data In Serial input for boundary scan. Test Data Out TRST Test Reset Input Asynchronous, active low input pin for resetting boundary-scan circuitry. I/O Pad Power Supply Pin 2.5V or 3.3V supply voltage. V PP TDI Test Clock Serial output for boundary scan. 2.5V supply voltage. V DDP TCK TDO Common ground supply voltage. Test Mode Select The TMS pin controls the use of boundary-scan circuitry. RCK Programming Supply Pin This pin may be connected to any voltage between GND and 16.5V during normal operation, or it can be left unconnected. For information on using this pin during programming, see the Performing Internal In-System Programming Using Actel's ProASICPLUS Devices application note. Running Clock A free running clock is needed during programming if the programmer cannot guarantee that TCK will be uninterrupted. NPECL PECL Negative Input Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected. PPECL PECL Positive input Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected. 54 AVDD PLL Power Supply AGND PLL Power Ground Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s Pa c ka ge P i n A s si g nm e n t s 208- P in P Q FP 208 1 208-Pin PQFP Advanced v0.6 55 Pr o A S I C P L U S F a m ily F la s h F P GA s 208- P in P Q FP 56 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 1 GND GND GND GND GND GND 2 I/O I/O I/O I/O I/O I/O 3 I/O I/O I/O I/O I/O I/O 4 I/O I/O I/O I/O I/O I/O 5 I/O I/O I/O I/O I/O I/O 6 I/O I/O I/O I/O I/O I/O 7 I/O I/O I/O I/O I/O I/O 8 I/O I/O I/O I/O I/O I/O 9 I/O I/O I/O I/O I/O I/O 10 I/O I/O I/O I/O I/O I/O 11 I/O I/O I/O I/O I/O I/O 12 I/O I/O I/O I/O I/O I/O 13 I/O I/O I/O I/O I/O I/O 14 I/O I/O I/O I/O I/O I/O 15 I/O I/O I/O I/O I/O I/O 16 VDD VDD VDD VDD VDD VDD 17 GND GND GND GND GND GND 18 I/O I/O I/O I/O I/O I/O 19 I/O I/O I/O I/O I/O I/O 20 I/O I/O I/O I/O I/O I/O 21 I/O I/O I/O I/O I/O I/O 22 VDDP VDDP VDDP VDDP VDDP VDDP 23 I/O I/O I/O I/O I/O I/O 24 GL GL GL GL GL GL 25 AGND AGND AGND AGND AGND AGND 26 NPECL NPECL NPECL NPECL NPECL NPECL 27 AVDD AVDD AVDD AVDD AVDD AVDD 28 PPECL PPECL PPECL PPECL PPECL PPECL 29 GND GND GND GND GND GND 30 GL GL GL GL GL GL 31 I/O I/O I/O I/O I/O I/O 32 I/O I/O I/O I/O I/O I/O 33 I/O I/O I/O I/O I/O I/O 34 I/O I/O I/O I/O I/O I/O 35 I/O I/O I/O I/O I/O I/O 36 VDD VDD VDD VDD VDD VDD 37 I/O I/O I/O I/O I/O I/O 38 I/O I/O I/O I/O I/O I/O 39 I/O I/O I/O I/O I/O I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 208- P in P Q FP (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 40 VDDP VDDP VDDP VDDP VDDP VDDP 41 GND GND GND GND GND GND 42 I/O I/O I/O I/O I/O I/O 43 I/O I/O I/O I/O I/O I/O 44 I/O I/O I/O I/O I/O I/O 45 I/O I/O I/O I/O I/O I/O 46 I/O I/O I/O I/O I/O I/O 47 I/O I/O I/O I/O I/O I/O 48 I/O I/O I/O I/O I/O I/O 49 I/O I/O I/O I/O I/O I/O 50 I/O I/O I/O I/O I/O I/O 51 I/O I/O I/O I/O I/O I/O 52 GND GND GND GND GND GND 53 VDDP VDDP VDDP VDDP VDDP VDDP 54 I/O I/O I/O I/O I/O I/O 55 I/O I/O I/O I/O I/O I/O 56 I/O I/O I/O I/O I/O I/O 57 I/O I/O I/O I/O I/O I/O 58 I/O I/O I/O I/O I/O I/O 59 I/O I/O I/O I/O I/O I/O 60 I/O I/O I/O I/O I/O I/O 61 I/O I/O I/O I/O I/O I/O 62 I/O I/O I/O I/O I/O I/O 63 I/O I/O I/O I/O I/O I/O 64 I/O I/O I/O I/O I/O I/O 65 GND GND GND GND GND GND 66 I/O I/O I/O I/O I/O I/O 67 I/O I/O I/O I/O I/O I/O 68 I/O I/O I/O I/O I/O I/O 69 I/O I/O I/O I/O I/O I/O 70 I/O I/O I/O I/O I/O I/O 71 VDD VDD VDD VDD VDD VDD 72 VDDP VDDP VDDP VDDP VDDP VDDP 73 I/O I/O I/O I/O I/O I/O 74 I/O I/O I/O I/O I/O I/O 75 I/O I/O I/O I/O I/O I/O 76 I/O I/O I/O I/O I/O I/O 77 I/O I/O I/O I/O I/O I/O 78 I/O I/O I/O I/O I/O I/O Advanced v0.6 57 Pr o A S I C P L U S F a m ily F la s h F P GA s 208- P in P Q FP (C ont inu ed) 58 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 79 I/O I/O I/O I/O I/O I/O 80 I/O I/O I/O I/O I/O I/O 81 GND GND GND GND GND GND 82 I/O I/O I/O I/O I/O I/O 83 I/O I/O I/O I/O I/O I/O 84 I/O I/O I/O I/O I/O I/O 85 I/O I/O I/O I/O I/O I/O 86 I/O I/O I/O I/O I/O I/O 87 I/O I/O I/O I/O I/O I/O 88 VDD VDD VDD VDD VDD VDD 89 VDDP VDDP VDDP VDDP VDDP VDDP 90 I/O I/O I/O I/O I/O I/O 91 I/O I/O I/O I/O I/O I/O 92 I/O I/O I/O I/O I/O I/O 93 I/O I/O I/O I/O I/O I/O 94 I/O I/O I/O I/O I/O I/O 95 I/O I/O I/O I/O I/O I/O 96 I/O I/O I/O I/O I/O I/O 97 GND GND GND GND GND GND 98 I/O I/O I/O I/O I/O I/O 99 I/O I/O I/O I/O I/O I/O 100 I/O I/O I/O I/O I/O I/O 101 TCK TCK TCK TCK TCK TCK 102 TDI TDI TDI TDI TDI TDI 103 TMS TMS TMS TMS TMS TMS 104 VDDP VDDP VDDP VDDP VDDP VDDP 105 GND GND GND GND GND GND 106 VPP VPP VPP VPP VPP VPP 107 VPN VPN VPN VPN VPN VPN 108 TDO TDO TDO TDO TDO TDO 109 TRST TRST TRST TRST TRST TRST 110 RCK RCK RCK RCK RCK RCK 111 I/O I/O I/O I/O I/O I/O 112 I/O I/O I/O I/O I/O I/O 113 I/O I/O I/O I/O I/O I/O 114 I/O I/O I/O I/O I/O I/O 115 I/O I/O I/O I/O I/O I/O 116 I/O I/O I/O I/O I/O I/O 117 I/O I/O I/O I/O I/O I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 208- P in P Q FP (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 118 I/O I/O I/O I/O I/O I/O 119 I/O I/O I/O I/O I/O I/O 120 I/O I/O I/O I/O I/O I/O 121 I/O I/O I/O I/O I/O I/O 122 GND GND GND GND GND GND 123 VDDP VDDP VDDP VDDP VDDP VDDP 124 I/O I/O I/O I/O I/O I/O 125 I/O I/O I/O I/O I/O I/O 126 VDD VDD VDD VDD VDD VDD 127 I/O I/O I/O I/O I/O I/O 128 GL GL GL GL GL GL 129 PPECL PPECL PPECL PPECL PPECL PPECL 130 GND GND GND GND GND GND 131 AVDD AVDD AVDD AVDD AVDD AVDD 132 NPECL NPECL NPECL NPECL NPECL NPECL 133 AGND AGND AGND AGND AGND AGND 134 GL GL GL GL GL GL 135 I/O I/O I/O I/O I/O I/O 136 I/O I/O I/O I/O I/O I/O 137 I/O I/O I/O I/O I/O I/O 138 VDDP VDDP VDDP VDDP VDDP VDDP 139 I/O I/O I/O I/O I/O I/O 140 I/O I/O I/O I/O I/O I/O 141 GND GND GND GND GND GND 142 VDD VDD VDD VDD VDD VDD 143 I/O I/O I/O I/O I/O I/O 144 I/O I/O I/O I/O I/O I/O 145 I/O I/O I/O I/O I/O I/O 146 I/O I/O I/O I/O I/O I/O 147 I/O I/O I/O I/O I/O I/O 148 I/O I/O I/O I/O I/O I/O 149 I/O I/O I/O I/O I/O I/O 150 I/O I/O I/O I/O I/O I/O 151 I/O I/O I/O I/O I/O I/O 152 I/O I/O I/O I/O I/O I/O 153 I/O I/O I/O I/O I/O I/O 154 I/O I/O I/O I/O I/O I/O 155 I/O I/O I/O I/O I/O I/O 156 GND GND GND GND GND GND Advanced v0.6 59 Pr o A S I C P L U S F a m ily F la s h F P GA s 208- P in P Q FP (C ont inu ed) 60 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 157 VDDP VDDP VDDP VDDP VDDP VDDP 158 I/O I/O I/O I/O I/O I/O 159 I/O I/O I/O I/O I/O I/O 160 I/O I/O I/O I/O I/O I/O 161 I/O I/O I/O I/O I/O I/O 162 GND GND GND GND GND GND 163 I/O I/O I/O I/O I/O I/O 164 I/O I/O I/O I/O I/O I/O 165 I/O I/O I/O I/O I/O I/O 166 I/O I/O I/O I/O I/O I/O 167 I/O I/O I/O I/O I/O I/O 168 I/O I/O I/O I/O I/O I/O 169 I/O I/O I/O I/O I/O I/O 170 VDDP VDDP VDDP VDDP VDDP VDDP 171 VDD VDD VDD VDD VDD VDD 172 I/O I/O I/O I/O I/O I/O 173 I/O I/O I/O I/O I/O I/O 174 I/O I/O I/O I/O I/O I/O 175 I/O I/O I/O I/O I/O I/O 176 I/O I/O I/O I/O I/O I/O 177 I/O I/O I/O I/O I/O I/O 178 GND GND GND GND GND GND 179 I/O I/O I/O I/O I/O I/O 180 I/O I/O I/O I/O I/O I/O 181 I/O I/O I/O I/O I/O I/O 182 I/O I/O I/O I/O I/O I/O 183 I/O I/O I/O I/O I/O I/O 184 I/O I/O I/O I/O I/O I/O 185 I/O I/O I/O I/O I/O I/O 186 VDDP VDDP VDDP VDDP VDDP VDDP 187 VDD VDD VDD VDD VDD VDD 188 I/O I/O I/O I/O I/O I/O 189 I/O I/O I/O I/O I/O I/O 190 I/O I/O I/O I/O I/O I/O 191 I/O I/O I/O I/O I/O I/O 192 I/O I/O I/O I/O I/O I/O 193 I/O I/O I/O I/O I/O I/O 194 I/O I/O I/O I/O I/O I/O 195 GND GND GND GND GND GND Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 208- P in P Q FP (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 196 I/O I/O I/O I/O I/O I/O 197 I/O I/O I/O I/O I/O I/O 198 I/O I/O I/O I/O I/O I/O 199 I/O I/O I/O I/O I/O I/O 200 I/O I/O I/O I/O I/O I/O 201 I/O I/O I/O I/O I/O I/O 202 I/O I/O I/O I/O I/O I/O 203 I/O I/O I/O I/O I/O I/O 204 I/O I/O I/O I/O I/O I/O 205 I/O I/O I/O I/O I/O I/O 206 I/O I/O I/O I/O I/O I/O 207 I/O I/O I/O I/O I/O I/O 208 VDDP VDDP VDDP VDDP VDDP VDDP Advanced v0.6 61 Pr o A S I C P L U S F a m ily F la s h F P GA s P a c ka ge P i n A s si g nm e n t s (Continued) 456- P in P BGA (B ott om Vi ew) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 62 Advanced v0.6 8 7 6 5 4 3 2 1 Pr o A SI C P L U S F a m ily F la s h F P GA s 4 5 6 - P in P BG A Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function A1 VDDP VDDP VDDP VDDP VDDP VDDP A2 VDDP VDDP VDDP VDDP VDDP VDDP A3 NC NC I/O I/O I/O I/O A4 NC NC I/O I/O I/O I/O A5 NC NC I/O I/O I/O I/O A6 NC NC I/O I/O I/O I/O A7 NC NC I/O I/O I/O I/O A8 I/O I/O I/O I/O I/O I/O A9 I/O I/O I/O I/O I/O I/O A10 I/O I/O I/O I/O I/O I/O A11 I/O I/O I/O I/O I/O I/O A12 I/O I/O I/O I/O I/O I/O A13 I/O I/O I/O I/O I/O I/O A14 I/O I/O I/O I/O I/O I/O A15 I/O I/O I/O I/O I/O I/O A16 I/O I/O I/O I/O I/O I/O A17 I/O I/O I/O I/O I/O I/O A18 I/O I/O I/O I/O I/O I/O A19 I/O I/O I/O I/O I/O I/O A20 NC NC I/O I/O I/O I/O A21 NC NC I/O I/O I/O I/O A22 NC NC I/O I/O I/O I/O A23 NC NC I/O I/O I/O I/O A24 NC NC I/O I/O I/O I/O A25 VDDP VDDP VDDP VDDP VDDP VDDP A26 VDDP VDDP VDDP VDDP VDDP VDDP B1 VDDP VDDP VDDP VDDP VDDP VDDP B2 VDDP VDDP VDDP VDDP VDDP VDDP B3 NC NC NC I/O I/O I/O B4 NC NC I/O I/O I/O I/O B5 NC NC I/O I/O I/O I/O B6 NC NC I/O I/O I/O I/O B7 NC NC I/O I/O I/O I/O B8 I/O I/O I/O I/O I/O I/O B9 I/O I/O I/O I/O I/O I/O B10 I/O I/O I/O I/O I/O I/O B11 I/O I/O I/O I/O I/O I/O B12 I/O I/O I/O I/O I/O I/O B13 I/O I/O I/O I/O I/O I/O Advanced v0.6 63 Pr o A S I C P L U S F a m ily F la s h F P GA s 456- P in P BGA (C ont inu ed) 64 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function B14 I/O I/O I/O I/O I/O I/O B15 I/O I/O I/O I/O I/O I/O B16 I/O I/O I/O I/O I/O I/O B17 I/O I/O I/O I/O I/O I/O B18 I/O I/O I/O I/O I/O I/O B19 I/O I/O I/O I/O I/O I/O B20 NC NC I/O I/O I/O I/O B21 NC NC I/O I/O I/O I/O B22 NC NC I/O I/O I/O I/O B23 NC NC I/O I/O I/O I/O B24 NC NC I/O I/O I/O I/O B25 VDDP VDDP VDDP VDDP VDDP VDDP B26 VDDP VDDP VDDP VDDP VDDP VDDP C1 VDDP VDDP VDDP VDDP VDDP VDDP C2 NC I/O I/O I/O I/O I/O C3 VDDP VDDP VDDP VDDP VDDP VDDP C4 NC NC NC I/O I/O I/O C5 NC NC I/O I/O I/O I/O C6 NC NC I/O I/O I/O I/O C7 I/O I/O I/O I/O I/O I/O C8 I/O I/O I/O I/O I/O I/O C9 I/O I/O I/O I/O I/O I/O C10 I/O I/O I/O I/O I/O I/O C11 I/O I/O I/O I/O I/O I/O C12 I/O I/O I/O I/O I/O I/O C13 I/O I/O I/O I/O I/O I/O C14 I/O I/O I/O I/O I/O I/O C15 I/O I/O I/O I/O I/O I/O C16 I/O I/O I/O I/O I/O I/O C17 I/O I/O I/O I/O I/O I/O C18 I/O I/O I/O I/O I/O I/O C19 I/O I/O I/O I/O I/O I/O C20 I/O I/O I/O I/O I/O I/O C21 NC NC I/O I/O I/O I/O C22 NC NC I/O I/O I/O I/O C23 NC NC I/O I/O I/O I/O C24 VDDP VDDP VDDP VDDP VDDP VDDP C25 NC NC NC I/O I/O I/O C26 NC NC NC I/O I/O I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 456- P in P BGA (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function D1 NC NC NC I/O I/O I/O D2 NC NC NC I/O I/O I/O D3 NC I/O I/O I/O I/O I/O D4 VDDP VDDP VDDP VDDP VDDP VDDP D5 NC NC I/O I/O I/O I/O D6 NC NC I/O I/O I/O I/O D7 I/O I/O I/O I/O I/O I/O D8 I/O I/O I/O I/O I/O I/O D9 I/O I/O I/O I/O I/O I/O D10 I/O I/O I/O I/O I/O I/O D11 I/O I/O I/O I/O I/O I/O D12 I/O I/O I/O I/O I/O I/O D13 I/O I/O I/O I/O I/O I/O D14 I/O I/O I/O I/O I/O I/O D15 I/O I/O I/O I/O I/O I/O D16 I/O I/O I/O I/O I/O I/O D17 I/O I/O I/O I/O I/O I/O D18 I/O I/O I/O I/O I/O I/O D19 I/O I/O I/O I/O I/O I/O D20 I/O I/O I/O I/O I/O I/O D21 I/O I/O I/O I/O I/O I/O D22 NC NC I/O I/O I/O I/O D23 VDDP VDDP VDDP VDDP VDDP VDDP D24 NC I/O I/O I/O I/O I/O D25 NC NC NC I/O I/O I/O D26 NC NC NC I/O I/O I/O E1 NC I/O I/O I/O I/O I/O E2 NC I/O I/O I/O I/O I/O E3 NC I/O I/O I/O I/O I/O E4 NC I/O I/O I/O I/O I/O E5 VDD VDD VDD VDD VDD VDD E6 VDD VDD VDD VDD VDD VDD E7 VDD VDD VDD VDD VDD VDD E8 VDD VDD VDD VDD VDD VDD E9 I/O I/O I/O I/O I/O I/O E10 I/O I/O I/O I/O I/O I/O E11 I/O I/O I/O I/O I/O I/O E12 I/O I/O I/O I/O I/O I/O E13 I/O I/O I/O I/O I/O I/O Advanced v0.6 65 Pr o A S I C P L U S F a m ily F la s h F P GA s 456- P in P BGA (C ont inu ed) 66 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function E14 I/O I/O I/O I/O I/O I/O E15 I/O I/O I/O I/O I/O I/O E16 I/O I/O I/O I/O I/O I/O E17 I/O I/O I/O I/O I/O I/O E18 I/O I/O I/O I/O I/O I/O E19 I/O I/O I/O I/O I/O I/O E20 VDD VDD VDD VDD VDD VDD E21 VDD VDD VDD VDD VDD VDD E22 VDD VDD VDD VDD VDD VDD E23 NC I/O I/O I/O I/O I/O E24 NC I/O I/O I/O I/O I/O E25 NC I/O I/O I/O I/O I/O E26 NC I/O I/O I/O I/O I/O F1 NC I/O I/O I/O I/O I/O F2 NC I/O I/O I/O I/O I/O F3 NC I/O I/O I/O I/O I/O F4 NC I/O I/O I/O I/O I/O F5 VDD VDD VDD VDD VDD VDD F22 VDD VDD VDD VDD VDD VDD F23 NC I/O I/O I/O I/O I/O F24 NC I/O I/O I/O I/O I/O F25 NC I/O I/O I/O I/O I/O F26 NC I/O I/O I/O I/O I/O G1 I/O I/O I/O I/O I/O I/O G2 I/O I/O I/O I/O I/O I/O G3 NC I/O I/O I/O I/O I/O G4 NC I/O I/O I/O I/O I/O G5 VDD VDD VDD VDD VDD VDD G22 VDD VDD VDD VDD VDD VDD G23 NC I/O I/O I/O I/O I/O G24 NC I/O I/O I/O I/O I/O G25 NC I/O I/O I/O I/O I/O G26 I/O I/O I/O I/O I/O I/O H1 I/O I/O I/O I/O I/O I/O H2 I/O I/O I/O I/O I/O I/O H3 I/O I/O I/O I/O I/O I/O H4 I/O I/O I/O I/O I/O I/O H5 VDD VDD VDD VDD VDD VDD H22 VDD VDD VDD VDD VDD VDD Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 456- P in P BGA (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function H23 I/O I/O I/O I/O I/O I/O H24 I/O I/O I/O I/O I/O I/O H25 I/O I/O I/O I/O I/O I/O H26 I/O I/O I/O I/O I/O I/O J1 I/O I/O I/O I/O I/O I/O J2 I/O I/O I/O I/O I/O I/O J3 I/O I/O I/O I/O I/O I/O J4 I/O I/O I/O I/O I/O I/O J5 I/O I/O I/O I/O I/O I/O J22 I/O I/O I/O I/O I/O I/O J23 I/O I/O I/O I/O I/O I/O J24 I/O I/O I/O I/O I/O I/O J25 I/O I/O I/O I/O I/O I/O J26 I/O I/O I/O I/O I/O I/O K1 I/O I/O I/O I/O I/O I/O K2 I/O I/O I/O I/O I/O I/O K3 I/O I/O I/O I/O I/O I/O K4 I/O I/O I/O I/O I/O I/O K5 I/O I/O I/O I/O I/O I/O K22 I/O I/O I/O I/O I/O I/O K23 I/O I/O I/O I/O I/O I/O K24 I/O I/O I/O I/O I/O I/O K25 I/O I/O I/O I/O I/O I/O K26 I/O I/O I/O I/O I/O I/O L1 I/O I/O I/O I/O I/O I/O L2 I/O I/O I/O I/O I/O I/O L3 I/O I/O I/O I/O I/O I/O L4 I/O I/O I/O I/O I/O I/O L5 I/O I/O I/O I/O I/O I/O L11 GND GND GND GND GND GND L12 GND GND GND GND GND GND L13 GND GND GND GND GND GND L14 GND GND GND GND GND GND L15 GND GND GND GND GND GND L16 GND GND GND GND GND GND L22 I/O I/O I/O I/O I/O I/O L23 I/O I/O I/O I/O I/O I/O L24 I/O I/O I/O I/O I/O I/O L25 I/O I/O I/O I/O I/O I/O Advanced v0.6 67 Pr o A S I C P L U S F a m ily F la s h F P GA s 456- P in P BGA (C ont inu ed) 68 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function L26 I/O I/O I/O I/O I/O I/O M1 GL GL GL GL GL GL M2 GL GL GL GL GL GL M3 I/O I/O I/O I/O I/O I/O M4 I/O I/O I/O I/O I/O I/O M5 I/O I/O I/O I/O I/O I/O M11 GND GND GND GND GND GND M12 GND GND GND GND GND GND M13 GND GND GND GND GND GND M14 GND GND GND GND GND GND M15 GND GND GND GND GND GND M16 GND GND GND GND GND GND M22 GL GL GL GL GL GL M23 I/O I/O I/O I/O I/O I/O M24 I/O I/O I/O I/O I/O I/O M25 I/O I/O I/O I/O I/O I/O M26 I/O I/O I/O I/O I/O I/O N1 I/O I/O I/O I/O I/O I/O N2 I/O I/O I/O I/O I/O I/O N3 AGND AGND AGND AGND AGND AGND N4 PPECL PPECL PPECL PPECL PPECL PPECL N5 AVDD AVDD AVDD AVDD AVDD AVDD N11 GND GND GND GND GND GND N12 GND GND GND GND GND GND N13 GND GND GND GND GND GND N14 GND GND GND GND GND GND N15 GND GND GND GND GND GND N16 GND GND GND GND GND GND N22 NPECL NPECL NPECL NPECL NPECL NPECL N23 GL GL GL GL GL GL N24 AVDD AVDD AVDD AVDD AVDD AVDD N25 I/O I/O I/O I/O I/O I/O N26 AGND AGND AGND AGND AGND AGND P1 I/O I/O I/O I/O I/O I/O P2 I/O I/O I/O I/O I/O I/O P3 I/O I/O I/O I/O I/O I/O P4 I/O I/O I/O I/O I/O I/O P5 NPECL NPECL NPECL NPECL NPECL NPECL P11 GND GND GND GND GND GND Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 456- P in P BGA (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function P12 GND GND GND GND GND GND P13 GND GND GND GND GND GND P14 GND GND GND GND GND GND P15 GND GND GND GND GND GND P16 GND GND GND GND GND GND P22 I/O I/O I/O I/O I/O I/O P23 I/O I/O I/O I/O I/O I/O P24 I/O I/O I/O I/O I/O I/O P25 I/O I/O I/O I/O I/O I/O P26 PPECL PPECL PPECL PPECL PPECL PPECL R1 I/O I/O I/O I/O I/O I/O R2 I/O I/O I/O I/O I/O I/O R3 I/O I/O I/O I/O I/O I/O R4 I/O I/O I/O I/O I/O I/O R5 I/O I/O I/O I/O I/O I/O R11 GND GND GND GND GND GND R12 GND GND GND GND GND GND R13 GND GND GND GND GND GND R14 GND GND GND GND GND GND R15 GND GND GND GND GND GND R16 GND GND GND GND GND GND R22 I/O I/O I/O I/O I/O I/O R23 I/O I/O I/O I/O I/O I/O R24 I/O I/O I/O I/O I/O I/O R25 I/O I/O I/O I/O I/O I/O R26 I/O I/O I/O I/O I/O I/O T1 I/O I/O I/O I/O I/O I/O T2 I/O I/O I/O I/O I/O I/O T3 I/O I/O I/O I/O I/O I/O T4 I/O I/O I/O I/O I/O I/O T5 I/O I/O I/O I/O I/O I/O T11 GND GND GND GND GND GND T12 GND GND GND GND GND GND T13 GND GND GND GND GND GND T14 GND GND GND GND GND GND T15 GND GND GND GND GND GND T16 GND GND GND GND GND GND T22 I/O I/O I/O I/O I/O I/O T23 I/O I/O I/O I/O I/O I/O Advanced v0.6 69 Pr o A S I C P L U S F a m ily F la s h F P GA s 456- P in P BGA (C ont inu ed) 70 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function T24 I/O I/O I/O I/O I/O I/O T25 I/O I/O I/O I/O I/O I/O T26 I/O I/O I/O I/O I/O I/O U1 I/O I/O I/O I/O I/O I/O U2 I/O I/O I/O I/O I/O I/O U3 I/O I/O I/O I/O I/O I/O U4 I/O I/O I/O I/O I/O I/O U5 I/O I/O I/O I/O I/O I/O U22 I/O I/O I/O I/O I/O I/O U23 I/O I/O I/O I/O I/O I/O U24 I/O I/O I/O I/O I/O I/O U25 I/O I/O I/O I/O I/O I/O U26 I/O I/O I/O I/O I/O I/O V1 I/O I/O I/O I/O I/O I/O V2 I/O I/O I/O I/O I/O I/O V3 I/O I/O I/O I/O I/O I/O V4 I/O I/O I/O I/O I/O I/O V5 I/O I/O I/O I/O I/O I/O V22 I/O I/O I/O I/O I/O I/O V23 I/O I/O I/O I/O I/O I/O V24 I/O I/O I/O I/O I/O I/O V25 I/O I/O I/O I/O I/O I/O V26 I/O I/O I/O I/O I/O I/O W1 I/O I/O I/O I/O I/O I/O W2 I/O I/O I/O I/O I/O I/O W3 I/O I/O I/O I/O I/O I/O W4 I/O I/O I/O I/O I/O I/O W5 VDD VDD VDD VDD VDD VDD W22 VDD VDD VDD VDD VDD VDD W23 I/O I/O I/O I/O I/O I/O W24 I/O I/O I/O I/O I/O I/O W25 I/O I/O I/O I/O I/O I/O W26 I/O I/O I/O I/O I/O I/O Y1 I/O I/O I/O I/O I/O I/O Y2 I/O I/O I/O I/O I/O I/O Y3 I/O I/O I/O I/O I/O I/O Y4 NC I/O I/O I/O I/O I/O Y5 VDD VDD VDD VDD VDD VDD Y22 VDD VDD VDD VDD VDD VDD Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 456- P in P BGA (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function Y23 NC I/O I/O I/O I/O I/O Y24 NC I/O I/O I/O I/O I/O Y25 NC I/O I/O I/O I/O I/O Y26 NC I/O I/O I/O I/O I/O AA1 I/O I/O I/O I/O I/O I/O AA2 NC I/O I/O I/O I/O I/O AA3 NC I/O I/O I/O I/O I/O AA4 NC I/O I/O I/O I/O I/O AA5 VDD VDD VDD VDD VDD VDD AA22 VDD VDD VDD VDD VDD VDD AA23 NC I/O I/O I/O I/O I/O AA24 NC I/O I/O I/O I/O I/O AA25 NC I/O I/O I/O I/O I/O AA26 NC I/O I/O I/O I/O I/O AB1 NC I/O I/O I/O I/O I/O AB2 NC I/O I/O I/O I/O I/O AB3 NC I/O I/O I/O I/O I/O AB4 NC I/O I/O I/O I/O I/O AB5 VDD VDD VDD VDD VDD VDD AB6 VDD VDD VDD VDD VDD VDD AB7 VDD VDD VDD VDD VDD VDD AB8 I/O I/O I/O I/O I/O I/O AB9 I/O I/O I/O I/O I/O I/O AB10 I/O I/O I/O I/O I/O I/O AB11 I/O I/O I/O I/O I/O I/O AB12 I/O I/O I/O I/O I/O I/O AB13 I/O I/O I/O I/O I/O I/O AB14 I/O I/O I/O I/O I/O I/O AB15 I/O I/O I/O I/O I/O I/O AB16 I/O I/O I/O I/O I/O I/O AB17 I/O I/O I/O I/O I/O I/O AB18 I/O I/O I/O I/O I/O I/O AB19 I/O I/O I/O I/O I/O I/O AB20 VDD VDD VDD VDD VDD VDD AB21 VDD VDD VDD VDD VDD VDD AB22 VDD VDD VDD VDD VDD VDD AB23 NC I/O I/O I/O I/O I/O AB24 NC I/O I/O I/O I/O I/O AB25 NC I/O NC I/O I/O I/O Advanced v0.6 71 Pr o A S I C P L U S F a m ily F la s h F P GA s 456- P in P BGA (C ont inu ed) 72 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function AB26 NC NC I/O I/O I/O I/O AC1 NC I/O I/O I/O I/O I/O AC2 NC I/O I/O I/O I/O I/O AC3 NC I/O I/O I/O I/O I/O AC4 VDDP VDDP VDDP VDDP VDDP VDDP AC5 NC NC I/O I/O I/O I/O AC6 I/O I/O I/O I/O I/O I/O AC7 I/O I/O I/O I/O I/O I/O AC8 I/O I/O I/O I/O I/O I/O AC9 I/O I/O I/O I/O I/O I/O AC10 I/O I/O I/O I/O I/O I/O AC11 I/O I/O I/O I/O I/O I/O AC12 I/O I/O I/O I/O I/O I/O AC13 I/O I/O I/O I/O I/O I/O AC14 I/O I/O I/O I/O I/O I/O AC15 I/O I/O I/O I/O I/O I/O AC16 I/O I/O I/O I/O I/O I/O AC17 I/O I/O I/O I/O I/O I/O AC18 I/O I/O I/O I/O I/O I/O AC19 I/O I/O I/O I/O I/O I/O AC20 I/O I/O I/O I/O I/O I/O AC21 TMS TMS TMS TMS TMS TMS AC22 TDO TDO TDO TDO TDO TDO AC23 VDDP VDDP VDDP VDDP VDDP VDDP AC24 RCK RCK RCK RCK RCK RCK AC25 NC NC I/O I/O I/O I/O AC26 NC I/O I/O I/O I/O I/O AD1 NC NC NC I/O I/O I/O AD2 NC I/O I/O I/O I/O I/O AD3 VDDP VDDP VDDP VDDP VDDP VDDP AD4 NC NC I/O I/O I/O I/O AD5 NC NC I/O I/O I/O I/O AD6 NC NC I/O I/O I/O I/O AD7 I/O I/O I/O I/O I/O I/O AD8 I/O I/O I/O I/O I/O I/O AD9 I/O I/O I/O I/O I/O I/O AD10 I/O I/O I/O I/O I/O I/O AD11 I/O I/O I/O I/O I/O I/O AD12 I/O I/O I/O I/O I/O I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 456- P in P BGA (C ont inu ed) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function AD13 I/O I/O I/O I/O I/O I/O AD14 I/O I/O I/O I/O I/O I/O AD15 I/O I/O I/O I/O I/O I/O AD16 I/O I/O I/O I/O I/O I/O AD17 I/O I/O I/O I/O I/O I/O AD18 I/O I/O I/O I/O I/O I/O AD19 I/O I/O I/O I/O I/O I/O AD20 NC NC I/O I/O I/O I/O AD21 TCK TCK TCK TCK TCK TCK AD22 VPP VPP VPP VPP VPP VPP AD23 NC NC NC I/O I/O I/O AD24 VDDP VDDP VDDP VDDP VDDP VDDP AD25 NC NC I/O I/O I/O I/O AD26 NC NC I/O I/O I/O I/O AE1 VDDP VDDP VDDP VDDP VDDP VDDP AE2 VDDP VDDP VDDP VDDP VDDP VDDP AE3 NC NC I/O I/O I/O I/O AE4 NC NC I/O I/O I/O I/O AE5 NC NC I/O I/O I/O I/O AE6 NC NC I/O I/O I/O I/O AE7 NC NC I/O I/O I/O I/O AE8 I/O I/O I/O I/O I/O I/O AE9 I/O I/O I/O I/O I/O I/O AE10 I/O I/O I/O I/O I/O I/O AE11 I/O I/O I/O I/O I/O I/O AE12 I/O I/O I/O I/O I/O I/O AE13 I/O I/O I/O I/O I/O I/O AE14 I/O I/O I/O I/O I/O I/O AE15 I/O I/O I/O I/O I/O I/O AE16 I/O I/O I/O I/O I/O I/O AE17 I/O I/O I/O I/O I/O I/O AE18 I/O I/O I/O I/O I/O I/O AE19 I/O I/O I/O I/O I/O I/O AE20 NC NC I/O I/O I/O I/O AE21 NC NC I/O I/O I/O I/O AE22 NC NC I/O I/O I/O I/O AE23 VPN VPN VPN VPN VPN VPN AE24 TRST TRST TRST TRST TRST TRST AE25 VDDP VDDP VDDP VDDP VDDP VDDP Advanced v0.6 73 Pr o A S I C P L U S F a m ily F la s h F P GA s 456- P in P BGA (C ont inu ed) 74 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function AE26 VDDP VDDP VDDP VDDP VDDP VDDP AF1 VDDP VDDP VDDP VDDP VDDP VDDP AF2 VDDP VDDP VDDP VDDP VDDP VDDP AF3 NC NC I/O I/O I/O I/O AF4 NC NC I/O I/O I/O I/O AF5 NC NC I/O I/O I/O I/O AF6 NC NC I/O I/O I/O I/O AF7 NC NC I/O I/O I/O I/O AF8 NC NC NC I/O I/O I/O AF9 I/O I/O I/O I/O I/O I/O AF10 I/O I/O I/O I/O I/O I/O AF11 I/O I/O I/O I/O I/O I/O AF12 I/O I/O I/O I/O I/O I/O AF13 I/O I/O I/O I/O I/O I/O AF14 I/O I/O I/O I/O I/O I/O AF15 I/O I/O I/O I/O I/O I/O AF16 I/O I/O I/O I/O I/O I/O AF17 I/O I/O I/O I/O I/O I/O AF18 NC NC I/O I/O I/O I/O AF19 NC NC I/O I/O I/O I/O AF20 NC NC I/O I/O I/O I/O AF21 NC NC I/O I/O I/O I/O AF22 NC NC I/O I/O I/O I/O AF23 TDI TDI TDI TDI TDI TDI AF24 NC NC I/O I/O I/O I/O AF25 VDDP VDDP VDDP VDDP VDDP VDDP AF26 VDDP VDDP VDDP VDDP VDDP VDDP Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s Pa c ka ge A ss i gn m e nt s (Continued) 144- FB GA (Bot t om V iew ) 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M Advanced v0.6 75 Pr o A S I C P L U S F a m ily F la s h F P GA s 144- FB GA P i n Pin Number 76 14 4-FB GA P in (Co nti nue d) APA150 Function APA300 Function APA450 Function A1 I/O I/O I/O A2 I/O I/O A3 I/O A4 Pin Number APA150 Function APA300 Function APA450 Function D4 I/O I/O I/O I/O D5 I/O I/O I/O I/O I/O D6 I/O I/O I/O I/O I/O I/O D7 I/O I/O I/O A5 I/O I/O I/O D8 I/O I/O I/O A6 GND GND GND D9 I/O I/O I/O A7 I/O I/O I/O D10 I/O I/O I/O A8 VDD VDD VDD D11 I/O I/O I/O A9 I/O I/O I/O D12 I/O I/O I/O A10 I/O I/O I/O E1 VDD VDD VDD A11 I/O I/O I/O E2 I/O I/O I/O A12 I/O I/O I/O E3 I/O I/O I/O B1 I/O I/O I/O E4 VDDP VDDP VDDP B2 GND GND GND E5 I/O I/O I/O B3 I/O I/O I/O E6 VDDP VDDP VDDP B4 I/O I/O I/O E7 VDDP VDDP VDDP B5 I/O I/O I/O E8 AVDD AVDD AVDD B6 I/O I/O I/O E9 VDDP VDDP VDDP B7 I/O I/O I/O E10 VDD VDD VDD B8 I/O I/O I/O E11 NPECL NPECL NPECL B9 I/O I/O I/O E12 AGND AGND AGND B10 I/O I/O I/O F1 GL GL GL B11 GND GND GND F2 AGND AGND AGND B12 I/O I/O I/O F3 I/O I/O I/O C1 I/O I/O I/O F4 I/O I/O I/O C2 GL GL GL F5 GND GND GND C3 I/O I/O I/O F6 GND GND GND C4 VDD VDD VDD F7 GND GND GND C5 I/O I/O I/O F8 I/O I/O I/O C6 I/O I/O I/O F9 GL GL GL C7 I/O I/O I/O F10 GND GND GND C8 I/O I/O I/O F11 PPECL PPECL PPECL C9 I/O I/O I/O F12 GL GL GL C10 I/O I/O I/O G1 PPECL PPECL PPECL C11 I/O I/O I/O G2 GND GND GND C12 I/O I/O I/O G3 AVDD AVDD AVDD D1 I/O I/O I/O G4 NPECL NPECL NPECL D2 I/O I/O I/O G5 GND GND GND D3 I/O I/O I/O G6 GND GND GND Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 144- FB GA Pi n ( Cont i nued) Pin Number 144- FB GA Pi n ( Cont i nued) APA150 Function APA300 Function APA450 Function G7 GND GND GND G8 I/O I/O G9 I/O G10 Pin Number APA150 Function APA300 Function APA450 Function K10 GND GND GND I/O K11 I/O I/O I/O I/O I/O K12 I/O I/O I/O I/O I/O I/O L1 GND GND GND G11 I/O I/O I/O L2 I/O I/O I/O G12 I/O I/O I/O L3 I/O I/O I/O H1 VDD VDD VDD L4 I/O I/O I/O H2 I/O I/O I/O L5 VDDP VDDP VDDP H3 I/O I/O I/O L6 I/O I/O I/O H4 I/O I/O I/O L7 I/O I/O I/O H5 VDD VDD VDD L8 I/O I/O I/O H6 I/O I/O I/O L9 TMS TMS TMS H7 I/O I/O I/O L10 RCK RCK RCK H8 I/O I/O I/O L11 I/O I/O I/O H9 I/O I/O I/O L12 TRST TRST TRST H10 VDDP VDDP VDDP M1 I/O I/O I/O H11 I/O I/O I/O M2 I/O I/O I/O H12 VDD VDD VDD M3 I/O I/O I/O J1 I/O I/O I/O M4 I/O I/O I/O J2 I/O I/O I/O M5 I/O I/O I/O J3 VDDP VDDP VDDP M6 I/O I/O I/O J4 I/O I/O I/O M7 I/O I/O I/O J5 I/O I/O I/O M8 I/O I/O I/O J6 I/O I/O I/O M9 TDI TDI TDI J7 VDD VDD VDD M10 VDDP VDDP VDDP J8 TCK TCK TCK M11 VPP VPP VPP J9 I/O I/O I/O M12 VPN VPN VPN J10 TDO TDO TDO J11 I/O I/O I/O J12 I/O I/O I/O K1 I/O I/O I/O K2 I/O I/O I/O K3 I/O I/O I/O K4 I/O I/O I/O K5 I/O I/O I/O K6 I/O I/O I/O K7 GND GND GND K8 I/O I/O I/O K9 I/O I/O I/O Advanced v0.6 77 Pr o A S I C P L U S F a m ily F la s h F P GA s Pa c ka ge A ss i gn m e nt s (Continued) 256- FB GA ( Bot t om V iew ) Pin one corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T 78 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 256- P in FBG A Pin Number APA150 Function APA300 Function APA450 Function APA600 Function A1 GND GND GND GND A2 I/O I/O I/O I/O A3 I/O I/O I/O I/O A4 I/O I/O I/O I/O A5 I/O I/O I/O I/O A6 I/O I/O I/O I/O A7 I/O I/O I/O I/O A8 I/O I/O I/O I/O A9 I/O I/O I/O I/O A10 I/O I/O I/O I/O A11 I/O I/O I/O I/O A12 I/O I/O I/O I/O A13 I/O I/O I/O I/O A14 I/O I/O I/O I/O A15 I/O I/O I/O I/O A16 GND GND GND GND B1 I/O I/O I/O I/O B2 I/O I/O I/O I/O B3 I/O I/O I/O I/O B4 I/O I/O I/O I/O B5 I/O I/O I/O I/O B6 I/O I/O I/O I/O B7 I/O I/O I/O I/O B8 I/O I/O I/O I/O B9 I/O I/O I/O I/O B10 I/O I/O I/O I/O B11 I/O I/O I/O I/O B12 I/O I/O I/O I/O B13 I/O I/O I/O I/O B14 I/O I/O I/O I/O B15 I/O I/O I/O I/O B16 I/O I/O I/O I/O C1 I/O I/O I/O I/O C2 I/O I/O I/O I/O C3 I/O I/O I/O I/O C4 I/O I/O I/O I/O C5 I/O I/O I/O I/O C6 I/O I/O I/O I/O C7 I/O I/O I/O I/O Advanced v0.6 79 Pr o A S I C P L U S F a m ily F la s h F P GA s 256- P in FBG A ( Cont i nued) 80 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function C8 I/O I/O I/O I/O C9 I/O I/O I/O I/O C10 I/O I/O I/O I/O C11 I/O I/O I/O I/O C12 I/O I/O I/O I/O C13 I/O I/O I/O I/O C14 I/O I/O I/O I/O C15 I/O I/O I/O I/O C16 I/O I/O I/O I/O D1 I/O I/O I/O I/O D2 I/O I/O I/O I/O D3 I/O I/O I/O I/O D4 I/O I/O I/O I/O D5 I/O I/O I/O I/O D6 I/O I/O I/O I/O D7 I/O I/O I/O I/O D8 I/O I/O I/O I/O D9 I/O I/O I/O I/O D10 I/O I/O I/O I/O D11 I/O I/O I/O I/O D12 I/O I/O I/O I/O D13 I/O I/O I/O I/O D14 I/O I/O I/O I/O D15 I/O I/O I/O I/O D16 I/O I/O I/O I/O E1 I/O I/O I/O I/O E2 I/O I/O I/O I/O E3 I/O I/O I/O I/O E4 I/O I/O I/O I/O E5 I/O I/O I/O I/O E6 VDDP VDDP VDDP VDDP E7 VDDP VDDP VDDP VDDP E8 I/O I/O I/O I/O E9 I/O I/O I/O I/O E10 VDDP VDDP VDDP VDDP E11 VDDP VDDP VDDP VDDP E12 I/O I/O I/O I/O E13 I/O I/O I/O I/O E14 I/O I/O I/O I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 256- P in FBG A ( Cont i nued) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function E15 I/O I/O I/O I/O E16 I/O I/O I/O I/O F1 I/O I/O I/O I/O F2 I/O I/O I/O I/O F3 I/O I/O I/O I/O F4 I/O I/O I/O I/O F5 VDDP VDDP VDDP VDDP F6 GND GND GND GND F7 VDD VDD VDD VDD F8 VDD VDD VDD VDD F9 VDD VDD VDD VDD F10 VDD VDD VDD VDD F11 GND GND GND GND F12 VDDP VDDP VDDP VDDP F13 I/O I/O I/O I/O F14 I/O I/O I/O I/O F15 I/O I/O I/O I/O F16 I/O I/O I/O I/O G1 I/O I/O I/O I/O G2 I/O I/O I/O I/O G3 I/O I/O I/O I/O G4 I/O I/O I/O I/O G5 VDDP VDDP VDDP VDDP G6 VDD VDD VDD VDD G7 GND GND GND GND G8 GND GND GND GND G9 GND GND GND GND G10 GND GND GND GND G11 VDD VDD VDD VDD G12 VDDP VDDP VDDP VDDP G13 I/O I/O I/O I/O G14 I/O I/O I/O I/O G15 I/O I/O I/O I/O G16 I/O I/O I/O I/O H1 GL GL GL GL H2 NPECL NPECL NPECL NPECL H3 I/O I/O I/O I/O H4 AGND AGND AGND AGND H5 I/O I/O I/O I/O Advanced v0.6 81 Pr o A S I C P L U S F a m ily F la s h F P GA s 256- P in FBG A ( Cont i nued) 82 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function H6 VDD VDD VDD VDD H7 GND GND GND GND H8 GND GND GND GND H9 GND GND GND GND H10 GND GND GND GND H11 VDD VDD VDD VDD H12 I/O I/O I/O I/O H13 I/O I/O I/O I/O H14 NPECL NPECL NPECL NPECL H15 AGND AGND AGND AGND H16 GL GL GL GL J1 GL GL GL GL J2 PPECL PPECL PPECL PPECL J3 AVDD AVDD AVDD AVDD J4 I/O I/O I/O I/O J5 I/O I/O I/O I/O J6 VDD VDD VDD VDD J7 GND GND GND GND J8 GND GND GND GND J9 GND GND GND GND J10 GND GND GND GND J11 VDD VDD VDD VDD J12 I/O I/O I/O I/O J13 PPECL PPECL PPECL PPECL J14 I/O I/O I/O I/O J15 AVDD AVDD AVDD AVDD J16 GL GL GL GL K1 I/O I/O I/O I/O K2 I/O I/O I/O I/O K3 I/O I/O I/O I/O K4 I/O I/O I/O I/O K5 VDDP VDDP VDDP VDDP K6 VDD VDD VDD VDD K7 GND GND GND GND K8 GND GND GND GND K9 GND GND GND GND K10 GND GND GND GND K11 VDD VDD VDD VDD K12 VDDP VDDP VDDP VDDP Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 256- P in FBG A ( Cont i nued) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function K13 I/O I/O I/O I/O K14 I/O I/O I/O I/O K15 I/O I/O I/O I/O K16 I/O I/O I/O I/O L1 I/O I/O I/O I/O L2 I/O I/O I/O I/O L3 I/O I/O I/O I/O L4 I/O I/O I/O I/O L5 VDDP VDDP VDDP VDDP L6 GND GND GND GND L7 VDD VDD VDD VDD L8 VDD VDD VDD VDD L9 VDD VDD VDD VDD L10 VDD VDD VDD VDD L11 GND GND GND GND L12 VDDP VDDP VDDP VDDP L13 I/O I/O I/O I/O L14 I/O I/O I/O I/O L15 I/O I/O I/O I/O L16 I/O I/O I/O I/O M1 I/O I/O I/O I/O M2 I/O I/O I/O I/O M3 I/O I/O I/O I/O M4 I/O I/O I/O I/O M5 I/O I/O I/O I/O M6 VDDP VDDP VDDP VDDP M7 VDDP VDDP VDDP VDDP M8 I/O I/O I/O I/O M9 I/O I/O I/O I/O M10 VDDP VDDP VDDP VDDP M11 VDDP VDDP VDDP VDDP M12 I/O I/O I/O I/O M13 I/O I/O I/O I/O M14 I/O I/O I/O I/O M15 I/O I/O I/O I/O M16 I/O I/O I/O I/O N1 I/O I/O I/O I/O N2 I/O I/O I/O I/O N3 I/O I/O I/O I/O Advanced v0.6 83 Pr o A S I C P L U S F a m ily F la s h F P GA s 256- P in FBG A ( Cont i nued) 84 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function N4 I/O I/O I/O I/O N5 I/O I/O I/O I/O N6 I/O I/O I/O I/O N7 I/O I/O I/O I/O N8 I/O I/O I/O I/O N9 I/O I/O I/O I/O N10 I/O I/O I/O I/O N11 I/O I/O I/O I/O N12 I/O I/O I/O I/O N13 I/O I/O I/O I/O N14 RCK RCK RCK RCK N15 I/O I/O I/O I/O N16 I/O I/O I/O I/O P1 I/O I/O I/O I/O P2 I/O I/O I/O I/O P3 I/O I/O I/O I/O P4 I/O I/O I/O I/O P5 I/O I/O I/O I/O P6 I/O I/O I/O I/O P7 I/O I/O I/O I/O P8 I/O I/O I/O I/O P9 I/O I/O I/O I/O P10 I/O I/O I/O I/O P11 I/O I/O I/O I/O P12 I/O I/O I/O I/O P13 TCK TCK TCK TCK P14 VPP VPP VPP VPP P15 TRST TRST TRST TRST P16 I/O I/O I/O I/O R1 I/O I/O I/O I/O R2 I/O I/O I/O I/O R3 I/O I/O I/O I/O R4 I/O I/O I/O I/O R5 I/O I/O I/O I/O R6 I/O I/O I/O I/O R7 I/O I/O I/O I/O R8 I/O I/O I/O I/O R9 I/O I/O I/O I/O R10 I/O I/O I/O I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 256- P in FBG A ( Cont i nued) Pin Number APA150 Function APA300 Function APA450 Function APA600 Function R11 I/O I/O I/O I/O R12 I/O I/O I/O I/O R13 I/O I/O I/O I/O R14 TDI TDI TDI TDI R15 VPN VPN VPN VPN R16 TDO TDO TDO TDO T1 GND GND GND GND T2 I/O I/O I/O I/O T3 I/O I/O I/O I/O T4 I/O I/O I/O I/O T5 I/O I/O I/O I/O T6 I/O I/O I/O I/O T7 I/O I/O I/O I/O T8 I/O I/O I/O I/O T9 I/O I/O I/O I/O T10 I/O I/O I/O I/O T11 I/O I/O I/O I/O T12 I/O I/O I/O I/O T13 I/O I/O I/O I/O T14 I/O I/O I/O I/O T15 TMS TMS TMS TMS T16 GND GND GND GND Advanced v0.6 85 Pr o A S I C P L U S F a m ily F la s h F P GA s P a c ka ge P i n A s si g nm e n t s (Continued) 676- P in FBG A ( Bot t om V iew ) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 86 Advanced v0.6 8 7 6 5 4 3 2 1 Pr o A SI C P L U S F a m ily F la s h F P GA s 676- FB GA Pi n 676- FB GA Pi n ( Cont i nued) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function A1 GND GND B14 I/O I/O A2 GND GND B15 I/O I/O A3 I/O I/O B16 I/O I/O A4 I/O I/O B17 I/O I/O A5 I/O I/O B18 I/O I/O A6 I/O I/O B19 I/O I/O A7 I/O I/O B20 I/O I/O A8 I/O I/O B21 I/O I/O A9 I/O I/O B22 I/O I/O A10 I/O I/O B23 I/O I/O A11 I/O I/O B24 I/O I/O A12 I/O I/O B25 GND GND A13 I/O I/O B26 GND GND A14 I/O I/O C1 GND GND A15 I/O I/O C2 GND GND A16 I/O I/O C3 GND GND A17 I/O I/O C4 GND GND A18 I/O I/O C5 I/O I/O A19 I/O I/O C6 I/O I/O A20 I/O I/O C7 I/O I/O A21 I/O I/O C8 I/O I/O A22 I/O I/O C9 I/O I/O A23 I/O I/O C10 I/O I/O A24 I/O I/O C11 I/O I/O A25 GND GND C12 I/O I/O A26 GND GND C13 I/O I/O B1 GND GND C14 I/O I/O B2 GND GND C15 I/O I/O B3 GND GND C16 I/O I/O B4 GND GND C17 I/O I/O B5 I/O I/O C18 I/O I/O B6 I/O I/O C19 I/O I/O B7 I/O I/O C20 I/O I/O B8 I/O I/O C21 I/O I/O B9 I/O I/O C22 I/O I/O B10 I/O I/O C23 I/O I/O B11 I/O I/O C24 I/O I/O B12 I/O I/O C25 I/O I/O B13 I/O I/O C26 I/O I/O Advanced v0.6 87 Pr o A S I C P L U S F a m ily F la s h F P GA s 676- FB GA P i n ( Cont i nued) 88 67 6-FB GA P in (Co nti nue d) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function D1 I/O I/O E14 I/O I/O D2 I/O I/O E15 I/O I/O D3 GND GND E16 I/O I/O D4 I/O I/O E17 I/O I/O D5 I/O I/O E18 I/O I/O D6 I/O I/O E19 I/O I/O D7 I/O I/O E20 I/O I/O D8 I/O I/O E21 I/O I/O D9 I/O I/O E22 I/O I/O D10 I/O I/O E23 I/O I/O D11 I/O I/O E24 I/O I/O D12 I/O I/O E25 I/O I/O D13 I/O I/O E26 I/O I/O D14 I/O I/O F1 I/O I/O D15 I/O I/O F2 I/O I/O D16 I/O I/O F3 I/O I/O D17 I/O I/O F4 I/O I/O D18 I/O I/O F5 GND GND D19 I/O I/O F6 I/O I/O D20 I/O I/O F7 NC NC D21 I/O I/O F8 I/O I/O D22 I/O I/O F9 I/O I/O D23 I/O I/O F10 I/O I/O D24 I/O I/O F11 I/O I/O D25 I/O I/O F12 I/O I/O D26 I/O I/O F13 I/O I/O E1 I/O I/O F14 I/O I/O E2 I/O I/O F15 I/O I/O E3 I/O I/O F16 I/O I/O E4 I/O I/O F17 I/O I/O E5 I/O I/O F18 I/O I/O E6 I/O I/O F19 I/O I/O E7 I/O I/O F20 I/O I/O E8 I/O I/O F21 I/O I/O E9 I/O I/O F22 I/O I/O E10 I/O I/O F23 I/O I/O E11 I/O I/O F24 I/O I/O E12 I/O I/O F25 I/O I/O E13 I/O I/O F26 I/O I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 676- FB GA Pi n ( Cont i nued) 676- FB GA Pi n ( Cont i nued) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function G1 I/O I/O H14 VDDP VDDP G2 I/O I/O H15 VDDP VDDP G3 I/O I/O H16 VDDP VDDP G4 I/O I/O H17 VDDP VDDP G5 I/O I/O H18 VDDP VDDP G6 I/O I/O H19 VDD VDD G7 I/O I/O H20 VDD VDD G8 VDD VDD H21 I/O I/O G9 NC NC H22 I/O I/O G10 I/O I/O H23 I/O I/O G11 NC NC H24 I/O I/O G12 I/O I/O H25 I/O I/O G13 NC NC H26 I/O I/O G14 I/O I/O J1 I/O I/O G15 NC NC J2 I/O I/O G16 I/O I/O J3 I/O I/O G17 NC NC J4 I/O I/O G18 I/O I/O J5 I/O I/O G19 VDDP VDDP J6 I/O I/O G20 NC NC J7 NC NC G21 I/O I/O J8 VDDP VDDP G22 I/O I/O J9 VDD VDD G23 I/O I/O J10 VDD VDD G24 I/O I/O J11 VDD VDD G25 I/O I/O J12 VDD VDD G26 I/O I/O J13 VDD VDD H1 I/O I/O J14 VDD VDD H2 I/O I/O J15 VDD VDD H3 I/O I/O J16 VDD VDD H4 I/O I/O J17 VDD VDD H5 I/O I/O J18 VDD VDD H6 I/O I/O J19 VDDP VDDP H7 VDDP VDDP J20 NC NC H8 VDD VDD J21 I/O I/O H9 VDDP VDDP J22 I/O I/O H10 VDDP VDDP J23 I/O I/O H11 VDDP VDDP J24 I/O I/O H12 VDDP VDDP J25 I/O I/O H13 VDDP VDDP J26 I/O I/O Advanced v0.6 89 Pr o A S I C P L U S F a m ily F la s h F P GA s 676- FB GA P i n ( Cont i nued) 90 67 6-FB GA P in (Co nti nue d) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function K1 I/O I/O L14 GND GND K2 I/O I/O L15 GND GND K3 I/O I/O L16 GND GND K4 I/O I/O L17 GND GND K5 I/O I/O L18 VDD VDD K6 I/O I/O L19 VDDP VDDP K7 I/O I/O L20 NC NC K8 VDDP VDDP L21 I/O I/O K9 VDD VDD L22 I/O I/O K10 GND GND L23 I/O I/O K11 GND GND L24 I/O I/O K12 GND GND L25 I/O I/O K13 GND GND L26 I/O I/O K14 GND GND M1 I/O I/O K15 GND GND M2 I/O I/O K16 GND GND M3 I/O I/O K17 GND GND M4 I/O I/O K18 VDD VDD M5 I/O I/O K19 VDDP VDDP M6 I/O I/O K20 I/O I/O M7 I/O I/O K21 I/O I/O M8 VDDP VDDP K22 I/O I/O M9 VDD VDD K23 I/O I/O M10 GND GND K24 I/O I/O M11 GND GND K25 I/O I/O M12 GND GND K26 I/O I/O M13 GND GND L1 I/O I/O M14 GND GND L2 I/O I/O M15 GND GND L3 I/O I/O M16 GND GND L4 I/O I/O M17 GND GND L5 I/O I/O M18 VDD VDD L6 I/O I/O M19 VDDP VDDP L7 NC NC M20 I/O I/O L8 VDDP VDDP M21 I/O I/O L9 VDD VDD M22 I/O I/O L10 GND GND M23 I/O I/O L11 GND GND M24 I/O I/O L12 GND GND M25 I/O I/O L13 GND GND M26 I/O I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 676- FB GA Pi n ( Cont i nued) 676- FB GA Pi n ( Cont i nued) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function N1 GL GL P14 GND GND N2 AGND AGND P15 GND GND N3 I/O I/O P16 GND GND N4 I/O I/O P17 GND GND N5 NPECL NPECL P18 VDD VDD N6 I/O I/O P19 VDDP VDDP N7 NC NC P20 I/O I/O N8 VDDP VDDP P21 I/O I/O N9 VDD VDD P22 I/O I/O N10 GND GND P23 I/O I/O N11 GND GND P24 PPECL PPECL N12 GND GND P25 AVDD AVDD N13 GND GND P26 AGND AGND N14 GND GND R1 I/O I/O N15 GND GND R2 I/O I/O N16 GND GND R3 I/O I/O N17 GND GND R4 I/O I/O N18 VDD VDD R5 I/O I/O N19 VDDP VDDP R6 I/O I/O N20 NC NC R7 NC NC N21 I/O I/O R8 VDDP VDDP N22 GL GL R9 VDD VDD N23 I/O I/O R10 GND GND N24 NPECL NPECL R11 GND GND N25 GL GL R12 GND GND N26 I/O I/O R13 GND GND P1 GL GL R14 GND GND P2 AVDD AVDD R15 GND GND P3 I/O I/O R16 GND GND P4 I/O I/O R17 GND GND P5 PPECL PPECL R18 VDD VDD P6 I/O I/O R19 VDDP VDDP P7 I/O I/O R20 NC NC P8 VDDP VDDP R21 I/O I/O P9 VDD VDD R22 I/O I/O P10 GND GND R23 I/O I/O P11 GND GND R24 I/O I/O P12 GND GND R25 I/O I/O P13 GND GND R26 I/O I/O Advanced v0.6 91 Pr o A S I C P L U S F a m ily F la s h F P GA s 676- FB GA P i n ( Cont i nued) 92 67 6-FB GA P in (Co nti nue d) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function T1 I/O I/O U14 GND GND T2 I/O I/O U15 GND GND T3 I/O I/O U16 GND GND T4 I/O I/O U17 GND GND T5 I/O I/O U18 VDD VDD T6 I/O I/O U19 VDDP VDDP T7 I/O I/O U20 NC NC T8 VDDP VDDP U21 I/O I/O T9 VDD VDD U22 I/O I/O T10 GND GND U23 I/O I/O T11 GND GND U24 I/O I/O T12 GND GND U25 I/O I/O T13 GND GND U26 I/O I/O T14 GND GND V1 I/O I/O T15 GND GND V2 I/O I/O T16 GND GND V3 I/O I/O T17 GND GND V4 I/O I/O T18 VDD VDD V5 I/O I/O T19 VDDP VDDP V6 I/O I/O T20 I/O I/O V7 I/O I/O T21 I/O I/O V8 VDDP VDDP T22 I/O I/O V9 VDD VDD T23 I/O I/O V10 VDD VDD T24 I/O I/O V11 VDD VDD T25 I/O I/O V12 VDD VDD T26 I/O I/O V13 VDD VDD U1 I/O I/O V14 VDD VDD U2 I/O I/O V15 VDD VDD U3 I/O I/O V16 VDD VDD U4 I/O I/O V17 VDD VDD U5 I/O I/O V18 VDD VDD U6 I/O I/O V19 VDDP VDDP U7 NC NC V20 I/O I/O U8 VDDP VDDP V21 I/O I/O U9 VDD VDD V22 I/O I/O U10 GND GND V23 I/O I/O U11 GND GND V24 I/O I/O U12 GND GND V25 I/O I/O U13 GND GND V26 I/O I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 676- FB GA Pi n ( Cont i nued) 676- FB GA Pi n ( Cont i nued) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function W1 I/O I/O Y14 I/O I/O W2 I/O I/O Y15 NC NC W3 I/O I/O Y16 I/O I/O W4 I/O I/O Y17 NC NC W5 I/O I/O Y18 I/O I/O W6 I/O I/O Y19 VDD VDD W7 VDD VDD Y20 VPP VPP W8 VDD VDD Y21 I/O I/O W9 VDDP VDDP Y22 I/O I/O W10 VDDP VDDP Y23 I/O I/O W11 VDDP VDDP Y24 I/O I/O W12 VDDP VDDP Y25 I/O I/O W13 VDDP VDDP Y26 I/O I/O W14 VDDP VDDP AA1 I/O I/O W15 VDDP VDDP AA2 I/O I/O W16 VDDP VDDP AA3 I/O I/O W17 VDDP VDDP AA4 I/O I/O W18 VDDP VDDP AA5 I/O I/O W19 VDD VDD AA6 GND GND W20 VDDP VDDP AA7 I/O I/O W21 I/O I/O AA8 I/O I/O W22 I/O I/O AA9 I/O I/O W23 I/O I/O AA10 I/O I/O W24 I/O I/O AA11 I/O I/O W25 I/O I/O AA12 I/O I/O W26 I/O I/O AA13 I/O I/O Y1 I/O I/O AA14 I/O I/O Y2 I/O I/O AA15 I/O I/O Y3 I/O I/O AA16 I/O I/O Y4 I/O I/O AA17 I/O I/O Y5 I/O I/O AA18 I/O I/O Y6 I/O I/O AA19 I/O I/O Y7 I/O I/O AA20 I/O I/O Y8 VDDP VDDP AA21 TDO TDO Y9 NC NC AA22 GND GND Y10 I/O I/O AA23 GND GND Y11 NC NC AA24 I/O I/O Y12 I/O I/O AA25 I/O I/O Y13 NC NC AA26 I/O I/O Advanced v0.6 93 Pr o A S I C P L U S F a m ily F la s h F P GA s 676- FB GA P i n ( Cont i nued) 94 67 6-FB GA P in (Co nti nue d) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function AB1 I/O I/O AC14 I/O I/O AB2 I/O I/O AC15 I/O I/O AB3 I/O I/O AC16 I/O I/O AB4 I/O I/O AC17 I/O I/O AB5 I/O I/O AC18 I/O I/O AB6 GND GND AC19 I/O I/O AB7 GND GND AC20 I/O I/O AB8 I/O I/O AC21 I/O I/O AB9 I/O I/O AC22 TMS TMS AB10 I/O I/O AC23 RCK RCK AB11 I/O I/O AC24 I/O I/O AB12 I/O I/O AC25 I/O I/O AB13 I/O I/O AC26 I/O I/O AB14 I/O I/O AD1 I/O I/O AB15 I/O I/O AD2 I/O I/O AB16 I/O I/O AD3 I/O I/O AB17 I/O I/O AD4 I/O I/O AB18 I/O I/O AD5 I/O I/O AB19 I/O I/O AD6 I/O I/O AB20 I/O I/O AD7 I/O I/O AB21 TCK TCK AD8 I/O I/O AB22 TRST TRST AD9 I/O I/O AB23 I/O I/O AD10 I/O I/O AB24 I/O I/O AD11 I/O I/O AB25 I/O I/O AD12 I/O I/O AB26 I/O I/O AD13 I/O I/O AC1 I/O I/O AD14 I/O I/O AC2 I/O I/O AD15 I/O I/O AC3 I/O I/O AD16 I/O I/O AC4 I/O I/O AD17 I/O I/O AC5 GND GND AD18 I/O I/O AC6 I/O I/O AD19 I/O I/O AC7 I/O I/O AD20 I/O I/O AC8 I/O I/O AD21 I/O I/O AC9 GND GND AD22 I/O I/O AC10 I/O I/O AD23 TDI TDI AC11 I/O I/O AD24 VPN VPN AC12 I/O I/O AD25 I/O I/O AC13 I/O I/O AD26 I/O I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 676- FB GA Pi n ( Cont i nued) 676- FB GA Pi n ( Cont i nued) Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function AE1 GND GND AF14 I/O I/O AE2 GND GND AF15 I/O I/O AE3 GND GND AF16 I/O I/O AE4 I/O I/O AF17 I/O I/O AE5 I/O I/O AF18 I/O I/O AE6 I/O I/O AF19 I/O I/O AE7 I/O I/O AF20 I/O I/O AE8 I/O I/O AF21 I/O I/O AE9 I/O I/O AF22 I/O I/O AE10 I/O I/O AF23 I/O I/O AE11 I/O I/O AF24 I/O I/O AE12 I/O I/O AF25 GND GND AE13 I/O I/O AF26 GND GND AE14 I/O I/O AE15 I/O I/O AE16 I/O I/O AE17 I/O I/O AE18 I/O I/O AE19 I/O I/O AE20 I/O I/O AE21 I/O I/O AE22 I/O I/O AE23 I/O I/O AE24 I/O I/O AE25 GND GND AE26 GND GND AF1 GND GND AF2 GND GND AF3 GND GND AF4 GND GND AF5 I/O I/O AF6 I/O I/O AF7 I/O I/O AF8 I/O I/O AF9 I/O I/O AF10 I/O I/O AF11 I/O I/O AF12 I/O I/O AF13 I/O I/O Advanced v0.6 95 Pr o A S I C P L U S F a m ily F la s h F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 896- P in FBG A ( Bot t om V iew ) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 96 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 896 FB GA Pi n 896 FB GA Pi n ( Cont i nued) APA750 Function APA1000 Function APA750 Function APA1000 Function A2 GND GND B12 I/O I/O A3 GND GND B13 I/O I/O A4 I/O I/O B14 I/O I/O A5 GND GND B15 I/O I/O A6 I/O I/O B16 I/O I/O A7 GND GND B17 I/O I/O A8 I/O I/O B18 I/O I/O A9 I/O I/O B19 I/O I/O A10 I/O I/O B20 I/O I/O A11 I/O I/O B21 I/O I/O A12 I/O I/O B22 I/O I/O A13 I/O I/O B23 I/O I/O A14 I/O I/O B24 I/O I/O A15 I/O I/O B25 VDD VDD A16 I/O I/O B26 I/O I/O A17 I/O I/O B27 VDD VDD A18 I/O I/O B28 I/O I/O A19 I/O I/O B29 GND GND A20 I/O I/O B30 GND GND A21 I/O I/O C1 GND GND A22 I/O I/O C2 I/O I/O A23 I/O I/O C3 VDD VDD A24 GND GND C4 I/O I/O A25 I/O I/O C5 VDDP VDDP A26 GND GND C6 I/O I/O A27 I/O I/O C7 I/O I/O A28 GND GND C8 I/O I/O A29 GND GND C9 I/O I/O B1 GND GND C10 I/O I/O B2 GND GND C11 I/O I/O B3 I/O I/O C12 I/O I/O B4 VDD VDD C13 I/O I/O B5 I/O I/O C14 I/O I/O B6 VDD VDD C15 I/O I/O B7 I/O I/O C16 I/O I/O B8 I/O I/O C17 I/O I/O B9 I/O I/O C18 I/O I/O B10 I/O I/O C19 I/O I/O B11 I/O I/O C20 I/O I/O Pin Number Pin Number Advanced v0.6 97 Pr o A S I C P L U S F a m ily F la s h F P GA s 896 FB GA P i n ( Cont i nued) APA750 Function APA1000 Function APA750 Function APA1000 Function C21 I/O I/O D30 I/O I/O C22 I/O I/O E1 GND GND C23 I/O I/O E2 I/O I/O C24 I/O I/O E3 VDDP VDDP C25 I/O I/O E4 I/O I/O C26 VDDP VDDP E5 VDD VDD C27 I/O I/O E6 I/O I/O C28 VDD VDD E7 VDDP VDDP C29 NC I/O E8 I/O I/O C30 GND GND E9 I/O I/O D1 I/O I/O E10 I/O I/O D2 VDD VDD E11 I/O I/O D3 I/O I/O E12 I/O I/O D4 GND GND E13 I/O I/O D5 I/O I/O E14 I/O I/O D6 I/O I/O E15 I/O I/O D7 I/O I/O E16 I/O I/O D8 I/O I/O E17 I/O I/O D9 I/O I/O E18 I/O I/O D10 I/O I/O E19 I/O I/O D11 I/O I/O E20 I/O I/O D12 I/O I/O E21 I/O I/O D13 I/O I/O E22 I/O I/O D14 I/O I/O E23 I/O I/O D15 I/O I/O E24 VDDP VDDP D16 I/O I/O E25 I/O I/O D17 I/O I/O E26 VDD VDD D18 I/O I/O E27 I/O I/O D19 I/O I/O E28 VDDP VDDP D20 I/O I/O E29 I/O I/O D21 I/O I/O E30 GND GND D22 I/O I/O F1 I/O I/O D23 I/O I/O F2 VDD VDD D24 I/O I/O F3 I/O I/O D25 I/O I/O F4 I/O I/O D26 I/O I/O F5 I/O I/O D27 GND GND F6 GND GND D28 I/O I/O F7 I/O I/O D29 VDD VDD F8 I/O I/O Pin Number 98 89 6 FB GA P in (Co nti nue d) Pin Number Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) APA750 Function APA1000 Function APA750 Function APA1000 Function F9 I/O I/O G18 I/O I/O F10 I/O I/O G19 I/O I/O F11 I/O I/O G20 I/O I/O F12 I/O I/O G21 I/O I/O F13 I/O I/O G22 VDDP VDDP F14 I/O I/O G23 I/O I/O F15 I/O I/O G24 VDD VDD F16 I/O I/O G25 I/O I/O F17 I/O I/O G26 VDDP VDDP F18 I/O I/O G27 I/O I/O F19 I/O I/O G28 I/O I/O F20 I/O I/O G29 I/O I/O F21 I/O I/O G30 GND GND F22 I/O I/O H1 I/O I/O F23 I/O I/O H2 I/O I/O F24 I/O I/O H3 I/O I/O F25 GND GND H4 I/O I/O F26 I/O I/O H5 I/O I/O F27 I/O I/O H6 I/O I/O F28 I/O I/O H7 I/O I/O F29 VDD VDD H8 GND GND F30 I/O I/O H9 NC I/O G1 GND GND H10 NC I/O G2 I/O I/O H11 NC I/O G3 I/O I/O H12 NC I/O G4 I/O I/O H13 NC I/O G5 VDDP VDDP H14 NC I/O G6 I/O I/O H15 NC I/O G7 VDD VDD H16 NC I/O G8 I/O I/O H17 NC I/O G9 VDDP VDDP H18 NC I/O G10 I/O I/O H19 NC I/O G11 I/O I/O H20 NC I/O G12 I/O I/O H21 NC I/O G13 I/O I/O H22 NC I/O G14 I/O I/O H23 GND GND G15 I/O I/O H24 I/O I/O G16 I/O I/O H25 I/O I/O G17 I/O I/O H26 I/O I/O Pin Number Pin Number Advanced v0.6 99 Pr o A S I C P L U S F a m ily F la s h F P GA s 896 FB GA P i n ( Cont i nued) APA750 Function APA1000 Function APA750 Function APA1000 Function H27 I/O I/O K6 I/O I/O H28 I/O I/O K7 I/O I/O H29 I/O I/O K8 I/O I/O H30 I/O I/O K9 NC I/O J1 I/O I/O K10 VDD VDD J2 I/O I/O K11 NC I/O J3 I/O I/O K12 VDDP VDDP J4 I/O I/O K13 VDDP VDDP J5 I/O I/O K14 VDDP VDDP J6 I/O I/O K15 VDDP VDDP J7 VDDP VDDP K16 VDDP VDDP J8 I/O I/O K17 VDDP VDDP J9 VDD VDD K18 VDDP VDDP J10 NC I/O K19 VDDP VDDP J11 NC I/O K20 NC I/O J12 NC I/O K21 VDD VDD J13 NC I/O K22 NC I/O J14 NC I/O K23 I/O I/O J15 NC I/O K24 I/O I/O J16 NC I/O K25 I/O I/O J17 NC I/O K26 I/O I/O J18 NC I/O K27 I/O I/O J19 NC I/O K28 I/O I/O J20 NC I/O K29 I/O I/O J21 NC I/O K30 I/O I/O J22 VDD VDD L1 I/O I/O J23 I/O I/O L2 I/O I/O J24 VDDP VDDP L3 I/O I/O J25 I/O I/O L4 I/O I/O J26 I/O I/O L5 I/O I/O J27 I/O I/O L6 I/O I/O J28 I/O I/O L7 I/O I/O J29 I/O I/O L8 I/O I/O J30 I/O I/O L9 NC I/O K1 I/O I/O L10 NC I/O K2 I/O I/O L11 VDD VDD K3 I/O I/O L12 VDD VDD K4 I/O I/O L13 VDD VDD K5 I/O I/O L14 VDD VDD Pin Number 100 89 6 FB GA P in (Co nti nue d) Pin Number Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) APA750 Function APA1000 Function APA750 Function APA1000 Function L15 VDD VDD M24 I/O I/O L16 VDD VDD M25 I/O I/O L17 VDD VDD M26 I/O I/O L18 VDD VDD M27 I/O I/O L19 VDD VDD M28 I/O I/O L20 VDD VDD M29 I/O I/O L21 NC I/O M30 I/O I/O L22 NC I/O N1 I/O I/O L23 I/O I/O N2 I/O I/O L24 I/O I/O N3 I/O I/O L25 I/O I/O N4 I/O I/O L26 I/O I/O N5 I/O I/O L27 I/O I/O N6 I/O I/O L28 I/O I/O N7 I/O I/O L29 I/O I/O N8 I/O I/O L30 I/O I/O N9 NC I/O M1 I/O I/O N10 VDDP VDDP M2 I/O I/O N11 VDD VDD M3 I/O I/O N12 GND GND M4 I/O I/O N13 GND GND M5 I/O I/O N14 GND GND M6 I/O I/O N15 GND GND M7 I/O I/O N16 GND GND M8 I/O I/O N17 GND GND M9 NC I/O N18 GND GND M10 VDDP VDDP N19 GND GND M11 VDD VDD N20 VDD VDD M12 GND GND N21 VDDP VDDP M13 GND GND N22 NC I/O M14 GND GND N23 I/O I/O M15 GND GND N24 I/O I/O M16 GND GND N25 I/O I/O M17 GND GND N26 I/O I/O M18 GND GND N27 I/O I/O M19 GND GND N28 I/O I/O M20 VDD VDD N29 I/O I/O M21 VDDP VDDP N30 I/O I/O M22 NC I/O P1 I/O I/O M23 I/O I/O P2 I/O I/O Pin Number Pin Number Advanced v0.6 101 Pr o A S I C P L U S F a m ily F la s h F P GA s 896 FB GA P i n ( Cont i nued) APA750 Function APA1000 Function APA750 Function APA1000 Function P3 I/O I/O R12 GND GND P4 I/O I/O R13 GND GND P5 I/O I/O R14 GND GND P6 I/O I/O R15 GND GND P7 I/O I/O R16 GND GND P8 I/O I/O R17 GND GND P9 I/O I/O R18 GND GND P10 VDDP VDDP R19 GND GND P11 VDD VDD R20 VDD VDD P12 GND GND R21 VDDP VDDP P13 GND GND R22 I/O I/O P14 GND GND R23 I/O I/O P15 GND GND R24 I/O I/O P16 GND GND R25 I/O I/O P17 GND GND R26 I/O I/O P18 GND GND R27 NPECL NPECL P19 GND GND R28 AGND AGND P20 VDD VDD R29 I/O I/O P21 VDDP VDDP R30 I/O I/O P22 I/O I/O T1 I/O I/O P23 I/O I/O T2 AVDD AVDD P24 I/O I/O T3 GL GL P25 I/O I/O T4 PPECL PPECL P26 I/O I/O T5 I/O I/O P27 I/O I/O T6 I/O I/O P28 I/O I/O T7 I/O I/O P29 I/O I/O T8 I/O I/O P30 I/O I/O T9 I/O I/O R1 I/O I/O T10 VDDP VDDP R2 I/O I/O T11 VDD VDD R3 AGND AGND T12 GND GND R4 NPECL NPECL T13 GND GND R5 GL GL T14 GND GND R6 I/O I/O T15 GND GND R7 I/O I/O T16 GND GND R8 I/O I/O T17 GND GND R9 NC I/O T18 GND GND R10 VDDP VDDP T19 GND GND R11 VDD VDD T20 VDD VDD Pin Number 102 89 6 FB GA P in (Co nti nue d) Pin Number Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) APA750 Function APA1000 Function APA750 Function APA1000 Function T21 VDDP VDDP U30 I/O I/O T22 I/O I/O V1 I/O I/O T23 I/O I/O V2 I/O I/O T24 I/O I/O V3 I/O I/O T25 I/O I/O V4 I/O I/O T26 PPECL PPECL V5 I/O I/O T27 GL GL V6 I/O I/O T28 GL GL V7 I/O I/O T29 AVDD AVDD V8 I/O I/O T30 I/O I/O V9 NC I/O U1 I/O I/O V10 VDDP VDDP U2 I/O I/O V11 VDD VDD U3 I/O I/O V12 GND GND U4 I/O I/O V13 GND GND U5 I/O I/O V14 GND GND U6 I/O I/O V15 GND GND U7 I/O I/O V16 GND GND U8 I/O I/O V17 GND GND U9 NC I/O V18 GND GND U10 VDDP VDDP V19 GND GND U11 VDD VDD V20 VDD VDD U12 GND GND V21 VDDP VDDP U13 GND GND V22 NC I/O U14 GND GND V23 I/O I/O U15 GND GND V24 I/O I/O U16 GND GND V25 I/O I/O U17 GND GND V26 I/O I/O U18 GND GND V27 I/O I/O U19 GND GND V28 I/O I/O U20 VDD VDD V29 I/O I/O U21 VDDP VDDP V30 I/O I/O U22 NC I/O W1 I/O I/O U23 I/O I/O W2 I/O I/O U24 I/O I/O W3 I/O I/O U25 I/O I/O W4 I/O I/O U26 I/O I/O W5 I/O I/O U27 I/O I/O W6 I/O I/O U28 I/O I/O W7 I/O I/O U29 I/O I/O W8 I/O I/O Pin Number Pin Number Advanced v0.6 103 Pr o A S I C P L U S F a m ily F la s h F P GA s 896 FB GA P i n ( Cont i nued) APA750 Function APA1000 Function APA750 Function APA1000 Function W9 NC I/O Y18 VDD VDD W10 VDDP VDDP Y19 VDD VDD W11 VDD VDD Y20 VDD VDD W12 GND GND Y21 NC I/O W13 GND GND Y22 NC I/O W14 GND GND Y23 I/O I/O W15 GND GND Y24 I/O I/O W16 GND GND Y25 I/O I/O W17 GND GND Y26 I/O I/O W18 GND GND Y27 I/O I/O W19 GND GND Y28 I/O I/O W20 VDD VDD Y29 I/O I/O W21 VDDP VDDP Y30 I/O I/O W22 NC I/O AA1 I/O I/O W23 I/O I/O AA2 I/O I/O W24 I/O I/O AA3 I/O I/O W25 I/O I/O AA4 I/O I/O W26 I/O I/O AA5 I/O I/O W27 I/O I/O AA6 I/O I/O W28 I/O I/O AA7 I/O I/O W29 I/O I/O AA8 I/O I/O W30 I/O I/O AA9 NC I/O Y1 I/O I/O AA10 VDD VDD Y2 I/O I/O AA11 NC I/O Y3 I/O I/O AA12 VDDP VDDP Y4 I/O I/O AA13 VDDP VDDP Y5 I/O I/O AA14 VDDP VDDP Y6 I/O I/O AA15 VDDP VDDP Y7 I/O I/O AA16 VDDP VDDP Y8 I/O I/O AA17 VDDP VDDP Y9 NC I/O AA18 VDDP VDDP Y10 NC I/O AA19 VDDP VDDP Y11 VDD VDD AA20 NC I/O Y12 VDD VDD AA21 VDD VDD Y13 VDD VDD AA22 NC I/O Y14 VDD VDD AA23 I/O I/O Y15 VDD VDD AA24 I/O I/O Y16 VDD VDD AA25 I/O I/O Y17 VDD VDD AA26 I/O I/O Pin Number 104 89 6 FB GA P in (Co nti nue d) Pin Number Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) APA750 Function APA1000 Function APA750 Function APA1000 Function AA27 I/O I/O AC6 I/O I/O AA28 I/O I/O AC7 I/O I/O AA29 I/O I/O AC8 GND GND AA30 I/O I/O AC9 NC I/O AB1 I/O I/O AC10 NC I/O AB2 I/O I/O AC11 NC I/O AB3 I/O I/O AC12 NC I/O AB4 I/O I/O AC13 NC I/O AB5 I/O I/O AC14 NC I/O AB6 I/O I/O AC15 NC I/O AB7 VDDP VDDP AC16 NC I/O AB8 I/O I/O AC17 NC I/O AB9 VDD VDD AC18 NC I/O AB10 NC I/O AC19 NC I/O AB11 NC I/O AC20 NC I/O AB12 NC I/O AC21 NC I/O AB13 NC I/O AC22 NC I/O AB14 NC I/O AC23 GND GND AB15 NC I/O AC24 I/O I/O AB16 NC I/O AC25 I/O I/O AB17 NC I/O AC26 I/O I/O AB18 NC I/O AC27 I/O I/O AB19 NC I/O AC28 I/O I/O AB20 NC I/O AC29 I/O I/O AB21 NC I/O AC30 I/O I/O AB22 VDD VDD AD1 GND GND AB23 I/O I/O AD2 I/O I/O AB24 VDDP VDDP AD3 I/O I/O AB25 I/O I/O AD4 I/O I/O AB26 I/O I/O AD5 VDDP VDDP AB27 I/O I/O AD6 I/O I/O AB28 I/O I/O AD7 VDD VDD AB29 I/O I/O AD8 I/O I/O AB30 I/O I/O AD9 VDDP VDDP AC1 I/O I/O AD10 I/O I/O AC2 I/O I/O AD11 I/O I/O AC3 I/O I/O AD12 I/O I/O AC4 I/O I/O AD13 I/O I/O AC5 I/O I/O AD14 I/O I/O Pin Number Pin Number Advanced v0.6 105 Pr o A S I C P L U S F a m ily F la s h F P GA s 896 FB GA P i n ( Cont i nued) APA750 Function APA1000 Function APA750 Function APA1000 Function AD15 I/O I/O AE24 I/O I/O AD16 I/O I/O AE25 GND GND AD17 I/O I/O AE26 I/O I/O AD18 I/O I/O AE27 I/O I/O AD19 I/O I/O AE28 I/O I/O AD20 I/O I/O AE29 VDD VDD AD21 I/O I/O AE30 I/O I/O AD22 VDDP VDDP AF1 GND GND AD23 TCK TCK AF2 I/O I/O AD24 VDD VDD AF3 VDDP VDDP AD25 TRST TRST AF4 I/O I/O AD26 VDDP VDDP AF5 VDD VDD AD27 I/O I/O AF6 I/O I/O AD28 I/O I/O AF7 VDDP VDDP AD29 I/O I/O AF8 I/O I/O AD30 GND GND AF9 I/O I/O AE1 I/O I/O AF10 I/O I/O AE2 VDD VDD AF11 I/O I/O AE3 I/O I/O AF12 I/O I/O AE4 I/O I/O AF13 I/O I/O AE5 I/O I/O AF14 I/O I/O AE6 GND GND AF15 I/O I/O AE7 I/O I/O AF16 I/O I/O AE8 I/O I/O AF17 I/O I/O AE9 I/O I/O AF18 I/O I/O AE10 I/O I/O AF19 I/O I/O AE11 I/O I/O AF20 I/O I/O AE12 I/O I/O AF21 I/O I/O AE13 I/O I/O AF22 I/O I/O AE14 I/O I/O AF23 I/O I/O AE15 I/O I/O AF24 VDDP VDDP AE16 I/O I/O AF25 I/O I/O AE17 I/O I/O AF26 VDD VDD AE18 I/O I/O AF27 TDO TDO AE19 I/O I/O AF28 VDDP VDDP AE20 I/O I/O AF29 VPN VPN AE21 I/O I/O AF30 GND GND AE22 I/O I/O AG1 I/O I/O AE23 I/O I/O AG2 VDD VDD Pin Number 106 89 6 FB GA P in (Co nti nue d) Pin Number Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 896 FB GA Pi n ( Cont i nued) 896 FB GA Pi n ( Cont i nued) APA750 Function APA1000 Function APA750 Function APA1000 Function AG3 I/O I/O AH12 I/O I/O AG4 GND GND AH13 I/O I/O AG5 I/O I/O AH14 I/O I/O AG6 I/O I/O AH15 I/O I/O AG7 I/O I/O AH16 I/O I/O AG8 I/O I/O AH17 I/O I/O AG9 I/O I/O AH18 I/O I/O AG10 I/O I/O AH19 I/O I/O AG11 I/O I/O AH20 I/O I/O AG12 I/O I/O AH21 I/O I/O AG13 I/O I/O AH22 I/O I/O AG14 I/O I/O AH23 I/O I/O AG15 I/O I/O AH24 I/O I/O AG16 I/O I/O AH25 I/O I/O AG17 I/O I/O AH26 VDDP VDDP AG18 I/O I/O AH27 TDI TDI AG19 I/O I/O AH28 VDD VDD AG20 I/O I/O AH29 VPP VPP AG21 I/O I/O AH30 GND GND AG22 I/O I/O AJ1 GND GND AG23 I/O I/O AJ2 GND GND AG24 I/O I/O AJ3 I/O I/O AG25 I/O I/O AJ4 VDD VDD AG26 I/O I/O AJ5 I/O I/O AG27 GND GND AJ6 VDD VDD AG28 RCK RCK AJ7 I/O I/O AG29 VDD VDD AJ8 I/O I/O AG30 I/O I/O AJ9 I/O I/O AH1 GND GND AJ10 I/O I/O AH2 I/O I/O AJ11 I/O I/O AH3 VDD VDD AJ12 I/O I/O AH4 I/O I/O AJ13 I/O I/O AH5 VDDP VDDP AJ14 I/O I/O AH6 I/O I/O AJ15 I/O I/O AH7 I/O I/O AJ16 I/O I/O AH8 I/O I/O AJ17 I/O I/O AH9 I/O I/O AJ18 I/O I/O AH10 I/O I/O AJ19 I/O I/O AH11 I/O I/O AJ20 I/O I/O Pin Number Pin Number Advanced v0.6 107 Pr o A S I C P L U S F a m ily F la s h F P GA s 896 FB GA P i n ( Cont i nued) APA750 Function APA1000 Function AJ21 I/O I/O AJ22 I/O I/O AJ23 I/O I/O AJ24 I/O I/O AJ25 VDD VDD AJ26 I/O I/O AJ27 VDD VDD AJ28 TMS TMS AJ29 GND GND AJ30 GND GND AK2 GND GND AK3 GND GND AK4 I/O I/O AK5 GND GND AK6 I/O I/O AK7 GND GND AK8 I/O I/O AK9 I/O I/O AK10 I/O I/O AK11 I/O I/O AK12 I/O I/O AK13 I/O I/O AK14 I/O I/O AK15 I/O I/O AK16 I/O I/O AK17 I/O I/O AK18 I/O I/O AK19 I/O I/O AK20 I/O I/O AK21 I/O I/O AK22 I/O I/O AK23 I/O I/O AK24 GND GND AK25 I/O I/O AK26 GND GND AK27 I/O I/O AK28 GND GND AK29 GND GND Pin Number 108 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s Pa c ka ge P i n A s si g nm e n t s (Continued) 1152 -P in FB GA (Bot t om V ie w) A1 Ball Pad Corner 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP Advanced v0.6 109 Pr o A S I C P L U S F a m ily F la s h F P GA s 1 1 5 2 -P in F B G A 1 152- P in FBGA 11 52-P i n F BGA 1152 -P in FB GA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function A2 NC B14 VDDP C25 I/O E2 GND A3 GND B15 VDDP C26 GND E3 GND A4 GND B16 I/O C27 I/O E4 I/O A5 GND B17 GND C28 GND E5 VDD A6 I/O B18 GND C29 I/O E6 I/O A7 VDD B19 I/O C30 GND E7 VDDP A8 VDD B20 VDDP C31 GND E8 I/O A9 VDD B21 VDDP C32 NC E9 I/O A10 VDD B22 I/O C33 GND E10 I/O A11 I/O B23 GND C34 GND E11 I/O A12 GND B24 I/O D1 GND E12 I/O A13 I/O B25 NC D2 GND E13 I/O A14 VDDP B26 I/O D3 GND E14 I/O A15 VDDP B27 NC D4 GND E15 I/O A16 I/O B28 I/O D5 I/O E16 I/O A17 GND B29 NC D6 VDD E17 I/O A18 GND B30 GND D7 I/O E18 I/O A19 I/O B31 GND D8 VDD E19 I/O A20 VDDP B32 GND D9 I/O E20 I/O A21 VDDP B33 NC D10 I/O E21 I/O A22 I/O B34 NC D11 I/O E22 I/O A23 GND C1 GND D12 I/O E23 I/O A24 I/O C2 GND D13 I/O E24 I/O A25 VDD C3 NC D14 I/O E25 I/O A26 VDD C4 GND D15 I/O E26 I/O A27 VDD C5 GND D16 I/O E27 I/O A28 VDD C6 I/O D17 I/O E28 VDDP A29 I/O C7 GND D18 I/O E29 I/O A30 GND C8 I/O D19 I/O E30 VDD A31 GND C9 GND D20 I/O E31 I/O A32 GND C10 I/O D21 I/O E32 GND A33 NC C11 I/O D22 I/O E33 GND B1 NC C12 I/O D23 I/O E34 GND B2 NC C13 I/O D24 I/O F1 I/O B3 GND C14 I/O D25 I/O F2 NC B4 GND C15 I/O D26 I/O F3 I/O B5 GND C16 I/O D27 VDD F4 VDD B6 NC C17 I/O D28 I/O F5 I/O B7 I/O C18 I/O D29 VDD F6 GND B8 NC C19 I/O D30 I/O F7 I/O B9 I/O C20 I/O D31 GND F8 I/O B10 NC C21 I/O D32 GND F9 I/O B11 I/O C22 I/O D33 GND F10 I/O B12 GND C23 I/O D34 GND F11 I/O B13 I/O C24 I/O E1 GND F12 I/O 110 Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 1152 -P in FB GA 1152 -P in FB GA 1152 -P in FB GA 115 2-P in FB GA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function F13 I/O G24 I/O J1 VDD K12 I/O F14 I/O G25 I/O J2 I/O K13 I/O F15 I/O G26 VDDP J3 GND K14 I/O F16 I/O G27 I/O J4 I/O K15 I/O F17 I/O G28 VDD J5 I/O K16 I/O F18 I/O G29 I/O J6 I/O K17 I/O F19 I/O G30 VDDP J7 VDDP K18 I/O F20 I/O G31 I/O J8 I/O K19 I/O F21 I/O G32 GND J9 VDD K20 I/O F22 I/O G33 I/O J10 I/O K21 I/O F23 I/O G34 VDD J11 VDDP K22 I/O F24 I/O H1 VDD J12 I/O K23 I/O F25 I/O H2 NC J13 I/O K24 I/O F26 I/O H3 I/O J14 I/O K25 GND F27 I/O H4 VDD J15 I/O K26 I/O F28 I/O H5 I/O J16 I/O K27 I/O F29 GND H6 I/O J17 I/O K28 I/O F30 I/O H7 I/O J18 I/O K29 I/O F31 VDD H8 GND J19 I/O K30 I/O F32 I/O H9 I/O J20 I/O K31 I/O F33 NC H10 I/O J21 I/O K32 I/O F34 NC H11 I/O J22 I/O K33 NC G1 VDD H12 I/O J23 I/O K34 VDD G2 I/O H13 I/O J24 VDDP L1 I/O G3 GND H14 I/O J25 I/O L2 I/O G4 I/O H15 I/O J26 VDD L3 I/O G5 VDDP H16 I/O J27 I/O L4 I/O G6 I/O H17 I/O J28 VDDP L5 I/O G7 VDD H18 I/O J29 I/O L6 I/O G8 I/O H19 I/O J30 I/O L7 I/O G9 VDDP H20 I/O J31 I/O L8 I/O G10 I/O H21 I/O J32 GND L9 VDDP G11 I/O H22 I/O J33 I/O L10 I/O G12 I/O H23 I/O J34 VDD L11 VDD G13 I/O H24 I/O K1 VDD L12 I/O G14 I/O H25 I/O K2 NC L13 I/O G15 I/O H26 I/O K3 I/O L14 I/O G16 I/O H27 GND K4 I/O L15 I/O G17 I/O H28 I/O K5 I/O L16 I/O G18 I/O H29 I/O K6 I/O L17 I/O G19 I/O H30 I/O K7 I/O L18 I/O G20 I/O H31 VDD K8 I/O L19 I/O G21 I/O H32 I/O K9 I/O L20 I/O G22 I/O H33 NC K10 GND L21 I/O G23 I/O H34 VDD K11 I/O L22 I/O Advanced v0.6 111 Pr o A S I C P L U S F a m ily F la s h F P GA s 1152 -P in FB GA 1 152- P in FBGA 11 52-P i n F BGA 1152 -P in FB GA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function L23 I/O M34 GND P11 I/O R22 VDD L24 VDD N1 I/O P12 VDDP R23 VDDP L25 I/O N2 I/O P13 VDD R24 I/O L26 VDDP N3 I/O P14 GND R25 I/O L27 I/O N4 I/O P15 GND R26 I/O L28 I/O N5 I/O P16 GND R27 I/O L29 I/O N6 I/O P17 GND R28 I/O L30 I/O N7 I/O P18 GND R29 I/O L31 I/O N8 I/O P19 GND R30 I/O L32 I/O N9 I/O P20 GND R31 I/O L33 I/O N10 I/O P21 GND R32 I/O 112 L34 I/O N11 I/O P22 VDD R33 VDDP M1 GND N12 I/O P23 VDDP R34 VDDP M2 GND N13 VDD P24 I/O T1 I/O M3 I/O N14 VDD P25 I/O T2 I/O M4 I/O N15 VDD P26 I/O T3 I/O M5 I/O N16 VDD P27 I/O T4 I/O M6 I/O N17 VDD P28 I/O T5 I/O M7 I/O N18 VDD P29 I/O T6 I/O M8 I/O N19 VDD P30 I/O T7 I/O M9 I/O N20 VDD P31 I/O T8 I/O M10 I/O N21 VDD P32 I/O T9 I/O M11 I/O N22 VDD P33 VDDP T10 I/O M12 VDD N23 I/O P34 VDDP T11 I/O M13 I/O N24 I/O R1 VDDP T12 VDDP M14 VDDP N25 I/O R2 VDDP T13 VDD M15 VDDP N26 I/O R3 I/O T14 GND M16 VDDP N27 I/O R4 I/O T15 GND M17 VDDP N28 I/O R5 I/O T16 GND M18 VDDP N29 I/O R6 I/O T17 GND M19 VDDP N30 I/O R7 I/O T18 GND M20 VDDP N31 I/O R8 I/O T19 GND M21 VDDP N32 I/O R9 I/O T20 GND M22 I/O N33 I/O R10 I/O T21 GND M23 VDD N34 I/O R11 I/O T22 VDD M24 I/O P1 VDDP R12 VDDP T23 VDDP M25 I/O P2 VDDP R13 VDD T24 I/O M26 I/O P3 I/O R14 GND T25 I/O M27 I/O P4 I/O R15 GND T26 I/O M28 I/O P5 I/O R16 GND T27 I/O M29 I/O P6 I/O R17 GND T28 I/O M30 I/O P7 I/O R18 GND T29 I/O M31 I/O P8 I/O R19 GND T30 I/O M32 I/O P9 I/O R20 GND T31 I/O M33 GND P10 I/O R21 GND T32 I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 1152 -P in FB GA 1152 -P in FB GA 1152 -P in FB GA 115 2-P in FB GA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function T33 I/O V10 I/O W21 GND Y32 I/O T34 I/O V11 I/O W22 VDD Y33 VDDP U1 GND V12 VDDP W23 VDDP Y34 VDDP U2 GND V13 VDD W24 I/O AA1 VDDP U3 I/O V14 GND W25 I/O AA2 VDDP U4 I/O V15 GND W26 I/O AA3 I/O U5 AGND V16 GND W27 I/O AA4 I/O U6 NPECL V17 GND W28 I/O AA5 I/O U7 GL V18 GND W29 I/O AA6 I/O U8 I/O V19 GND W30 I/O AA7 I/O U9 I/O V20 GND W31 I/O AA8 I/O U10 I/O V21 GND W32 I/O AA9 I/O U11 I/O V22 VDD W33 I/O AA10 I/O U12 VDDP V23 VDDP W34 I/O AA11 I/O U13 VDD V24 I/O Y1 VDDP AA12 VDDP U14 GND V25 I/O Y2 VDDP AA13 VDD U15 GND V26 I/O Y3 I/O AA14 GND U16 GND V27 I/O Y4 I/O AA15 GND U17 GND V28 PPECL Y5 I/O AA16 GND U18 GND V29 GL Y6 I/O AA17 GND U19 GND V30 GL Y7 I/O AA18 GND U20 GND V31 AVDD Y8 I/O AA19 GND U21 GND V32 I/O Y9 I/O AA20 GND U22 VDD V33 GND Y10 I/O AA21 GND U23 VDDP V34 GND Y11 I/O AA22 VDD U24 I/O W1 I/O Y12 VDDP AA23 VDDP U25 I/O W2 I/O Y13 VDD AA24 I/O U26 I/O W3 I/O Y14 GND AA25 I/O U27 I/O W4 I/O Y15 GND AA26 I/O U28 I/O W5 I/O Y16 GND AA27 I/O U29 NPECL W6 I/O Y17 GND AA28 I/O U30 AGND W7 I/O Y18 GND AA29 I/O U31 I/O W8 I/O Y19 GND AA30 I/O U32 I/O W9 I/O Y20 GND AA31 I/O U33 GND W10 I/O Y21 GND AA32 I/O U34 GND W11 I/O Y22 VDD AA33 VDDP V1 GND W12 VDDP Y23 VDDP AA34 VDDP V2 GND W13 VDD Y24 I/O AB1 I/O V3 I/O W14 GND Y25 I/O AB2 I/O V4 AVDD W15 GND Y26 I/O AB3 I/O V5 GL W16 GND Y27 I/O AB4 I/O V6 PPECL W17 GND Y28 I/O AB5 I/O V7 I/O W18 GND Y29 I/O AB6 I/O V8 I/O W19 GND Y30 I/O AB7 I/O V9 I/O W20 GND Y31 I/O AB8 I/O Advanced v0.6 113 Pr o A S I C P L U S F a m ily F la s h F P GA s 1152 -P in FB GA 1 152- P in FBGA 11 52-P i n F BGA 1152 -P in FB GA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function AB9 I/O AC20 VDDP AD31 I/O AF8 I/O AB10 I/O AC21 VDDP AD32 I/O AF9 VDD AB11 I/O AC22 I/O AD33 I/O AF10 I/O AB12 I/O AC23 VDD AD34 I/O AF11 VDDP AB13 VDD AC24 I/O AE1 VDD AF12 I/O AB14 VDD AC25 I/O AE2 NC AF13 I/O AB15 VDD AC26 I/O AE3 I/O AF14 I/O AB16 VDD AC27 I/O AE4 I/O AF15 I/O AB17 VDD AC28 I/O AE5 I/O AF16 I/O AB18 VDD AC29 I/O AE6 I/O AF17 I/O AB19 VDD AC30 I/O AE7 I/O AF18 I/O AB20 VDD AC31 I/O AE8 I/O AF19 I/O AB21 VDD AC32 I/O AE9 I/O AF20 I/O AB22 VDD AC33 GND AE10 GND AF21 I/O AB23 I/O AC34 GND AE11 I/O AF22 I/O AB24 I/O AD1 I/O AE12 I/O AF23 I/O AB25 I/O AD2 I/O AE13 I/O AF24 VDDP AB26 I/O AD3 I/O AE14 I/O AF25 TCK AB27 I/O AD4 I/O AE15 I/O AF26 VDD AB28 I/O AD5 I/O AE16 I/O AF27 TRST AB29 I/O AD6 I/O AE17 I/O AF28 VDDP AB30 I/O AD7 I/O AE18 I/O AF29 I/O AB31 I/O AD8 I/O AE19 I/O AF30 I/O AB32 I/O AD9 VDDP AE20 I/O AF31 I/O AB33 I/O AD10 I/O AE21 I/O AF32 GND 114 AB34 I/O AD11 VDD AE22 I/O AF33 I/O AC1 GND AD12 I/O AE23 I/O AF34 VDD AC2 GND AD13 I/O AE24 I/O AG1 VDD AC3 I/O AD14 I/O AE25 GND AG2 NC AC4 I/O AD15 I/O AE26 I/O AG3 I/O AC5 I/O AD16 I/O AE27 I/O AG4 VDD AC6 I/O AD17 I/O AE28 I/O AG5 I/O AC7 I/O AD18 I/O AE29 I/O AG6 I/O AC8 I/O AD19 I/O AE30 I/O AG7 I/O AC9 I/O AD20 I/O AE31 I/O AG8 GND AC10 I/O AD21 I/O AE32 I/O AG9 I/O AC11 I/O AD22 I/O AE33 NC AG10 I/O AC12 VDD AD23 I/O AE34 VDD AG11 I/O AC13 I/O AD24 VDD AF1 VDD AG12 I/O AC14 VDDP AD25 I/O AF2 I/O AG13 I/O AC15 VDDP AD26 VDDP AF3 GND AG14 I/O AC16 VDDP AD27 I/O AF4 I/O AG15 I/O AC17 VDDP AD28 I/O AF5 I/O AG16 I/O AC18 VDDP AD29 I/O AF6 I/O AG17 I/O AC19 VDDP AD30 I/O AF7 VDDP AG18 I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s 1152 -P in FB GA 1152 -P in FB GA 1152 -P in FB GA 115 2-P in FB GA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function AG19 I/O AH30 VDDP AK7 VDDP AL18 I/O AG20 I/O AH31 VPN AK8 I/O AL19 I/O AG21 I/O AH32 GND AK9 I/O AL20 I/O AG22 I/O AH33 I/O AK10 I/O AL21 I/O AG23 I/O AH34 VDD AK11 I/O AL22 I/O AG24 I/O AJ1 I/O AK12 I/O AL23 I/O AG25 I/O AJ2 NC AK13 I/O AL24 I/O AG26 I/O AJ3 I/O AK14 I/O AL25 I/O AG27 GND AJ4 VDD AK15 I/O AL26 I/O AG28 I/O AJ5 I/O AK16 I/O AL27 VDD AG29 I/O AJ6 GND AK17 I/O AL28 I/O AG30 I/O AJ7 I/O AK18 I/O AL29 VDD AG31 VDD AJ8 I/O AK19 I/O AL30 TMS AG32 I/O AJ9 I/O AK20 I/O AL31 GND AG33 NC AJ10 I/O AK21 I/O AL32 GND AG34 VDD AJ11 I/O AK22 I/O AL33 GND AH1 VDD AJ12 I/O AK23 I/O AL34 GND AH2 I/O AJ13 I/O AK24 I/O AM1 GND AH3 GND AJ14 I/O AK25 I/O AM2 GND AH4 I/O AJ15 I/O AK26 I/O AM3 NC AH5 VDDP AJ16 I/O AK27 I/O AM4 GND AH6 I/O AJ17 I/O AK28 VDDP AM5 GND AH7 VDD AJ18 I/O AK29 TDI AM6 I/O AH8 I/O AJ19 I/O AK30 VDD AM7 GND AH9 VDDP AJ20 I/O AK31 VPP AM8 I/O AH10 I/O AJ21 I/O AK32 GND AM9 GND AH11 I/O AJ22 I/O AK33 GND AM10 I/O AH12 I/O AJ23 I/O AK34 GND AM11 I/O AH13 I/O AJ24 I/O AL1 GND AM12 I/O AH14 I/O AJ25 I/O AL2 GND AM13 I/O AH15 I/O AJ26 I/O AL3 GND AM14 I/O AH16 I/O AJ27 I/O AL4 GND AM15 I/O AH17 I/O AJ28 I/O AL5 I/O AM16 I/O AH18 I/O AJ29 GND AL6 VDD AM17 I/O AH19 I/O AJ30 RCK AL7 I/O AM18 I/O AH20 I/O AJ31 VDD AL8 VDD AM19 I/O AH21 I/O AJ32 I/O AL9 I/O AM20 I/O AH22 I/O AJ33 NC AL10 I/O AM21 I/O AH23 I/O AJ34 NC AL11 I/O AM22 I/O AH24 I/O AK1 GND AL12 I/O AM23 I/O AH25 I/O AK2 GND AL13 I/O AM24 I/O AH26 VDDP AK3 GND AL14 I/O AM25 I/O AH27 I/O AK4 I/O AL15 I/O AM26 GND AH28 VDD AK5 VDD AL16 I/O AM27 I/O AH29 TDO AK6 I/O AL17 I/O AM28 GND Advanced v0.6 115 Pr o A S I C P L U S F a m ily F la s h F P GA s 1152 -P in FB GA 1 152- P in FBGA Pin Number APA1000 Function Pin Number APA1000 Function AM29 I/O AP7 VDD AM30 GND AP8 VDD AM31 GND AP9 VDD AM32 NC AP10 VDD AM33 GND AP11 I/O AM34 GND AP12 GND AN1 NC AP13 I/O AN2 NC AP14 VDDP AN3 GND AP15 VDDP AN4 GND AP16 I/O AN5 GND AP17 GND AN6 NC AP18 GND AN7 I/O AP19 I/O AN8 NC AP20 VDDP AN9 I/O AP21 VDDP AN10 NC AP22 I/O AN11 I/O AP23 GND AN12 GND AP24 I/O AN13 I/O AP25 VDD AN14 VDDP AP26 VDD AN15 VDDP AP27 VDD AN16 I/O AP28 VDD AN17 GND AP29 I/O AN18 GND AP30 GND AN19 I/O AP31 GND AN20 VDDP AP32 GND AN21 VDDP AP33 NC 116 AN22 I/O AN23 GND AN24 I/O AN25 NC AN26 I/O AN27 NC AN28 I/O AN29 NC AN30 GND AN31 GND AN32 GND AN33 NC AN34 NC AP2 NC AP3 GND AP4 GND AP5 GND AP6 I/O Advanced v0.6 Pr o A SI C P L U S F a m ily F la s h F P GA s Li s t o f C ha ng e s The following table lists critical changes that were made in the current version of the document. Previous version Advanced v0.5 Advanced v0.4 Changes in current version (Advanced v0.6) The description for the VPN pin has changed. Page page 54 The "Plastic Device Resources" table on page 4 has been updated. page 4 Figure 19 and Figure 20 on page 28 have been updated. page 28 The "Tristate Buffer Delays" table on page 30 has been updated. page 30 The "Output Buffer Delays" table on page 31 has been updated. page 31 The "Input Buffer Delays" table on page 32 has been updated. page 32 The "Global Input Buffer Delays" table on page 32 has been updated. page 32 The "456-Pin PBGA" table on page 63 has been updated. page 63 The "676-FBGA Pin" table on page 87 has been updated. page 87 The "ProASICPLUS Product Profile" section on page 1 has been changed. page 1 The "Plastic Device Resources" section on page 4 has been updated. page 4 The Supply Voltages table on page 10 has been updated. page 10 WDATA has ben changed to DI, and RDATA has been changed to DO to make them consistent with the signal names found in the Macro Library Guide. Advanced v0.3 Figure 13 on page 15 and Figure 14 on page 16 have been updated. page 15 and page 16 The "Design Environment" section on page 17 and Figure 18 on page 18 have been updated. page 17 and page 18 The table in the "Package Thermal Characteristics" section on page 19 has been updated. page 19 The "Calculating Power Dissipation" section on page 20 is new. page 20 The "Programming and Storage Temperature Limits" section on page 22 is new. page 22 The "Supply Voltages" section on page 22 has been updated. page 22 The "DC Electrical Specifications (VDDP = 2.5V +/-0.2V)" section on page 23 was updated. page 23 The "DC Electrical Specifications (VDDP = 3.3V +/-0.3V and VDD 2.5+/-0.2V)" section on page 24 was updated. page 24 The "AC Specifications (3.3V PCI Revision 2.2 Operation)" section on page 26 was updated. page 26 The "Clock Conditioning Circuit" section on page 27 was updated. page 27 Figure 19 on page 28 was updated. page 28 Figure 20 on page 28 is new. page 28 Tables 5, 6, and 7 from Advanced v0.3 were removed. The "Memory Block SRAM Interface Signals" section on page 35 was updated. page 35 The "Memory Block FIFO Interface Signals" section on page 46 was updated. page 46 All pinout tables have been updated, and several packages are new: 208-Pin PQFP - APA150, APA300, APA450, APA600 456-Pin PBGA - APA150, APA300, APA450, APA600 144-Pin FBGA - APA150, APA300, APA450 256-Pin FBGA - APA150, APA300, APA450, APA600 676-Pin FBGA - APA600 Advanced v0.1 Figure 15 on page 16 has been updated Advanced v0.6 page 16 117 Pr o A S I C P L U S F a m ily F la s h F P GA s D at a S he et Ca t e g o r i e s In order to provide the latest information to designers, some data sheets are published before data has been fully characterized. Product Briefs are modified versions of data sheets. Data sheets are marked as "Advanced," "Preliminary," and "Web-only." The definition of these categories are as follows: P rod uct B ri ef The product brief is a modified version of an Advanced data sheet containing general product information. This brief summarizes specific device and family information for non-release products. Adv anc ed The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. P rel im i nar y The data sheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unm ar ked (pr odu ct ion) The data sheet contains information that is considered to be final. W eb- only V er si ons Web-only versions have three numbers in the version number (example: v2.0.1). A web-only version means Actel is posting the data sheet so customers have the latest information, but we are not printing the version because some information is going to change shortly after posting. 118 Advanced v0.6 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. Maxfli Court, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Tel: +44 (0)1276 401450 Fax: +44 (0)1276 401490 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81 03-3445-7671 Fax: +81 03-3445-7668 5172161-5/4.02