CY7C4261V-15JI - Cypress Semiconductor Corp.

16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-06013 Rev. *B Revised August 2, 2005

Features

• 3.3V operation for low power consumption and easy

integration into low-voltage systems

• High-speed, low-power, first-in first-out (FIFO)

memories

• 16K × 9 (CY7C4261V)

• 32K × 9 (CY7C4271V)

• 64K × 9 (CY7C4281V)

• 128K × 9 (CY7C4291V)

• 0.35-micron CMOS for optimum speed/power

• High-speed 100-MHz operation (10-ns read/write cycle

times)

•Low power

—I

CC = 25 mA

—I

SB = 4 mA

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, and programmable Almost Empty and

Almost Full status flags

• Output Enable (OE) pin

• Independent read and write enable pins

• Supports free-running 50% duty cycle clock inputs

• Width- Expansion capability

• Pin-compatible 3.3V solutions for CY7C4261/71/81/91

• Pin-compatible density upgrade to CY7C42X1V family

• Pb-Free Packages Available

Functional Description

The CY7C4261/71/81/91V are high-speed, low-power FIFO

memories with clocked read and write interfaces. All are nine

bits wide. The CY7C4261/71/81/91V are pin-compatible to the

CY7C42x1V Synchronous FIFO family. Programmable

features include Almost Full/Almost Empty flags. These FIFOs

provide solutions for a wide variety of data buffering needs,

including high-speed data acquisition, multiprocessor inter-

faces, and communications buffering.

These FIFOs have 9-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a free-running clock (WCLK) and two

write-enable pins (WEN1, WEN2/LD).

When WEN1 is LOW and WEN2/LD is HIGH, data is written

into the FIFO on the rising edge of the WCLK signal. While

WEN1 and WEN2/LD are held active, data is continually

written into the FIFO on each WCLK cycle. The output port is

controlled in a similar manner by a free-running read clock

(RCLK) and two read enable pins (REN1, REN2). In addition,

the CY7C4261/71/81/91V has an output enable pin (OE). The

read (RCLK) and write (WCLK) clocks may be tied together for

single-clock operation or the two clocks may be run indepen-

dently for asynchronous read/write applications. Clock

frequencies up to 100 MHz are achievable. Depth expansion

is possible using one enable input for system control, while the

other enable is controlled by expansion logic to direct the flow

of data.

LogicBlock Diagram

THREE-STATE

OUTPUT REGISTER READ

CONTROL

FLAG

LOGIC

WRITE

CONTROL

WRITE

POINTER READ

POINTER

RESET

LOGIC

INPUT

FLAG

PROGRAM

D0–8

RCLK

Q0–8

WEN1

WCLK

Dual Port

WEN2/LD

REN1 REN2

PAE

PAF

RAM Array

16K/32K

x 9

64K/128K

PLCC

RCLK

VCC

GND

WCLK

WEN2/LD

PAF

PAE

REN1

REN2

4321 313032

14 15 16 17 18 19 20

WEN1

Top View

CY7C4261V

CY7C4271V

Pin Configuration

CY7C4281V

CY7C4291V

CY7C4281V/CY7C4291V CY7C4261V/CY7C4271V16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 2 of 16

Selection Guide

7C4261/71/81/91V-10 7C4261/71/81/91V-15 7C4261/71/81/91V-25 Unit

Maximum Frequency 100 66.7 40 MHz

Maximum Access Time 8 10 15 ns

Minimum Cycle Time 10 15 25 ns

Minimum Data or Enable Set-up 3.5 4 6 ns

Minimum Data or Enable Hold 0 0 1 ns

Maximum Flag Delay 8 10 15 ns

Active Power Supply

Current (ICC1)Commercial 25 25 25 mA

Industrial 30

CY7C4261V CY7C4271V CY7C4281V CY7C4291V

Density 16K x 9 32K x 9 64K x 9 128K x 9

Package 32-pin PLCC 32-pin PLCC 32-pin PLCC 32-pin PLCC

Pin Definitions

Signal Name Description I/O Description

D0−8Data Inputs I Data Inputs for 9-bit bus.

Q0−8Data Outputs O Data Outputs for 9-bit bus.

WEN1 Write Enable 1 I The only write enable when device is configured to have programmable flags.

Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF

is HIGH. If the FIFO is configured to have two write enables, data is written on a

LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.

WEN2/LD

Dual Mode Pin

Write Enable 2 I If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this

pin operates as a control to write or read the programmable flag offsets. WEN1 must be

LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into

the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags,

WEN2/LD is held LOW to write or read the programmable flag offsets.

Load

REN1, REN2 Read Enable

Inputs

IEnables the device for Read operation. Both REN1 and REN2 must be asserted to

allow a read operation.

WCLK Write Clock I The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is

HIGH and the FIFO is not Full. When LD is asserted, WCLK writes data into the

programmable flag-offset register.

RCLK Read Clock I The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and

the FIFO are not Empty. When WEN2/LD is LOW, RCLK reads data out of the program-

mable flag-offset register.

EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.

FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.

PAE Programmable

Almost Empty

OWhen PAE is LOW, the FIFO is almost empty based on the almost empty offset

value programmed into the FIFO. PAE is synchronized to RCLK.

PAF Programmable

Almost Full

OWhen PAF is LOW, the FIFO is almost full based on the almost full offset value

programmed into the FIFO. PAF is synchronized to WCLK.

RS Reset I Resets device to empty condition. A reset is required before an initial read or write

operation after power-up.

OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are

connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 3 of 16

Functional Description (continued)

The CY7C4261/71/81/91V provides four status pins: Empty,

Full, Programmable Almost Empty, and Programmable

Almost Full. The Almost Empty/Almost Full flags are program-

mable to single word granularity. The programmable flags

default to Empty + 7 and Full – 7.

The flags are synchronous, i.e., they change state relative to

either the read clock (RCLK) or the write clock (WCLK). When

entering or exiting the Empty and Almost Empty states, the

flags are updated exclusively by the RCLK. The flags denoting

Almost Full, and Full states are updated exclusively by WCLK.

The synchronous flag architecture guarantees that the flags

maintain their status for at least one cycle

All configurations are fabricated using an advanced 0.35µ

CMOS technology. Input ESD protection is greater than

2001V, and latch-up is prevented by the use of guard rings.

Architecture

The CY7C4261/71/81/91V consists of an array of 16K, 32K,

64K, or 128K words of nine bits each (implemented by a

dual-port array of SRAM cells), a read pointer, a write pointer,

control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2,

RS), and flags (EF, PAE, PAF, FF).

Resetting the FIFO

Upon power-up, the FIFO must be reset with a Reset (RS)

cycle. This causes the FIFO to enter the Empty condition

signified by EF being LOW. All data outputs (Q0–8) go LOW

tRSF after the rising edge of RS. In order for the FIFO to reset

to its default state, the user must not read or write while RS is

LOW. All flags are guaranteed to be valid tRSF after RS is taken

LOW.

FIFO Operation

When the WEN1 signal is active LOW, WEN2 is active HIGH,

and FF is active HIGH, data present on the D0–8 pins is written

into the FIFO on each rising edge of the WCLK signal.

Similarly, when the REN1 and REN2 signals are active LOW

and EF is active HIGH, data in the FIFO memory will be

presented on the Q0-8 outputs. New data will be presented on

each rising edge of RCLK while REN1 and REN2 are active.

REN1 and REN2 must set up tENS before RCLK for it to be a

valid read function. WEN1 and WEN2 must occur tENS before

WCLK for it to be a valid write function.

An output enable (OE) pin is provided to three-state the Q0–8

outputs when OE is asserted. When OE is enabled (LOW),

data in the output register will be available to the Q0-8 outputs

after tOE. If devices are cascaded, the OE function will only

output data on the FIFO that is read enabled.

The FIFO contains overflow circuitry to disallow additional

writes when the FIFO is full, and underflow circuitry to disallow

additional reads when the FIFO is empty. An empty FIFO

maintains the data of the last valid read on its Q0-8 outputs

even after additional reads occur.

Write Enable 1 (WEN1). If the FIFO is configured for program-

mable flags, Write Enable 1 (WEN1) is the only write enable

control pin. In this configuration, when Write Enable 1 (WEN1)

is LOW, data can be loaded into the input register and RAM

array on the LOW-to-HIGH transition of every write clock

(WCLK). Data is stored is the RAM array sequentially and

independently of any on-going read operation.

Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.

The FIFO is configured at Reset to have programmable flags

or to have two write enables, which allows for depth

expansion. If Write Enable 2/Load (WEN2/LD) is set active

HIGH at Reset (RS = LOW), this pin operates as a second

write enable pin.

If the FIFO is configured to have two write enables, when Write

Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD)

is HIGH, data can be loaded into the input register and RAM

array on the LOW-to-HIGH transition of every write clock

(WCLK). Data is stored in the RAM array sequentially and

independently of any on-going read operation.

Programming

When WEN2/LD is held LOW during Reset, this pin is the load

(LD) enable for flag offset programming. In this configuration,

WEN2/LD can be used to access the four 9-bit offset registers

contained in the CY7C4261/71/81/91V for writing or reading

data to these registers.

When the device is configured for programmable flags and

both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH

transition of WCLK writes data from the data inputs to the

empty offset least significant bit (LSB) register. The second,

third, and fourth LOW-to-HIGH transitions of WCLK store data

in the empty offset most significant bit (MSB) register, full

offset LSB register, and full offset MSB register, respectively,

when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH

transition of WCLK while WEN2/LD and WEN1 are LOW

writes data to the empty LSB register again. Figure 1 shows

the registers sizes and default values for the various device

types.

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 4 of 16

It is not necessary to write to all the offset registers at one time.

A subset of the offset registers can be written; then by bringing

the WEN2/LD input HIGH, the FIFO is returned to normal read

and write operation. The next time WEN2/LD is brought LOW,

a write operation stores data in the next offset register in

sequence.

The contents of the offset registers can be read to the data

outputs when WEN2/LD is LOW and both REN1 and REN2

are LOW. LOW-to-HIGH transitions of RCLK read register

contents to the data outputs. Writes and reads should not be

performed simultaneously on the offset registers.

Programmable Flag (PAE, PAF) Operation

Whether the flag offset registers are programmed as

described in Table 1 or the default values are used, the

programmable almost-empty flag (PAE) and programmable

almost-full flag (PAF) states are determined by their corre-

sponding offset registers and the difference between the read

and write pointers.

The number formed by the empty offset least significant bit

referred to as n and determines the operation of PAE. PAF is

synchronized to the LOW-to-HIGH transition of RCLK by one

flip-flop and is LOW when the FIFO contains n or fewer unread

words. PAE is set HIGH by the LOW-to-HIGH transition of

RCLK when the FIFO contains (n+1) or greater unread words.

The number formed by the full offset least significant bit

as m and determines the operation of PAF. PAE is synchronized

to the LOW-to-HIGH transition of WCLK by one flip-flop and is

set LOW when the number of unread words in the FIFO is

greater than or equal to CY7C4261V (16k – m), CY7C4271V

(32k – m), CY7C4281V (64k – m) and CY7C4291V

(128k – m). PAF is set HIGH by the LOW-to-HIGH transition

of WCLK when the number of available memory locations is

greater than m.

Note:

1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.

Figure 1. Offset Register Location and Default Values

64k x 9

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

(MSB)

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

(MSB)

128k x 9

(MSB)

Default Value = 000h

16k x 9

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

(MSB)

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

(MSB)

32k x 9

(MSB)

Default Value = 000h

8586

Table 1. Writing the Offset Registers[1]

LD WEN WCLK Selection

0 1 No Operation

1 0 Write Into FIFO

1 1 No Operation

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 5 of 16

Width-Expansion Configuration

Word width may be increased simply by connecting the corre-

sponding input controls signals of multiple devices. A

composite flag should be created for each of the end-point

status flags (EF and FF). The partial status flags (PAE and

PAF) can be detected from any one device. Figure 2 demon-

strates a 18-bit word width by using two CY7C42x1Vs. Any

word width can be attained by adding additional CY7C42x1Vs.

When the CY7C42x1V is in a Width-Expansion Configuration,

the Read Enable (REN2) control input can be grounded (see

Figure 2). In this configuration, the Write Enable 2/Load

(WEN2/LD) pin is set to LOW at Reset so that the pin operates

as a control to load and read the programmable flag offsets.

Flag Operation

The CY7C4261/71/81/91V devices provide five flag pins to

indicate the condition of the FIFO contents. Empty, Full, PAE,

and PAF are synchronous.

Full Flag

The Full Flag (FF) will go LOW when the device is full. Write

operations are inhibited whenever FF is LOW regardless of the

state of WEN1 and WEN2/LD. FF is synchronized to WCLK,

i.e., it is exclusively updated by each rising edge of WCLK.

Empty Flag

The Empty Flag (EF) will go LOW when the device is empty.

Read operations are inhibited whenever EF is LOW,

regardless of the state of REN1 and REN2. EF is synchronized

to RCLK, i.e., it is exclusively updated by each rising edge of

RCLK.

Notes:

2. n = Empty Offset (n = 7 default value).

3. m = Full Offset (m = 7 default value).

Table 2. Status Flags

Number of Words in FIFO

FF PAF PAE EFCY7C4261V CY7C4271V CY7C4281V CY7C4291V

00 0 0 HHLL

1 to n[2] 1 to n[2] 1 to n[2] 1 to n[2] HH LH

(n + 1) to (1638 − (m + 1)) (n + 1) to (32768 − (m + 1)) (n + 1) to (65536 − (m + 1)) (n + 1) to (131072 −

(m + 1))

HH HH

(16384 − m)[3] to 16383 (32768 − m)[3] to 32767 (65536 − m)[3] to 65535 (131072 − m)[3] to 131071 H L H H

16384 32768 65536 131072 L L H H

Figure 2. Block Diagram of 16k/32k/64k/128k x 9 Low-Voltage Deep Sync FIFO Memory

Used in a Width-Expansion Configuration

FF EF EF

WRITECLOCK (WCLK)

WRITE ENABLE 1(WEN1)

WRITE ENABLE 2/LOAD

(WEN2/LD)

PROGRAMMABLE(PAF)

FULL FLAG (FF)# 1

CY7C4261V

918

DATAIN (D)

RESET(RS)

READ CLOCK (RCLK)

READ ENABLE 1 (REN1)

OUTPUT ENABLE (OE)

PROGRAMMABLE(PAE)

EMPTY FLAG (EF)#1

DATA OUT (Q)

918

Read Enable 2 (REN2)

EMPTY FLAG (EF)#2

FULL FLAG (FF)# 2

Read Enable 2 (REN2)

CY7C4271V

CY7C4281V

CY7C4291V

CY7C4261V

CY7C4271V

CY7C4281V

CY7C4291V

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 6 of 16

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ...................................–65°C to +150°C

Ambient Temperature with

Power Applied...............................................–55°C to +125°C

Supply Voltage to Ground Potential ............... –0.5V to +3.6V

DC Voltage Applied to Outputs

in High-Z State .......................................–0.5V to VCC + 0.5V

DC Input Voltage ................................... –0.5V to VCC + 0.5V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.....................................................> 200 mA

Operating Range

Range Ambient Temperature VCC[4]

Commercial 0°C to +70°C 3.3V ±300 mV

Industrial −40°C to +85°C 3.3V ±300 mV

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

7C4261/71/81/91V-

UnitMin. Max. Min. Max. Min. Max.

VOH Output HIGH

Voltage

VCC = Min., IOH = −1.0 mA

VCC = 3.0V, IOH = −2.0 mA

2.4 2.4 2.4 V

VOL Output LOW

Voltage

VCC = Min., IOL = 4.0 mA

VCC = 3.0V, IOL = 8.0 mA

.04 0.4 0.4 V

VIH Input HIGH

Voltage 2.0 VCC 2.0 VCC 2.0 VCC V

VIL Input LOW

Voltage

−0.5 0.8 −0.5 0.8 −0.5 0.8 V

IIX Input Leakage

Current

VCC = Max. −10 +10 −10 +10 −10 +10 µA

IOZL

IOZH

Output OFF,

High Z Current OE > VIH,

VSS < VO< VCC

−10 +10 −10 +10 −10 +10 µA

ICC1[5] Active Power

Supply Current

Com’l 25 25 25 mA

Ind 30 mA

ISB[6] Average

Standby Current

Com’l 4 4 4 mA

Ind 4 mA

Capacitance[7]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 3.3V

5pF

COUT Output Capacitance 7 pF

AC Test Loads and Waveforms (-15 and -25)[8, 9]

Notes:

4. VCC Range for commercial -10 ns is 3.3V ±150mV.

5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency of 20 MHz, while data inputs

switch at 10 MHz. Outputs are unloaded.)

6. All inputs = VCC − 0.2V, except WCLK and RCLK (which are at frequency = 0 MHz). All outputs are unloaded.

7. Tested initially and after any design or process changes that may affect these parameters.

8. CL = 30 pF for all AC parameters except for tOHZ.

9. CL = 5 pF for tOHZ.

INCLUDING

3.0V

3.3V

OUTPUT

R1 = 330Ω

R2=510Ω

JIG AND

SCOPE

GND

90%

10%

90%

10%

≤3ns ≤3ns

OUTPUT 2.0V

Equivalent to: THÉ VENIN EQUIVALENT

200 Ω

All Input Pulses

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 7 of 16

AC Test Loads and Waveforms (continued) (-10)

3.0V

GND

90%

10%

90%

10%

≤3ns ≤3ns

All Input Pulses

I/O

50Ω

VCC/2

Z0 = 50Ω

Switching Characteristics Over the Operating Range

Parameter Description

7C4261/71/81/91V-

UnitMin. Max. Min. Max. Min. Max.

tSClock Cycle Frequency 100 66.7 40 MHz

tAData Access Time 2 8 2 10 2 15 ns

tCLK Clock Cycle Time 10 15 25 ns

tCLKH Clock HIGH Time 4.5 6 10 ns

tCLKL Clock LOW Time 4.5 6 10 ns

tDS Data Set-up Time 3.5 4 6 ns

tDH Data Hold Time 0 0 1 ns

tENS Enable Set-up Time 3.5 4 6 ns

tENH Enable Hold Time 0 0 1 ns

tRS Reset Pulse Width[10] 10 15 25 ns

tRSS Reset Set-up Time 8 10 15 ns

tRSR Reset Recovery Time 8 10 15 ns

tRSF Reset to Flag and Output Time 10 15 25 ns

tOLZ Output Enable to Output in Low Z[11] 000ns

tOE Output Enable to Output Valid 3 7 3 10 3 12 ns

tOHZ Output Enable to Output in High Z[11] 3738312ns

tWFF Write Clock to Full Flag 8 10 15 ns

tREF Read Clock to Empty Flag 8 10 15 ns

tPAF Clock to Programmable Almost-Full Flag 8 10 15 ns

tPAE Clock to Programmable Almost-Full Flag 8 10 15 ns

tSKEW1 Skew Time between Read Clock and Write

Clock for Empty Flag and Full Flag

5 6 10 ns

tSKEW2 Skew Time between Read Clock and Write

Clock for Almost-Empty Flag and

Almost-Full Flag

10 15 18 ns

Notes:

10. Pulse widths less than minimum values are not allowed.

11. Values guaranteed by design, not currently tested.

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 8 of 16

Switching Waveforms

Write Cycle Timing

Read Cycle Timing

Notes:

12. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time

between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.

13. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time

between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.

tCLKH tCLKL

NO OPERATION

tDS

tSKEW1

tENS

WEN1

tCLK

tDH

tWFF tWFF

tENH

WCLK

D0–D17

REN1, REN2

RCLK

NO OPERATION

WEN2

(if applicable)

[12]

REN1, REN2

tCLKH tCLKL

NO OPERATION

tSKEW1

WEN1

tCKL

tOHZ

tREF tREF

RCLK

Q0–Q17

WCLK

tOE

tENS

tOLZ

tENH

VALID DATA

WEN2

[13]

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 9 of 16

Reset Timing[14]

Notes:

14. The clocks (RCLK, WCLK) can be free-running during reset.

15. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.

16. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable

for the programmable flag offset registers.

Switching Waveforms (continued)

tRS

tRSR

Q0−Q8

tRSF

tRSF OE = 1

OE=0

REN1,

REN2

EF,PAE

FF,PAF

tRSS

tRSR

tRSS

tRSR

tRSS

EN2/LD

WEN1

[16]

[15]

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 10 of 16

First Data Word Latency after Reset with Read and Write

Notes:

17. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK

+ tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).

18. The first word is available the cycle after EF goes HIGH, always.

Switching Waveforms (continued)

(FIRST VALID WRITE)

tSKEW1

WEN1

WCLK

Q0–Q8

REN1,

REN2

tOE

tENS

tOLZ

tDS

RCLK

tREF

tFRL

D1D2D3D4

D0D1

D0–D8

WEN2

(if applicable)

[17]

[18]

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 11 of 16

Empty Flag Timing

Switching Waveforms (continued)

DATA WRITE 2

DATA WRITE 1

tENS

tSKEW1

DATA IN OUTPUT REGISTER

WEN1

WCLK

Q0–Q8

REN1,

REN2

tDS

tENH

RCLK

tREF

tFRL

D0–D8

DATA READ

tSKEW1

tFRL

tREF

tDS

tENS

tENH

tENS

WEN2

(if applicable)

tENH tENS tENH

tREF

LOW

[17] [17]

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 12 of 16

Full Flag Timing

Programmable Almost Empty Flag Timing

Notes:

19. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of

WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.

20. PAE offset = n.

21. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.

Switching Waveforms (continued)

Q0–Q8

REN1,

REN2

WEN1

WEN2

(if applicable)

D0–D8

NEXT DATA READ

DATA WRITE

NO WRITE

DATA IN OUTPUT REGISTER

WCLK

RCLK

DATA READ

tSKEW1 tDS

tENS

tENH

tWFF

tSKEW1

tENS

tENH

tWFF

DATA WRITE

NO WRITE

tWFF

LOW

[12] [12]

tENH

WCLK

PAE

RCLK

tCLKH

tENS

tCLKL

tENS

tPAE

N + 1 WORDS

IN FIFO

tENH

tENS

tENH

tENS

tPAE

REN1,

REN2

WEN1

WEN2

(if applicable)

tSKEW2

Note

[19]

Note21

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 13 of 16

Programmable Almost Full Flag Timing

Write Programmable Registers

Notes:

22. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.

23. PAF offset = m.

24. 16K − m words for CY7C4261V, 32K – m words for CY7C4271V, 64K − m words for CY7C4281V, and 128K − m words for CY4291V.

25. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge

of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.

Switching Waveforms (continued)

Note

tENH

WCLK

PAF

RCLK

tCLKH

tENS

(FULL −M) WORDS

IN FIFO

tCLKL

tENS

FULL −(M+1)WORDS

IN FIFO

tENH

tENS

tENH

tENS

tPAF

REN1,

REN2

WEN1

WEN2

(if applicable)

tSKEW2 tPAF

[24]

[25]

tENH

WEN2/LD

WCLK

tCLKH

tENS

tCLKL

PAE OFFSET

LSB

D0–D8

WEN1

tENS

PAF OFFSET

MSB

tCLK

tDS tDH

PAE OFFSET

MSB

PAF OFFSET

LSB

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 14 of 16

Read Programmable Registers

Ordering Information

16Kx9 Low-voltage Deep Sync FIFO

Speed (ns) Ordering Code Package Name Package Type Operating Range

10 CY7C4261V-10JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4261V-10JXC J65 32-Lead Pb-Free Plastic Leaded Chip Carrier Commercial

15 CY7C4261V-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4261V-15JXC J65 32-Lead Pb-Free Plastic Leaded Chip Carrier Commercial

CY7C4261V-15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

25 CY7C4261V-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

32Kx9 Low-voltage Deep Sync FIFO

Speed (ns) Ordering Code Package Name Package Type Operating Range

10 CY7C4271V-10JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4271V-10JXC J65 32-Lead Pb-Free Plastic Leaded Chip Carrier Commercial

15 CY7C4271V-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4271V-15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

25 CY7C4271V-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

64kx9 Low-voltage Deep Sync FIFO

Speed (ns) Ordering Code Package Name Package Type Operating Range

10 CY7C4281V-10JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4281V-10JXC J65 32-Lead Pb-Free Plastic Leaded Chip Carrier Commercial

15 CY7C4281V-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4281V-15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

25 CY7C4281V-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

128kx9 Low-voltage Deep Sync FIFO

Speed (ns) Ordering Code Package Name Package Type Operating Range

10 CY7C4291V-10JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4291V-10JXC J65 32-Lead Pb-Free Plastic Leaded Chip Carrier Commercial

15 CY7C4291V-15JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

CY7C4291V-15JXC J65 32-Lead Pb-Free Plastic Leaded Chip Carrier Commercial

CY7C4291V-15JI J65 32-Lead Plastic Leaded Chip Carrier Industrial

25 CY7C4291V-25JC J65 32-Lead Plastic Leaded Chip Carrier Commercial

Switching Waveforms (continued)

PAF OFFSET

MSB

PAF OFFSET

LSB

tENH

WEN2/LD

RCLK

tCLKH

tENS

tCLKL

PAE OFFSET LSB

Q0–Q15

REN1,

REN2

tENS

PAE OFFSET MSB

tCLK

UNKNOWN

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 15 of 16

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Deep Sync is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the

trademarks of their respective holders.

Package Diagram

51-85002-*B

32-Lead Pb-Free Plastic Leaded Chip Carrier J65

32-Lead Plastic Leaded Chip Carrier J65

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

Document #: 38-06013 Rev. *B Page 16 of 16

Document History Page

Document Title: CY7C4261V/CY7C4271V/CY7C4281V/CY7C4291V 16K/32K/64K/128K/X9 Low-Voltage Deep Sync FIFO

Document Number: 38-06013

REV. ECN NO. Issue Date

Orig. of

Change Description of Change

** 106474 09/15/01 SZV Changed Spec number from 38-00656 to 38-06013

*A 127858 09/04/03 FSG Changed: tSKEW2 to tSKEW1 in Switching Waveforms “Empty Flag Timing” diagram

Fixed flag timing diagram in Switching Waveforms section

*B 386127 See ECN ESH Added Pb-Free logo to top of front page

Added CY7C4291V-15JXC, CY7C91V-10JXC, CY7C4281V-10JXC,

CY7C4271V-10JXC, CY7C4261V-10JXC, CY7C4261V-15JXC to ordering infor-

mation.