PC755BMGSU366LE - E2V Technologies (UK), Ltd.

Features

• 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz (PC755)

• 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745)

• 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

• Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

• PD Typical 6.4W at 400 MHz, Full Operating Conditions

• Nap, Doze and Sleep Modes for Power Savings

• Superscalar (3 Instructions per Clock Cycle) Two Instruction + Branch

• 4 Beta Byte Virtual Memory, 4-GByte of Physical Memory

• 64-bit Data and 32-bit Address Bus Interface

• 32-KB Instruction and Data Cache

• Six Independent Execution Units

• Write-back and Write-through Operations

• fINT max = 400 MHz (TBC)

• fBUS max = 100 MHz

• Voltage I/O 2.5V/3.3V; Voltage Int 2.0V

Description

The PC755 and PC745 PowerPC® microprocessors are high-performance, low-

power, 32-bit implementations of the PowerPC Reduced Instruction Set Computer

(RISC) architecture, especially enhanced for embedded applications.

The PC755 and PC745 microprocessors differ only in that the PC755 features an

enhanced, dedicated L2 cache interface with on-chip L2 tags. The PC755 is a drop-in

replacement for the award winning PowerPC 750 microprocessor and is footprint and

user software code compatible with the MPC7400 microprocessor with AltiVec™ tech-

nology. The PC745 is a drop-in replacement for the PowerPC 740 microprocessor and

is also footprint and user software code compatible with the PowerPC 603e micropro-

cessor. PC755/745 microprocessors provide on-chip debug support and are fully

JTAG-compliant.

The PC745 microprocessor is pin compatible with the TSPC603e family.

GS suffix

CI-CGA360

Ceramic Ball Grid Array with

Solder Column Interposer (SCI)

ZF suffix

PBGA255

Flip-Chip Plastic Ball Grid Array

ZF suffix

PBGA360

Flip-Chip Plastic Ball Grid Array

GH suffix

HITCE 255

Ceramic Ball Grid Array

GH suffix

HITCE 360

Ceramic Ball Grid Array

G suffix

CBGA360

Ceramic Ball Grid Array

PowerPC®

755/745

32-bit RISC

Microprocessor

PC755/745

2138F–HIREL–06/05

PC755/745

Screening

This product is manufactured in full compliance with:

•HiTCE CBGA according to Atmel standards

•CBGA + CI-CGA + FC-PBGA up screenings based upon Atmel standards

•Full military temperature ranges (Tj = -55°C, +125°C)

•Industrial temperature ranges (Tj = -40°C, +110°C)

1. General Description

1.1 Simplified Block Diagram

The PC755 is targeted for low power systems and supports power management features such

as doze, nap, sleep, and dynamic power management. The PC755 consists of a processor core

and an internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus.

Figure 1-1. PC755 Block Diagram

Additional Features

* Time Base Counter/Decrementer

* Clock Multiplier

* JTAG/COP Interface

* Thermal/Power Management

* Performance Monitor

Fetcher Branch Processing

BTIC

64-Entry

+ x : FPSCR

CR FPSCR

L2CR

CTR

BHT

Data MMU

Instruction MMU

Not in the PC745

EAPA

+ x :

Instruction Unit

Unit

Instruction Queue

(6-Word)

2 Instructions

Reservation Station Reservation Station Reservation Station

Integer Unit 1 System Register

Unit

Dispatch Unit 64-Bit

(2 Instructions)

SRs

ITLB

(Shadow) IBAT

Array 32-Kbyte

I Cache

Tags

128-Bit

(4 Instructions)

Reservation Station

32-Bit

Floating-Point

Unit

Rename Buffers

(6)

FPR File

32-Bit 64-Bit 64-Bit

Reservation Station

(2-Entry)

Load/Store Unit

(EA Calculation)

Store Queue

GPR File

Rename Buffers

(6)

32-Bit

SRs

(Original)

DTLB

DBAT

Array

64-Bit

Completion Unit

Reorder Buffer

(6-Entry)

Tags 32-Kbyte

D Cache

60x Bus Interface Unit

Instruction Fetch Queue

L1 Castout Queue

Data Load Queue L2 Controller

L2 Tags

L2 Bus Interface

Unit

L2 Castout Queue

32-Bit Address Bus

32-/64-Bit Data Bus

17-Bit L2 Address Bus

64-Bit L2 Data Bus

Integer Unit 2

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PC755/745

1.2 General Parameters

The following list provides a summary of the general parameters of the PC755:

1.3 Features

This section summarizes features of the PC755’s implementation of the PowerPC architecture.

Major features of the PC755 are as follows:

• Branch Processing Unit

– Four instructions fetched per clock

– One branch processed per cycle (plus resolving 2 speculations)

– Up to 1 speculative stream in execution, 1 additional speculative stream in fetch

– 512-entry Branch History Table (BHT) for dynamic prediction

– 64-entry, 4-way set associative Branch Target Instruction Cache (BTIC) for

eliminating branch delay slots

• Dispatch Unit

– Full hardware detection of dependencies (resolved in the execution units)

– Dispatch two instructions to six independent units (system, branch, load/store, fixed-

point unit 1, fixed-point unit 2, floating-point)

– Serialization control (predispatch, postdispatch, execution serialization)

• Decode

– Register file access

– Forwarding control

– Partial instruction decode

• Completion

– 6 entry completion buffer

– Instruction tracking and peak completion of two instructions per cycle

– Completion of instructions in program order while supporting out-of-order instruction

execution, completion serialization and all instruction flow changes

Technology 0.22 µm CMOS, five-layer metal, 1 layer poly

Die size 6.61 mm x 7.73 mm (51 mm2)

Transistor count 6.75 million

Logic design Fully-static Packages

PC745 Surface mount 255 Plastic Ball Grid Array (PBGA)

Surface mount 255 Ceramic Ball Grid Array (Hi-TCE)

PC755 Surface mount 360 Plastic Ball Grid Array (PBGA)

Surface mount 360 Ceramic Ball Grid Array (CI-CGA, CBGA, HiTCE)

Core power supply 2V ± 100 mV DC (nominal; some parts support core voltages down to 1.8V;

see ”Recommended Operating Conditions(1)” on page 16

I/O power supply 2.5V ± 100 mV DC or 3.3V ± 165 mV DC (input thresholds are configuration

pin selectable)

2138F–HIREL–06/05

PC755/745

• Fixed Point Units (FXUs) that share 32 GPRs for Integer Operands

– Fixed Point Unit 1 (FXU1)-multiply, divide, shift, rotate, arithmetic, logical

– Fixed Point Unit 2 (FXU2)-shift, rotate, arithmetic, logical

– Single-cycle arithmetic, shifts, rotates, logical

– Multiply and divide support (multi-cycle)

– Early out multiply

• Floating-point Unit and a 32-entry FPR File

– Support for IEEE-754 standard single and double precision floating point arithmetic

– Hardware support for divide

– Hardware support for denormalized numbers

– Single-entry reservation station

– Supports non-IEEE mode for time-critical operations

• System Unit

– Executes CR logical instructions and miscellaneous system instructions

– Special register transfer instructions

• Load/Store Unit

– One cycle load or store cache access (byte, half-word, word, double-word)

– Effective address generation

– Hits under misses (one outstanding miss)

– Single-cycle unaligned access within double word boundary

– Alignment, zero padding, sign extend for integer register file

– Floating point internal format conversion (alignment, normalization)

– Sequencing for load/store multiples and string operations

– Store gathering

– Cache and TLB instructions

– Big and Little-endian byte addressing supported

– Misaligned Little-endian supported

– Level 1 Cache structure

– 32K, 32 bytes line, 8-way set associative instruction cache (iL1)

– 32K, 32 bytes line, 8-way set associative data cache (dL1)

– Cache locking for both instruction and data caches, selectable by group of ways

– Single-cycle cache access

– Pseudo least-recently used (PLRU) replacement

– Copy-back or Write Through data cache (on a page per page basis)

– Supports all PowerPC memory coherency modes

– Non-Blocking instruction and data cache (one outstanding miss under hits)

– No snooping of instruction cache

• Level 2 (L2) Cache Interface (not implemented on PC745)

– Internal L2 cache controller and tags; external data SRAMs

– 256K, 512K, and 1-Mbyte 2-way set associative L2 cache support

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PC755/745

– Copyback or write-through data cache (on a page basis, or for all L2)

– Instruction-only mode and data-only mode.

– 64 bytes (256K/512K) or 128 bytes (1M) sectored line size

– Supports flow through (register-buffer) synchronous burst SRAMs, pipelined

(register-register) synchronous burst SRAMs (3-1-1-1 or strobeless 4-1-1-1) and

pipelined (register-register) late-write synchronous burst SRAMs

– L2 configurable to direct mapped SRAM interface or split cache/direct mapped or

private memory

– Core-to-L2 frequency divisors of 1, 1.5, 2, 2.5, and 3 supported

– 64-bit data bus

– Selectable interface voltages of 2.5V and 3.3V

– Parity checking on both L2 address and data

• Memory Management Unit

– 128 entry, 2-way set associative instruction TLB

– 128 entry, 2-way set associative data TLB

– Hardware reload for TLBs

– Hardware or optional software tablewalk support

– 8 instruction BATs and 8 data BATs

– 8 SPRGs, for assistance with software tablewalks

– Virtual memory support for up to 4 hexabytes (252) of virtual memory

– Real memory support for up to 4 gigabytes (232) of physical memory

• Bus Interface

– Compatible with 60X processor interface

– 32-bit address bus

– 64-bit data bus, 32-bit mode selectable

– Bus-to-core frequency multipliers of 2x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x,

7.5x, 8x, 10x supported

– Selectable interface voltages of 2.5V and 3.3V.

– Parity checking on both address and data busses

• Power Management

– Low-power design with thermal requirements very similar to PC740/750.

– Selectable interface voltage of 1.8V/2.0V can reduce power in output buffers

(compared to 3.3V)

– Three static power saving modes: doze, nap, and sleep

– Dynamic power management

• Testability

– LSSD scan design

– IEEE 1149.1 JTAG interface

• Integrated Thermal Management Assist Unit

– One-ship thermal sensor and control logic

– Thermal Management Interrupt for software regulation of junction temperature

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PC755/745

2. Pin Assignments

Figure 2-1 (in part A) shows the pinout of the PC745, 255PBGA and HiTCE CBGA packages as

viewed from the top surface. Part B shows the side profile of the PBGA package to indicate the

direction of the top surface view.

Figure 2-1. Pinout of the PC745, 255 PBGA and HiTCE CBGA Packages as Viewed from the Top

Surface

Figure 2-2 (in part A) shows the pinout of the PC755, 360 PBGA packages as viewed from the

top surface. Part B shows the side profile of the PBGA package to indicate the direction of the

top surface view.

1234 5678 91011121314151

Not to Scale

View

Die

Substrate Assembly

Encapsulant

Part B

Part A

2138F–HIREL–06/05

PC755/745

Figure 2-2. Pinout of the PC755, 360 PBGA, CBGA, HiTCE CBGA and CI-CGA Packages as

Viewed from the Top Surface

1234 5678 91011121314151

Not to Scale

17 18 19

View

Die

Substrate Assembly

Encapsulant

Part B

Part A

2138F–HIREL–06/05

PC755/745

2.1 Pinout Listings

Table 2-1 provides the pinout listing for the PC745, 255 PBGA package.

Table 2-1. Pinout Listing for the PC745, 255 PBGA and HiTCE CBGA Packages

Signal Name Pin Number Active I/O

I/F Voltages Supported(1)

1.8V/2.0V 3.3V

A[0-31]

C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15,

H1, E16, H2, F13, J1, F14, J2, F15, H3, F16, F4, G13, K1,

G15, K2, H16, M1, J15, P1

High I/O – –

AACK L2 Low Input – –

ABB K4 Low I/O – –

AP[0-3] C1, B4, B3, B2 High I/O – –

ARTRY J4 Low I/O – –

AVDD A10 – – 2V 2V

BG L1 Low Input – –

BR B6 Low Output – –

BVSEL(3)(4)(5) B1 High Input GND 3.3V

CI E1 Low Output – –

CKSTP_IN D8 Low Input – –

CKSTP_OUT A6 Low Output – –

CLK_OUT D7 – Output – –

DBB J14 Low I/O – –

DBG N1 Low Input – –

DBDIS H15 Low Input – –

DBWO G4 Low Input – –

DH[0-31]

P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11,

R10, P9, N9, T10, R9, T9, P8, N8, R8, T8, N7, R7, T7, P6,

N6, R6, T6, R5, N5, T5, T4

High I/O – –

DL[0-31]

K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16,

N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12,

T13, P3, N3, N4, R3, T1, T2, P4, T3, R4

High I/O – –

DP[0-7] M2, L3, N2, L4, R1, P2, M4, R2 High I/O – –

DRTRY G16 Low Input – –

GBL F1 Low I/O – –

GND

C5, C12, E3, E6, E8, E9, E11, E14, F5, F7, F10, F12, G6,

G8, G9, G11, H5, H7, H10, H12, J5, J7, J10, J12, K6, K8, K9,

K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14, P5, P12

HRESET A7 Low Input – –

INT B15 Low Input – –

L1_TSTCLK(2) D11 High Input – –

L2_TSTCLK(2) D12 High Input – –

LSSD_MODE(2) B10 Low Input – -–

2138F–HIREL–06/05

PC755/745

Notes: 1. OVDD supplies power to the processor bus, JTAG, and all control signals and VDD supplies power to the processor core and

the PLL (after filtering to become AVDD). These columns serve as a reference for the nominal voltage supported on a given

signal as selected by the BVSEL pin configuration of Table 5-1 and the voltage supplied. For actual recommended value of

VIN or supply voltages see ”Absolute Maximum Ratings(1)” on page 14.

2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.

3. To allow for future I/O voltage changes, provide the option to connect BVSEL independently to either OVDD (selects 3.3V) or

to OGND (selects 1.8V/2.0V).

4. Uses one of 15 existing no-connects in PC745’s 255-BGA package.

5. Internal pull up on die.

6. Internally tied to GND in the PC745 255-BGA package to indicate to the power supply that a low-voltage processor is

present. This signal is not a power supply input.

MCP C13 Low Input – –

NC (No-

Connect) B7, B8, C3, C6, C8, D5, D6, H4, J16, A4, A5, A2, A3, B5 – – – –

OVDD C7, E5, E7, E10, E12, G3, G5, G12, G14, K3, K5, K12, K14,

M5, M7, M10, M12, P7, P10 – – 1.8V/2.0V 3.3V

PLL_CFG[0-3] A8, B9, A9, D9 High Input – –

QACK D3 Low Input – –

QREQ J3 Low Output – –

RSRV D1 Low Output – –

SMI A16 Low Input – –

SRESET B14 Low Input – –

SYSCLK C9 – Input – –

TA H14 Low Input – –

TBEN C2 High Input – –

TBST A14 Low I/O – –

TCK C11 High Input – –

TDI(5) A11 High Input – –

TDO A12 High Output – –

TEA H13 Low Input – –

TLBISYNC C4 Low Input – –

TMS(5) B11 High Input – –

TRST(5) C10 Low Input – –

TS J13 Low I/O – –

TSIZ[0-2] A13, D10, B12 High Output – –

TT[0-4] B13, A15, B16, C14, C15 High I/O – –

WT D2 Low Output – –

VDD 2 F6, F8, F9, F11, G7, G10, H6, H8, H9, H11, J6, J8, J9, J11,

K7, K10, L6, L8, L9, L11 – – 2V 2V

VOLTDET(6) F3 High Output – –

Table 2-1. Pinout Listing for the PC745, 255 PBGA and HiTCE CBGA Packages (Continued)

Signal Name Pin Number Active I/O

I/F Voltages Supported(1)

1.8V/2.0V 3.3V

2138F–HIREL–06/05

PC755/745

Table 2-2 provides the pinout listing for the PC755, 360 PBGA, CBGA, HiTCE CBGA and CI-CGA

Table 2-2. Pinout Listing for the PC755, 360 PBGA, CBGA, HiTCE CBGA and CI-CGA Packages(8)

Signal Name Pin Number Active I/O

I/F Voltages

Supported(1)

1.8V/2.0V 3.3V

A[0-31]

A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2,

E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2,

High I/O – –

AACK N3 Low Input – –

ABB L7 Low I/O – –

AP[0-3] C4, C5, C6, C7 High I/O – –

ARTRY L6 Low I/O – –

AVDD A8 - - 2V 2V

BG H1 Low Input – –

BR E7 Low Output – –

BVSEL(3)(5)(6) W1 High Input GND 3.3V

CI C2 Low Output – –

CKSTP_IN B8 Low Input – –

CKSTP_OUT D7 Low Output – –

CLK_OUT E3 – Output – –

DBB K5 Low I/O – –

DBDIS G1 Low Input – –

DBG K1 Low Input – –

DBWO D1 Low Input – –

DH[0-31]

W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9,

R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4,

W3, U4, R5

High I/O – –

DL[0-31]

M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, P12, T13,

W13, U13, V10, W8, T11, U11, V12, V8, T1, P1, V1, U1, N1, R2,

V3, U3, W2

High I/O – –

DP[0-7] L1, P2, M2, V2, M1, N2, T3, R1 High I/O – –

DRTRY H6 Low Input – –

GBL B1 Low I/O – –

GND

D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9, G11,

H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12, K14, K16,

L9, L11, M5, M8, M10, M12, M15, N9, N11, P4, P6, P10, P14, P16,

R8, R12, T4, T6, T10, T14, T16

––GNDGND

HRESET B6 Low Input – –

INT C11 Low Input – –

L1_TSTCLK(2) F8 High Input – –

L2ADDR[0-16] L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16, H18, H17,

J14, J13, H19, G18 High Output – –

2138F–HIREL–06/05

PC755/745

L2AVDD L13 – – 2V 2V

L2CE P17 Low Output – –

L2CLKOUTA N15 – Output – –

L2CLKOUTB L16 – Output – –

L2DATA[0-63]

U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17, W18,

V18, U18, V19, U19, T18, T17, R19, R18, R17, R15, P19, P18,

P13, N14, N13, N19, N17, M17, M13, M18, H13, G19, G16, G15,

G14, G13, F19, F18, F13, E19, E18, E17, E15, D19, D18, D17,

C18, C17, B19, B18, B17, A18, A17, A16, B16, C16, A14, A15,

C15, B14, C14, E13

High I/O – –

L2DP[0-7] V14, U16, T19, N18, H14, F17, C19, B15 High I/O – –

L2OVDD D15, E14, E16, H16, J15, L15, M16, P15, R14, R16, T15, F15 – – 1.8V/2V 3.3V

L2SYNC_IN L14 – Input – –

L2SYNC_OUT M14 – Output – –

L2_TSTCLK(2) F7 High Input – –

L2VSEL(1)(3)(5)(6) A19 High Input GND 3.3V

L2WE N16 Low Output – –

L2ZZ G17 High Output – –

LSSD_MODE(2) F9 Low Input – –

MCP B11 Low Input – –

NC (No-Connect) B3, B4, B5, W19, K9, K114, K194–– – –

OVDD D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4, R6, R9,

R11, T5, T8, T12 – – 1.8V/2V 3.3V

PLL_CFG[0-3] A4, A5, A6, A7 High Input – –

QACK B2 Low Input – –

QREQ J3 Low Output – –

RSRV D3 Low Output – –

SMI A12 Low Input – –

SRESET E10 Low Input – –

SYSCLK H9 – Input – –

TA F1 Low Input – –

TBEN A2 High Input – –

TBST A11 Low I/O – –

TCK B10 High Input – –

TDI(6) B7 High Input – –

TDO D9 High Output – –

Table 2-2. Pinout Listing for the PC755, 360 PBGA, CBGA, HiTCE CBGA and CI-CGA Packages(8) (Continued)

Signal Name Pin Number Active I/O

I/F Voltages

Supported(1)

1.8V/2.0V 3.3V

2138F–HIREL–06/05

PC755/745

Notes: 1. OVDD supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and

L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0-16], L2DATA[0-63], L2DP[0-7] and L2SYNC-OUT) and

the L2 control signals; and VDD supplies power to the processor core and the PLL and DLL (after filtering to become AVDD

and L2AVDD respectively). These columns serve as a reference for the nominal voltage supported on a given signal as

selected by the BVSEL/L2VSEL pin configurations of Table 5-1 and the voltage supplied. For actual recommended value of

VIN or supply voltages see ”Recommended Operating Conditions(1)” on page 16.

2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.

3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVDD

(selects 3.3V) or to OGND (selects 1.8V/2.0V).

4. These pins are reserved for potential future use as additional L2 address pins.

5. Uses one of 9 existing no-connects in PC750’s 360-BGA package.

6. Internal pull up on die.

7. Internally tied to L2OVDD in the PC755 360-BGA package to indicate the power present at the L2 cache interface. This signal

is not a power supply input.

8. This is different from the PC745 255-BGA package.

TEA J1 Low Input – –

TLBISYNC A3 Low Input – –

TMS(6) C8 High Input – –

TRST(6) A10 Low Input – –

TS K7 Low I/O – –

TSIZ[0-2] A9, B9, C9 High Output – –

TT[0-4] C10, D11, B12, C12, F11 High I/O – –

WT C3 Low Output – –

VDD G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12 – – 2V 2V

VOLTDET(7) K13 High Output – –

Table 2-2. Pinout Listing for the PC755, 360 PBGA, CBGA, HiTCE CBGA and CI-CGA Packages(8) (Continued)

Signal Name Pin Number Active I/O

I/F Voltages

Supported(1)

1.8V/2.0V 3.3V

2138F–HIREL–06/05

PC755/745

3. Signal Description

Figure 3-1. PC755 Microprocessor Signal Groups

ABB

TT[0-4]

AP[0-3]

TBST

TS1Z[0-2]

GBL

AACK

ARTRY

DBG

DBWO

DBB

L2ADDR [16-0]

L2DATA [0-63]

L2DP [0-7]

L2CLK-OUT [A-B]

L2WE

A[0-31]

L2SYNC_OUT

L2SYNC_IN

INT

SMI

MCP

HRESET

CKSTP_IN

CKSTP_OUT

SYSCLK,

PLL_CFG [0-3]

Factory Test

JTAG:COP

ADDRESS

ARBITRATION

ADDRESS

START

ADDRESS

BUS

TRANSFER

ATTRIBUTE

ADDRESS

TERMINATION

DATA

ARBITRATION

L2 CACHE

L2 VSEL

ADDRESS/

DATA

L2 CACHE

CLOCK/CONTROL

INTERRUPTS

RESET

CLOCK

CONTROL

TEST INTERFACE

D[0-63]

DATA

TRANSFER D[P0-7]

DBDIS

DATA

TERMINATION DRTRY

TEA

PC755B

L2AV

L2V

SRESET

RSRV

TBEN

TLBISYNC

QREQ

QACK

PROCESSOR

STATUS

CONTROL

CLK_OUT

L2CE

L2ZZ

Not supported in the PC745B

GND

OVDD

VOLTDET

2138F–HIREL–06/05

PC755/745

4. Detailed Specifications

This specification describes the specific requirements for the microprocessor PC755, in compli-

ance with Atmel Grenoble standard screening.

5. Applicable Documents

1) MIL-STD-883: Test methods and procedures for electronics.

2) MIL-PRF-38535 appendix A: General specifications for microcircuits.

The microcircuits are in accordance with the applicable documents and as specified herein.

5.1 Design and Construction

5.1.1 Terminal Connections

Depending on the package, the terminal connections is shown in Table 2-1, Table 2-2 and Fig-

ure 3-1.

Notes: 1. Functional and tested operating conditions are given in ”Recommended Operating Conditions(1)” on page 16. Absolute max-

imum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those

listed may affect device reliability or cause permanent damage to the device.

2. Caution: VIN must not exceed OVDD or L2OVDD by more than 0.3V at any time including during power-on reset.

3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 1.6V during normal operation. During power-on

reset and power-down sequences, L2OVDD/OVDD may exceed VDD/AVDD/L2AVDD by up to 3.3V for up to 20 ms, or by 2.5V

for up to 40 ms. Excursions beyond 3.3V or 40 ms are not supported.

4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4V during normal operation. During power-on

reset and power-down sequences, VDD/AVDD/L2AVDD may exceed L2OVDD/OVDD by up to 1.0V for up to 20 ms, or by 0.7V

for up to 40 ms. Excursions beyond 1.0V or 40 ms are not supported.

5. This is a DC specifications only. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure

5-1.

5.1.2 Absolute Maximum Ratings(1)

Characteristic Symbol Maximum Value Unit

Core supply voltage(4) VDD -0.3 to 2.5 V

PLL supply voltage(4) AVDD -0.3 to 2.5 V

L2 DLL supply voltage(4) L2AVDD -0.3 to 2.5 V

Processor bus supply voltage(3) OVDD -0.3 to 3.6 V

L2 bus supply voltage(3) L2OVDD -0.3 to 3.6 V

Input voltage Processor bus(2)(5) Vin -0.3 to OVDD + 0.3V V

L2 Bus(2)(5) Vin -0.3 to L2OVDD + 0.3V V

JTAG Signals Vin -0.3 to 3.6 V

Storage temperature range Tstg -55/+150 °C

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Figure 5-1 shows the allowable undershoot and overshoot voltage on the PC755 and PC745.

Figure 5-1. Overshoot/Undershoot Voltage

The PC755 provides several I/O voltages to support both compatibility with existing systems and

migration to future systems. The PC755 core voltage must always be provided at nominal 2.0V

(see ”Recommended Operating Conditions(1)” on page 16 for actual recommended core volt-

age). Voltage to the L2 I/Os and Processor Interface I/Os are provided through separate sets of

supply pins and may be provided at the voltages shown in Table 5-1. The input voltage threshold

for each bus is selected by sampling the state of the voltage select pins BVSEL and L2VSEL

during operation. These signals must remain stable during part operation and cannot change.

The output voltage will swing from GND to the maximum voltage applied to the OVDD or L2OVDD

power pins.

Table 5-1 describes the input threshold voltage setting.

Notes: 1. Caution: The input threshold selection must agree with the OVDD/L2OVDD voltages supplied.

2. The input threshold settings above are different for all revisions prior to Rev. 2.8 (Rev. E). For more information, contact your

local Atmel sales office.

(L2) OVDD +20%

(L2) OVDD +5%

(L2) OVDD

Gnd - 1.0V

Gnd - 0.3V

Gnd

VIH

Not to exceed 10%

of tSYSCLK

VIL

Table 5-1. Input Threshold Voltage Setting

Part Revision BVSEL Signal Processor Bus Interface Voltage L2VSEL Signal L2 Bus Interface Voltage

E0 Not Available 0 Not Available

1 2.5V/3.3V 1 2.5V/3.3V

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Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not

guaranteed.

2. Revisions prior to Rev. 2.8 (Rev. E) offered different I/O voltage support.

3. 2.0V nominal.

4. 2.5V nominal.

5. 3.3V nominal.

5.1.3 Recommended Operating Conditions(1)

Recommended Value

Unit300 MHz, 350 MHz 400 MHz

Characteristic Symbol Min Max Min Max

Core supply voltage(3) VDD 1.80 2.10 1.90 2.10 V

PLL supply voltage(3) AVDD 1.80 2.10 1.90 2.10 V

L2 DLL supply voltage(3) L2AVDD 1.80 2.10 1.90 2.10 V

Processor bus supply voltage(2)(4)(5) BVSEL = 1 OVDD

2.375 2.625 2.375 2.625 V

3.135 3.465 3.135 3.465 V

L2 bus supply voltage(2)(4)(5) L2VSEL = 1 L2OVDD

2.375 2.625 2.375 2.625 V

3.135 3.465 3.135 3.465 V

Input voltage

Processor bus Vin GND OVDD GND OVDD V

L2 Bus Vin GND L2OVDD GND L2OVDD V

JTAG Signals Vin GND OVDD GND OVDD V

Die-junction temperature Military temperature range Tj-55 125 -55 125 °C

Industrial temperature Tj-40 110 -40 110 °C

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6. Thermal Characteristics

6.1 Package Characteristics

Table 6-1 provides the package thermal characteristics for the PC755.

Notes: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) tempera-

ture, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1) with the calculated case temperature. The actual value of RθJC for the part is less than 0.1°C/W.

Note: Refer to Section “Thermal Management Information“ page 19 for more details about thermal management.

6.1.1 Package Thermal Characteristics for HiTCE

Table 6-2 provides the package thermal characteristics for the PC755, HiTCE.

Notes: 1. Simulation, no convection air flow

2. Per JEDEC JESD51-6 with the board horizontal

3. Per JEDEC JESD51-8

4. Per JEDEC JESD51-2 with the board horizontal

Table 6-1. Package Thermal Characteristics

Characteristic Symbol

Value

Unit

PC755

CBGA

PC755

PBGA

PC745

PBGA

Junction-to-ambient thermal resistance, natural convection()(2) RθJA 24 31 34 °C/W

Junction-to-ambient thermal resistance, natural convection, four-layer

(2s2p) board()(3) RθJMA 17 25 26 °C/W

Junction-to-ambient thermal resistance, 200 ft./min. airflow, single-layer

(1s) board()(3) RθJMA 18 25 27 °C/W

Junction-to-ambient thermal resistance, 200 ft./min. airflow, four-layer

(2s2p) board()(3) RθJMA 14 21 22 °C/W

Junction-to-board thermal resistance(4) RθJB 81717°C/W

Junction-to-case thermal resistance(5) RθJC < 0.1 < 0.1 < 0.1 °C/W

Table 6-2. Package Thermal Characteristics for HiTCE Package

Characteristic Symbol

Value

UnitPC755 HiTCE PC745 HiTCE

Junction-to-bottom of balls(1) RθJ6.8 6.5 °C/W

Junction-to-ambient thermal resistance, natural convection,

four-layer (2s2p) board RθJMA 20.7(1)(2) 20.9(1)(4) °C/W

Junction to board thermal resistance RθJB 11.0 10.2(3) °C/W

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The board designer can choose between several types of heat sinks to place on the PC755.

There are several commercially-available heat sinks for the PC755 provided by the following

vendors.

For the exposed-die packaging technology, shown in ”Recommended Operating Conditions(1)”

on page 16, the intrinsic conduction thermal resistance paths are as follows:

• The die junction-to-case (or top-of-die for exposed silicon) thermal resistance

• The die junction-to-ball thermal resistance

Figure 6-1 depicts the primary heat transfer path for a package with an attached heat sink

mounted to a printed-circuit board.

Heat generated on the active side of the chip is conducted through the silicon, then through the

heat sink attach material (or thermal interface material), and finally to the heat sink where it is

removed by forced-air convection.

Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop

in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduc-

tion/convective thermal resistances are the dominant terms.

Figure 6-1. C4 Package with Head Sink Mounted to a Printed-circuit Board

Note the internal versus external package resistance.

Table 6-3. Package Thermal Characteristics for CI-CGA

Characteristic Symbol

Value

UnitPC755 CI-CGA

Junction to board thermal resistance RθJB 8.42 °C/W

External Resistance

Internal Resistance

Radiation Convection

Heat Sink

Printed ± Circuit Board

Thermal Interface Material

Package/Leads

Die Junction

Die/Package

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6.1.2 Thermal Management Assistance

The PC755 incorporates a thermal management assist unit (TAU) composed of a thermal sen-

sor, digital-to-analog converter, comparator, control logic, and dedicated special-purpose

registers (SPRs). Specifications for the thermal sensor portion of the TAU are found in Table 6-

4. More information on the use of this feature is given in the Freescale PC755 RISC Micropro-

cessor User’s manual.

Notes: 1. The temperature is the junction temperature of the die. The thermal assist unit’s raw output

does not indicate an absolute temperature, but must be interpreted by software to derive the

absolute junction temperature. For information about the use and calibration of the TAU, see

Freescale Application Note AN1800/D, “Programming the Thermal Assist Unit in the PC750

Microprocessor”.

2. The comparator settling time value must be converted into the number of CPU clocks that

need to be written into the THRM3 SPR.

3. Guaranteed by design and characterization.

6.1.3 Thermal Management Information

This section provides thermal management information for air-cooled applications. Proper ther-

mal control design is primarily dependent upon the system-level design-the heat sink, airflow

and thermal interface material. To reduce the die-junction temperature, heat sinks may be

attached to the package by several methods-adhesive, spring clip to holes in the printed-circuit

board or package, and mounting clip and screw assembly; see Figure 6-2. This spring force

should not exceed 5.5 pounds of force.

Figure 6-2. Package Exploded Cross-Sectional View with Several Heat Sink Options

Table 6-4. Thermal Sensor Specifications at Recommended Operating Conditions

(see ”Recommended Operating Conditions(1)” on page 16)

Characteristic Min Max Unit

Temperature range(1) 0 127 °C

Comparator settling time(2)(3) 20 – s

Resolution(3) 4–°C

Accuracy(3) -12 +12 °C

Adhesive

Thermal Interface Material

Heat Sink

Clip

Printed ± Circuit Board Option

BGA Package

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Ultimately, the final selection of an appropriate heat sink depends on many factors, such as ther-

mal performance at a given air velocity, spatial volume, mass, attachment method, assembly,

and cost.

6.1.4 Adhesives and Thermal Interface Materials

Figure 6-3. Thermal Performance of Select Thermal Interface Material

A thermal interface material is recommended at the package lid-to-heat sink interface to mini-

mize the thermal contact resistance. For those applications where the heat sink is attached by

spring clip mechanism, Figure 6-3 shows the thermal performance of three thin-sheet thermal-

interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal

grease as a function of contact pressure. As shown, the performance of these thermal interface

materials improves with increasing contact pressure. The use of thermal grease significantly

reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance

approximately 7 times greater than the thermal grease joint.

Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit

board (see Figure 6-2). This spring force should not exceed 5.5 pounds of force. Therefore, the

synthetic grease offers the best thermal performance, considering the low interface pressure.

The board designer can choose between several types of thermal interface. Heat sink adhesive

materials should be selected based upon high conductivity, yet adequate mechanical strength to

meet equipment shock/vibration requirements.

0.5

1.5

2Silicone Sheet (0.006 inch)

Bare Joint

Floroether Oil Sheet (0.007 inch)

Graphite/Oil Sheet (0.005 inch)

Synthetic Grease

Contact Pressure (psi)

Specific Thermal Resistance (Kin2/W)

0 1020304050607080

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6.1.5 Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:

Tj = Ta + Tr + (θjc + θint + θsa) × Pd

Where:

Tj is the die-junction temperature

Ta is the inlet cabinet ambient temperature

Tr is the air temperature rise within the computer cabinet

θjc is the junction-to-case thermal resistance

θint is the adhesive or interface material thermal resistance

θsa is the heat sink base-to-ambient thermal resistance

Pd is the power dissipated by the device

During operation the die-junction temperatures (Tj) should be maintained less than the value

specified in Table 5. The temperature of the air cooling the component greatly depends upon the

ambient inlet air temperature and the air temperature rise within the electronic cabinet. An elec-

tronic cabinet inlet-air temperature (Ta) may range from 30 to 40°C. The air temperature rise

within a cabinet (Tr) may be in the range of 5 to 10°C. The thermal resistance of the thermal

interface material (θint) is typically about 1°C/W. Assuming a Ta of 30°C, a Tr of 5oC, a CBGA

package θjc = 0.03, and a power consumption (Pd) of 5.0 watts, the following expression for Tj is

obtained:

Die-junction temperature: Tj = 30°C + 5°C + (0.03°C/W + 1.0°C/W + θsa) × 5.0 W

For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (θsa) versus air-

flow velocity is shown in Figure 6-4.

Figure 6-4. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow

Velocity

0 0.5 1 1.5 2 2.5 3 3.5

Thermalloy #2328B Pin±fin Heat Sink

Approach Air Velocity (m/s)

(25 x28 x 15 mm)

Heat Sink Thermal Resistance °C/W)

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Assuming an air velocity of 0.5 m/s, we have an effective Rsa of 7°C/W, thus

Tj = 30°C + 5°C+ (0.03°C/W +1.0°C/W + 7°C/W) × 5.0 W

resulting in a die-junction temperature of approximately 81°C which is well within the maximum

operating temperature of the component.

Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering, and Aavid

Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need

air flow.

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a com-

mon figure-of-merit used for comparing the thermal performance of various microelectronic

packaging technologies, one should exercise caution when only using this metric in determining

thermal management because no single parameter can adequately describe three-dimensional

heat flow. The final die-junction operating temperature, is not only a function of the component-

level thermal resistance, but the system-level design and its operating conditions. In addition to

the component’s power consumption, a number of factors affect the final operating die-junction

temperature — airflow, board population (local heat flux of adjacent components), heat sink effi-

ciency, heat sink attach, heat sink placement, next-level interconnect technology, system air

temperature rise, altitude, etc.

Due to the complexity and the many variations of system-level boundary conditions for today’s

microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation,

convection and conduction) may vary widely. For these reasons, we recommend using conju-

gate heat transfer models for the board, as well as, system-level designs. To expedite system-

level thermal analysis, several “compact” thermal-package models are available within FLO-

THERM®. These are available upon request.

7. Power consideration

7.1 Power management

The PC755 provides four power modes, selectable by setting the appropriate control bits in the

MSR and HIDO registers. The four power modes are as follows:

• Full-power: This is the default power state of the PC755. The PC755 is fully powered and the

internal functional units operate at the full processor clock speed. If the dynamic power

management mode is enabled, functional units that are idle will automatically enter a low-

power state without affecting performance, software execution, or external hardware.

• Doze: All the functional units of the PC755 are disabled except for the time base/decrementer

registers and the bus snooping logic. When the processor is in doze mode, an external

asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or

soft reset, or machine check brings the PC755 into the full-power state. The PC755 in doze

mode maintains the PLL in a fully powered state and locked to the system external clock

input (SYSCLK) so a transition to the full-power state takes only a few processor clock cycles.

• Nap: The nap mode further reduces power consumption by disabling bus snooping, leaving

only the time base register and the PLL in a powered state. The PC755 returns to the full-

power state upon receipt of an external asynchronous interrupt, a system management

interrupt, a decrementer exception, a hard or soft reset, or a machine check input (MCP). A

return to full-power state from a nap state takes only a few processor clock cycles.

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When the processor is in nap mode, if QACK is negated, the processor is put in doze mode

to support snooping.

• Sleep: Sleep mode minimizes power consumption by disabling all internal functional units,

after which external system logic may disable the PPL and SUSCLK. Returning the PC755 to

the full-power state requires the enabling of the PPL and SYSCLK, followed by the assertion

of an external asynchronous interrupt, a system management interrupt, a hard or soft reset,

or a machine check input (MCP) signal after the time required to relock the PPL.

7.2 Power Dissipation

Notes: 1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O

supply power (OVDD and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and

L2OVDD power is system dependent, but is typically < 10% of VDD power. Worst case power

consumption for AVDD = 15 mW and L2AVDD = 15 mW.

2. Maximum power is measured at nominal VDD (see ”Recommended Operating Conditions(1)” on

page 16) while running an entirely cache-resident, contrived sequence of instructions which

keep the execution units maximally busy.

3. Typical power is an average value measured at the nominal recommended VDD

(see ”Recommended Operating Conditions(1)” on page 16) and 65×C in a system while run-

ning a typical code sequence.

4. Not 100% tested. Characterized and periodically sampled.

Table 7-1. Power Consumption for PC755

Processor (CPU) Frequency

Unit300 MHz 350 MHz 400 MHz

Full-Power Mode

Typical(1)(3)(4) 3.1 3.6 5.4 W

Maximum(1)(2) 4.5 5.3 8 W

Doze Mode

Maximum(1)(2)(4) 1.8 2 2.3 W

Nap Mode

Maximum(1)(2)(4) 111W

Sleep Mode

Maximum(1)(2)(4) 550 550 550 mW

Sleep Mode-PLL and DLL Disabled

Maximum(1)(2) 510 510 510 mW

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8. Electrical Characteristics

8.1 Static Characteristics

Notes: 1. Nominal voltages; See ”Recommended Operating Conditions(1)” on page 16.

2. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals.

3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals.

4. Capacitance is periodically sampled rather than 100% tested.

5. The leakage is measured for nominal OVDD and VDD, or both OVDD and VDD must vary in the same direction (for example,

both OVDD and VDD vary by either +5% or -5%).

8.2 Dynamic Characteristics

After fabrication, parts are sorted by maximum processor core frequency as shown in ”Clock AC

Specifications” on page 25 and tested for conformance to the AC specifications for that fre-

quency. These specifications are for 275, 300, 333 MHz processor core frequencies. The

processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the

PLL_CFG[0-3] signals. Parts are sold by maximum processor core frequency.

Table 8-1. DC Electrical Specifications at Recommended Operating Conditions (see ”Recommended Operating Condi-

tions(1)” on page 16)

Characteristic

Nominal bus

Voltage(1) Symbol Min Max Unit

Input high voltage (all inputs except SYSLCK)(2)(3) 2.5 VIH 1.6 (L2)OVDD + 0.3 V

3.3 VIH 2 (L2)OVDD + 0.3 V

Input low voltage (all inputs except SYSLCK)(2) 2.5 VIL -0.3 0.6 V

3.3 VIL -0.3 0.8 V

SYSCLK input high voltage 2.5 KVIH 1.8 OVDD + 0.3 V

3.3 KVIH 2.4 OVDD + 0.3 V

SYSCLK input low voltage 2.5 KVIL -0.3 0.4 V

3.3 KVIL -0.3 0.4 V

Input leakage current, (2)(3)

VIN = L2OVDD/OVDD

Iin –10µA

Hi-Z (off-state) leakage current, (2)(3)(5)

VIN = L2OVDD/OVDD

ITSI –10µA

Output high voltage, IOH = -6 mA 2.5 VOH 1.7 – V

3.3 VOH 2.4 – V

Output low voltage, IOL = 6 mA 2.5 VOL –0.45V

3.3 VOL –0.4V

Capacitance, VIN = 0V, f = 1 MHz (3)(4) Cin –5pF

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8.2.1 Clock AC Specifications

Table 8-2 provides the clock AC timing specifications as defined in ”Absolute Maximum Rat-

ings(1)” on page 14.

Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) fre-

quency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to the PLL_CFG[0-3] signal description in Table 9-1,” for valid PLL_CFG[0-3] settings

2. Rise and fall times measurements are now specified in terms of slew rates, rather than time to account for selectable I/O bus

interface levels. The minimum slew rate of 1v/ns is equivalent to a 2ns maximum rise/fall time measured at 0.4V and 2.4V or

a rise/fall time of 1ns measured at 0.4V to 1.4V.

3. Timing is guaranteed by design and characterization.

4. This represents total input jitter – short term and long term combined and is guaranteed by design.

5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for

PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies

when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held

asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

Figure 8-1 provides the SYSCLK input timing diagram.

Figure 8-1. SYSCLK Input Timing Diagram

8.2.1.1 Processor Bus AC Specifications

Table 8-3 provides the processor bus AC timing specifications for the PC755 as defined in Fig-

ure 8-2 and Figure 8-4. Timing specifications for the L2 bus are provided in ”L2 Clock AC

Specifications” on page 28.

Table 8-2. Clock AC Timing Specifications at Recommended Operating Conditions (See ”Recommended Operating

Conditions(1)” on page 16)

Characteristic Symbol

Maximum Processor Core Frequency

Unit

300 MHz 350 MHz 400 MHz

Min Max Min Max Min Max

Processor frequency(1) fcore 200 300 200 350 200 400 MHz

VCO frequency(1) fVCO 400 600 400 700 400 800 MHz

SYSCLK frequency(1) fSYSCLK 25 100 25 100 25 100 MHz

SYSCLK cycle time tSYSCLK 10 40 10 40 10 40 ns

SYSCLK rise and fall time(2) tKR & tKF –2–2–2 ns

tKR & tKF –1.4–1.4–1.4 ns

SYSCLK duty cycle measured at OVDD/2(3) tKHKL/tSYSCLK 40 60 40 60 40 60 %

SYSCLK jitter(3)(4) – 150 – 150 – 150 ps

Internal PLL relock time(3)(5) –100–100–100 µs

SYSCLK VMVMVM

KVIH

KVIL

VM = Midpoint Voltage (OVDD/2)

tSYSCLK

tKR tKF

tKHKL

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Notes: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input

SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-

nal in question. All output timings assume a purely resistive 50Ω load (See Figure 8-2). Input and output timings are

measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. THe symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and

t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to

the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from SYSCLK(K)

going highs) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal

(I) went invalid (X) with respect to the rising clock edge (KH) - note the position of the reference and its state for inputs – and

output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX). For additional explana-

tion of AC timing specifications in Freescale PowerPC microprocessors, see the application note “Understanding AC Timing

Specifications for PowerPC Microprocessors.”

3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 8-2).

4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of

255 bus clocks after the PLL re-lock time during the power-on reset sequence.

5. tSYSCLK is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied

by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.

6. Mode select signals are BVSEL, L2VSEL, PLL_CFG[0-3]

7. Guaranteed by design and characterization.

8. Bus mode select pins must remain stable during operation. Changing the logic states of BVSEL or L2VSEL during operation

will cause the bus mode voltage selection to change. Changing the logic states of the PLL_CFG pins during operation will

cause the PLL division ratio selection to change. Both of these conditions are considered outside the specification and are

not supported. Once HRESET is negated the states of the bus mode selection pins must remain stable.

Figure 8-2 provides the mode select input timing diagram for the PC755.

Figure 8-2. Mode Input Timing Diagram

Figure 8-3 provides the AC test load for the PC755.

Figure 8-3. AC Test Load

Table 8-3. Processor Bus Mode Selection AC Timing Specifications(1)

At VDD = AVDD = 2.0V 100 mV; -55 ≤ Tj ≤ +125°C, OVDD = 3.3V 165 mV and OVDD = 1.8V ± 100 mV and

OVDD = 2.0V 100 mV

Parameter

Symbols(2) All Speed Grades

UnitMin Max

Mode select input setup to HRESET(3)(4)(5)(6)(7) tMVRH 8–t

SYSCLk

HRESET to mode select input hold(3)(4)(6)(7)(8) tMXRH 0–ns

HRESET

Mode Signals

VM = Midpoint Voltage (OVDD/2)

tMVRH tMXRH

OVDD/2

OUTPUT Z0 = 50Ω

RL = 50Ω

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Notes: 1. Revisions prior to Rev 2.8 (Rev E) were limited in performance and did not conform to this specification. Contact your local

Freescale sales office for more information.

2. Guaranteed by design and characterization.

3. tSYSCLK is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied

by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. Per the 60x bus protocol, TS, ABB and DBB are driven only by the currently active bus master. They are asserted low then

precharged high before returning to high-Z as shown in Figure 6-1. The nominal precharge width for TS, ABB or DBB is 0.5

x tSYSCLK, i.e. less than the minimum tSYSCLK period, to ensure that another master asserting TS, ABB, or DBB on the following

clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid

time is tested for precharge.The high-Z behavior is guaranteed by design.

5. Per the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following

AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting it low in

the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle after the

assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK; i.e., it should be high-Z as shown in Figure 6-1

before the first opportunity for another master to assert ARTRY. Output valid and output hold timing is tested for the signal

asserted. Output valid time is tested for precharge. The high-Z and precharge behavior is guaranteed by design.

Table 8-4. Processor Bus AC Timing Specifications(1) at Recommended Operating Conditions

Parameter Symbols

All Speed Grades

UnitMin Max

Setup Times: All Inputs tIVKH 2.5 – ns

Input Hold Times: TLBISYNC, MCP, SMI tIXKH 0.6 – ns

Input Hold Times: All Inputs, except TLBISYNC, MCP, SMI tIXKH 0.2 – ns

Valid Times: All Outputs tKHOV –4.1ns

Output Hold Times: All Outputs tKHOX 1–ns

SYSCLK to Output Enable(2) tKHOE 0.5 – ns

SYSCLK to Output High Impedance (all except ABB, ARTRY, DBB)(2) tKHOZ –6ns

SYSCLK to ABB, DBB High Impedance After Precharge(2)(3)(4) tKHABPZ –1t

SYSCLK

Maximum Delay to ARTRY Precharge(2)(3)(5) tKHARP –1t

SYSCLK

SYSCLK to ARTRY High Impedance After Precharge(2)(3)(5) tKHARPZ –2t

SYSCLK

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Figure 8-4 provides the input/output timing diagram for the PC755.

Figure 8-4. Input/Output Timing Diagram

8.2.1.2 L2 Clock AC Specifications

The L2CLK frequency is programmed by the L2 Configuration Register (L2CR[4:6]) core-to-L2

divisor ratio. See Table 8-5 for example core and L2 frequencies at various divisors. Table 8-5

provides the potential range of L2CLK output AC timing specifications as defined in Figure 8-5.

The minimum L2CLK frequency of Table 8-5 is specified by the maximum delay of the internal

DLL. The variable-tap DLL introduces up to a full clock period delay in the L2CLKOUTA,

L2CLKOUTB, and L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase

aligned with the next core clock (divided by the L2 divisor ratio). Do not choose a core-to-L2 divi-

sor which results in an L2 frequency below this minimum, or the L2CLKOUT signals provided for

SRAM clocking will not be phase aligned with the PC755 core clock at the SRAMs.

The maximum L2CLK frequency shown in Table 8-5 is the core frequency divided by one. Very

few L2 SRAM designs will be able to operate in this mode. Most designs will select a greater

core-to-L2 divisor to provide a longer L2CLK period for read and write access to the L2 SRAMs.

The maximum L2CLK frequency for any application of the PC755 will be a function of the AC

timings of the PC755, the AC timings for the SRAM, bus loading, and printed circuit board trace

length.

Freescale is similarly limited by system constraints and cannot perform tests of the L2 interface

on a socketed part on a functional tester at the maximum frequencies of Table 8-5. Therefore

functional operation and AC timing information are tested at core-to-L2 divisors of 2 or greater.

SYSCLK

All Inputs

All Outputs

(Except TS, ABB,

ARTRY, DBB)

TRYAR

tIVKH tIXKH

tKHOE

tKHOV tKHOX

tKHABPZ

tKHOV

tKHOX

tKHOZ

tKHARPZ

tKHOV

tKHOX

tKHARP

tKHOV

tKHOZ

VM = Midpoint Voltage (OVDD/2 or VIN/2)

TS, ABB, DBB

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Functionality of core-to-L2 divisors of 1 or 1.5 is verified at less than maximum rated

frequencies.

L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is

SYSCLK multiplied up to the core frequency and divided down to the L2CLK frequency). In other

words, the AC timings of Table 8-6 and Table 8-7 are entirely independent of L2SYNC_IN. In a

closed loop system, where L2SYNC_IN is driven through the board trace by L2SYNC_OUT,

L2SYNC_IN only controls the output phase of L2CLKOUTA and L2CLKOUTB which are used to

latch or enable data at the SRAMs. However, since in a closed loop system L2SYNC_IN is held

in phase alignment with the internal L2CLK, the signals of Table 8-6 and Table 8-7 are refer-

enced to this signal rather than the not-externally-visible internal L2CLK. During manufacturing

test, these times are actually measured relative to SYSCLK.

The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned

to the L2SYNC_IN input of the PC755 to synchronize L2CLKOUT at the SRAM with the proces-

sor’s internal clock. L2CLKOUT at the SRAM can be offset forward or backward in time by

shortening or lengthening the routing of L2SYNC_OUT to L2SYNC_IN. See Freescale Applica-

tion Note AN179/D “PowerPC™ Backside L2 Timing Analysis for the PCB Design Engineer.”

The L2CLKOUTA and L2CLKOUTB signals should not have more than two loads.

Notes: 1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, L2CLK_OUT and L2SYNC_OUT pins. The L2CLK frequency to core fre-

quency settings must be chosen so that the resulting L2CLK frequency and core frequency do not exceed their respective

maximum or minimum operating frequencies. The maximum L2LCK frequency will be system dependent. L2CLK_OUTA and

L2CLK_OUTB must have equal loading.

2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.

3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to

compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization.

4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the DLL.

5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.

6. This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL tap as the

phase comparator seeks to minimize the phase difference between L2SYNC_IN and the internal L2CLK. This number must

be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects L2CLKOUT and the L2 address/data/control

signals equally and therefore is already comprehended in the AC timing and does not have to be considered in the L2 timing

analysis.

7. Guaranteed by design.

Table 8-5. L2CLK Output AC Timing Specification. At VDD = AVDD = 2.0V 100 mV; -55 ≤ Tj ≤ +125°C, OVDD = 3.3V

165 mV and OVDD = 1.8V 100 mV and OVDD = 2.0V 100 mV

Parameter Symbols

All Speed Grades

UnitMin Max

L2CLK frequency(1)(4) f L2CLK 80 450 MHz

L2CLK cycle time t L2CLK 2.5 12.5 ns

L2CLK duty cycle(2)(7) tCHCL/tL2CLK 45 55 %

Internal DLL-relock time(3)(7) – 640 – L2CLK

DLL capture window(5)(7) – 0 10 ns

L2CLKOUT output-to-output skew(6)(7) tL2CSKW –50ps

L2CLKOUT output jitter(6)(7) – – ±150 ps

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The L2CLK_OUT timing diagram is shown in Figure 8-5.

Figure 8-5. L2CLK_OUT Output Timing Diagram

VM = Midpoint Voltage (L2OVdd/2)

L2CLK_OUTA

L2CLK_OUTB

L2 Differential Clock Mode

L2 Single-Ended Clock Mode

L2SYNC_OUT

L2CLK_OUTA VM

tL2CR tL2CF

L2CLK_OUTB

VMVM

L2SYNC_OUT

VM VM VM

tL2CSKW

tL2CLK

tCHCL

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8.2.1.3 L2 Bus Input AC Specifications

Table 8-6 provides the L2 bus interface AC timing specifications for the PC755 as defined in Fig-

ure 8-6 and Figure 8-7 for the loading conditions described in Figure 8-8.

Notes: 1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD.

2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of

the input L2SYNC_IN (see Figure 6-3). Input timings are measured at the pins.

3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the sig-

nal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50Ω load (See

Figure 8-1).

4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous Bur-

stRAMs, L2CR[14-15] = 01 or 10 is recommended. For pipelined late write synchronous BurstRAMs, L2CR[14-15] = 11 is

recommended.

5. Guaranteed by design and characterization.

6. Revisions prior to Rev 2.8 (Rev E) were limited in performance.and did not conform to this specification. Contact your local

Atmel sales office for more information.

Table 8-6. L2 Bus Interface AC Timing Specifications at Recommended Operating Conditions

Parameter Symbol

All Speed Grades

UnitMin Max

L2SYNC_IN rise and Fall Time(1) tL2CR & tL2CF –1.0ns

Setup Times: Data and Parity(2) tDVL2CH 1.2 - ns

Input Hold Times: Data and Parity(2) tDXL2CH 0-ns

Valid Times: (3)(4)

All Outputs when L2CR[14-15] = 00

All Outputs when L2CR[14-15] = 01

All Outputs when L2CR[14-15] = 10

All Outputs when L2CR[14-15] = 11

tL2CHOV

3.1

3.2

3.3

3.7

Output Hold Times: (3)

All Outputs when L2CR[14-15] = 00

All Outputs when L2CR[14-15] = 01

All Outputs when L2CR[14-15] = 10

All Outputs when L2CR[14-15] = 11

tL2CHOX

0.5

0.7

0.9

1.1

L2SYNC_IN to High Impedance:(3)(5)

All Outputs when L2CR[14-15] = 00

All Outputs when L2CR[14-15] = 01

All Outputs when L2CR[14-15] = 10

All Outputs when L2CR[14-15] = 11

tL2CHOZ

2.4

2.6

2.8

3.0

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Figure 8-6 shows the L2 bus input timing diagrams for the PC755.

Figure 8-6. L2 Bus Input Timing Diagrams

Figure 8-7 shows the L2 bus output timing diagrams for the PC755.

Figure 8-7. L2 Bus Output Timing Diagrams

Figure 8-8 provides the AC test load for L2 interface of the PC755.

Figure 8-8. AC Test Load for the L2 Interface

8.2.2 IEEE 1149.1 AC Timing Specifications

Table 8-7 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 8-9,

Figure 8-10, Figure 8-11, and Figure 8-12.

L2SYNC_IN VM

VM = Midpoint Voltage (L2OVDD/2)

tDVL2CH tDXL2CH

tL2CR tL2CF

L2 Data and Data

Parity Inputs

L2SYNC_IN VM

VM = Midpoint Voltage (L2OVDD/2)

L2DATA BUS

tL2CHOX

tL2CHOZ

tL2CHOV

All Outputs

Output L2OVdd/2

RL = 50Ω

Z0 = 50Ω

Table 8-7. JTAG AC Timing Specifications (Independent of SYSCLK)(1)

Parameter Symbol Min Max Unit

TCK Frequency of operation fTCLK 016MHz

TCK Cycle time fTCLK 62.5 - ns

TCK Clock pulse width measured at 1.4V tJHJL 31 - ns

TCK Rise and fall times tJR & tJF 02ns

TRST Assert time(2) tTRST 25 - ns

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Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in ques-

tion. The output timings are measured at the pins. All output timings assume a purely resistive 50Ω load (See Figure 8-9).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

Figure 8-9 provides the AC test load for TDO and the boundary-scan outputs of the PC755.

Figure 8-9. Alternate AC Test Load for the JTAG Interface

Figure 8-10 provides the JTAG clock input timing diagram.

Figure 8-10. JTAG Clock Input Timing Diagram

Figure 8-11 provides the TRST timing diagram.

Figure 8-11. TRST Timing Diagram

Input Setup Times:(3)

- Boundary-scan data

- TMS, TDI

tDVJH

tIVJH

Input Hold Times:(3)

- Boundary-scan data

- TMS, TDI

tDXJH

tIXJH

Valid Times:(4)

- Boundary-scan data

- TDO

tJLDV

tJLOV

Output Hold Times:(4)

- Boundary-scan data

- TDO

tJLDV

tJLOV

TCK to output high impedance:(4)(5)

- Boundary-scan data

- TDO

tJLDZ

tJLOZ

Table 8-7. JTAG AC Timing Specifications (Independent of SYSCLK)(1) (Continued)

Parameter Symbol Min Max Unit

OVDD/2

Output Z0 = 50Ω

RL = 50Ω

TCLK VMVMVM

VM = Midpoint Voltage (OVDD/2)

tTCLK

tJR tJF

tJHJL

TRST

tTRST

VM = Midpoint Voltage (OVDD/2)

VM VM

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Figure 8-12 provides the boundary-scan timing diagram.

Figure 8-12. Boundary-Scan Timing Diagram

Figure 8-13 provides the test access port timing diagram.

Figure 8-13. Test Access Port Timing Diagram

8.2.2.1 JTAG Configuration Signals

Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is

optional in the IEEE 1149.1 specification, but is provided on all processors that implement the

PowerPC architecture. While it is possible to force the TAP controller to the reset state using

only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the

TRST signal is asserted during power-on reset. Because the JTAG interface is also used for

accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not

practical.

TCK

Boundary

Data Inputs

Boundary

Data Outputs

Boundary

Data Outputs

VM = Midpoint Voltage (OVDD/2)

tDXJH

tDVJH

tJLDV

JLDZ

Output

Data

Valid

tJLDH

Output Data Valid

Input

Data Valid

TCK

TDI, TMS

TDO

tIXJH

tIVJH

tJLOV

tJLOZ

tJLOH

VM = Midpoint Voltage (OVDD/2)

Output

Data Valid

Input

Data Valid

Output Data Valid

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The COP function of these processors allows a remote computer system (typically, a PC with

dedicated hardware and debugging software) to access and control the internal operations of

the processor. The COP interface connects primarily through the JTAG port of the processor,

with some additional status monitoring signals. The COP port requires the ability to indepen-

dently assert HRESET or TRST in order to fully control the processor. If the target system has

independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or

push-button switches, then the COP reset signals must bemerged into these signals with logic.

The arrangement shown in Figure 8-14 allows the COP port to independently assert HRESET or

TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP

header will not be used, TRST should be tied to HRESET through a 0Ω isolation resistor so that

it is asserted when the systemreset signal (HRESET) is asserted ensuring that the JTAG scan

chain is initialized during power-on. While Freescale recommends that the COP header be

designed into the system as shown in Figure 8-14, if this is not possible, the isolation resistor will

allow future access to TRST in the case where a JTAG interfacemay need to be wired onto the

system in debug situations.

The COP header shown in Figure 8-14 adds many benefits — breakpoints, watchpoints, register

and memory examination/modification, and other standard debugger features are possible

through this interface — and can be as inexpensive as an unpopulated footprint for a header to

be added when needed.

The COP interface has a standard header for connection to the target system, based on the

0.025" square-post 0.100" centered header assembly (often called a Berg header). The connec-

tor typically has pin 14 removed as a connector key.

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Figure 8-14. JTAG Interface Connection

Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the PC755.

Connect pin 5 of the COP header to OVDD with a 10 kΩ pull-up resistor.

2. Key location; pin 14 is not physically present on the COP header.

3. Component not populated. Populate only if debug tool does not drive QACK.

4. Populate only if debug tool uses an open-drain type output and does not actively deassert

QACK.

5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from

the COP header though an AND gate to TRST of the part. If the JTAG interface is not imple-

mented, connect HRESET from the target source to TRST of the part through a 0Ω isolation

resistor.

The COP header shown in Figure 8-15 adds many benefits—breakpoints, watchpoints, register

and memory examination/modification and other standard debugger features are possible

through this interface – and can be as inexpensive as an unpopulated footprint for a header to

be added when needed.

HRESET

From Target

Board Sources

SRESET

VDD_SENSE

2kΩ10 kΩ

10 kΩ

CHKSTP_IN

8TMS

TDO

TDI

TCK

4TRST

(if any)

COP Header

14 2

Key

10 kΩ

QACK

CHKSTP_OUT

KEY

No pin

COP Connector

Physical Pin Out

10 kΩ 4

HRESET

SRESET

OVDD

CHKSTP_IN

TMS

TDO

TDI

TCK

QACK

TRST

CHKSTP_OUT

OVDD

2kΩ3

0Ω5

HRESET

10 kΩ

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The COP interface has a standard header for connection to the target system, based on the

0.025” square-post 0.100” centered header assembly (often called a “Berg” header). The con-

nector typically has pin 14 removed as a connector key.

Figure 8-15 shows the COP connector diagram.

Figure 8-15. COP Connector Diagram

There is no standardized way to number the COP header shown in Figure 8-15; consequently,

many different pin numbers have been observed from emulator vendors. Some are numbered

top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others

number the pins counter clockwise from pin one (as with an IC). Regardless of the numbering,

the signal placement recommended in Figure 8-15 is common to all known emulators.

The QACK signal shown in Table 8-7 is usually hooked up to the PCI bridge chip in a system

and is an input to the PC755 informing it that it can go into the quiescent state. Under normal

operation this occurs during a low power mode selection. In order for COP to work the PC755

must see this signal asserted (pulled down). While shown on the COP header, not all emulator

products drive this signal. To preserve correct power down operation, QACK should be merged

so that it also can be driven by the PCI bridge.

CKSTP_OUT

13 9 5 1

610 2

TOP VIEW

15 11 7

16 12 8 4

KEY

No pin

HRESET

SRESET

TMS

RUN/STOP

TCK

TDI

TDO

Ground

TRST

VDD_SENSE

Pins 10, 12 and 14 are no-connects.

Pin 14 is not physically present

QACK

CHKSTP_IN

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9. Preparation for Delivery

9.1 Packaging

Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.

9.2 Certificate of Compliance

Atmel offers a certificate of compliances with each shipment of parts, affirming the products are

in compliance either with MIL-PRF-883 and guarantying the parameters not tested at tempera-

ture extremes for the entire temperature range.

9.3 Handling

MOS devices must be handled with certain precautions to avoid damage due to accumulation of

static charge. Input protection devices have been designed in the chip to minimize the effect of

static buildup. However, the following handling practices are recommended:

1. Devices should be handled on benches with conductive and grounded surfaces

2. Ground test equipment, tools and operator

3. Do not handle devices by the leads

4. Store devices in conductive foam or carriers

5. Avoid use of plastic, rubber, or silk in MOS areas

6. Maintain relative humidity above 50 percent if practical

7. For CI-CGA packages, use specific tray to take care of the highest height of the package

compared with the normal CBGA

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9.4 Clock Relationship Choices

The PC755’s PLL is configured by the PLL_CFG[0-3] signals. For a given SYSCLK (bus) fre-

quency, the PLL configuration signals set the internal CPU and VCO frequency of operation.

The PLL configuration for the PC755 is shown in Figure 10-2 for example frequencies.

Notes: 1. PLL_CFG[0:3] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO

frequencies which are not useful, not supported, or not tested for by the PC755; see ”Clock AC Specifications” on page 25

for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode

is set for 1:1 mode operation. This mode is intended for factory use and emulator tool use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL off mode, no clocking occurs inside the PC755 regardless of the SYSCLK input.

Table 9-1. PC755 Microprocessor PLL Configuration

PLL_CFG [0-3]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-Core

Multiplier

Core-to VCO

Multiplier

Bus 33

MHz

Bus 50

MHz

Bus 66

MHz

Bus 75

MHz

Bus 80

MHz

Bus 100

MHz

0100 2x 2x -----

200

(400)

1000 3x 2x - - 200

(400)

225

(450)

240

(480)

300

(600)

1110 3.5x 2x - - 233

(466)

263

(525)

280

(560)

350

(700)

1010 4x 2x - 200

(400)

266

(533)

300

(600)

320

(640)

400

(800)

0111 4.5x 2x - 225

(450)

300

(600)

338

(675)

360

(720) -

1011 5x 2x - 250

(500)

333

(666)

375

(750)

400

(800) -

1001 5.5x 2x - 275

(550)

366

5733°---

1101 6x 2x 200

(400)

300

(600)

400

(800) ---

0101 6.5x 2x 216

(433)

325

(650) ----

0010 7x 2x 233

(466)

350

(700) ----

0001 7.5x 2x 250

(500)

375

(750) ----

1100 8x 2x 266

(533)

400

(800) ----

0110 10x 2x 333

(666) -----

0011 PLL off/bypass PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied

1111 PLL off PLL off, no core clocking occurs

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The PC755 generates the clock for the external L2 synchronous data SRAMs by dividing the

core clock frequency of the PC755. The divided-down clock is then phase-adjusted by an on-

chip delay-lock-loop (DLL) circuit and should be routed from the PC755 to the external RAMs. A

separate clock output, L2SYNC_OUT is sent out half the distance to the SRAMs and then

returned as an input to the DLL on pin L2SYNC_IN so that the rising-edge of the clock as seen

at the external RAMs can be aligned to the clocking of the internal latches in the L2 bus

interface.

The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR

external RAMs, the frequency of the PC755 core, and the phase adjustment range that the L2

DLL supports. Figure 8-9 shows various example L2 clock frequencies that can be obtained for

a given set of core frequencies. The minimum L2 frequency target is 80 MHz.

Note: The core and L2 frequencies are for reference only. Some examples may represent core or L2 fre-

quencies which are not useful, not supported, or not tested for by the PC755; see ”L2 Clock AC

Specifications” on page 28 for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for

L2CLK frequencies less than 110 MHz.

Table 9-2. Sample Core-to-L2 Frequencies

Core Frequency in MHz 1 1.5 2 2.5 3

250 250 166 125 100 83

266 266 177 133 106 89

275 275 183 138 110 92

300 300 200 150 120 100

325 325 217 163 130 108

333 333 222 167 133 111

350 350 233 175 140 117

366 366 244 183 146 122

375 375 250 188 150 125

400 400 266 200 160 133

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10. System Design Information

10.1 PLL Power Supply Filtering

The AVDD and L2AVDD power signals are provided on the PC755 to provide power to the clock

generation phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability

of the internal clock, the power supplied to the AVDD input signal should be filtered of any noise in

the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown

in Figure 10-2 using surface mount capacitors with minimum Effective Series Inductance (ESL)

is recommended. Consistent with the recommendations of Dr. Howard Johnson in High Speed

Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of

equal value are recommended over a single large value capacitor.

The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from

nearby circuits. An identical but separate circuit should be placed as close as possible to the

L2AVDD pin. It is often possible to route directly from the capacitors to the AVDD pin, which is on

the periphery of the 360 BGA footprint, without the inductance of vias. The L2AVDD pin may be

more difficult to route but is proportionately less critical.

Figure 10-1. PLL Power Supply Filter Circuit

10.2 Power Supply Voltage Sequencing

The notes in Figure 10-3 contain cautions about the sequencing of the external bus voltages and

core voltage of the PC755 (when they are different). These cautions are necessary for the long

term reliability of the part. If they are violated, the ESD (Electrostatic Discharge) protection

diodes will be forward biased and excessive current can flow through these diodes. If the system

power supply design does not control the voltage sequencing, the circuit of Figure 10-3 can be

added to meet these requirements. The MUR420 Schottky diodes of Figure 10-3 control the

maximum potential difference between the external bus and core power supplies on power-up

and the 1N5820 diodes regulate the maximum potential difference on power-down.

Figure 10-2. Example Voltage Sequencing Circuit

VDD AVDD (or L2AVDD)

10 Ω

2.2 µF 2.2 µF

GND

Low ESL Surface Mount Capacitors

3.3V 2.0V

MURS320

1N5820

MURS320

1N5820

2138F–HIREL–06/05

PC755/745

10.3 Decoupling Recommendations

Due to the PC755’s dynamic power management feature, large address and data buses, and

high operating frequencies, the PC755 can generate transient power surges and high frequency

noise in its power supply, especially while driving large capacitive loads. This noise must be pre-

vented from reaching other components in the PC755 system, and the PC755 itself requires a

clean, tightly regulated source of power. Therefore, it is recommended that the system designer

place at least one decoupling capacitor at each VDD, OVDD, and L2OVDD pin of the PC755. It is

also recommended that these decoupling capacitors receive their power from separate VDD,

(L2)OVDD and GND power planes in the PCB, utilizing short traces to minimize inductance.

These capacitors should have a value of 0.01 µF or 0.1 µF. Only ceramic SMT (surface mount

technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 ori-

entations where connections are made along the length of the part.

In addition, it is recommended that there be several bulk storage capacitors distributed around

the PCB, feeding the VDD, L2OVDD, and OV vplanes, to enable quick recharging of the smaller

chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rat-

ing to ensure the quick response time necessary. They should also be connected to the power

and ground planes through two vias to minimize inductance. Suggested bulk capacitors – 100-

330 µF (AVX TPS tantalum or Sanyo OSCON).

10.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropri-

ate signal level through a resistor. Unused active low inputs should be tied to OVDD. Unused

active high inputs should be connected to GND. All NC (no-connect) signals must remain

unconnected.

Power and ground connections must be made to all external VDD, OVDD, L2OVDD, and GND pins

of the PC755.

10.5 Output Buffer DC Impedance

The PC755 60x and L2 I/O drivers are characterized over process, voltage, and temperature. To

measure Z0, an external resistor is connected from the chip pad to (L2)OVDD or GND. Then, the

value of each resistor is varied until the pad voltage is (L2)OVDD/2 (See Figure 10-4).

The output impedance is the average of two components, the resistances of the pull-up and pull-

down devices. When Data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the

voltage at the pad equals (L2)OVDD/2. RN then becomes the resistance of the pull-down devices.

When Data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the

pad equals (L2)OVDD/2. RP then becomes the resistance of the pull-up devices.

NO TAG describes the driver impedance measurement circuit described above.

2138F–HIREL–06/05

PC755/745

Figure 10-3. Driver Impedance Measurement Circuit

Alternately, the following is another method to determine the output impedance of the PC755. A

voltage source, Vforce, is connected to the output of the PC755 as in Figure 10-4. Data is held

low, the voltage source is set to a value that is equal to (L2)OVDD/2 and the current sourced by

Vforce is measured. The voltage drop across the pull-down device, which is equal to (L2)OVDD/2,

is divided by the measured current to determine the output impedance of the pull-down device,

RN. Similarly, the impedance of the pull-up device is determined by dividing the voltage drop of

the pull-up, (L2)OVDD/2, by the current sank by the pull-up when the data is high and Vforce is

equal to (L2)OVDD/2. This method can be employed with either empirical data from a test set up

or with data from simulation models, such as IBIS.

RP and RN are designed to be close to each other in value. Then Z0 = (RP + RN)/2.

Figure 10-4 describes the alternate driver impedance measurement circuit.

Figure 10-4. Alternate Driver Impedance Measurement Circuit

(L2)OVDD

OGND

Pad

Data

SW1

SW2

(L2)OVDD

BGA

Data

OGND

Vforce

2138F–HIREL–06/05

PC755/745

Table 10-1 summarizes the signal impedance results. The driver impedance values were char-

acterized at 0°C, 65°C, and 105°C. The impedance increases with junction temperature and is

relatively unaffected by bus voltage.

10.6 Pull-up Resistor Requirements

The PC755 requires pull-up resistors (1 kΩ – 5 kΩ) on several control pins of the bus interface to

maintain the control signals in the negated state after they have been actively negated and

released by the processor or other bus masters. These pins are TS, ABB, AACK, ARTRY, DBB,

DBWO, TA, TEA, and DBDIS. DRTRY should also be connected to a pull-up resistor (1 kΩ – 5

kΩ) if it will be used by the system; otherwise, this signal should be connected to HRESET to

select NO-DRTRY mode.

Three test pins also require pull-up resistors (100Ω – 1 kΩ). These pins are L1_TSTCLK,

L2_TSTCLK, and LSSD_MODE. These signals are for factory use only and must be pulled up to

OVDD for normal machine operation.

In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 kΩ – 5

kΩ) if it is used by the system.

During inactive periods on the bus, the address and transfer attributes may not be driven by any

master and may, therefore, float in the high-impedance state for relatively long periods of time.

Since the processor must continually monitor these signals for snooping, this float condition may

cause additional power draw by the input receivers on the processor or by other receivers in the

system. These signals can be pulled up through weak (10 kΩ) pull-up resistors by the system or

may be otherwise driven by the system during inactive periods of the bus to avoid this additional

power draw, but address bus pull-up resistors are not necessary for proper device operation.

The snooped address and transfer attribute inputs are:

A[0:31], AP[0:3], TT[0:4], TBST, and GBL.

The data bus input receivers are normally turned off when no read operation is in progress and,

therefore, do not require pull-up resistors on the bus. Other data bus receivers in the system,

however, may require pull-ups, or that those signals be otherwise driven by the system during

inactive periods by the system. The data bus signals are: DH[0:31], DL[0:31], and DP[0:7].

If 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be

disabled, and their outputs will drive logic zeros when they would otherwise normally be driven.

For this mode, these pins do not require pull-up resistors, and should be left unconnected by the

system to minimize possible output switching.

If address or data parity is not used by the system, and the respective parity checking is disabled

through HID0, the input receivers for those pins are disabled, and those pins do not require pull-

up resistors and should be left unconnected by the system. If all parity generation is disabled

through HID0, then all parity checking should also be disabled through HID0, and all parity pins

may be left unconnected by the system.

Table 10-1. Impedance Characteristics. VDD = 2.0V, OVDD = 3.3V, Tc = 0 - 105°C

Impedance Processor bus L2 bus Symbol Unit

RN 25-36 25-36 Z0W

RP 26-39 26-39 Z0W

2138F–HIREL–06/05

PC755/745

11. Package Mechanical Data

The following sections provide the package parameters and mechanical dimensions for the

PC745, 255 PBGA package as well as the PC755, 360 CBGA and PBGA packages. While both

the PC755 plastic and the ceramic packages are described here, both packages are not guaran-

teed to be available at the same time. All new designs should allow for either ceramic or plastic

BGA packages for this device. For more information on designing a common footprint for both

plastic and ceramic package types, please contact your local Atmel sales office.

11.1 Package Parameters for the PC745

The package parameters are as provided in the following list. The package type is 21 × 21 mm,

255-lead plastic ball grid array (PBGA).

Table 11-1. Package Parameters

Parameter HiTCE PBGA

Package outline 21 × 21 mm 21 × 21 mm

Interconnects 255 (16 × 16 ball array – 1) 255 (16 × 16 ball array – 1)

Pitch 1.27 mm (50 mil) 1.27 mm (50 mil)

Minimum module height 2.42 2.25 mm

Maximum module height 3.08 2.80 mm

Ball diameter (typical) 0.89 mm (35 mil) 0.75 mm (29.5 mil)

2138F–HIREL–06/05

PC755/745

11.1.1 Mechanical Dimensions of the PC745 HiTCE Package

Figure 11-2 provides the mechanical dimensions and bottom surface nomenclature of the

PC745, 255 HiTCE package.

Figure 11-1. Mechanical Dimensions and Bottom Surface Nomenclature of the PC745 HiTCE

255X

12345678910111213141516

A0.3

C0.15

Dim Min Max

A2.42 3.08

A1 0.8 1.0

A2 0.90 1.14

A3 0.60

b0.82 0.93

e1.27 BSC

21.00 BSC

7.87

6.75

Millimeters

0.2

A1 CORNER

0.2

0.2 C

Notes:

1. Dimensioning and tolerancing per

ASME Y14.5M, 1994

2. Dimensions in millimeters

3. Top side A1 corner index is a metalized

feature with various shapes. Bottom side

A1 corner is designated with a ball missing

from the array

4. Capacitor Pads may be unpopulated

2138F–HIREL–06/05

PC755/745

11.1.2 Mechanical Dimensions of the PC745 PBGA Package

Figure 11-2 provides the mechanical dimensions and bottom surface nomenclature of the

PC745, 255 PBGA package.

Figure 11-2. Mechanical Dimensions and Bottom Surface Nomenclature of the PC745 PBGA

11.2 Package Parameter for the PC755

The package parameters are as provided in the following list. The package type is 25 x 25 mm,

360-lead plastic ball grid array (PBGA).

255X

12345678910111213141516

A0.3

C0.15

Dim Min Max

A2.25 2.80

A1 0.50 0.70

A2 1.00 1.20

A3 0.60

b0.60 0.90

e1.27 BSC

21.00 BSC

7.87

6.75

Millimeters

0.2

A1 CORNER

0.2

0.2 C

Notes:

1. Dimensioning and tolerancing per

ASME Y14.5M, 1994

2. Dimensions in millimeters

3. Top side A1 corner index is a metalized

feature with various shapes. Bottom side

A1 corner is designated with a ball missing

from the array

4. Capacitor Pads may be unpopulated

Table 11-2. Package Parameters

Parameter HiTCE-CBGA PBGA

Package Outline 25 mm × 25 mm 25 mm × 25 mm

Interconnects 360 (19 x 19 ball array – 1) 360 (19 x 19 ball array – 1

Pitch 1.27 mm (50 mil) 1.27 mm (50 mil)

Minimum module height 2,65 mm 2.22 mm

Maximum module height 3,2 mm 2.77 mm

Ball diameter 0,89 mm (35 mil) 0.75 mm (29.5 mil)

2138F–HIREL–06/05

PC755/745

11.2.1 Mechanical Dimensions of the PC755 PBGA

Figure 11-3 provides the mechanical dimensions and bottom surface nomenclature of the

PC755, 360 PBGA package.

Figure 11-3. Mechanical Dimensions and Bottom Surface Nomenclature of the PC755 PBGA

Notes:

1. Dimensioning and tolerancing per

ASME Y14.5M, 1994

2. Dimensions in millimeters

3. Top side A1 corner index is a metalized

feature with various shapes. Bottom side

A1 corner is designated with a ball missing

from the array

0.2

360X

A1 CORNER

0.2

12345678910111213141516

0.2 C

171819

Millimeters

DIM Min Max

A2.22 2.77

A1 0.50 0.70

A2 1.00 1.20

A3 —0.60

b0.60 0.90

D25.00 BSC

D1 6.75

E25.00 BSC

E1 7.87

e1.27 BSC

BC A0.3

C0.15

2138F–HIREL–06/05

PC755/745

11.2.2 Mechanical Dimensions of the PC755 CBGA Package

Figure 11-5 provides the mechanical dimensions and bottom surface nomenclature of the

PC755, 360 CBGA package.

Figure 11-4. Mechanical Dimensions and Bottom Surface Nomenclature of PC755 (CBGA)

360X

12345678910111213141516

A0.3

0.15

171819

Millimeters

DIM Min Max

A2.65 3.20

A1 0.79 0.99

A2 1.10 1.30

A3 —0.60

b0.82 0.93

D25.00 BSC

D1 6.75

E25.00 BSC

E1 7.87

e1.27 BSC

0.2

A1 CORNER

0.2

0.15

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M, 1994

2. Dimensions in millimeters

3. Top side A1 corner index is a metalized feature with various

shapes. Bottom side A1 corner is designated with a ball

missing from the array

2138F–HIREL–06/05

PC755/745

11.2.3 Mechanical Dimensions of the PC755 HiTCE Package

Figure 11-5 provides the mechanical dimensions and bottom surface nomenclature of the

PC755, 360 HiTCE package.

Figure 11-5. Mechanical Dimensions and Bottom Surface Nomenclature of PC755 (HiTCE)

360X

12345678910111213141516

A0.3

0.15

0.15 C

171819

Millimeters

DIM Min Max

A2.65 3.24

A1 0.79 0.99

A2 1.10 1.30

A3 —0.60

b0.82 0.93

D25.00 BSC

D1 6.75

E25.00 BSC

E1 7.87

e1.27 BSC

0.2

A1 CORNER

0.2

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M, 1994

2. Dimensions in millimeters

3. Top side A1 corner index is a metalized feature with various

shapes. Bottom side A1 corner is designated with a ball

missing from the array

2138F–HIREL–06/05

PC755/745

11.2.4 Mechanical Dimensions of the PC755 CI-CGA Package

Figure 11-6 provides the mechanical dimensions and bottom surface nomenclature of PC755,

360 CI-CGA package.

Figure 11-6. Mechanical Dimensions and Bottom Surface Nomenclature of PC755 (CI-CGA)

360X

12345678910111213141516

A0.3

0.15

171819

Millimeters

DIM Min Max

A4.08 BSC

A2 1.10 1.30

1.545 1.695

A3 —0.60

b0.79 0.990

D25.00 BSC

D1 6.75

E25.00 BSC

E1 7.87

0.2

A1 CORNER

0.2

A4 0.82 0.9

A5 0.14 BSC

A6 0.25 0.35

1.27 BSC

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M, 1994

2. Dimensions in millimeters

3. Top side A1 corner index is a metalized feature with various

shapes. Bottom side A1 corner is designated with a ball

missing from the array

B0.15

2138F–HIREL–06/05

PC755/745

12. Ordering Information

Note: For availability of different versions, contact your Atmel sales office.

PCX745

PCX755 M ZF U 300 L x

Type

Package:

ZF: FC-PBGA

Screening Level(1)

U: Upscreening Test

Revision Level(1)

E: Rev. 2.8

Temperature Range: Tj

M: -55 C, +125 C

V: -40 C, +110 C

Bus divider

(to be confirmed)

L: Any valid PLL configuration

Max internal processor speed

300: 300 MHz

350: 350 MHz

366: 366 MHz

400: 400 MHz

Type

Package:

G: CBGA

GS: CI-CGA

GH: HiTCE

Screening Level(1)

U: Upscreening Test

Blank: Standard

Revision Level(1)

E: Rev. 2.8

Temperature Range: Tj

M: -55 C, +125 C

V: -40 C, +110 C

Bus divider

(to be confirmed)

L: Any valid PLL configuration

Max internal processor speed

300: 300 MHz

350: 350 MHz

366: 366 MHz

400: 400 MHz

PC745

PC755 M GH U 300 L x

B for 300, 350, 366 MHz

C for 400 MHz

B for 300, 350, 366 MHz

C for 400 MHz

2138F–HIREL–06/05

PC755/745

13. Definitions

13.1 Life Support Applications

These products are not designed for use in life support appliances, devices, or systems where

malfunction of these products can reasonably be expected to result in personal injury. Atmel

customers using or selling these products for use in such applications do so at their own risk and

agree to fully indemnity Atmel for any damages resulting from such improper use or sale.

13.2 Differences with Commercial Part

14. Document Revision History

Table 19 provides a revision history for this hardware specification.

Commercial part Military part

Temperature range Tj = 0 to 105°CT

j = -55°C to 125°C

Table 14-1. Revision History

Revision

Number Date Substantive Change(s)

2138F 05/2005

Added HiTCE package for PowerPC 745

Removed phrase "for the ceramic ball grid array (CBGA) package" from Section 6.1.3 on page 19;

this information applies to devices in all packages

Figure 8-14: updated COP Connector Diagram to recommend a weak pull-up resistor on TCK

2138E 10/2004 Product specification release subsequent to product qualification

Motorola changed to Freescale

2138D 06/2003 Preliminary β-site

2138F–HIREL–06/05

PC755/745

Table of Contents

Features .................................................................................................... 1

Description ............................................................................................... 1

Screening.................................................................................................. 2

1 General Description ................................................................................. 2

1.1 Simplified Block Diagram .........................................................................................2

1.2 General Parameters .................................................................................................3

1.3 Features ...................................................................................................................3

2 Pin Assignments ...................................................................................... 6

2.1 Pinout Listings ..........................................................................................................8

3 Signal Description ................................................................................. 13

4 Detailed Specifications .......................................................................... 14

5 Applicable Documents .......................................................................... 14

5.1 Design and Construction ........................................................................................14

6 Thermal Characteristics ........................................................................ 17

6.1 Package Characteristics .........................................................................................17

7 Power consideration .............................................................................. 22

7.1 Power management ...............................................................................................22

7.2 Power Dissipation ...................................................................................................23

8 Electrical Characteristics ...................................................................... 24

8.1 Static Characteristics ..............................................................................................24

8.2 Dynamic Characteristics .........................................................................................24

9 Preparation for Delivery ........................................................................ 38

9.1 Packaging ...............................................................................................................38

9.2 Certificate of Compliance .......................................................................................38

9.3 Handling .................................................................................................................38

9.4 Clock Relationship Choices ....................................................................................39

10 System Design Information .................................................................. 41

10.1 PLL Power Supply Filtering ..................................................................................41

10.2 Power Supply Voltage Sequencing ......................................................................41

10.3 Decoupling Recommendations ............................................................................42

2138F–HIREL–06/05

PC755/745

10.4 Connection Recommendations ............................................................................42

10.5 Output Buffer DC Impedance ...............................................................................42

10.6 Pull-up Resistor Requirements .............................................................................44

11 Package Mechanical Data ..................................................................... 45

11.1 Package Parameters for the PC745 .....................................................................45

11.2 Package Parameter for the PC755 ......................................................................47

12 Ordering Information ............................................................................. 52

13 Definitions .............................................................................................. 53

13.1 Life Support Applications ......................................................................................53

13.2 Differences with Commercial Part ........................................................................53

14 Document Revision History .................................................................. 53

Printed on recycled paper.

2138F–HIREL–06/05 xM

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Freescale, Inc. AltiVec™ is a trademark of Freescale, Inc. Other terms and product names may be trademarks of others.

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