© Semiconductor Components Industries, LLC, 2010
December, 2010 − Rev. 0
1Publication Order Number:
NTMFS4827NE/D
NTMFS4827NE
Power MOSFET
30 V, 58.5 A, Single N−Channel, SO−8 FL
Features
•Low RDS(on) to Minimize Conduction Losses
•Low Capacitance to Minimize Driver Losses
•Optimized Gate Charge to Minimize Switching Losses
•Dual Sided Cooling Capability
•These are Pb−Free Device
Applications
•CPU Power Delivery
•DC−DC Converters
•High Side Switching
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS 30 V
Gate−to−Source Voltage VGS ±20 V
Continuous Drain
Current RqJA
(Note 1)
Steady
State
TA = 25°CID13.8 A
TA = 85°C 10
Power Dissipation
RqJA (Note 1)
TA = 25°C PD2.14 W
Continuous Drain
Current RqJA v
10 sec
TA = 25°CID22.4 A
TA = 85°C 16.1
Power Dissipation
RqJA, t v 10 sec
TA = 25°C PD5.61 W
Continuous Drain
Current RqJA
(Note 2)
TA = 25°CID8.8 A
TA = 85°C 6.4
Power Dissipation
RqJA (Note 2)
TA = 25°C PD0.87 W
Continuous Drain
Current RqJC
(Note 1)
TC = 25°CID58.5 A
TC = 85°C 42.3
Power Dissipation
RqJC (Note 1)
TC = 25°C PD38.5 W
Pulsed Drain
Current
tp=10msTA = 25°C IDM 117 A
Current limited by package TA = 25°C IDmaxpkg 100 A
Operating Junction and Storage
Temperature
TJ,
TSTG
−40 to
+150
°C
Source Current (Body Diode) IS38.5 A
Drain to Source dV/dt dV/dt 6 V/ns
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 50 V, VGS = 10 V,
IL = 24 Apk, L = 0.3 mH, RG = 25 W)
EAS 86 mJ
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
MARKING
DIAGRAM
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A = Assembly Location
Y = Year
WW = Work Week
G= Pb−Free Package
4827NE
AYWWG
G
1
V(BR)DSS RDS(ON) MAX ID MAX
30 V 6.95 mW @ 10 V 58.5 A
10.8 mW @ 4.5 V
G (4)
S (1,2,3)
N−CHANNEL MOSFET
D (5,6)
Device Package Shipping†
ORDERING INFORMATION
NTMFS4827NET1G SO−8FL
(Pb−Free)
1500 /
Tape & Reel
NTMFS4827NET3G SO−8FL
(Pb−Free)
5000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
S
S
S
G
D
D
D
D
*For additional information on our Pb−Free strategy
and soldering details, please download the ON
Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
(Note: Microdot may be in either location)
46.9 A
NTMFS4827NE
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2
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Symbol Value Unit
Junction−to−Case (Drain) RqJC 3.25
°C/W
Junction−to−Ambient – Steady State (Note 1) RqJA 58.3
Junction−to−Ambient – Steady State (Note 2) RqJA 144.1
Junction−to−Ambient − t v 10 sec RqJA 22.3
Junction−to−To p RqJT 9.8
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA30 V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
25 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V,
VDS = 24 V
TJ = 25 °C 1
mA
TJ = 125°C 10
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V ±100 nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250 mA1.45 1.8 2.5 V
Negative Threshold Temperature Coefficient VGS(TH)/TJmV/°C
Drain−to−Source On Resistance RDS(on) VGS = 10 V to
11.5 V
ID = 30 A 5.3 6.95
mW
ID = 15 A 5.2
VGS = 4.5 V ID = 30 A 8.6 10.8
ID = 15 A 8.4
Forward Transconductance gFS VDS = 1.5 V, ID = 30 A 54 S
CHARGES AND CAPACITANCES
Input Capacitance CISS
VGS = 0 V, f = 1 MHz, VDS = 12 V
1400
pF
Output Capacitance COSS 282
Reverse Transfer Capacitance CRSS 136
Total Gate Charge QG(TOT)
VGS = 4.5 V, VDS = 15 V; ID = 30 A
10.7 16
nC
Threshold Gate Charge QG(TH) 1.4
Gate−to−Source Charge QGS 4.1
Gate−to−Drain Charge QGD 3.8
Total Gate Charge QG(TOT) VGS = 11.5 V, VDS = 15 V,
ID = 30 A
25 nC
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time td(ON)
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
RG = 3.0 W
13.3
ns
Rise Time tr38
Turn−Off Delay Time td(OFF) 16.6
Fall Time tf3.8
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
NTMFS4827NE
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3
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter UnitMaxTypMinTest ConditionSymbol
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time td(ON)
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
8.2
ns
Rise Time tr20
Turn−Off Delay Time td(OFF) 23
Fall Time tf3.1
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V,
IS = 30 A
TJ = 25°C 0.85 1.0
V
TJ = 125°C 0.74
Reverse Recovery Time tRR
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
11
ns
Charge Time ta7.5
Discharge Time tb3.5
Reverse Recovery Charge QRR 2.0 nC
PACKAGE PARASITIC VALUES
Source Inductance LS
TA = 25°C
1.3 nH
Drain Inductance LD0.005
Gate Inductance LG1.84
Gate Resistance RG0.5 1.1 2.0 W
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
NTMFS4827NE
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4
TYPICAL PERFORMANCE CURVES
0
10
20
30
40
50
60
70
80
90
0123456
Figure 1. On−Region Characteristics
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
10 V
TJ = 25°C
VGS = 4.5 V
5.0 V 4.0 V
3.8 V
3.6 V
3.4 V
3.2 V
3.0 V
2.8 V
2.6 V 0
10
20
30
40
50
60
70
80
90
100
0123456
ID, DRAIN CURRENT (A)
Figure 2. Transfer Characteristics
VGS, GATE−TO−SOURCE VOLTAGE (V)
VDS ≥ 10 V
TJ = 25°C
TJ = 125°C
TJ = −55°C
0
0.01
0.02
0.03
0.04
246810
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 30 A
TJ = 25°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0.002
0.0045
0.007
0.0095
0.012
0.0145
0.017
0.0195
30 40 50 60 70 80 90 100
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
ID, DRAIN CURRENT (A)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VGS = 4.5 V
VGS = 11.5 V
TJ = 25°C
0.6
0.8
1
1.2
1.4
1.6
1.8
−50 −25 0 25 50 75 100 125 150
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
ID = 30 A
VGS = 10 V
10
100
1000
10000
5 1015202530
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
IDSS, LEAKAGE (nA)
TJ = 150°C
VGS = 0 V
TJ = 125°C
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5
TYPICAL PERFORMANCE CURVES
0
200
400
600
800
1000
1200
1400
1600
1800
2000
0 5 10 15 20 25 30
Figure 7. Capacitance Variation
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
TJ = 25°C
Coss
Ciss
Crss
0
2
4
6
8
10
12
0 4 8 12162024
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Qg, TOTAL GATE CHARGE (nC)
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 30 A
TJ = 25°C
QT
VGS
Qgd
Qgs
1
10
100
1000
1 10 100
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
RG, GATE RESISTANCE (W)
t, TIME (ns)
VDD = 15 V
ID = 30 A
VGS = 11.5 V
tf
tr
td(off)
td(on)
0
5
10
15
20
25
30
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 10. Diode Forward Voltage vs. Current
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
IS, SOURCE CURRENT (A)
VGS = 0 V
TJ = 25°C
0.1
1
10
100
1000
0.1 1 10 100
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
10 ms
100 ms
1 ms
10 ms
dc
VGS = 20 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
0
10
20
30
40
50
60
70
80
90
100
25 50 75 100 125 150
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
TJ, STARTING JUNCTION TEMPERATURE(°C)
EAS, SINGLE PULSE DRAIN−TO−
SOURCE AVALANCHE ENERGY (mJ)
ID = 24 A
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6
TYPICAL PERFORMANCE CURVES
0
10
20
30
40
50
60
70
80
90
0 102030405060708090
Figure 13. gFS vs. Drain Current
DRAIN CURRENT (A)
gFS (S)
VDS = 1.5 V
0.1
1
10
100
0.1 1 10 100 1000 10000
Figure 14. Avalanche Characteristics
PULSE WIDTH (ms)
Id (A)
125°C
100°C25°C
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7
PACKAGE DIMENSIONS
DFN6 5x6, 1.27P (SO8 FL)
CASE 488AA−01
ISSUE C
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
M3.00 3.40
q0 −−−
_
3.80
12
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
1234
56
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D1
E1 q
D
E
2
2
B
A
0.20 C
0.20 C
2 X
2 X
DIM MIN NOM
MILLIMETERS
A0.90 1.00
A1 0.00 −−−
b0.33 0.41
c0.23 0.28
D5.15 BSC
D1 4.50 4.90
D2 3.50 −−−
E6.15 BSC
E1 5.50 5.80
E2 3.45 −−−
e1.27 BSC
G0.51 0.61
K0.51 −−−
L0.51 0.61
L1 0.05 0.17
A
0.10 C
0.10 C
DETAIL A
14
6
L1
e/2
8X
D2
G
E2
K
b
A0.10 BC
0.05 cL
DETAIL A
A1
e
3 X
c
4 X
C
SEATING
PLANE
5
MAX
1.10
0.05
0.51
0.33
5.10
4.22
6.10
4.30
0.71
−−−
0.71
0.20
M
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1.270
2X
0.750
1.000
0.905
0.475
4.530
1.530
4.560
0.495
3.200
1.330
0.965
2X
2X
3X 4X
4X
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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