HY5DU281622ET-4 - Hynix Semiconductor, Inc.

HY5DU281622ET

128M(8Mx16) GDDR SDRAM

HY5DU281622ET

This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any respon-

sibility for use of circuits described. No patent licenses are implied.

Rev. 0.5 / Jan. 2005 1

Rev. 0.5 / Jan. 2005 2

HY5DU281622ET

Revision History

Revision No. History Draft Date Remark

0.1 Defined target spec. July 2003

0.2 1) Insert Overshoot/Undershoot Specification

2) Insert tDSS/tDSH Parameter Oct. 2003

0.3 tPDEX value Change Mar. 2004

0.4 tRC_APCG changed to 12 clock from 11 clock at 166Mhz speed bin Oct. 2004

0.5 166Mhz speed bin delete, AC parameter change (tRC_APCG at 200Mhz) Jan. 2005

Rev. 0.5 / Jan. 2005 3

HY5DU281622ET

DESCRIPTION

The Hynix HY5DU281622ET is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for

the point-to-point applications which require high densities and high bandwidth.

The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the

clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,

Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-

nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible

with SSTL_2.

FEATURES

• 2.8V +/- 0.1V VDD and VDDQ power supply

supports 400/375/350/333/300MHz

•2.5V +/- 5% VDD and VDDQ power supply

supports 275/250/200/166MHz

•All inputs and outputs are compatible with SSTL_2

interface

• JEDEC Standard 400 mil x 875 mil 66 Pin TSOP II,

with 0.65mm pin pitch

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous - data transaction aligned to

bidirectional data strobe (UDQS,LDQS)

• Data outputs on DQS edges when read (edged DQ)

Data inputs on DQS centers when write (centered

DQ)

• Data(DQ) and Write masks(DM) latched on the both

rising and falling edges of the data strobe

•All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

• Write mask byte controls by DM (UDM,LDM)

• Programmable /CAS Latency 5, 4 and 3 are sup-

ported

• Programmable Burst Length 2, 4 and 8 with both

sequential and interleave mode

• Internal 4 bank operation with single pulsed /RAS

• tRAS Lock-Out function are supported

• Auto refresh and self refresh are supported

• 4096 refresh cycles / 32ms

• Full strength, Half strength and Weak Impedance

driver options controlled by EMRS

ORDERING INFORMATION

Part No. Power

Supply

Clock

Frequency Max Data Rate interface Package

HY5DU281622ET-25

VDD/VDDQ=2.8V

400MHz 800Mbps/pin

SSTL_2 400 x 875mil 2

66 Pin TSOP II

HY5DU281622ET-26 375MHz 750Mbps/pin

HY5DU281622ET-28 350MHz 700Mbps/pin

HY5DU281622ET-30 333MHz 666Mbps/pin

HY5DU281622ET-33 300MHz 600Mbps/pin

HY5DU281622ET-36

VDD/VDDQ=2.5V

275MHz 550Mbps/pin

HY5DU281622ET-4 250MHz 500Mbps/pin

HY5DU281622ET-5 200MHz 400Mbps/pin

Rev. 0.5 / Jan. 2005 4

HY5DU281622ET

PIN CONFIGURATION (Top View)

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDDQ

LDQS

VDD

LDM

/WE

/CAS

/RAS

/CS

BA0

BA1

A10/AP

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSSQ

UDQS

VREF

VSS

UDM

/CK

CKE

A11

VSS

400mil X 875mil

66pin TSOP -II

0.65mm pin pitch

ROW AND COLUMN ADDRESS TABLE

ITEMS 8Mx16

Organization 2M x 16 x 4banks

Row Address A0 - A11

Column Address A0-A8

Bank Address BA0, BA1

Auto Precharge Flag A10

Refresh 4K

Rev. 0.5 / Jan. 2005 5

HY5DU281622ET

PIN DESCRIPTION

PIN TYPE DESCRIPTION

CK, /CK Input

Clock: CK and /CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output

(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

CKE Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF

REFRESH entry and exit. CKE is asynchronous for output disable. CKE must be main-

tained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and

CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during

SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd

is applied.

/CS Input

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-

mands are masked when CS is registered high. CS provides for external bank selection on

systems with multiple banks. CS is considered part of the command code.

BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-

CHARGE command is being applied.

A0 ~ A11 Input

Address Inputs: Provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A10 is sampled during a precharge command to

determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10

HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The

address inputs also provide the op code during a MODE REGISTER SET command. BA0

and BA1 define which mode register is loaded during the MODE REGISTER SET command

(MRS or EMRS).

/RAS, /CAS, /WE Input Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being

entered.

UDM, LDM Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with that input data during a WRITE access. DM is sampled

on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ

and DQS loading. LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data

on DQ8-Q15

UDQS, L D Q S I / O

Data Strobe: Output with read data, input with write data. Edge aligned with read data,

centered in write data. Used to capture write data. LDQS corresponds to the data on

DQ0-Q7; UDQS corresponds to the data on DQ8-Q15

DQ0 ~ DQ15 I/O Data input / output pin : Data Bus

VDD/VSS Supply Power supply for internal circuits and input buffers.

VDDQ/VSSQ Supply Power supply for output buffers for noise immunity.

VREF Supply Reference voltage for inputs for SSTL interface.

NC NC No connection.

Rev. 0.5 / Jan. 2005 6

HY5DU281622ET

FUNCTIONAL BLOCK DIAGRAM

4Banks x 2Mbit x 16 I/O Double Data Rate Synchronous DRAM

kx‚WaX\„

Bank

Control

Write Data Register

2-bit Prefetch Unit

CLK

CKE

LDM

/WE

/RAS

/CAS

/CS

/CLK

Mode

Row

Decoder

Sense AMP

2Mx16/Bank0

2Mx16/Bank3

2Mx16/Bank2

2Mx16/Bank1

2-bit Prefetch Unit

Output Buffer

Input Buffer

Data Strobe

Transmitter

DLL

Block

A0~A11

Column Address

Counter

Column Decoder

Data Strobe

Receiver

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h‹‹™Œšš

iœ••Œ™

jsr

Vjsr

skxzSG|kxz

jsr†kss

skxz

|kxz

t–‹Œ

yŒŽ•š›Œ™

UDM

BA0, BA1

Rev. 0.5 / Jan. 2005 7

HY5DU281622ET

SIMPLIFIED COMMAND TRUTH TABLE

Command CKEn-1 CKEn CS RAS CAS WE ADDR A10/

AP BA Note

Extended Mode Register SetH X LLLL OP code 1,2

Mode Register Set H X LLLL OP code 1,2

Device Deselect

HXXX

No Operation LHHH

Bank Active H X L L H H RA V 1

Read

H X LHLHCA

Read with Autoprecharge H1,3

Write

HXLHLLCA

Write with Autoprecharge H1,4

Precharge All Banks

HXLLHLX

HX1,5

Precharge selected Bank LV1

Read Burst Stop H X L H H L X 1

Auto Refresh H HLLLH X 1

Self Refresh

Entry H L LLLH

Exit L H

HXXX

LHHH

Precharge Power

Down Mode

Entry H L

HXXX

LHHH 1

Exit L H

HXXX 1

LHHH 1

Active Power

Down Mode

Entry H L

HXXX

LVVV 1

Exit L H X 1

Note :

1. UDM, LDM states are Don’t Care. Refer to below Write Mask Truth Table.(note 6)

2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before

entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from

Prechagre command.

3. If a Read with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented

to activate bank until CK(n+BL/2+tRP).

4. If a Write with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented

to activate bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery

Time(tWR) is needed to guarantee that the last data have been completely written.

5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.

6. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of

VIHmin ~ VILmax

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

Rev. 0.5 / Jan. 2005 8

HY5DU281622ET

WRITE MASK TRUTH TABLE

Function CKEn-1 CKEn /CS, /RAS,

/CAS, /WE DM ADDR A8/

AP BA Note

Data Write H X X L X 1,2,3

Data-In Mask H X X H X 1,2,3

Note :

1. Write Mask command masks burst write data with reference to UDQS/LDQS and it is not related with read data.

2. LDM corresponds to the data on DQ0-Q7 and UDM corresponds to the data on DQ8-Q15

3. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of

VIHmin ~ VILmax

Rev. 0.5 / Jan. 2005 9

HY5DU281622ET

OPERATION COMMAND TRUTH TABLE - I

Current

State /CS /RAS /CAS /WE Address Command Action

IDLE

HXXX X DSEL NOP or power down3

LHHH X NOP NOP or power down3

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP ILLEGAL4

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4

L L H H BA, RA ACT Row Activation

LLHL BA, AP PRE/PALL NOP

LLLH X AREF/SREF Auto Refresh or Self Refresh5

L L L L OPCODE MRS Mode Register Set

ROW

ACTIVE

HXXX X DSEL NOP

LHHH X NOP NOP

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP Begin read : optional AP6

L H L L BA, CA, AP WRITE/WRITEAP Begin write : optional AP6

LLHHBA, RA ACT ILLEGAL4

LLHL BA, AP PRE/PALL Precharge7

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

READ

H X X X X DSEL Continue burst to end

L H H H X NOP Continue burst to end

L H H L X BST Terminate burst

L H L H BA, CA, AP READ/READAP Term burst, new read:optional AP8

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

LLHHBA, RA ACT ILLEGAL4

L L H L BA, AP PRE/PALL Term burst, precharge

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

WRITE

H X X X X DSEL Continue burst to end

L H H H X NOP Continue burst to end

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP Term burst, new read:optional AP8

L H L L BA, CA, AP WRITE/WRITEAP Term burst, new write:optional AP

Rev. 0.5 / Jan. 2005 10

HY5DU281622ET

OPERATION COMMAND TRUTH TABLE - II

Current

State /CS /RAS /CAS /WE Address Command Action

WRITE

LLHHBA, RA ACT ILLEGAL4

L L H L BA, AP PRE/PALL Term burst, precharge

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

READ

WITH

AUTOPRE-

CHARGE

H X X X X DSEL Continue burst to end

L H H H X NOP Continue burst to end

LHHL X BST ILLEGAL

LHLHBA, CA, AP READ/READAP ILLEGAL10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL10

LLHHBA, RA ACT ILLEGAL4,10

LLHL BA, AP PRE/PALL ILLEGAL4,10

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

WRITE

AUTOPRE-

CHARGE

H X X X X DSEL Continue burst to end

L H H H X NOP Continue burst to end

LHHL X BST ILLEGAL

LHLHBA, CA, AP READ/READAP ILLEGAL10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL10

LLHHBA, RA ACT ILLEGAL4,10

LLHL BA, AP PRE/PALL ILLEGAL4,10

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

PRE-

CHARGE

H X X X X DSEL NOP-Enter IDLE after tRP

L H H H X NOP NOP-Enter IDLE after tRP

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP ILLEGAL4,10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4,10

LLHHBA, RA ACT ILLEGAL4,10

L L H L BA, AP PRE/PALL NOP-Enter IDLE after tRP

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

Rev. 0.5 / Jan. 2005 11

HY5DU281622ET

OPERATION COMMAND TRUTH TABLE - III

Current

State /CS /RAS /CAS /WE Address Command Action

ROW

ACTIVATING

H X X X X DSEL NOP - Enter ROW ACT after tRCD

L H H H X NOP NOP - Enter ROW ACT after tRCD

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP ILLEGAL4,10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4,10

LLHHBA, RA ACT ILLEGAL4,9,10

LLHL BA, AP PRE/PALL ILLEGAL4,10

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

WRITE

RECOVERING

H X X X X DSEL NOP - Enter ROW ACT after tWR

L H H H X NOP NOP - Enter ROW ACT after tWR

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP ILLEGAL

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

LLHHBA, RA ACT ILLEGAL4,10

LLHL BA, AP PRE/PALL ILLEGAL4,11

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

WRITE

RECOVERING

WITH

AUTOPRE-

CHARGE

H X X X X DSEL NOP - Enter precharge after tDPL

L H H H X NOP NOP - Enter precharge after tDPL

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP ILLEGAL4,8,10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4,10

LLHHBA, RA ACT ILLEGAL4,10

LLHL BA, AP PRE/PALL ILLEGAL4,11

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

REFRESHING

H X X X X DSEL NOP - Enter IDLE after tRC

L H H H X NOP NOP - Enter IDLE after tRC

LHHL X BST ILLEGAL11

L H L H BA, CA, AP READ/READAP ILLEGAL11

Rev. 0.5 / Jan. 2005 12

HY5DU281622ET

OPERATION COMMAND TRUTH TABLE - IV

Note :

1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input, BA - Bank Address, AP - AutoPrecharge Address,

CA - Column Address, RA - Row Address, NOP - NO Operation.(see note 12)

2. All entries assume that CKE was active(high level) during the preceding clock cycle.

3. If both banks are idle and CKE is inactive(low level), then in power down mode.

4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of that

bank.

5. If both banks are idle and CKE is inactive(low level), then self refresh mode.

6. Illegal if tRCD is not met.

7. Illegal if tRAS is not met.

8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

9. Illegal if tRRD is not met.

10. Illegal for single bank, but legal for other banks in multi-bank devices.

11. Illegal for all banks.

12. In here, Don’t Care means logical value only, it doesn’t mean ’Don’t care for DC level of each signals’. DC level should be out of

VIHmin ~ VILmax

Current

State /CS /RAS /CAS /WE Address Command Action

WRITE

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL11

LLHHBA, RA ACT ILLEGAL11

LLHL BA, AP PRE/PALL ILLEGAL11

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

MODE

ACCESSING

H X X X X DSEL NOP - Enter IDLE after tMRD

L H H H X NOP NOP - Enter IDLE after tMRD

LHHL X BST ILLEGAL11

L H L H BA, CA, AP READ/READAP ILLEGAL11

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL11

LLHHBA, RA ACT ILLEGAL11

LLHL BA, AP PRE/PALL ILLEGAL11

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

Rev. 0.5 / Jan. 2005 13

HY5DU281622ET

CKE FUNCTION TRUTH TABLE

Note :

When CKE=L, all DQ and UDQS/LDQS should be in Hi-Z state.

1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.

2. All commands can be stored after 2 clocks from low to high transition of CKE.

3. Illegal, if CK is suspended or stopped during the power down mode.

4. Self refresh can be asserted only from the all banks idle state.

5. Disabling CK may cause malfunction of any banks which are in active state.

Current

State

CKEn-

1CKEn /CS /RAS /CAS /WE /ADD Action

SELF

REFRESH1

H X XXXXX INVALID

L HHXXXXExit self refresh, enter idle after tSREX

L H L H H H X Exit self refresh, enter idle after tSREX

LHLHHLX ILLEGAL

LHLHLXX ILLEGAL

LHLLXXX ILLEGAL

L LXXXXX NOP, continue self refresh

POWER

DOWN2

H X XXXXX INVALID

L HHXXXX Exit power down, enter idle

L H L H H H X Exit power down, enter idle

LHLHHLX ILLEGAL

LHLHLXX ILLEGAL

LHLLXXX ILLEGAL

L LXXXXXNOP, continue power down mode

ALL BANKS

IDLE4

H H X X X X X See operation command truth table

H L LLLHX Enter self refresh

HLHXXXX Exit power down

H L L H H H X Exit power down

HLLHHLX ILLEGAL

HLLHLXX ILLEGAL

HLLLHXX ILLEGAL

HLLLLLX ILLEGAL

L LXXXXX NOP

ANY STATE

OTHER

THAN

ABOVE

H H X X X X X See operation command truth table

H L XXXXX ILLEGAL5

L H XXXXX INVALID

L LXXXXX INVALID

Rev. 0.5 / Jan. 2005 14

HY5DU281622ET

SIMPLIFIED STATE DIAGRAM

MRS SREF

SREX

PDEN

PDEX

ACT

AREF

PDEX

PDEN

BST

READWRITE

WRITE

WRITEAP

READ

READAP

PRE(PALL)

Command Input

Automatic Sequence

IDLE

AUTO

REFRESH

PRE-

CHARGE

POWER-UP

POWER APPLIED

MODE

SET

POWER

DOWN

WRITE

WITH

AUTOPRE-

CHARGE

POWER

DOWN

WRITE

READ

WITH

AUTOPRE-

CHARGE

BANK

ACTIVE

READ

SELF

REFRESH

Rev. 0.5 / Jan. 2005 15

HY5DU281622ET

POWER-UP SEQUENCE AND DEVICE INITIALIZATION

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF is

applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS

LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state,

where they will remain until driven in normal operation (by a read access). After all power supply and reference volt-

ages are stable, and the clock is stable, the DDR SDRAM requires a 200Ps delay prior to applying an executable com-

mand.

Once the 200Ps delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be

brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED

MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE

parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Reg-

ister set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command

for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting

the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.

1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-

MOS low state. (All the other input pins may be undefined.)

No power sequencing is specified during power up or power down given the following cirteria :

• VDD and VDDQ are driven from a single power converter output.

• VTT is limited to 1.4025V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation).

• VREF tracks VDDQ/2.

• If the above criteria cannot be met by the system design, then the following sequencing and voltage relation-

ship must be adhered to during power up :

2. Start clock and maintain stable clock for a minimum of 200Psec.

3. After stable power and clock, apply NOP or DESELECT conditionS and take CKE high.

4. Following the NOP command, a PRECHARGE ALL command should be applied

5. Issue Extended Mode Register Set (EMRS) to enable DLL.

6. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200

cycles(tXSRD) of clock are required for locking DLL)

7. Issue Precharge commands for all banks of the device.

8. Issue 2 or more Auto Refresh commands.

Voltage description Sequencing Voltage relationship to avoid latch-up

VDDQ After or with VDD < VDD + 0.3V

VTT After or with VDDQ < VDDQ + 0.3V

VREF After or with VDDQ < VDDQ + 0.3V

Rev. 0.5 / Jan. 2005 16

HY5DU281622ET

9. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.

Power-Up Sequence

CODE

CODE CODE CODE

CODE

CODE CODE CODE

CODE

CODE CODE

CODE

NOP PRE MRS

EMRS PRE

NOP MRS

AREF ACT RD

VDD

VDDQ

VTT

VREF

/CLK

CLK

CKE

CMD

ADDR

A10

BA0, BA1

DQS

DQ'S

LVCMOS Low Level

tIS tIH

tVTD

T=200usec tRP tMRD tRP tRFC tMRD

tXSRD*

READ

Non-Read

Command

Power UP

VDD and CK stable Precharge All EMRS Set MRS Set

Reset DLL

(with A8=H)

Precharge All 2 or more

Auto Refresh

MRS Set

(with A8=L)

* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command

tMRD

Rev. 0.5 / Jan. 2005 17

HY5DU281622ET

MODE REGISTER SET (MRS)

The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,

burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low

signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE

must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write

the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is

determined, the information will be held until resetted by another MRS command.

A2 A1 A0

Burst Length

Sequential Interleave

000Reserved Reserved

001 2 2

010 4 4

011 8 8

100Reserved Reserved

1 0 1 Reserved Reserved

1 1 0 Reserved Reserved

1 1 1 Reserved Reserved

A3 Burst Type

0Sequential

1 Interleave

A7 Tes t Mo de

0Normal

1Vendor

test mode

A8 DLL Reset

0No

1Yes

BA0 MRS Type

0MRS

1EMRS

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 RFU* DR TM CAS Latency BT Burst Length

* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.

And, if MRS/EMRS are programmed with ‘Reserved’ code, it could be the cause of mal-function.

A6 A5 A4 CAS Latency

000 Reserved

001 Reserved

010 Reserved

011 3

100 4

101 5

110 Reserved

111 Reserved

Rev. 0.5 / Jan. 2005 18

HY5DU281622ET

BURST DEFINITION

BURST LENGTH & TYPE

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst

length determines the maximum number of column locations that can be accessed for a given Read or Write com-

mand. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All

accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is

reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is

set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a

given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within

the block. The programmed burst length applies to both Read and Write bursts.

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the

burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the

burst type and the starting column address, as shown in Burst Definitionon Table

Burst Length Starting Address (A2,A1,A0) Sequential Interleave

XX0 0, 1 0, 1

XX1 1, 0 1, 0

X00 0, 1, 2, 3 0, 1, 2, 3

X01 1, 2, 3, 0 1, 0, 3, 2

X10 2, 3, 0, 1 2, 3, 0, 1

X11 3, 0, 1, 2 3, 2, 1, 0

000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6

010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5

011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4

100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2

110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1

111 0, 1, 2, 3, 4, 5, 6, 7 7, 6, 5, 4, 3, 2, 1, 0

Rev. 0.5 / Jan. 2005 19

HY5DU281622ET

CAS LATENCY

The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the

availability of the first burst of output data. The latency can be programmed 3 or 4 clocks.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident

with clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

DLL RESET

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-

ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically

disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any

time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally

applied clock before an any command can be issued.

OUTPUT DRIVER IMPEDANCE CONTROL

This device supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-to-

point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2,

Class II, and Matched impedance driver, about 30% of Full drive strength.

Rev. 0.5 / Jan. 2005 20

HY5DU281622ET

EXTENDED MODE REGISTER SET (EMRS)

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func-

tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits

shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0)

and will retain the stored information until it is programmed again or the device loses power.

The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller

must wait the specified time before initiating any subsequent operation. Violating either of these requirements will

result in unspecified operation.

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 1 RFU* DS RFU* DS DLL

A0 DLL enable

0Enable

1Diable

BA0 MRS Type

0MRS

1EMRS

A6 A1 Output Driver Impedance Control

00 Full

01 Half (60%)

10 Reserved

11 Weak (33%)

* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.

Rev. 0.5 / Jan. 2005 21

HY5DU281622ET

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Note : 1. VDDQ must not exceed the level of VDD.

2. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same.

Peak to peak noise on VREF may not exceed ± 2% of the DC value.

3. VTT is expected to be set equal to VREF, and Vtt of the transmitting device must track VREF of the receiving device.

4. Supports 275/ 250/ 200/166Mhz

5. Supports 400/375/350/333/300Mhz

DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V.

2. DOUT is disabled, VOUT=0 to 2.625V, It means, output logic high voltage and low voltage is depend on output channel conditions.

Parameter Symbol Rating Unit

Ambient Temperature TA0 ~ 70 oC

Storage Temperature TSTG -55 ~ 125 oC

Voltage on Any Pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V

Voltage on VDD relative to VSS VDD -0.5 ~ 3.6 V

Voltage on VDDQ relative to VSS VDDQ -0.5 ~ 3.6 V

Output Short Circuit Current IOS 50 mA

Power Dissipation PD2W

Soldering Temperature˜Time TSOLDER 260 ˜10 oC ˜sec

Parameter Symbol Min Typ Max Unit Note

Power Supply Voltage

VDD 2.375 2.5 2.625 V 1,4

VDDQ 2.375 2.5 2.625 V 1,4

VDD 2.7 2.8 2.9 V 1,5

VDDQ 2.7 2.8 2.9 V 1,5

Input High Voltage VIH VREF + 0.15 - VDDQ + 0.3 V

Input Low Voltage VIL -0.3 - VREF - 0.15 V

Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V 3

Reference Voltage VREF 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V2

Parameter Symbol Min Max Unit Note

Input Leakage Current ILI -5 5 uA 1

Output Leakage Current ILO -5 5 uA 2

Output High Voltage VOH VTT + 0.76 - V IOH = -15.2mA,2

Output Low Voltage VOL -VTT - 0.76 V IOL = +15.2mA,2

Rev. 0.5 / Jan. 2005 22

HY5DU281622ET

DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Note :

1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.

2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.

Parameter Symbol Test Condition

Speed

Unit Note

25 26 28 30 33

Operating Current IDD0

One bank; Active - Precharge;

tRC=tRC(min); tCK=tCK(min);

DQ,DM and DQS inputs changing

twice per clock cycle; address and

control inputs changing once per

clock cycle

230 220 210 200 190 mA 1

Operating Current IDD1 Burst l e n g t h = 4 , O n e b a n k a c t i v e

tRC t tRC(min), IOL=0mA 230 220 210 200 190 mA 1

Precharge Standby

Current in Power Down

Mode

IDD2P CKE d VIL(max), tCK=min 40 40 40 40 40 mA

Precharge Standby

Current in Non Power

Down Mode

IDD2N

CKE t VIH(min), /CS t VIH(min),

tCK = min, Input signals are

changed one time during 2clks

150 140 130 120 110 mA

Active Standby Cur-

rent in Power Down

Mode

IDD3P CKE d VIL(max), tCK=min 40 40 40 40 40 mA

Active Standby Cur-

rent in Non Power

Down Mode

IDD3N

CKE t VIH(min), /CS t VIH(min),

tCK=min, Input signals are

changed one time during 2clks

190 180 170 160 150 mA

Burst Mode Operating

Current IDD4 tCK t tCK(min), IOL=0mA

A ll banks active 380 360 340 320 300 mA 1

Auto Refresh Current IDD5 tRC t t RFC(min),

A ll banks active 380 360 340 320 300 mA 1,2

Self Refresh Current IDD6 CKE d 0.2V 44444mA

Operating Current -

Four Bank Operation IDD7

Four bank interleaving with BL=4,

Refer to the following page for

detailed test condition

530 510 490 470 450 mA

Rev. 0.5 / Jan. 2005 23

HY5DU281622ET

DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Note :

1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.

2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.

Parameter Symbol Test Condition

Speed

Unit Note

36 4 5

Operating Current IDD0

One bank; Active - Precharge;

tRC=tRC(min); tCK=tCK(min); DQ,DM

and DQS inputs changing twice per

clock cycle; address and control inputs

changing once per clock cycle

180 170 160 mA 1

Operating Current IDD1 Burst le ng t h= 2, O n e ba n k a ct i ve

tRC t tRC(min), IOL=0mA 180 170 160 mA 1

Precharge Standby Cur-

rent in Power Down Mode IDD2P CKE d VIL(max), tCK=min 40 40 40 mA

Precharge Standby Cur-

rent in Non Power Down

Mode

IDD2N

CKE t VIH(min), /CS t VIH(min), tCK =

min, Input signals are changed one

time during 2clks

100 90 80 mA

Active Standby Current in

Power Down Mode IDD3P CKE d VIL(max), tCK=min 40 40 40 mA

Active Standby Current in

Non Power Down Mode IDD3N

CKE t VIH(min), /CS t VIH(min),

tCK=min, Input signals are changed one

time during 2clks

140 130 120 mA

Burst Mode Operating Cur-

rent IDD4 tCK t tCK(min), IOL=0mA

All banks active 280 260 240 mA 1

Auto Refresh Current IDD5 tRC t tRFC(min),

All banks active 280 260 240 mA 1,2

Self Refresh Current IDD6 CKE d 0.2V 4 4 4 mA

Operating Current - Four

Bank Operation IDD7

Four bank interleaving with BL=4, Refer

to the following page for detailed test

condition

430 410 390 mA

Rev. 0.5 / Jan. 2005 24

HY5DU281622ET

AC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Note :

1. VID is the magnitude of the difference between the input level on CK and the input on /CK.

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Parameter Symbol Min Max Unit Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.45 V

Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.45 V

Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ + 0.6 V 1

Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2

Parameter Value Unit

Reference Voltage VDDQ x 0.5 V

Termination Voltage VDDQ x 0.5 V

AC Input High Level Voltage (VIH, min) VREF + 0.45 V

AC Input Low Level Voltage (VIL, max) VREF - 0.45 V

Input Timing Measurement Reference Level Voltage VREF V

Output Timing Measurement Reference Level Voltage VTT V

Input Signal maximum peak swing 1.5 V

Input minimum Signal Slew Rate 1 V/ns

Termination Resistor (RT)50:

Series Resistor (RS)25:

Output Load Capacitance for Access Time Measurement (CL)30 pF

Rev. 0.5 / Jan. 2005 25

HY5DU281622ET

AC Overshoot/Undershoot specifications for Address and Command pins

AC Overshoot/Undershoot specifications for Data, Strobe and Mask Pins

Parameter 200MHz Specifications

Maximum peak amplitude allowwed for overshoot 1.5 V

Maximum peak amplitude allowwed for undershoot 1.5 V

The area between the overshoot signal and VDD must be less than or equal to(See below Fig) 4.5 V-nS

The area between the overshoot signal and GND must be less than or equal to(See below Fig) 4.5 V-nS

Parameter 200MHz Specifications

Maximum peak amplitude allowwed for overshoot 1.2 V

Maximum peak amplitude allowwed for undershoot 1.2 V

The area between the overshoot signal and VDD must be less than or equal to(See below Fig) 2.4 V-nS

The area between the overshoot signal and GND must be less than or equal to(See below Fig) 2.4 V-nS

0123456

-1

-2

-3

Volts

(V)

Time(ns)

Ground

Max. area=4.5V-ns

Max. amplitude=1.5V

0 1 23456

-1

-2

-3

Volts

(V)

Time(ns)

Ground

Max. area=2.4V-ns

Max. amplitude=1.2V

Rev. 0.5 / Jan. 2005 26

HY5DU281622ET

AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)

Parameter Symbol

25 26 28

Unit Note

Min Max Min Max Min Max

Row Cycle Time(Manual Precharge) tRC 22 - 21 - 20 - CK

Row Cycle Time(Auto Precharge) tRC_APCG 24 - 23 - 22 -

Auto Refresh Row Cycle Time tRFC 26 - 25 - 24 - CK

Row Active Time tRAS 16 100K 15 100K 14 100K CK

Row Address to Column Address Delay for Read tRCDRD 6- 6 -6-

Row Address to Column Address Delay for Write tRCDWR 4-4 -4-

Row Active to Row Active Delay tRRD 4-4 -4-

Column Address to Column Address Delay tCCD 2- 2 -2-

Row Precharge Time tRP 6-6 -6-

Write Recovery Time tWR 4- 4 -4-

Last Data-In to Read Command tDRL 2- 2 -2-

Auto Precharge Write Recovery + Precharge Time tDAL 10 - 10 - 10 - CK

System Clock Cycle Time

CL=5

tCK

2.5 6 2.6 6 - -

CL=4 --- -2.86

Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 CK

Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 CK

Data-Out edge to Clock edge Skew tAC -0.55 0.55 -0.6 0.6 -0.6 0.6 ns

DQS-Out edge to Clock edge Skew tDQSCK -0.55 0.55 -0.6 0.6 -0.6 0.6 ns

DQS-Out edge to Data-Out edge Skew tDQSQ - 0.35 - 0.35 - 0.35 ns

Data-Out hold time from DQS tQH tHPmin

-tQHS -tHPmin

-tQHS -ns 1,6

Clock Half Period tHP tCH/L

min -tCH/L

min -ns 1,5

Data Hold Skew Factor tQHS - 0.35 - 0.35 - 0.35 ns 6

Input Setup Time tIS 0.75 - 0.75 - 0.75 - ns 2

Input Hold Time tIH 0.75 - 0.75 - 0.75 - ns 2

Write DQS High Level Width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 CK

Write DQS Low Level Width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 CK

Clock to First Rising edge of DQS-In tDQSS 0.85 1.15 0.85 1.15 0.85 1.15 CK

Data-In Setup Time to DQS-In (DQ & DM) tDS 0.35 - 0.35 - 0.35 - ns 3

Data-In Hold Time to DQS-In (DQ & DM) tDH 0.35 - 0.35 - 0.35 - ns 3

Rev. 0.5 / Jan. 2005 27

HY5DU281622ET

Note :

1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

3. Data latched at both rising and falling edges of Data Strobes(UDQS,LDQS) : DQ, LDM,UDM.

4. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).

6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).

tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and

output pattern effects, and p-channel to n-channel variation of the output drivers.

7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.

Signal transitions through the DC region must be monotonic.

Parameter Symbol

25 26 28

Unit Note

Min Max Min Max Min Max

DQS falling edge to CK setup time tDSS 3.0 - 3.0 - 3.0 - CK

DQS falling edge hold time from CK tDSH 3.0 - 3.0 - 3.0 - CK

Write DQS Preamble Setup Time tWPRES 0- 0 -0-

Write DQS Preamble Hold Time tWPREH 0.35 - 0.35 - 0.35 - CK

Write DQS Postamble Time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 CK

Mode Register Set Delay tMRD 10 - 10 - 10 - ns

Exit Self Refresh to Any Execute Command tXSC 200 - 200 - 200 - CK 4

Power Down Exit Time tPDEX 2tCK

+ tIS -2tCK

+ tIS -CK

Average Periodic Refresh Interval tREFI - 7.8 - 7.8 - 7.8 us

Rev. 0.5 / Jan. 2005 28

HY5DU281622ET

AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)

Parameter Symbol

30 33 36

Unit Note

Min Max Min Max Min Max

Row Cycle Time(Manual Precharge) tRC 19 - 18 - 16 - CK

Row Cycle Time(Auto Precharge) tRC_APCG 21 - 20 - 18 -

Auto Refresh Row Cycle Time tRFC 23 - 22 - 20 - CK

Row Active Time tRAS 13 100K 12 100K 11 100K CK

Row Address to Column Address Delay for Read tRCDRD 6- 6 -5-

Row Address to Column Address Delay for Write tRCDWR 4-4 -3-

Row Active to Row Active Delay tRRD 4-4 -3-

Column Address to Column Address Delay tCCD 2- 1 -1-

Row Precharge Time tRP 6-6 -5-

Write Recovery Time tWR 4- 4 -3-

Last Data-In to Read Command tDRL 2- 2 -2-

Auto Precharge Write Recovery + Precharge Time tDAL 10 - 10 - 8 - CK

System Clock Cycle Time CL=4 tCK 363.363.610

Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 CK

Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 CK

Data-Out edge to Clock edge Skew tAC -0.6 0.6 -0.6 0.6 -0.6 0.6 ns

DQS-Out edge to Clock edge Skew tDQSCK -0.6 0.6 -0.6 0.6 -0.6 0.6 ns

DQS-Out edge to Data-Out edge Skew tDQSQ - 0.35 - 0.35 - 0.35 ns

Data-Out hold time from DQS tQH tHPmin

-tQHS -tHPmin

-tQHS -ns 1,6

Clock Half Period tHP tCH/L

min -tCH/L

min -ns 1,5

Data Hold Skew Factor tQHS - 0.35 - 0.35 - 0.4 ns 6

Input Setup Time tIS 0.75 - 0.75 - 0.75 - ns 2

Input Hold Time tIH 0.75 - 0.75 - 0.75 - ns 2

Write DQS High Level Width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 CK

Write DQS Low Level Width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 CK

Clock to First Rising edge of DQS-In tDQSS 0.85 1.15 0.85 1.15 0.85 1.15 CK

Data-In Setup Time to DQS-In (DQ & DM) tDS 0.35 - 0.35 - 0.4 - ns 3

Data-In Hold Time to DQS-In (DQ & DM) tDH 0.35 - 0.35 - 0.4 - ns 3

Rev. 0.5 / Jan. 2005 29