This is information on a product in full production.
June 2013 DocID18279 Rev 5 1/37
ST1CC40
3 A monolithic step-down current source with synchronous
rectification
Datasheet - production data
Features
3.0 V to 18 V operating input voltage range
850 kHz fixed switching frequency
100 mV typ. current sense voltage drop
6 A standby current in inhibit mode
7% output current accuracy
Synchronous rectification
95 mHS / 69 m LS typical RDS(on)
Peak current mode architecture
Embedded compensation network
Internal current limiting
Ceramic output capacitor compliant
Thermal shutdown
Applications
Battery charger
Signage
Emergency lighting
High brightness LED driving
General lighting
Description
The ST1CC40 device is an 850 kHz fixed
switching frequency monolithic step-down DC-DC
converter designed to operate as precise
constant current source with an adjustable current
capability up to 3 A DC. The regulated output
current is set connecting a sensing resistor to the
feedback pin. The embedded synchronous
rectification and the 100 mV typical RSENSE
voltage drop enhance the efficiency performance.
The size of the overall application is minimized
thanks to the high switching frequency and
ceramic output capacitor compatibility. The device
is fully protected against thermal overheating,
overcurrent and output short-circuit. Inhibit mode
minimizes the current consumption in standby.
The ST1CC40 is available in VFQFPN8 4 mm x 4
mm 8-lead, and standard SO8 package.
VFQFPN8 4x4
Figure 1. Typical application circuit
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Table of contents ST1CC40
2/37 DocID18279 Rev 5
Table of contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.4 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.5 Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.6 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2 GCO(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . 12
6.3 Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.4 LED small signal model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.5 Total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.6 eDesign studio software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.1 Sensing resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.2 Inductor and output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.3 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DocID18279 Rev 5 3/37
ST1CC40 Table of contents
37
7.2 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.3 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.4 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
List of tables ST1CC40
4/37 DocID18279 Rev 5
List of tables
Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Uncompensated error amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. List of ceramic capacitors for the ST1CC40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9. VFQFPN8 (4 x 4 x 1.08 mm) package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. SO8-BW package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DocID18279 Rev 5 5/37
ST1CC40 List of figures
37
List of figures
Figure 1. Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. ST1CC40 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Internal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Block diagram of the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Transconductance embedded error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Equivalent series resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Load equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Phase plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. eDesign studio screenshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Constant current protection triggering hiccup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. Demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. PCB layout (component side) VFQFPN8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18. PCB layout (bottom side) VFQFPN8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19. PCB layout (component side) SO8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 20. PCB layout (bottom side) SO8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 21. Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 22. Inhibit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 23. Thermal shutdown protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 24. Hiccup current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 25. OCP blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 26. Current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 27. VFQFPN8 (4 x 4 x 1.08 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 28. SO8-BW package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin settings ST1CC40
6/37 DocID18279 Rev 5
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
1.2 Pin description
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Table 1. Pin description
No.
Type Description
VFQFPN8 S08-BW
13VIN
AAnalog circuitry power supply connection
24INH
Inhibit input pin. Low signal level disables the device. Leave
this pin floating if not used
35FB
Feedback input. Connect a proper sensing resistor to set the
LED current
4 6 AGND Analog circuitry ground connection
5 - NC Not connected
68V
INSW Power input voltage
7 1 SW Regulator switching pin
8 2 PGND Power ground
- 7 GND Connect to AGND
DocID18279 Rev 5 7/37
ST1CC40 Maximum ratings
37
2 Maximum ratings
3 Thermal data
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
VINSW Power input voltage -0.3 to 20
V
VINA Input voltage -0.3 to 20
VINH Inhibit voltage -0.3 to VINA
VSW Output switching voltage -1 to VIN
VPG Power Good -0.3 to VIN
VFB Feedback voltage -0.3 to 2.5
IFB FB current -1 to +1 mA
PTOT Power dissipation at TA < 60 °C 2 W
TOP Operating junction temperature range -40 to 150 °C
Tstg Storage temperature range -55 to 150 °C
Table 3. Thermal data
Symbol Parameter Value Unit
RthJA
Maximum thermal resistance
junction-ambient(1)
1. Package mounted on demonstration board.
VFQFPN8 40
°C/W
SO8-BW 65
Electrical characteristics ST1CC40
8/37 DocID18279 Rev 5
4 Electrical characteristics
TJ= 25 °C, VCC = 12 V, unless otherwise specified.
Table 4. Electrical characteristics
Symbol Parameter Test conditions
Value
Unit
Min. Typ. Max.
VIN
Operating input voltage range See(1) 318
VDevice ON level 2.6 2.75 2.9
Device OFF level 2.4 2.55 2.7
VFB Feedback voltage
TJ = 25 °C 90 97 104
mV
TJ = 125 °C 90 100 110
IFB VFB pin bias current 600 nA
RDSON-P High-side switch on-resistance ISW = 750 mA 95 m
RDSON-N Low-side switch on-resistance ISW = 750 mA 69 m
ILIM Maximum limiting current See(2) 5A
Oscillator
FSW Switching frequency 0.7 0.85 1 MHz
D Duty cycle See(2) 0 100 %
DC characteristics
IqQuiescent current Duty cycle = 0 Vfb > 100 mV 1.5 2.5 mA
IQST-BY Total standby quiescent current
OFF 2.4 4.5 A
See(1) 6
Inhibit
VINH INH threshold voltage
Device ON level 1.2
V
Device OFF level 0.4
IINH INH current 2A
Soft-start
TSS Soft-start duration 1 ms
Protection
TSHDN
Thermal shutdown 150
°C
Hystereris 15
1. Specifications referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by
design, characterization and statistical correlation.
2. Guaranteed by design.
DocID18279 Rev 5 9/37
ST1CC40 Functional description
37
5 Functional description
The ST1CC40 device is based on a “peak current mode” architecture with fixed frequency
control. As a consequence, the intersection between the error amplifier output and the
sensed inductor current generates the control signal to drive the power switch.
The main internal blocks shown in the block diagram in Figure 3 are:
High-side and low-side embedded power element for synchronous rectification
A fully integrated sawtooth oscillator with a typical frequency of 850 kHz
A transconductance error amplifier
A high-side current sense amplifier to track the inductor current
A pulse width modulator (PWM) comparator and the circuitry necessary to drive the
internal power element
The soft-start circuitry to decrease the inrush current at power-up
The current limitation circuit based on the pulse-by-pulse current protection with
frequency divider
The inhibit circuitry
The thermal protection function circuitry
Figure 3. ST1CC40 block diagram
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Functional description ST1CC40
10/37 DocID18279 Rev 5
5.1 Power supply and voltage reference
The internal regulator circuit consists of a startup circuit, an internal voltage pre-regulator,
the BandGap voltage reference and the bias block that provides current to all the blocks.
The starter supplies the startup current to the entire device when the input voltage goes high
and the device is enabled (INHIBIT pin connected to ground). The pre-regulator block
supplies the bandgap cell with a pre-regulated voltage that has a very low supply voltage
noise sensitivity.
5.2 Voltage monitor
An internal block continuously senses the Vcc, Vref and Vbg. If the monitored voltages are
good, the regulator begins operating. There is also a hysteresis on the VCC (UVLO).
Figure 4. Internal circuit
5.3 Soft-start
The startup phase is implemented ramping the reference of the embedded error amplifier in
1 msec typ. time. It minimizes the inrush current and decreases the stress of the power
components at power-up.
During normal operation a new soft-start cycle takes place in case of:
Thermal shutdown event
UVLO event.
5.4 Error amplifier
The voltage error amplifier is the core of the loop regulation. It is a transconductance
operational amplifier whose non-inverting input is connected to the internal voltage
reference (100 mV), while the inverting input (FB) is connected to the output current sensing
resistor.
The error amplifier is internally compensated to minimize the size of the final application.
STARTER PREREGULATOR
IC BIAS
BANDGAP
VREF
VREG
Vcc
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DocID18279 Rev 5 11/37
ST1CC40 Functional description
37
The error amplifier output is compared with the inductor current sense information to
perform PWM control.
5.5 Inhibit
The inhibit block disables most of the circuitry when the INH input signal is low. The current
drawn from the input voltage is 6 µA typical in inhibit mode.
5.6 Thermal shutdown
The shutdown block generates a signal that disables the power stage if the temperature of
the chip goes higher than a fixed internal threshold (150 ± 10 °C typical). The sensing
element of the chip is close to the PDMOS area, ensuring fast and accurate temperature
detection. A 15 °C typical hysteresis prevents the device from turning ON and OFF
continuously during the protection operation.
Table 5. Uncompensated error amplifier characteristics
Description Value
Transconductance 250 µS
Low frequency gain 96 dB
CC195 pF
RC70 K
Application notes ST1CC40
12/37 DocID18279 Rev 5
6 Application notes
6.1 Closing the loop
Figure 5. Block diagram of the loop
6.2 GCO(s) control to output transfer function
The accurate control to output transfer function for a buck peak current mode converter can
be written as:
Equation 1
where R0 represents the load resistance, Ri the equivalent sensing resistor of the current
sense circuitry, p the single pole introduced by the LC filter and z the zero given by the
ESR of the output capacitor.
FH(s) accounts for the sampling effect performed by the PWM comparator on the output of
the error amplifier that introduces a double pole at one half of the switching frequency.
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DocID18279 Rev 5 13/37
ST1CC40 Application notes
37
Equation 2
Equation 3
where:
Equation 4
Sn represents the slope of the sensed inductor current, Se the slope of the external ramp
(VPP peak-to-peak amplitude) that implements the slope compensation to avoid sub-
harmonic oscillations at duty cycle over 50%.
The sampling effect contribution FH(s) is:
Equation 5
where:
Equation 6
and
Equation 7
6.3 Error amplifier compensation network
The ST1CC40 device embeds the error amplifier (see Figure 6) and a pre-defined
compensation network which is effective in stabilizing the system in most of the application
conditions.
Z
1
ESR COUT
-------------------------------=
P
1
RLOAD COUT
--------------------------------------mC1D–0,5–
LC
OUT fSW
---------------------------------------------+=
mC1Se
Sn
------ +=
SeVpp fSW
=
Sn
VIN VOUT
–
L
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=
FHs 1
1s
nQP
-------------------s2
n
2
------++
-------------------------------------------=
nfSW
=
QP
1
mC1D–0,5–
----------------------------------------------------------=
Application notes ST1CC40
14/37 DocID18279 Rev 5
Figure 6. Transconductance embedded error amplifier
RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect
system stability but it is useful to reduce the noise at the output of the error amplifier.
The transfer function of the error amplifier and its compensation network is:
Equation 8
where Avo = Gm · Ro.
The poles of this transfer function are (if Cc >> C0 + CP):
Equation 9
Equation 10
whereas the zero is defined as:
Equation 11
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fP HF
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FZ
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DocID18279 Rev 5 15/37
ST1CC40 Application notes
37
The embedded compensation network is RC = 70 K, CC = 195 pF while CP and CO can be
considered as negligible. The error amplifier output resistance is 240 Mso the relevant
singularities are:
Equation 12
6.4 LED small signal model
Once the system reaches the working condition the LEDs composing the row are biased
and their equivalent circuit can be considered as a resistor for frequencies << 1 MHz.
The LED manufacturer typically provides the equivalent dynamic resistance of the LED
biased at different DC current. This parameter is required to study the behavior of the
system in the small signal analysis.
For instance, the equivalent dynamic resistance of Luxeon III Star from Lumiled measured
with a different biasing current level is reported below:
In case the LED datasheet doesn’t report the equivalent resistor value, it can be simply
derived as the tangent to the diode I-V characteristic in the present working point (see
Figure 7).
Figure 7. Equivalent series resistor
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Application notes ST1CC40
16/37 DocID18279 Rev 5
Figure 8 shows the equivalent circuit of the LED constant current generator.
Figure 8. Load equivalent circuit
As a consequence, the LED equivalent circuit gives the LED(s) term correlating the output
voltage with the high impedance FB input:
Equation 13
6.5 Total loop gain
In summary, the open loop gain can be expressed as:
Equation 14
Example
Design specifications:
VIN = 12 V, VFW_LED = 3.5 V, nLED = 2, rLED = 1.1 , ILED = 700 mA, ILED RIPPLE = 2%
The inductor and capacitor value are dimensioned in order to meet the ILED RIPPLE
specifications (see Section 7.1.2 for output capacitor and inductor selection guidelines):
L = 10
H, COUT = 2.2
F MLCC (negligible ESR)
9,1
5G
&287
/
/
5G
5V
'OHG
5V
'
'
&287
9,1
/
/
'OHG
$0Y
LED nLED
RSENSE
nLED rLED RSENSE
+
----------------------------------------------------------=
Gs GCO sA0s
LED nLED
=
DocID18279 Rev 5 17/37
ST1CC40 Application notes
37
Accordingly, with Section 7.1.1 the sensing resistor value is:
Equation 15
Equation 16
The gain and phase margin Bode diagrams are plotted respectively in Figure 9 and
Figure 10.
Figure 9. Module plot
RS
100 mV
700 mA
---------------------140 m=
LED nLED
RSENSE
nLED rLED RSENSE
+
----------------------------------------------------------= 140 m
21,1 140 m+
------------------------------------------------- 0,06==
*V
G%
(;7(51$//22302'8/(
)UHTXHQF\>+]@
0RGXOH>G%@
$0Y
Application notes ST1CC40
18/37 DocID18279 Rev 5
Figure 10. Phase plot
The cutoff frequency and the phase margin are:
Equation 17
6.6 eDesign studio software
The ST1CC40 device is supported by the eDesign software which can be seen online on
the STMicroelectronics® home page (www.st.com).
*V
(;7(51$//223*$,13+$6(
)UHTXHQF\>+]@
3KDVH
$0Y
fC100 kHz=pm 47=
DocID18279 Rev 5 19/37
ST1CC40 Application notes
37
Figure 11. eDesign studio screenshot
The software easily supports the component sizing according to the technical information
given in this datasheet (see Section 6).
The final user is requested to fill in the requested information such as the input voltage
range, the selected LED parameters and the number of LEDs composing the row.
The software calculates external components according to the internal database. It is also
possible to define new components and ask the software to have them used.
Bode plots, estimated efficiency and thermal performance are provided.
Finally, the user can save the design and print all the information including the bill of material
of the board.
Application information ST1CC40
20/37 DocID18279 Rev 5
7 Application information
7.1 Component selection
7.1.1 Sensing resistor
In closed loop operation the ST1CC40 feedback pin voltage is 100 mV so the sensing
resistor calculation is expressed as:
Equation 18
Since the main loop (see Section 6.1) regulates the sensing resistor voltage drop, the
average current is regulated into the LEDs. The integration period is at minimum 5 * TSW
since the system bandwidth can be dimensioned up to FSW/5 at maximum.
The system performs the output current regulation over a period which is at least five times
longer than the switching frequency. The output current regulation neglects the ripple
current contribution and its reliance on external parameters like input voltage and output
voltage variations (line transient and LED forward voltage spread). This performance can
not be achieved with simpler regulation loops like a hysteretic control.
For the same reason the switching frequency is constant over the application conditions,
that helps to tune the EMI filtering and to guarantee the maximum LED current ripple
specifications in the application range. This performance cannot be achieved using constant
on/off-time architecture.
7.1.2 Inductor and output capacitor selection
The output capacitor filters the inductor current ripple that, given the application conditions,
depends on the inductor value. As a consequence, the LED current ripple, that is the main
specification for a switching current source, depends on the inductor and output capacitor
selection.
Figure 12. Equivalent circuit
RS
100 mV
ILED
--------------------=
'&5 '&5
&287
5V
9,1
/
(65 5G
9,1
/
(65
'OHG
'
&287
'
5V
5GQ
'OHGQ
$0Y
DocID18279 Rev 5 21/37
ST1CC40 Application information
37
The LED ripple current can be calculated as the inductor ripple current ratio flowing into the
output impedance using the Laplace transform (see Figure 11):
Equation 19
where the term 8/2 represents the main harmonic of the inductor current ripple (which has
a triangular shape) and IL is the inductor current ripple.
Equation 20
so L value can be calculated as:
Equation 21
where TOFF is the off-time of the embedded high switch, given by 1-D.
As a consequence, the lower the inductor value (so the higher the current ripple), the higher
the COUT value would be to meet the specifications.
A general rule to dimension L value is:
Equation 22
Finally the required output capacitor value can be calculated equalizing the LED current
ripple specification with the module of the Fourier transformer (see Equation 19) calculated
at FSW frequency.
Equation 23
Example (see Section : Example):
VIN = 12 V, ILED = 700 mA,
ILED/ILED = 2%, VFW_LED = 3.5 V, nLED = 2
The output capacitor value must be dimensioned according to Equation 23.
Finally, given the selected inductor value, a 2.2 µF ceramic capacitor value keeps the LED
current ripple ratio lower than 2% of the nominal current. An output ceramic capacitor type
(negligible ESR) is suggested to minimize the ripple contribution given a fixed capacitor
value.
IRIPPLE s
8
2
------IL1 s ESR COUT
+
1sR
SESR nLED RLED
++COUT
+
-----------------------------------------------------------------------------------------------------------=
IL
VOUT
L
-------------- TOFF
nLED VFW_LED 100mV+
L
------------------------------------------------------------------TOFF
==
LnLED VFW_LED 100mV+
IL
------------------------------------------------------------------TOFF
nLED VFW_LED 100mV+
IL
------------------------------------------------------------------1nLED VFW_LED 100mV+
VIN
------------------------------------------------------------------–
==
IL
ILED
----------- 0,5
IRIPPLE s=j IRIPPLE_SPEC
=
Application information ST1CC40
22/37 DocID18279 Rev 5
7.1.3 Input capacitor
The input capacitor must be able to support the maximum input operating voltage and the
maximum RMS input current.
Since step-down converters draw current from the input in pulses, the input current is
squared and the height of each pulse is equal to the output current. The input capacitor
must absorb all this switching current, whose RMS value can be up to the load current
divided by two (worst case, with duty cycle of 50%). For this reason, the quality of these
capacitors must be very high to minimize the power dissipation generated by the internal
ESR, thereby improving system reliability and efficiency. The critical parameter is usually the
RMS current rating, which must be higher than the RMS current flowing through the
capacitor. The maximum RMS input current (flowing through the input capacitor) is:
Equation 24
where is the expected system efficiency, D is the duty cycle and IO is the output DC
current. Considering = 1, this function reaches its maximum value at D = 0.5 and the
equivalent RMS current is equal to IO divided by 2. The maximum and minimum duty cycles
are:
Equation 25
and
Equation 26
Table 6. Inductor selection
Manufacturer Series Inductor value (µH) Saturation current (A)
Würth Elektronik
WE-HCI 7040 1 to 4.7 20 to 7
WE-HCI 7050 4.9 to 10 20 to 4.0
Coilcraft XPL 7030 2.2 to 10 29 to 7.2
IRMS IOD2D
2
---------------– D2
2
-------+=
DMAX
VOUT VF
+
VINMIN VSW
–
-------------------------------------=
DMIN
VOUT VF
+
VINMAX VSW
–
--------------------------------------=
DocID18279 Rev 5 23/37
ST1CC40 Application information
37
where VF is the freewheeling diode forward voltage and VSW the voltage drop across the
internal PDMOS. Considering the range DMIN to DMAX, it is possible to determine the max.
IRMS going through the input capacitor. Capacitors that can be considered are:
Electrolytic capacitors:
These are widely used due to their low price and their availability in a wide range of
RMS current ratings.
The only drawback is that, considering ripple current rating requirements, they are
physically larger than other capacitors.
Ceramic capacitors:
If available for the required value and voltage rating, these capacitors usually have
a higher RMS current rating for a given physical dimension (due to very low ESR).
The drawback is the considerably high cost.
Tantalum capacitors:
Small tantalum capacitors with very low ESR are becoming more available. However,
they can occasionally burn if subjected to very high current during charge.
Therefore, it is recommended to avoid this type of capacitor for the input filter of the
device as they may be stressed by a high surge current when connected to the power
supply.
In case the selected capacitor is ceramic (so neglecting the ESR contribution), the input
voltage ripple can be calculated as:
Equation 27
7.2 Layout considerations
The layout of switching DC-DC converters is very important to minimize noise and
interference. Power-generating portions of the layout are the main cause of noise and so
high switching current loop areas should be kept as small as possible and lead lengths as
short as possible.
High impedance paths (in particular the feedback connections) are susceptible to
interference, so they should be as far as possible from the high current paths. A layout
example is provided in Figure 13.
The input and output loops are minimized to avoid radiation and high frequency resonance
problems. The feedback pin to the sensing resistor path must be designed as short as
possible to avoid pick-up noise. Another important issue is the ground plane of the board.
Since the package has an exposed pad, it is very important to connect it to an extended
ground plane in order to reduce the thermal resistance junction-to-ambient.
Table 7. List of ceramic capacitors for the ST1CC40
Manufacturer Series Capacitor value (µF) Rated voltage (V)
TAIYO YUDEN UMK325BJ106MM-T 10 50
MURATA GRM42-2 X7R 475K 50 4.7 50
VIN PP
IO
CIN fSW
----------------------- 1D
----–
DD
----1D–+=
Application information ST1CC40
24/37 DocID18279 Rev 5
To increase the design noise immunity, different signal and power ground should be
implemented in the layout (see Section 7.5: Application circuit). The signal ground serves
the small signal components, the device analog ground pin, the exposed pad and a small
filtering capacitor connected to the VINA pin. The power ground serves the device ground
pin and the input filter. The different grounds are connected underneath the output capacitor.
Neglecting the current ripple contribution, the current flowing through this component is
constant during the switching activity and so this is the cleanest ground point of the buck
application circuit.
Figure 13. Layout example
7.3 Thermal considerations
The dissipated power of the device is tied to three different sources:
Conduction losses due to the RDS(on), which are equal to:
Equation 28
where D is the duty cycle of the application. Note that the duty cycle is theoretically given by
the ratio between VOUT (nLED VLED + 100 mV) and VIN, but in practice it is substantially
higher than this value to compensate for the losses in the overall application. For this
reason, the conduction losses related to the RDS(on) increase compared to an ideal case.
PON RRDSON_HS IOUT
2D =
POFF RRDSON_LS IOUT
21D–=
DocID18279 Rev 5 25/37
ST1CC40 Application information
37
Switching losses due to turning ON and OFF. These are derived using Equation 29:
Equation 29
where TRISE and TFALL represent the switching times of the power element that causes the
switching losses when driving an inductive load (see Figure 14). TSW is the equivalent
switching time.
Figure 14. Switching losses
Quiescent current losses.
Equation 30
Example (see Section : Example):
VIN = 12 V, VFW_LED = 3.5 V, nLED = 2, ILED = 700 mA
The typical output voltage is:
Equation 31
RDSON_HS has a typical value of 95 m and RDS(on)_LS is 69 m at 25 °C.
For the calculation we can estimate RDS(on)_HS = 140 m and RDS(on)_LS = 100 mas
a consequence of TJ increase during the operation.
TSW_EQ is approximately 12 ns.
IQ has a typical value of 1.5 mA at VIN = 12 V.
PSW VIN IOUT
TRISE TFALL
+
2
-----------------------------------------FSW VIN
=IOUT TSW_EQ FSW
=
AM14826v1
PQVIN IQ
=
VOUT nLED VFW_LED VFB
+7,1V==
Application information ST1CC40
26/37 DocID18279 Rev 5
The overall losses are:
Equation 32
Equation 33
The junction temperature of the device is:
Equation 34
where TA is the ambient temperature and RthJ-A is the thermal resistance junction-to-
ambient. The junction-to-ambient (RthJ-A) thermal resistance of the device assembled in
HSO8 package and mounted on the board is about 40 °C/W.
Assuming the ambient temperature is around 40 °C, the estimated junction temperature is:
Equation 35
7.4 Short-circuit protection
In overcurrent protection mode, when the peak current reaches the current limit threshold,
the device disables the power element and it is able to reduce the conduction time down to
the minimum value (approximately 100 nsec typ.) to keep the inductor current limited. This
is the pulse-by-pulse current limitation to implement the constant current protection feature.
In overcurrent condition, the duty cycle is strongly reduced and, in most applications, this is
enough to limit the switch current to the current threshold.
The inductor current ripple during ON and OFF phases can be written as:
ON phase
Equation 36
OFF phase
Equation 37
where DCRL is the series resistance of the inductor.
PTOT RDS(on)_HS IOUT
2DR
DS(on)_LS IOUT
21D–VIN IOUT fSW TSW
VIN IQ
+++=
PTOT 0,14 0,720,6 0,1 0,720,4 12+0,7 12 10 9–850 10312 1,5 10 3–
+ + 205mW=
TJTARthJA–PTOT
+=
TJ60 0,205 40 68C+=
IL TON
VIN VOUT
–DCRLRDS(on) HS
+I–
L
-------------------------------------------------------------------------------------------------TON
=
IL TON
VOUT DCRLRDS(on) LS
+I+–
L
----------------------------------------------------------------------------------------- TOFF
=
DocID18279 Rev 5 27/37
ST1CC40 Application information
37
The pulse-by-pulse current limitation is effective in implementing constant current protection
when:
Equation 38
From Equation 36 and Equation 37 we can gather that the implementation of the constant
current protection becomes more critical the lower the VOUT is and the higher VIN is.
In fact, in short-circuit condition the voltage applied to the inductor during the off-time
becomes equal to the voltage drop across parasitic components (typically the DCR of the
inductor and the RDS(on) of the low-side switch) since VOUT is negligible, while during TON
the voltage applied at the inductor is maximized and it is approximately equal to VIN.
In general, the worst case scenario is heavy short-circuit at the output with maximum input
voltage. Equation 36 and Equation 37 in overcurrent conditions can be simplified to:
Equation 39
considering TON that has already been reduced to its minimum.
Equation 40
where TSW = 1 /FSW and considering the nominal FSW.
At higher input voltage, IL TON may be higher than IL TOFF and so the inductor current
may escalate. As a consequence, the system typically meets Equation 38 at a current level
higher than the nominal value thanks to the increased voltage drop across stray
components. In most of the application conditions the pulse-by-pulse current limitation is
effective to limit the inductor current. Whenever the current escalates, a second level current
protection called “Hiccup mode” is enabled. Hiccup protection offers an additional protection
against heavy short-circuit condition at very high input voltage even considering the spread
of the minimum conduction time of the power element. If the hiccup current level (6.2 A typ.)
is triggered, the switching activity is prevented for 12 cycles.
Figure 15 shows the operation of the constant current protection when a short-circuit is
applied at the output at the maximum input voltage.
IL TON
IL TOFF
=
DCR R I V
IL TON
VIN DCRLRDS(on) HS
+I–
L
------------------------------------------------------------------------- TON MIN
VIN
L
---------90ns=
IL TOFF
DCRLRDS(on) LS
+–I
L
--------------------------------------------------------------- TSW 90ns–
DCRLRDS(on) LS
+–I
L
--------------------------------------------------------------- 1,18s=
Application information ST1CC40
28/37 DocID18279 Rev 5
Figure 15. Constant current protection triggering hiccup mode
7.5 Application circuit
Figure 16. Demonstration board application circuit
AM12814v1
VLJQDO*1'
SRZHU*1'
Q)9
&
9/('
X9
& 5 .
9,1
*1'
5
10
56
',0
9,1B$
',0
)%
$*1'
3*1'
6:
9,1B6:
(3
67&&
X9
&
/
/
X+
-3
9/('
$0Y
DocID18279 Rev 5 29/37
ST1CC40 Application information
37
Figure 17. PCB layout (component side) VFQFPN8 package
Table 8. Component list
Reference Part number Description Manufacturer
C1 100 nF 50 V
(size 0805)
C2 GRM31CR61E106KA12L 10 µF 25 V
(size 1206) Murata
C3 GRM21BR71E225KA73L 2.2 µF 25 V
(size 0805) Murata
R1 4.7 K5%
(size 0603)
R2 Not mounted
Rs ERJ14BSFR15U 0.151%
(size 1206) Panasonic
L1 XAL6060-223ME
22 µH
ISAT = 5.6 A (30% drop) IRMS = 6.9 A (40 C rise)
(size 6.36 x 6.56 x 6.1 mm)
Coilcraft
Application information ST1CC40
30/37 DocID18279 Rev 5
Figure 18. PCB layout (bottom side) VFQFPN8 package
Figure 19. PCB layout (component side) SO8 package
It is strongly recommended that the input capacitors are to be put as close as possible to the
relative pins, see C1 and C2.
DocID18279 Rev 5 31/37
ST1CC40 Application information
37
Figure 20. PCB layout (bottom side) SO8 package
Typical characteristics ST1CC40
32/37 DocID18279 Rev 5
8 Typical characteristics
Figure 21. Soft-start Figure 22. Inhibit operation
Figure 23. Thermal shutdown protection Figure 24. Hiccup current protection
Figure 25. OCP blanking time
Figure 26. Current regulation
AM12818v1
AM12819v1
AM12820v1
AM12821v1
130 ns typ.
AM12822v1
Vin 12V
Vled 7V
AM12823v1
DocID18279 Rev 5 33/37
ST1CC40 Package information
37
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 27. VFQFPN8 (4 x 4 x 1.08 mm) package outline
Table 9. VFQFPN8 (4 x 4 x 1.08 mm) package mechanical data
Symbol
Dimensions (mm)
Min. Typ. Max.
A 0.80 0.90 1.00
A1 0.02 0.05
A3 0.20
b 0.23 0.30 0.38
D 3.90 4.00 4.10
D2 2.82 3.00 3.23
E 3.90 4.00 4.10
E2 2.05 2.20 2.30
e0.80
L 0.40 0.50 0.60
Package information ST1CC40
34/37 DocID18279 Rev 5
Figure 28. SO8-BW package outline
Table 10. SO8-BW package mechanical data
Symbol
Dimensions (mm)
Min. Typ. Max.
A 135 1.75
A1 0.10 0.25
A2 1.10 1.65
B 0.33 0.51
C 0.19 0.25
D(1)
1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shouldn’t exceed 0.15 mm (.006 inch) in total (both sides).
4.80 5.00
E 3.80 4.00
e1.27
H 5.80 6.20
h 0.25 0.50
L 0.40 1.27
k 0° (min.), 8° (max.)
ddd 0.10
DocID18279 Rev 5 35/37
ST1CC40 Ordering information
37
10 Ordering information
Table 11. Ordering information
Order code Package Packaging
ST1CC40PUR VFQFPN8 4 x 4 8L Tape and reel
ST1CC40DR SO8-BW Tape and reel
Revision history ST1CC40
36/37 DocID18279 Rev 5
11 Revision history
Table 12. Document revision history
Date Revision Changes
04-Mar-2011 1Initial release.
21-Jun-2011 2 Updated coverpage
18-Oct-2012 3
Pin 2 operation has been updated:
Figure 1 and Ta ble 1 have been updated accordingly.
Figure 19 and Figure 20 have been added.
Minor text changes to improve the readability.
Status promoted from preliminary to production data.
04-Mar-2013 4
Updated Table 9: VFQFPN8 (4 x 4 x 1.08 mm) package mechanical
data and Section 7.1.2: Inductor and output capacitor selection.
Minor text changes to improve the readability.
18-Jun-2013 5
Unified package names in the whole document.
Updated Table 2 (changed “operating junction temperature range”
from -40 to 125 °C to -40 to 150 °C).
Updated Table 4 (updated data of IQST-BY symbol).
Updated Section 7.2 (replaced VCC by VINA).
Updated Section 9 (reversed order of Figure 27 and Table 9,
Figure 28 and Table 10, minor modifications).
Minor corrections throughout document.
DocID18279 Rev 5 37/37
ST1CC40
37
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