Low Capacitance, 4-/8-Channel,
±15 V/+12 V
i
CMOS Multiplexers
Data Sheet
ADG1208/ADG1209
Rev. E Document Feedback
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FEATURES
<1 pC charge injection over full signal range
1 pF off capacitance
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic compatible inputs
Rail-to-rail operation
Break-before-make switching action
Available in a 16-lead TSSOP, a 16-lead LFCSP, and a
16-lead SOIC
Typical power consumption < 0.03 µW
APPLICATIONS
Audio and video routing
Automatic test equipment
Data-acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
FUNCTIONAL BLOCK DIAGRAMS
ADG1208
S1
S8
D
ADG1209
S1A
S4B
DA
DB
S4A
S1B
1-OF-4
DECODER
1-OF-8
DECODER
A0 A1 ENA0 A1 A2 EN
05713-001
Figure 1.
GENERAL DESCRIPTION
The ADG1208 and ADG1209 are monolithic, iCMOS® analog
multiplexers comprising eight single channels and four differential
channels, respectively. The ADG1208 switches one of eight inputs
to a common output as determined by the 3-bit binary address
lines A0, A1, and A2. The ADG1209 switches one of four
differential inputs to a common differential output as determined
by the 2-bit binary address lines A0 and A1. An EN input on
both devices enable or disable the device. When disabled, all
channels are switched off. When on, each channel conducts
equally well in both directions and has an input signal range
that extends to the supplies.
The industrial CMOS (iCMOS) modular manufacturing
process combines high voltage complementary metal-oxide
semiconductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage devices has been able to achieve. Unlike analog
ICs using conventional CMOS processes, iCMOS components
can tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.
The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data acquisition
and sample-and-hold applications, where low glitch and fast
settling are required. Figure 2 shows that there is minimum
charge injection over the entire signal range of the device.
iCMOS construction also ensures ultralow power dissipation,
making the devices ideally suited for portable and battery-
powered instruments.
V
S
(V)
CHARGE INJECTI ON (p C)
1.0
0
–15 15
05713-051
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
–10 –5 0 5 10
MUX (SOURCE TO DRAIN)
T
A
=25°C
V
DD
= +15V
V
SS
=–15V
V
DD
= +5V
V
SS
=–5V
V
DD
= +12V
V
SS
= 0V
Figure 2. Source to Drain Charge Injection vs. Source Voltage
ADG1208/ADG1209 Data Sheet
Rev. E | Page 2 of 21
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 16
Test Circuits ..................................................................................... 17
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 21
REVISION HISTORY
6/2016—Rev. D to Rev. E
Changes to Analog Inputs Parameter, Table 3 .............................. 7
Added Digital Inputs Parameter, Table 3 ...................................... 7
Moved Figure 7 ............................................................................... 10
Change to Table 7 ........................................................................... 10
Deleted Table 8; Renumbered Sequentially ................................ 11
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
3/2016—Rev. C to Rev. D
Changes to Table 4 Title ................................................................... 8
Changes to Table 5 Title ................................................................... 9
Changes to Table 7 Title ................................................................. 10
Changes to Figure 7 ........................................................................ 11
Added Table 8; Renumbered Sequentially .................................. 11
Changes to Table 9 Title ................................................................. 12
8/2015—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Added Figure 4; Renumbered Sequentially .................................. 8
Changes to Table 4 ............................................................................ 8
Changes to Figure 5 .......................................................................... 9
Added Table 5; Renumbered Sequentially .................................... 9
Added Figure 7 ................................................................................ 10
Changes to Table 7 .......................................................................... 10
Changes to Figure 8 ........................................................................ 11
Added Table 8 .................................................................................. 11
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
1/2009—Rev. A to Rev. B
Change to IDD Parameter, Table 1 .................................................... 4
Change to IDD Parameter, Table 2 .................................................... 6
4/2007—Rev. 0 to Rev. A
Added 16-lead SOIC .......................................................... Universal
Changes to Table 1 ............................................................................. 3
Changes to Table 2 ............................................................................. 5
Changes to Figure 10 and Figure 11............................................. 10
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 18
4/2006—Revision 0: Initial Version
Data Sheet ADG1208/ADG1209
Rev. E | Page 3 of 21
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted. Temperature range is as follows: Y version: –40°C to +125°C.
Table 1.
Parameter +25ºC
−40ºC to
+85ºC
−40ºC to
+125ºC Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
V
SS
to V
DD
V
On Resistance, RON 120 Ω typ VS = ±10 V, IS = −1 mA, see Figure 31
200 240 270 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match Between Channels, ∆RON 3.5 Ω typ VS = ±10 V, IS = −1 mA
6 10 12 Ω max
On-Resistance Flatness, RFLAT (On) 20 Ω typ VS = −5 V/0 V/+5 V, IS = −1 mA
64
83
Ω max
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off)
±0.003
nA typ
V
D
= ±10 V, V
S
= −10 V, see Figure 32
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off ) ±0.003 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
ADG1208 ±0.1 ±0.6 ±1 nA max
ADG1209 ±0.1 ±0.6 ±1 nA max
Channel On Leakage, ID, IS (On) ±0.02 nA typ VS = VD = ±10 V, see Figure 33
ADG1208
±0.2
±1
nA max
ADG1209 ±0.2 ±0.6 ±1 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.0
V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH ±0.005 µA max VIN = VINL or VINH
±0.1 µA max
Digital Input Capacitance, CIN 2 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 80 ns typ RL = 300 Ω, CL = 35 pF
130 165 185 ns max VS = 10 V, see Figure 34
t
ON
(EN)
75
ns typ
R
L
= 300 Ω, C
L
= 35 pF
95 105 115 ns max VS = 10 V, see Figure 36
tOFF (EN) 83 ns typ RL = 300 Ω, CL = 35 pF
100 125 140 ns max VS = 10 V, see Figure 36
Break-Before-Make Time Delay, tBBM 25 ns typ RL = 300 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 10 V, see Figure 35
Charge Injection
0.4
pC typ
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF, see Figure 37
Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
Channel to Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
Total Harmonic Distortion Plus Noise 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz,
see Figure 41
−3 dB Bandwidth
550
MHz typ
R
L
= 50 Ω, C
L
= 5 pF, see Figure 39
CS (Off) 1 pF typ f = 1 MHz, VS = 0 V
1.5 pF max f = 1 MHz, VS = 0 V
CD (Off), ADG1208 6 pF typ f = 1 MHz, VS = 0 V
7 pF max f = 1 MHz, VS = 0 V
CD (Off), ADG1209 3.5 pF typ f = 1 MHz, VS = 0 V
4.5
pF max
f = 1 MHz, V
S
= 0 V
ADG1208/ADG1209 Data Sheet
Rev. E | Page 4 of 21
Parameter +25ºC
−40ºC to
+85ºC
−40ºC to
+125ºC Unit Test Conditions/Comments
CD, CS (On), ADG1208 7 pF typ f = 1 MHz, VS = 0 V
8 pF max f = 1 MHz, VS = 0 V
CD, CS (On), ADG1209 5 pF typ f = 1 MHz, VS = 0 V
6 pF max f = 1 MHz, VS = 0 V
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 0.002 µA typ Digital inputs = 0 V or VDD
1.0 µA max
IDD 220 µA typ Digital inputs = 5 V
380 µA max
ISS 0.002 µA typ Digital inputs = 0 V or VDD
1.0 µA max
I
SS
0.002
µA typ
Digital inputs = 5 V
1.0 µA max
VDD/VSS ±5/±16.5 V min/max |VDD| = |VSS|
1 Guaranteed by design, not subject to production test.
Data Sheet ADG1208/ADG1209
Rev. E | Page 5 of 21
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Temperature range is as follows: Y version: –40°C to +125°C.
Table 2.
Parameter +25ºC
−40ºC to
+85ºC
−40ºC to
+125ºC Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to VDD V
On Resistance, RON 300 Ω typ VS = 0 V to 10 V, IS = −1 mA, see Figure 31
475
567
625
Ω max
V
DD
= 10.8 V, V
SS
= 0 V
On-Resistance Match Between
Channels, ∆RON
5 Ω typ VS = 0 V to 10 V, IS = −1 mA
16 26 27 Ω max
On-Resistance Flatness, RFLAT (On) 60 Ω typ VS = 3 V/6 V/9 V, IS = −1 mA
LEAKAGE CURRENTS VDD = 13.2 V
Source Off Leakage, IS (Off) ±0.003 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off ) ±0.003 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
ADG1208
±0.1
±0.6
±1
nA max
ADG1209 ±0.1 ±0.6 ±1 nA max
Channel On Leakage ID, IS (On) ±0.02 nA typ VS = VD = 1 V or 10 V, see Figure 33
ADG1208 ±0.2 ±0.6 ±1 nA max
ADG1209 ±0.2 ±0.6 ±1 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, I
INL
or I
INH
±0.001
±0.1 µA max VIN = VINL or VINH
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS
1
Transition Time, tTRANSITION 100 ns typ RL = 300 Ω, CL = 35 pF
170 210 235 VS = 8 V, see Figure 34
tON (EN) 90 ns typ RL = 300 Ω, CL = 35 pF
110 140 160 VS = 8 V, see Figure 36
t
OFF
(EN)
105
ns typ
R
L
= 300 Ω, C
L
= 35 pF
130 155 175 VS = 8 V, see Figure 36
Break-Before-Make Time Delay, tBBM 45 ns typ RL = 300 Ω, CL = 35 pF
20 ns min VS1 = VS2 = 8 V, see Figure 35
Charge Injection −0.2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 37
Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
Channel to Channel Crosstalk
−85
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 40
−3 dB Bandwidth 450 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 39
CS (Off) 1.2 pF typ f = 1 MHz, VS = 6 V
1.8 pF max f = 1 MHz, VS = 6 V
CD (Off), ADG1208 7.5 pF typ f = 1 MHz, VS = 6 V
9 pF max f = 1 MHz, VS = 6 V
CD (Off), ADG1209 4.5 pF typ f = 1 MHz, VS = 6 V
5.5 pF max f = 1 MHz, VS = 6 V
CD, CS (On), ADG1208 9 pF typ f = 1 MHz, VS = 6 V
10.5 pF max f = 1 MHz, VS = 6 V
CD, CS (On), ADG1209 6 pF typ f = 1 MHz, VS = 6 V
7.5
pF max
f = 1 MHz, V
S
= 6 V
ADG1208/ADG1209 Data Sheet
Rev. E | Page 6 of 21
Parameter +25ºC
−40ºC to
+85ºC
−40ºC to
+125ºC Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = 13.2 V
IDD 0.002 µA typ Digital inputs = 0 V or VDD
1.0 µA max
IDD 220 µA typ Digital inputs = 5 V
380 µA max
VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V
1 Guaranteed by design, not subject to production test.
Data Sheet ADG1208/ADG1209
Rev. E | Page 7 of 21
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA (whichever occurs first)
Digital Inputs1 GND − 0.3 V to VDD + 0.3 V or
30 mA (whichever occurs first)
Continuous Current, S or D 30 mA
Peak Current, S or D (Pulsed at
1 ms, 10% Duty Cycle Maximum)
100 mA
Operating Temperature Range
Industrial (Y Version) −40°C to +125°C
Storage Temperature
−65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
TSSOP 112°C/W
LFCSP 30.4°C/W
SOIC 77°C/W
Reflow Soldering Peak
Temperature (Pb-Free)
260(+0/−5)°C
1 Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
ADG1208/ADG1209 Data Sheet
Rev. E | Page 8 of 21
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN
V
SS
S1
S4
S3
S2
A0
A2
GND
V
DD
S7
DS8
S6
S5
A1
ADG1208
TOP VIEW
(Not to Scale)
0
5713-002
Figure 3. 16-Lead TSSOP Pin Configuration (ADG1208)
0
5713-006
1
2
3
4
16
15
14
13
512
611
710
8 9
EN
V
SS
S1
S4
S3
S2
A0
A2
GND
V
DD
S7
DS8
S6
S5
A1
ADG1208
TOP VIEW
(Not to Scale)
Figure 4. 16-Lead SOIC Pin Configuration (ADG1208)
Table 4. 16-Lead TSSOP and 16-Lead SOIC Pin Function Descriptions (ADG1208)
Pin No. Mnemonic Description
1 A0 Logic Control Input.
2 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs
determine on switches.
3 VSS Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground.
4 S1 Source Terminal 1. Can be an input or an output.
5 S2 Source Terminal 2. Can be an input or an output.
6 S3 Source Terminal 3. Can be an input or an output.
7 S4 Source Terminal 4. Can be an input or an output.
8 D Drain Terminal. Can be an input or an output.
9 S8 Source Terminal 8. Can be an input or an output.
10 S7 Source Terminal 7. Can be an input or an output.
11 S6 Source Terminal 6. Can be an input or an output.
12 S5 Source Terminal 5. Can be an input or an output.
13 VDD Most Positive Power Supply Potential.
14 GND Ground (0 V) Reference.
15 A2 Logic Control Input.
16 A1 Logic Control Input.
Data Sheet ADG1208/ADG1209
Rev. E | Page 9 of 21
V
SS
S1
S2
S3
V
DD
GND
S5
S6
S4
D
S8
S7
A0
EN
A1
A2
05713-004
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
1. THE EXPOSED PAD IS CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER
JOINTS AND MAXIMUM THERMAL CAPABILITY,
IT IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, V
SS
.
ADG1208
TOP VIEW
(Not to Scale)
Figure 5. 16-Lead LFCSP Pin Configuration (ADG1208)
Table 5. 16-Lead LFCSP Pin Function Descriptions (ADG1208)
Pin No. Mnemonic Description
1 VSS Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground.
2 S1 Source Terminal 1. Can be an input or an output.
3 S2 Source Terminal 2. Can be an input or an output.
4 S3 Source Terminal 3. Can be an input or an output.
5 S4 Source Terminal 4. Can be an input or an output.
6 D Drain Terminal. Can be an input or an output.
7 S8 Source Terminal 8. Can be an input or an output.
8 S7 Source Terminal 7. Can be an input or an output.
9 S6 Source Terminal 6. Can be an input or an output.
10 S5 Source Terminal 5. Can be an input or an output.
11 VDD Most Positive Power Supply Potential.
12 GND Ground (0 V) Reference.
13 A2 Logic Control Input.
14 A1 Logic Control Input.
15 A0 Logic Control Input.
16 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs
determine on switches.
EPAD
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 6. ADG1208 Truth Table
A2 A1 A0 EN On Switch
X X X 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8
ADG1208/ADG1209 Data Sheet
Rev. E | Page 10 of 21
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN
V
SS
S1A
S4A
S3A
S2A
A0
GND
V
DD
S1B
S4B
DA DB
S3B
S2B
A1
ADG1209
TOP VIEW
(Not to Scale)
0
5713-003
Figure 6. 16-Lead TSSOP Pin Configuration (ADG1209)
0
5713-007
1
2
3
4
16
15
14
13
512
611
710
8 9
EN
VSS
S1A
S4A
S3A
S2A
A0
GND
VDD
S1B
S4B
DA DB
S3B
S2B
A1
ADG1209
TOP VIEW
(Not to Scale)
Figure 7.16-Lead SOIC Pin Configuration (ADG1209)
Table 7. 16-Lead TSSOP and 16-Lead SOIC Pin Function Descriptions (ADG1209)
Pin No. Mnemonic Description
1 A0 Logic Control Input.
2 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs
determine on switches.
3 VSS Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground.
4 S1A Source Terminal 1A. Can be an input or an output.
5 S2A Source Terminal 2A. Can be an input or an output.
6 S3A Source Terminal 3A. Can be an input or an output.
7 S4A Source Terminal 4A. Can be an input or an output.
8 DA Drain Terminal A. Can be an input or an output.
9 DB Drain Terminal B. Can be an input or an output.
10 S4B Source Terminal 4B. Can be an input or an output.
11 S3B Source Terminal 3B. Can be an input or an output.
12 S2B Source Terminal 2B. Can be an input or an output.
13 S1B Source Terminal 1B. Can be an input or an output.
14 VDD Most Positive Power Supply Potential.
15 GND Ground (0 V) Reference.
16 A1 Logic Control Input.
Data Sheet ADG1208/ADG1209
Rev. E | Page 11 of 21
V
SS
S1A
S2A
S3A
S1B
V
DD
S2B
S3B
S4A
DA
DB
S4B
A0
EN
A1
GND
05713-005
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
1. THE EXPOSED PAD IS CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER
JOINTS AND MAXIMUM THERMAL CAPABILITY,
IT IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, V
SS
.
ADG1209
TOP VIEW
(Not to Scale)
Figure 8. 16-Lead LFCSP Pin Configuration (ADG1209)
Table 8. 16-Lead LFCSP Pin Function Descriptions (ADG1209)
Pin No. Mnemonic Description
1 VSS Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground.
2 S1A Source Terminal 1A. Can be an input or an output.
3 S2A Source Terminal 2A. Can be an input or an output.
4 S3A Source Terminal 3A. Can be an input or an output.
5 S4A Source Terminal 4A. Can be an input or an output.
6 DA Drain Terminal A. Can be an input or an output.
7 DB Drain Terminal B. Can be an input or an output.
8 S4B Source Terminal 4B. Can be an input or an output.
9 S3B Source Terminal 3B. Can be an input or an output.
10 S2B Source Terminal 2B. Can be an input or an output.
11 S1B Source Terminal 1B. Can be an input or an output.
12 VDD Most Positive Power Supply Potential.
13 GND Ground (0 V) Reference.
14 A1 Logic Control Input.
15 A0 Logic Control Input.
16 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs
determine on switches.
EPAD
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 9. ADG1209 Truth Table
A1 A0 EN On Switch Pair
X X 0 None
0 0 1 1
0 1 1 2
1 0 1 3
1 1 1 4
ADG1208/ADG1209 Data Sheet
Rev. E | Page 12 of 21
TYPICAL PERFORMANCE CHARACTERISTICS
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
200
100
0
–18 –15 –12 –9 –6 –3 12 15906318
180
160
140
120
80
60
40
20
T
A
= 25°C V
DD
= +15V
V
SS
= –15V
V
DD
=+16.5V
V
SS
= –16.5V
V
DD
= +13.5V
V
SS
=–13.5V
05713-030
Figure 9. On Resistance as a Function of VD (VS) for Dual Supply
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
600
300
0
–6 –4 –2 402 6
500
400
200
100
TA= 25°C
VDD =+5V
VSS =–5V
VDD =+5.5V
VSS = –5.5V
VDD = +4.5V
VSS =–4.5V
05713-031
Figure 10. On Resistance as a Function of VD (VS) for Dual Supply
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
450
250
300
0
02 46 12810 14
400
350
150
200
100
50
T
A
= 25°C
V
DD
=12V
V
SS
=0V
V
DD
= 13.2V
V
SS
=0V
V
DD
=10.8V
V
SS
=0V
05713-032
Figure 11. On Resistance as a Function of VD (VS) for Single Supply
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
250
0
–15 –10 –5 1005 15
150
200
100
50
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
T
A
= –40°C
V
DD
= +15V
V
SS
= –15V
05713-033
Figure 12. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
SOURCE OR DRAIN VOLTAGE (V)
ON RESISTANCE (Ω)
600
0
024 1068 12
300
400
200
500
100
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
T
A
= –40°C
V
DD
= 12V
V
SS
= 0V
05713-034
Figure 13. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
400
–400
0 102030405060708090100110120
TEMPERATURE (°C)
LEAKAGE CURRENT (pA)
300
200
100
0
–100
–200
–300
I
S
(OFF) + –
I
D
(OFF) + –
I
D
,
S
(ON) + +
I
S
(OFF) – +
I
D
,
S
(ON) – –
I
D
(OFF) – +
05713-057
V
DD
= +15V
V
SS
= –15V
V
BIAS
= +10V/–10V
Figure 14. ADG1208 Leakage Currents as a Function of Temperature, Dual Supply
Data Sheet ADG1208/ADG1209
Rev. E | Page 13 of 21
150
–150
0 102030405060708090100110120
TEMPERATURE (°C)
LEAKAGE CURRENT (pA)
100
50
0
–50
–100
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
D
,
S
(ON) – –
I
D
,
S
(ON) + +
05713-058
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1V/10V
Figure 15. ADG1208 Leakage Currents as a Function of Temperature,
Single Supply
0
5713-035
LOGIC, IN
X
(V)
I
DD
(µA)
200
60
80
100
120
140
160
180
40
20
0
0 2 4 6 8 10121416
V
DD
= +12V
V
SS
=0V
V
DD
= +15V
V
SS
=–15V
I
DD
PER CHANNEL
T
A
=25C
Figure 16. IDD vs. Logic Level
VS(V)
CHARGE INJECTION (pC)
1.0
0
–15 15
05713-040
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
–10 –5 0 5 10
MUX (SOURCE TO DRAIN)
TA= 25°C
VDD = +15V
VSS = –15V
VDD =+5V
VSS = –5V
VDD = +12V
VSS =0V
Figure 17. Source-to-Drain Charge Injection vs. Source Voltage
VS(V)
CHARGE INJECTION (pC)
6
–6
–15 15
05713-041
–10 –5 0 5 10
DEMUX (DRAIN TO SOURCE)
TA= 25°C
4
2
0
–2
–4
VDD = +15V
VSS = –15V
VDD =+5V
VSS = –5V
VDD = +12V
VSS =0V
Figure 18. Drain-to-Source Charge Injection vs. Source Voltage
350
0
–40
TEMPERATURE (°C)
TIME (ns)
300
250
200
150
100
50
–20 020 40 60 80 100 120
V
DD
=+5V
V
SS
=–5V
V
DD
=+12V
V
SS
=0V
V
DD
= +15V
V
SS
= –15V
05713-052
Figure 19. tON/tOFF Times vs. Temperature
0
5713-049
FREQUENCY (Hz)
OFF ISOLATION (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
10k 100k 1M 10M 100M 1G
V
DD
=+15V
V
SS
= –15V
T
A
=25
C
Figure 20. Off Isolation vs. Frequency
ADG1208/ADG1209 Data Sheet
Rev. E | Page 14 of 21
FREQUENCY (Hz)
CROSSTALK (dB)
20
–120
10k 1G
05713-042
100k 1M 10M 100M
0
–20
–40
–60
–80
–100
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
ADJACENT CHANNELS
NONADJACENT
CHANNELS
Figure 21. ADG1208 Crosstalk vs. Frequency
0
–120
10k 1G
FREQUENCY (Hz)
CROSSTALK (dB)
–20
–40
–60
–80
–100
100k 1M 10M 100M
ADJACENT CHANNELS
NONADJACENT
CHANNELS
05713-053
Figure 22. ADG1209 Crosstalk vs. Frequency
–
6.0
–10.0
10k 1G
FREQUENCY (Hz)
ON RESPONSE (dB)
–6.5
–7.0
–7.5
–8.0
–8.5
–9.0
–9.5
100k 1M 10M 100M
05713-054
Figure 23. On Response vs. Frequency
FREQUENCY (Hz)
THD + N (%)
10
1
0.1
0.01
10 100 1k 10k 100k
LOAD = 10kΩ
T
A
= 25°C
V
DD
=+5V,V
SS
= –5V, V
S
= +3.5Vrms
V
DD
= +15V, V
SS
= –15V, V
S
=+5Vrms
05713-036
Figure 24. THD + N vs. Frequency
V
BIAS
(V)
CAPACITANCE (pF)
12
0
–15 15
05713-043
–10 –5 0 5 10
10
8
6
4
2
SOURCE/DRAIN ON
DRAIN OFF
SOURCE OFF
VDD = +15V
VSS = –15V
TA= 25°C
Figure 25. ADG1208 Capacitance vs. Source Voltage,
±15 V Dual Supply
VBIAS (V)
CAPACITANCE (pF)
12
0
012
05713-045
246810
10
8
6
4
2
VDD = 12V
VSS =0V
TA= 25°C
SOURCE/DRAIN ON
DRAIN OFF
SOURCE OFF
Figure 26. ADG1208 Capacitance vs. Source Voltage,
12 V Single Supply
Data Sheet ADG1208/ADG1209
Rev. E | Page 15 of 21
12
0
–5 5
V
BIAS
(V)
CAPACITANCE (pF)
10
8
6
4
2
–4 –3 –2 –1 0 1 2 3 4
V
DD
=+5V
V
SS
=–5V
T
A
= 25°C
SOURCE OFF
DRAIN OFF
SOURCE/DRAIN ON
05713-055
Figure 27. ADG1208 Capacitance vs. Source Voltage, ±5 V Dual Supply
V
BIAS
(V)
CAPACITANCE (pF)
8
0
–15 15
05713-046
–10 –5 0 5 10
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
7
6
5
4
3
2
1
SOURCE/DRAIN ON
DRAIN OFF
SOURCE OFF
Figure 28. ADG1209 Capacitance vs. Source Voltage, ±15 V Dual Supply
V
BIAS
(V)
CAPACITANCE (pF)
8
0
012
05713-047
246810
V
DD
= 12V
V
SS
=0V
T
A
= 25°C
7
6
5
4
3
2
1
SOURCE OFF
DRAIN OFF
SOURCE/DRAIN ON
Figure 29. ADG1209 Capacitance vs. Source Voltage, 12 V Single Supply
8
0
–5 5
V
BIAS
(V)
CAPACITANCE (pF)
–4 –3 –2 –1 0 1 2 3 4
V
DD
=+5V
V
SS
= –5V
T
A
=25°C
SOURCE OFF
DRAIN OFF
SOURCE/DRAIN ON
7
6
5
4
3
2
1
05713-056
Figure 30. ADG1209 Capacitance vs. Source Voltage, ±5 V Dual Supply
ADG1208/ADG1209 Data Sheet
Rev. E | Page 16 of 21
TERMINOLOGY
RON
Ohmic resistance between D and S.
ΔRON
Difference between the RON of any two channels.
IS (Off)
Source leakage current when the switch is off.
ID (Off)
Drain leakage current when the switch is off.
ID, IS (On)
Channel leakage current when the switch is on.
VD (VS)
Analog voltage on Terminal D, Terminal S.
CS (Off)
Channel input capacitance for off condition.
CD (Off)
Channel output capacitance for off condition.
CD, CS (On)
On switch capacitance.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
TBBM
Off time measured between the 80% point of both switches
when switching from one address state to another.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
IDD
Positive supply current.
ISS
Negative supply current.
Off Isolation
A measure of unwanted signal coupling through an off channel.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Total Harmonic Distortion Plus Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
Data Sheet ADG1208/ADG1209
Rev. E | Page 17 of 21
TEST CIRCUITS
I
DS
SD
V
S
V
05713-037
Figure 31. On Resistance
SD
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
05713-038
Figure 32. Off Leakage
SD
A
V
D
I
D
(ON)
NC
NC = NO CONNECT
05713-039
Figure 33. On Leakage
3V
0V
OUTPUT
tr
<20ns
tf
< 20ns
ADDRESS
DRIVE (V
IN
)
tTRANSITION tTRANSITION
50% 50%
90%
90%
OUTPUT
ADG1208
1
A0
A1
A2
50Ω
300Ω
GND
S1
S2–S7
S8
D
35pF
V
IN
2.4V EN
V
DD
V
SS
V
DD
V
SS
V
S1
V
S8
1
SIMILAR CONNECTION FOR ADG1209.
05713-022
Figure 34. Address to Output Switching Times, tTRANSITION
OUTPUT
ADG1208
1
A0
A1
A2
50Ω
300Ω
GND
S1
S2–S7
S8
D
35pF
V
IN
2.4V EN
V
DD
V
SS
V
DD
V
SS
V
S
1
SIMILAR CONNECTION FOR ADG1209.
3V
0V
OUTPUT
80% 80%
ADDRESS
DRIVE (V
IN
)
t
BBM
05713-023
Figure 35. Break-Before-Make Delay, tBBM
ADG1208/ADG1209 Data Sheet
Rev. E | Page 18 of 21
OUTPUT
ADG1208
1
A0
A1
A2
50Ω300Ω
GND
S1
S2–S8
D
35pF
V
IN
EN
V
DD
V
SS
V
DD
V
SS
V
S
1
SIMILAR CONNECTION FOR ADG1209.
3V
0V
O
UTPUT
50% 50%
t
OFF
(EN)
t
ON
(EN)
0.9V
O
0.9V
O
ENABLE
DRIVE (V
IN
)
05713-024
Figure 36. Enable Delay, tON (EN), tOFF (EN)
3V
V
IN
V
OUT
Q
INJ
=C
L
×∆V
OUT
∆V
OUT
DS
EN
GND C
L
1nF
V
OUT
V
IN
R
S
V
S
V
DD
V
SS
V
DD
V
SS
A0
A1
A2
ADG1208
1
1
SIMILAR CONNECTION FOR ADG1209.
05713-025
Figure 37. Charge Injection
Data Sheet ADG1208/ADG1209
Rev. E | Page 19 of 21
VOUT
50Ω
NETWORK
ANALYZER
RL
50Ω
S
D
50Ω
OFF ISOLATION = 20 log
VOUT
VS
VS
VDD VSS
0.1µF
V
DD
0.1µF
V
SS
GND
05713-026
Figure 38. Off Isolation
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
S
D
INSERTION LOSS = 20 log
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
05713-027
Figure 39. Bandwidth
CHANNEL-TO-CHANNEL CROSSTALK = 20 log V
OUT
GND
S1
D
S2
V
OUT
NETWORK
ANALYZER
R
L
50Ω
R
50Ω
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
05713-028
Figure 40. Channel to Channel Crosstalk
V
OUT
R
S
AUDIO PRECISION
R
L
10kΩ
IN
V
IN
S
D
V
S
V p-p
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
05713-029
Figure 41. THD + N
ADG1208/ADG1209 Data Sheet
Rev. E | Page 20 of 21
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 42. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.35
0.30
0.25
2.25
2.10 SQ
1.95
1
0.65
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
0.70
0.60
0.50
SEATING
PLANE
0.05 MAX
0.02 NOM
0.203 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGC.
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
04-15-2016-A
PKG-004025/5112
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
EXPOSED
PAD
Figure 43. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-23)
Dimensions shown in millimeters
Data Sheet ADG1208/ADG1209
Rev. E | Page 21 of 21
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AC
10.00 (0.3937)
9.80 (0.3858)
16 9
8
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
Figure 44. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG1208YRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1208YRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1208YCPZ-REEL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23
ADG1208YCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23
ADG1208YRZ −40°C to +125°C 16-Lead Narrow Body Small Outline Package [SOIC_N] R-16
ADG1208YRZ-REEL7 −40°C to +125°C 16-Lead Narrow Body Small Outline Package [SOIC_N] R-16
ADG1209YRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1209YRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1209YCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23
ADG1209YRZ −40°C to +125°C 16-Lead Narrow Body Small Outline Package [SOIC_N] R-16
ADG1209YRZ-REEL7 −40°C to +125°C 16-Lead Narrow Body Small Outline Package [SOIC_N] R-16
1 Z = RoHS Compliant Part.
©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05713-0-6/16(E)