SRC4192, SRC4193
SBFS022B
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The bit clock is either input or output at BCKO (pin 25). In
Slave mode, BCKO is configured as an input pin, and may
operate at rates from 32fS to 128fS, with a minimum of one
clock cycle for each data bit. The exception is the TDM
mode, where the BCKO must operate at N x 64fS, where N
is equal to the number of SRC4192 or SRC4193 devices
included on the TDM interface. In Master mode, BCKO
operates at a fixed rate of 64fS for all data formats except
TDM, where BCKO operates at the reference clock (RCKI)
frequency. Additional information regarding TDM mode op-
eration is included in the Applications Information section
of this data sheet.
The left/right word clock, LRCKO (pin 24), may be configured
as an input or output pin. In Slave mode, LRCKO is an input
pin, while in Master mode it is an output pin. In either case,
the clock rate is equal to fS, the output sampling frequency.
The clock duty cycle is fixed to 50% for I2S, Left justified, and
Right Justified formats in Master mode. The LRCKO pulse
width is fixed to 32 BCKO cycles for the TDM format in
Master mode.
Table 3 illustrates data format selection for the output port.
For the SRC4192, the OFMT0 (pin 19), OFMT1 (pin 18),
OWL0 (pin 17), and OWL1 (pin 16) inputs are utilized to set
the output port data format and word length. For the SRC4193,
the OFMT[1:0] and OWL[1:0] bits in Control Register 3 are
used to select the data format and word length.
SOFT MUTE FUNCTION
The soft mute function of the SRC4192 and SRC4193 may
be invoked by forcing the MUTE input (pin 14) high. For the
SRC4193, the mute function may also be accessed using the
MUTE bit in Control Register 1. The Soft mute function slowly
attenuates the output signal level down to all zeroes plus
±1LSB of dither. This provides an artifact-free muting of the
audio output port.
DIGITAL ATTENUATION (SRC4193 ONLY)
The SRC4193 includes independent digital attenuation for
the Left and Right audio channels. The attenuation ranges
from 0dB (or unity) to -127.5dB in 0.5dB steps. The attenu-
ation settings are programmed using Control Registers 4 and
5, corresponding to the Left and Right channels, respec-
tively.
The TRACK bit in Control Register 1 is used to select
Independent or Tracking attenuation modes. When TRACK
= 0, the Left and Right channels are controlled indepen-
dently. When TRACK = 1, the attenuation setting for the Left
channel is also used for the Right channel, and the Right
channel is said to track the Left channel attenuation setting.
READY OUTPUT
The SRC4192 and SRC4193 include an active low ready
output named
RDY
(pin 15). This is an output from the rate
estimator block, which indicates that the input-to-output sam-
pling frequency ratio has been determined. The ready signal
can be used as a flag or indicator output. The ready signal
can also be connected to the active high MUTE input (pin 14)
to provide an auto-mute function, so that the output port is
muted when the rate estimator is in transition.
RATIO OUTPUT (SRC4193 ONLY)
The SRC4193 includes a simple ratio flag output named
RATIO (pin 16). When RATIO is low, it indicates that the
output sampling frequency is lower than the input sampling
frequency. When RATIO is high, it indicates that the output
sampling frequency is higher than the input sampling fre-
quency. The ratio output can be used as an indicator or flag
output for an LED or host device.
SERIAL PERIPHERAL INTERFACE (SPI) PORT:
SRC4193 ONLY
The SPI port is a three-wire synchronous serial interface
used to access the on-chip control registers of the SRC4193.
The interface is comprised of a serial data clock input, CCLK
(pin 27), a serial data input, CDATA (pin 28), and an active
low chip-select input,
CS
(pin 26). Figure 8 illustrates the
protocol for writing control registers via the serial control port.
Figure 9 shows the critical timing parameters for the SPI port
interface, which are also listed in the Electrical Characteris-
tics table.
OFMT1 OFMT0 OUTPUT PORT DATA FORMAT
0 0 Left Justified
01 I
2S
1 0 TDM
1 1 Right Justified
OWL1 OWL0 OUTPUT PORT DATA WORD LENGTH
0 0 24-Bits
0 1 20-Bits
1 0 18-Bits
1 1 16-Bits
TABLE 2. Output Port Data Format Selection.
BYPASS MODE
The SRC4192 and SRC4193 include a bypass function,
which routes the input port data directly to the output port,
bypassing the ASRC function. Bypass mode may be invoked
by forcing the BYPAS input (pin 9) high for either the
SRC4192 or SRC4193. For the SRC4193, the bypass mode
may also be accessed using the BYPAS bit in Control
Register 1. For normal ASRC operation, the BYPAS pin and
control bit should be set to 0.
No dithering is applied to the output data in bypass mode,
and the digital attenuation and mute functions are also
unavailable.