DATASHEET 1024 Tap, Low Power, 2-Wire Interface, Digitally Controlled (XDCPTM) Potentiometer X9119 Features The X9119 integrates a single digitally controlled potentiometer (XDCPTM) on a monolithic CMOS integrated circuit. * 1024 resistor taps - 10-bit resolution The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile data registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. * Wiper resistance, 40 typical at VCC = 5V * 2-Wire serial interface for write, read, and transfer operations of the potentiometer The XDCPTM can be used as a 3-terminal potentiometer or as a 2-terminal variable resistor in a wide variety of applications including control, parameter adjustments and signal processing. * Four nonvolatile data registers * Nonvolatile storage of multiple wiper positions * Power-on recall, loads saved wiper position on power-up. * Standby current <3A maximum * VCC: 2.7V to 5.5V operation * 100k end-to-end resistance * 100 yr. data retention * Endurance: 100,000 data changes per bit per register * 14 Ld TSSOP * Low power CMOS * Single supply version of the X9118 * Pb-free available (RoHS compliant) VCC 2-WIRE BUS INTERFACE ADDRESS DATA STATUS RH BUS INTERFACE AND CONTROL WRITE READ TRANSFER CONTROL VSS NC POWER-ON RECALL 100k 1024-TAPS POT WIPER COUNTER REGISTER (WCR) DATA REGISTERS (DR0-DR3) NC WIPER RW RL FIGURE 1. FUNCTIONAL DIAGRAM July 5, 2016 FN8162.5 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2008, 2016. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. X9119 Applications System Level * Adjust the contrast in LCD displays Circuit Level * Vary the gain of a voltage amplifier * Control the power level of LED transmitters in communication systems * Provide programmable DC reference voltages for comparators and detectors * Set and regulate the DC biasing point in an RF power amplifier in wireless systems * Control the volume in audio circuits * Control the gain in audio and home entertainment systems * Trim out the offset voltage error in a voltage amplifier circuit * Provide the variable DC bias for tuners in RF wireless systems * Set the output voltage of a voltage regulator * Set the operating points in temperature control systems * Trim the resistance in Wheatstone bridge circuits * Control the operating point for sensors in industrial systems * Control the gain, characteristic frequency and Q-factor in filter circuits * Trim offset and gain errors in artificial intelligent systems * Set the scale factor and zero point in sensor signal conditioning circuits * Vary the frequency and duty cycle of timer ICs * Vary the DC biasing of a pin diode attenuator in RF circuits * Provide a control variable (I, V, or R) in feedback circuits Ordering Information PART NUMBER (Notes 2, 3) PART MARKING X9119TV14IZ X9119 TVZI X9119TV14Z X9119 TVZ X9119TV14Z-2.7 X9119 TVZF X9119TV14IZ-2.7 (Note 1) X9119 TVZG VCC LIMITS (V) POTENTIOMETER ORGANIZATION (k) 5 10% 100 2.7 to 5.5 TEMP RANGE (C) PACKAGE RoHS COMPLIANT -40 to +85 14 Ld TSSOP (4.4mm) PKG. DWG.# M14.173 0 to +70 14 Ld TSSOP (4.4mm) M14.173 0 to +70 14 Ld TSSOP (4.4mm) M14.173 -40 to +85 14 Ld TSSOP (4.4mm) M14.173 NOTES: 1. Add "T1" suffix for 2.5k unit tape and reel option. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for X9119. For more information on MSL, please see tech brief TB363. VCC POWER ON RECALL SCL SDA A2 A1 DR0 INTERFACE AND CONTROL CIRCUITRY DR1 DATA DR2 DR3 WIPER COUNTER REGISTER (WCR) RH 100k 1024-TAPS RL CONTROL A0 RW WP VSS FIGURE 2. DETAILED FUNCTIONAL DIAGRAM Submit Document Feedback 2 FN8162.5 July 5, 2016 X9119 DEVICE ADDRESS (A2-A0) Pin Configuration X9119 (14 LD TSSOP) TOP VIEW NC 1 14 VCC A0 NC 2 13 RL 3 12 RH A2 4 11 RW SCL 5 10 SDA VSS 6 9 8 NC A1 7 WP The Address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9119. A maximum of 8 devices may occupy the 2-wire serial bus. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW, prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Pin Assignments RW PIN NUMBER PIN NAME 1, 3, 10 NC No connect 2 A0 Device address for 2-wire bus Bias Supply Pins 4 A2 Device address for 2-wire bus 5 SCL Serial clock for 2-wire bus SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) 6 SDA Serial data input/output for 2-wire bus 7 VSS System ground 8 WP Hardware write protect Other Pins 9 A1 Device address for 2-wire bus NO CONNECT 11 RW Wiper terminal of the potentiometer 12 RH High terminal of the potentiometer No connect pins should be left open. These pins are used for Intersil manufacturing and testing purposes. 13 RL Low terminal of the potentiometer 14 VCC System supply voltage FUNCTION Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from a 2-wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open-drain output and may be wire-ORed with any number of open-drain or open collector outputs. An open-drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. SERIAL CLOCK (SCL) This input is used by a 2-wire master to supply a 2-wire serial clock to the X9119. Submit Document Feedback 3 The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. The VCC pin is the system supply voltage. The VSS pin is the system ground. Principals of Operation The X9119 is an integrated microcircuit incorporating a resistor array and its associated registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometer. This section provides detail description of the following: * Resistor Array Description * Serial Interface Description * Instruction and Register Description Resistor Array Description The X9119 is comprised of a resistor array. The array contains, in effect, 1023 discrete resistive segments that are connected in series (Figure 3 on page 4). The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches. FN8162.5 July 5, 2016 X9119 The WCR may be written directly. The data registers and the WCR can be read and written by the host system. Serial Interface Description SERIAL INTERFACE ACKNOWLEDGE Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9119 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9119 will be considered a slave device in all applications. The X9119 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9119 will respond with a final acknowledge (see Figure 4). CLOCK AND DATA CONVENTIONS ACKNOWLEDGE POLLING Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figure 6 on page 8). The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9119 initiates the internal write cycle. ACK polling, Flow 1 (see Figure 5 on page 5), can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9119 is still busy with the write operation, no ACK will be returned. If the X9119 has completed the write operation, an ACK will be returned and the master can then proceed with the next operation. START CONDITION All commands to the X9119 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9119 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met (Figure 6). STOP CONDITION All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 6). SERIAL DATA PATH RH SERIAL BUS INPUT FROM INTERFACE CIRCUITRY REGISTER 0 (DR0) REGISTER 1 (DR1) 10 REGISTER 2 (DR2) 10 REGISTER 3 (DR3) PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR) C O U N T E R D E C O D E R IF WCR = 000[HEX] THEN RW = RL IF WCR = 3FF[HEX] THEN RW = RH RL R W FIGURE 3. DETAILED POTENTIOMETER BLOCK DIAGRAM SERIAL INTERFACE DESCRIPTION Submit Document Feedback 4 FN8162.5 July 5, 2016 X9119 SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ST AR T ACKNO WLEDGE FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER NONVOLATILE WRITE COMMAND COMPLETED ENTER ACK POLLING ISSUE START ISSUE SLAVE ADDRESS ACK RETURNED? ISSUE STOP NO YES FURTHER OPERATION? NO YES ISSUE INSTRUCTION ISSUE STOP PROCEED PROCEED FIGURE 5. FLOW 1. ACK POLLING SEQUENCE Submit Document Feedback 5 FN8162.5 July 5, 2016 X9119 Instruction and Register Description Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A2-A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The R/W bit is the LSB and is be used to program the device for read or write operations. Device Addressing: Identification Byte (ID and A) Following a start condition, the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier. The ID[3:0] bits is the device ID for the X9119; this is fixed as 0101[B] (refer to Table 1). The A2-A0 bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A2-A0 input pins. The slave address is externally specified by the user. The X9119 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9119 to successfully continue the command sequence. INSTRUCTION BYTE AND REGISTER SELECTION The next byte sent to the X9119 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (IOP[2:0]). The RB and RA bits point to one of the four registers. The format is shown in Table 2. Table 3 provides a complete summary of the instruction set opcodes. TABLE 1. IDENTIFICATION BYTE FORMAT INTERNAL SLAVE ADDRESS DEVICE TYPE IDENTIFIES ID3 ID2 ID1 ID0 0 1 0 1 A2 A1 READ OR WRITE BIT A0 (MSB) R/W (LSB) TABLE 2. INSTRUCTION BYTE FORMAT INSTRUCTION OPCODE I2 REGISTER SELECTION I1 I0 0 RB RA 0 (MSB) 0 (LSB) REGISTER SELECTED RB RA DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1 TABLE 3. INSTRUCTION SET INSTRUCTION SET INSTRUCTION R/W I2 I1 I0 0 RB RA 0 0 OPERATION Read Wiper Counter Register 1 1 0 0 0 0 0 0 0 Read the contents of the wiper counter register. Write Wiper Counter Register 0 1 0 1 0 0 0 0 0 Write new value to the wiper counter register. Read Data Register 1 1 0 1 0 1/0 1/0 0 0 Read the contents of the data register pointed to RB-RA. Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the data register pointed to RB-RA. XFR Data Register to Wiper Counter Register 1 1 1 0 0 1/0 1/0 0 0 Transfer the contents of the data register pointed to by RB-RA to the wiper counter register. XFR Wiper Counter Register to Data Register 0 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the wiper counter register to the data register pointed to by RB-RA. NOTE: 1/0 = data is one or zero. Submit Document Feedback 6 FN8162.5 July 5, 2016 X9119 Instruction and Register Description Four of the six instructions are four bytes in length. These instructions are: Device Addressing * Read Wiper Counter Register - Reads the current wiper position of the selected potentiometer. WIPER COUNTER REGISTER (WCR) * Write Wiper Counter Register - Changes current wiper position of the selected potentiometer. The X9119 contains a wiper counter register (refer to Table 4) for the XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. The contents of the WCR can be altered in one of three ways: 1. It may be written directly by the host via the write wiper counter register instruction (serial load). 2. It may be written indirectly by transferring the contents of one of four associated data registers via the XFR data register. 3. It is loaded with the contents of its data register zero (R0) upon power-up. The wiper counter register is a volatile register; that is, its contents are lost when the X9119 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR. DATA REGISTERS (DR0 TO DR3) The potentiometer has four 10-bit nonvolatile data registers. These can be read or written directly by the host. Data can also be transferred between any of the four data registers and the wiper counter register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bit 9 to Bit 0 are used to store one of the 1024 wiper position (0 ~1023). * Read Data Register - Reads the contents of the selected Data Register. * Write Data Register - Writes a new value to the selected Data Register. The basic sequence of the four byte instructions is illustrated in Figure 6 on page 8. These 4-byte instructions exchange data between the WCR and one of the data registers. A transfer from a data register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a data register is a write-to-nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers. Two instructions (Figure 7 on page 8) require a 2-byte sequence to complete. These instructions transfer data between the host and the X9119; either between the host and one of the data registers or directly between the host and the wiper counter register. These instructions are: * XFR Data Register to Wiper Counter Register - This transfers the contents of one specified data register to the wiper counter register. * XFR Wiper Counter Register to Data Register - This transfers the contents of the wiper counter register to the specified data register. See "Instruction Format" on page 8 for more details. POWER-UP AND POWER-DOWN REQUIREMENTS There are no restrictions on the power-up condition of VCC and the voltages applied to the potentiometer pins provided that the VCC is always more positive than or equal to the voltages at RH, RL, and RW, i.e., VCC RH, RL, RW. There are no restrictions on the power-down condition. However, the datasheet parameters for the DCP do not apply until 1ms after VCC reaches its final value. TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9-WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V) WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 V V V V V V V V V V (MSB) (LSB) TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9-BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE, NV) BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NV NV NV NV NV NV NV NV NV NV MSB Submit Document Feedback LSB 7 FN8162.5 July 5, 2016 X9119 SCL SDA 0 0 1 1 S ID3 ID2 ID1 ID0 A2 A1 A0 R/W T A INTERNAL DEVICE ID R ADDRESS T I2 A C K I0 I1 0 0 0 RB RA 0 INSTRUCTION OPCODE 0 A C K REGISTER ADDRESS S T O P FIGURE 6. TWO-BYTE INSTRUCTION SEQUENCE SCL 0 SDA 1 0 1 0 0 X X 0 0 X S ID3 ID2 ID1 ID0 A2 A1 A0 R/W A I2 I1 I0 0 RB RA 0 C T K A DEVICE ID INTERNAL INSTRUCTION REGISTER R ADDRESS OPCODE ADDRESS T X X X X X A C K W C R 9 W A W W W C C C C C R K R R R 8 7 6 5 W C R 4 W C R 3 W C R 2 W C R 1 S T O P W A C C R K 0 WIPER OR DATA POSITION FIGURE 7. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS) Instruction Format READ WIPER COUNTER REGISTER (WCR) INSTRUCTION OPCODE R/W=1 DEVICE TYPE DEVICE IDENTIFIER ADDRESSES S T A 0 1 0 1 A2 A1 A0 R T S A C K 1 0 0 0 0 0 0 WIPER POSITION (SENT BY SLAVE ON SDA) WIPER POSITION (SENT BY SLAVE ON SDA) REGISTER ADDRESSES 0 S A C K X X X X X X W C R 8 W C R 9 M A C K W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 M A C K S T O P S A C K S T O P WRITE WIPER COUNTER REGISTER (WCR) 0 1 0 INSTRUCTION OPCODE DEVICE ADDRESSES 1 A2 A1 A0 R/W=0 DEVICE TYPE IDENTIFIER S T A R T S A C K 1 0 1 WIPER POSITION (SENT BY MASTER ON SDA) REGISTER ADDRESSES 0 0 0 0 0 S W A X X X X X X C C R K 9 W C R 8 WIPER POSITION (SENT BY MASTER ON SDA) S W W A C C C R R K 7 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 READ DATA REGISTER (DR) 0 1 0 DEVICE ADDRESSES 1 A2 A1 A0 INSTRUCTION OPCODE S A C K R/W=1 DEVICE TYPE IDENTIFIER S T A R T 1 0 1 0 REGISTER ADDRESSES RB RA 0 0 S A C K WIPER POSITION OR DATA (SENT BY SLAVE ON SDA) WIPER POSITION (SENT BY SLAVE ON SDA) X X X X X M W W A W W W W W W W W CR CR CR CR CR CR CR CR X CR CR C 7 6 5 4 3 2 1 0 9 8 K M A C K S T O P DEVICE TYPE IDENTIFIER INSTRUCTION OPCODE DEVICE ADDRESSES 0 1 0 1 A2 A1 A0 Submit Document Feedback R/W=0 S T A R T S A C K 8 1 1 0 0 REGISTER ADDRESSES WIPER POSITION OR DATA (SENT BY MASTER ON SDA) S W RB RA 0 0 A X X X X X X C C R K 9 W C R 8 WIPER POSITION OR DATA (SENT BY MASTER ON SDA) S W W A C C C R R K 7 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 S S A T C O K P HIGH-VOLTAGE WRITE CYCLE WRITE DATA REGISTER (DR) FN8162.5 July 5, 2016 X9119 TRANSFER WIPER COUNTER REGISTER (WCR) TO DATA REGISTER (DR) DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES A2 1 S A C K R/W=0 S T A R T A0 INSTRUCTION OPCODE 1 1 1 REGISTER ADDRESSES 0 RB RA 0 0 S A C K S T O P HIGH-VOLTAGE WRITE CYCLE TRANSFER DATA REGISTER (DR) TO WIPER COUNTER REGISTER (WCR) DEVICE TYPE IDENTIFIER 0 1 0 DEVICE ADDRESSES 1 A2 A1 A0 R/W=1 S T A R T S A C K INSTRUCTION OPCODE 1 1 0 0 REGISTER ADDRESSES RB RA 0 0 S S A T C O K P NOTES: 4. A2 ~ A0": stand for the device addresses sent by the master. 5. WCRx refers to wiper position data in the wiper counter register. Submit Document Feedback 9 FN8162.5 July 5, 2016 X9119 Absolute Maximum Ratings Thermal Information Voltage on SCL, SDA, or any address input with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1V to +7V V = | (VH-VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Operating Conditions Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85C Supply Voltage (VCC) Limits (Note 9) X9119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10% X9119-2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Analog Specifications PARAMETER (Over recommended operation conditions unless otherwise stated.) SYMBOL End-to-End Resistance TEST CONDITIONS MIN (Note 13) RTOTAL TYP 100 End-to-End Resistance Tolerance Power Rating +25C, each pot Wiper Current IW Wiper Resistance RW Voltage on any RH or RL Pin V TERM Noise % 50 mW 3 mA Wiper Current = 50A, VCC = 3V 150 300 5 V VSS = 0V VSS Rw(n)(actual) - Rw(n)(expected) (Note 9) -120 dBV 0.1 % 1.5 Rw(m + 1) - [Rw(m) + MI], where m = 8 to 1006 Rw(m + 1) - [Rw(m) + MI] (Note 9) Temperature Coefficient of RTOTAL Ratiometric Temperature Coefficient CH/CL/CW 20 110 Rw(n)(actual) - Rw(n)(expected), where n = 8 to 1006 Potentiometer Capacitances k 40 Resolution Relative Linearity (Note 7) UNIT Wiper Current = 50A, VCC = 5V Ref: 1V Absolute Linearity (Note 6) MAX (Note 13) See Macro model 0.5 1.5 MI (Note 8) 2.0 MI (Note 8) 0.5 MI (Note 8) 1.0 MI (Note 8) 300 ppm/C 20 ppm/C 10/10/25 pF NOTES: 6. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage as determined by wiper position when used as a potentiometer. 7. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 8. MI = RTOT/1023 or (RH - RL)/1023, single potentiometer 9. n = 0, 1, 2, ...,1023; m = 0, 1, 2, ..., 1022. 10. ESD Rating on RH, RL, RW pins is 1.5kV (HBM, 1.0A leakage maximum), ESD rating on all other pins is 2.0kV. Submit Document Feedback 10 FN8162.5 July 5, 2016 X9119 Operating Specifications (Over the recommended operating conditions unless otherwise specified.) PARAMETER SYMBOL TEST CONDITIONS VCC Supply Current (Active) ICC1 VCC Supply Current (Nonvolatile Write) MIN TYP MAX UNIT fSCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, active, read and volatile write states only) 3 mA ICC2 fSCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, active, non-volatile write state only) 5 mA VCC Current (Standby) ISB VCC = +5.5V; VIN = VSS or VCC; SDA = VCC; (for 2-wire, standby state only) 3 A Input Leakage Current ILI VIN = VSS to VCC 10 A Output Leakage Current ILO VOUT = VSS to VCC 10 A Input HIGH Voltage VIH VCC x 0.7 VCC + 1 V Input LOW Voltage VIL -1 VCC x 0.3 V Output LOW Voltage VOL 0.4 V Output HIGH Voltage VOH IOL = 3mA Endurance and Data Retention PARAMETER Minimum Endurance Data Retention MIN UNITS 100,000 Data changes per bit per register 100 years Capacitance TEST SYMBOL Input/Output Capacitance (SI) CIN/OUT (Note 11) Input Capacitance (SCL, WP, A1 and A0) CIN (Note 11) TEST CONDITIONS MAX UNIT VOUT = 0V 8 pF VIN = 0V 6 pF Power-Up Timing PARAMETER SYMBOL MIN MAX UNIT VCC Power-Up Rate tr VCC (Note 11) 0.2 50 V/ms Power-Up to Initiation Of Read Operation tPUR (Note 12) 1 ms Power-Up to Initiation Of Write Operation tPUW (Note 12) 50 ms NOTES: 11. Limits should be considered typical and are not production tested. 12. tPUR and tPUW are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be issued. These parameters are not 100% tested. 13. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. AC Test Conditions Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level VCC x 0.5 Submit Document Feedback 11 FN8162.5 July 5, 2016 X9119 Equivalent A.C. Load Circuit 5V 3V 1533 SPICE MACROMODEL 867 RTOTAL RL RH SDA OUTPUT SDA OUTPUT 100pF CW CL 10pF CL 10pF 25pF 100pF RW AC Timing High-Voltage Write Cycle Timing PARAMETER SYMBOL MIN MAX UNIT 400 kHz Clock Frequency fSCL Clock Cycle Time tCYC 2500 ns Clock High Time tHIGH 600 ns Clock Low Time tLOW 1300 ns Start Set-Up Time tSU:STA 600 ns Start Hold Time tHD:STA 600 ns Stop Set-Up Time tSU:STO 600 ns SDA Data Input Set-Up Time tSU:DAT 100 ns SDA Data Input Hold Time tHD:DAT 0 ns SCL and SDA Rise Time tR 300 ns SCL and SDA Fall Time tF 300 ns SCL Low to SDA Data Output Valid Time tAA 250 ns SDA Data Output Hold Time tDH 0 ns TI 50 ns tBUF 1300 ns A0, A1, A2 Set-Up Time tSU:WPA 0 ns A0, A1, A2 Hold Time tHD:WPA 0 ns SYMBOL TYP MAX UNIT tWR 5 10 ms SYMBOL MIN MAX UNIT tWRPO 5 10 s tWRL 5 10 s Noise Suppression Time Constant at SCL and SDA Inputs Bus Free Time (Prior to Any Transmission) High-Voltage Write Cycle Timing PARAMETER High-Voltage Write Cycle Time (Store Instructions) XDCP Timing PARAMETER Wiper Response Time After the Third (Last) Power Supply is Stable Wiper Response Time After Instruction Issued (All Load Instructions) Submit Document Feedback 12 FN8162.5 July 5, 2016 X9119 Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don't Care: Changes Allowed Changing: State Not Known N/A Center Line is HIGH Impedance Timing Diagrams ( START) (STOP) tR tF SCL tSU:STA tHD:STA tSU:STO tR tF SDA FIGURE 8. START AND STOP TIMING tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF FIGURE 9. INPUT TIMING SCL SDA tAA tDH FIGURE 10. OUTPUT TIMING Submit Document Feedback 13 FN8162.5 July 5, 2016 X9119 Timing Diagrams (STOP) SCL LSB SDA tWRL RW FIGURE 11. XDCP TIMING (FOR ALL LOAD INSTRUCTIONS) (START) (STOP) SCL ... (ANY INSTRUCTION) ... SDA ... TSU:WPA THD:WPA WP A0, A1, A2 FIGURE 12. WRITE PROTECT AND DEVICE ADDRESS PINS TIMING Submit Document Feedback 14 FN8162.5 July 5, 2016 X9119 Applications information Basic Configurations of Electronic Potentiometers +VR VR RW I FIGURE 13. THREE-TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER FIGURE 14. TWO-TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT Application Circuits VS + VIN VO - VO (REG) 317 R1 R2 IADJ R2 R1 VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO = (1+R2/R1)VS FIGURE 15. NONINVERTING AMPLIFIER R1 FIGURE 16. VOLTAGE REGULATOR R2 VS - VS + 100k VO - VO + +12V 10k } 10k } TL072 10k R1 R2 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) -12V FIGURE 17. OFFSET VOLTAGE ADJUSTMENT Submit Document Feedback 15 FIGURE 18. COMPARATOR WITH HYSTERESIS FN8162.5 July 5, 2016 X9119 Application Circuits (Continued) C + VS R2 R1 - R VO + VS VO - R3 R2 R4 R1 = R2 = R3 = R4 = 10k R1 GO = 1 + R2/R1 fc = 1/(2pRC) VO = G VS -1/2 G +1/2 FIGURE 19. ATTENUATOR FIGURE 20. FILTER R2 R2 } VS R1 } C1 + VS - R1 ZIN - VO + R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VO = G VS G = - R2/R1 FIGURE 21. INVERTING AMPLIFIER FIGURE 22. EQUIVALENT L-R CIRCUIT C R2 - + R1 - } RA + } RB FREQUENCY R1, R2, C AMPLITUDE RA, RB FIGURE 23. FUNCTION GENERATOR Submit Document Feedback 16 FN8162.5 July 5, 2016 X9119 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION July 5, 2016 FN8162.5 CHANGE Updated entire datasheet applying Intersil's new standards. Updated title. Updated Ordering Information table by removing obsolete parts, updating Note 1 and adding Note 3. Removed Lead temperature (soldering, 10s) from the Thermal Information section on page 10. Updated Absolute Linearity maximum specification from "1" to "1.5". Added Revision History and About Intersil sections. Updated POD to the latest revision changes are as follows: Updated drawing to remove table and added land pattern. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 17 FN8162.5 July 5, 2016 X9119 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 0.10 14 SEE DETAIL "X" 8 6.40 PIN #1 I.D. MARK 4.40 0.10 2 3 1 0.20 C B A 7 B 0.65 0.09-0.20 TOP VIEW END VIEW 1.00 REF 0.05 H C 0.90 +0.15/-0.10 1.20 MAX SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 GAUGE PLANE 0.25 5 0-8 0.05 MIN 0.15 MAX CBA SIDE VIEW 0.60 0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 18 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. FN8162.5 July 5, 2016