LTC4421
1
Rev. 0
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TYPICAL APPLICATION
FEATURES DESCRIPTION
High Power Prioritized
PowerPath Controller
The LTC
®
4421 connects one of two input supplies to a
common output based on user-defined priority and valid-
ity. By definition, the supply connected to V1 is the higher
priority supply, although this can be changed dynamically.
External resistive dividers set the undervoltage and over-
voltage thresholds that bound the valid voltage window.
Strong gate drivers switch the large external N-channel
MOSFETs quickly. Fast switchover circuitry minimizes
output droop when changing channels while preventing
reverse and cross conduction. A fast comparator detects
input short circuits and quickly turns off the N-channel
MOSFETs to minimize disruption.
External sense resistors set the maximum inrush and cur-
rent limit currents. During current limiting, the LTC4421
controls the N-channel MOSFET gate to regulate 25mV
across the sense resistor. When the sense resistor voltage
has been regulated to 25mV for a user-settable time, the
channel is disconnected and a fault is set.
APPLICATIONS
n 0V to 36V Wide Operating Range (60V Tolerant)
n Drives Large External N-Channel MOSFETs for High
Output Current Applications
n Accurately Limits Inrush Current
n Connects Highest Priority Valid Supply to Output Load
n Changes Channel Priority in Real Time
n ±2% OV, UV Input Comparators
n Individually Adjustable Current Limit Time-Out for
Each Channel
n Adjustable Input Validation Time
n Fast Switchover Minimizes VOUT Droop
n 36-Lead 5mm × 6mm QFN and SSOP Packages
n High Reliability Systems
n Server Based Back-Up Systems
n Industrial Handheld Instruments
n Battery Back-Up Systems
All registered trademarks and trademarks are the property of their respective owners.
4421 TA01
35.7k
12.7k
20k
1MΩ
16.5k
3.92k
8.06k
1MΩ
0.1µF
1µF
1.21Ω
1µF
1µF
470pF
220µF
2.5mΩ
2.5mΩ
GATE1
SOURCE1
OUT2
GATE2
SOURCE2
V1
EXTVCC
INTVCC
TMR1
OV1
OV2
V2
CPO
SENSE1
SENSE2
VALID1
VALID2
GND
FAULT1
FAULT2
CH1
CH2
DISABLE1
DISABLE2
SHDN
UVF1
UVF2
UVR1
UVR2
OUT1
TMR2
CASIN
CASOUT
QUAL
RETRY
CPOREF
PRIMARY
ILIM1 = 10A
ILIM2 = 10A
12V
VOUT
SECONDARY
28V
LTC4421
DIGITAL
STATUS
OUTPUTS
DIGITAL
CONTROL
INPUTS
UV1FALLING = 7.81V
UV1RISING = 11.04V
OV1RISING = 14.96V
UV2FALLING = 18.1V
UV2RISING = 25.2V
OV2RISING = 31.2V
2.8Ω
1µF
LTC4421
2
Rev. 0
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PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
V1, V2, EXTVCC ........................................ –10V to 60V
OUT1, OUT2, CPOREF .............................. –10V to 45V
Input Voltages
DISABLE1, DISABLE2, SHDN… .............. –0.3V to 60V
CASIN ...................................................... –0.3V to 6V
SENSE1, SENSE2, SOURCE1, SOURCE2 ..–10V to 45V
UVF1, UVF2, UVR1, UVR2, OV1, OV2 .... –0.3V to 60V
RE TRY, TMR1, TMR2, QUAL....–0.3V to INTVCC+0.3V
Output Voltages
VALID1, VALID2, CH1, CH2,
FA U LT1 , FAU LT2 , CPO ............................. –0.3V to 60V
INTVCC ..................................................... –0.3V to 6V
(Notes 1, 2)
GATE1, GATE2 (Note 3) .............................–0.3V to CPO
CASOUT… ................................................... –0.3V to 6V
Output Currents
FA U LT1 , FAU LT2 , CH1, CH2, VALID1, VALID2,
CASOUT ............................................................... 5mA
Operating Ambient Temperature Range
LTC4421C ................................................ 0°C to 70°C
LTC4421I .............................................–40°C to 85°C
LTC4421H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
11 12 13 14
TOP VIEW
37
UHE PACKAGE
36-LEAD (5mm × 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 43°C/W, θJC = 5°C/W
EXPOSED PAD (Pin 37), PCB GND CONNECTION OPTIONAL
15 16 17 18
36 35 34 33 32 31 30 29
21
22
23
24
25
26
27
28
8
7
6
5
4
3
2
1SOURCE1
GATE1
V1
UVF1
UVR1
OV1
TMR1
DISABLE1
CH1
VALID1
SOURCE2
GATE2
V2
UVF2
UVR2
OV2
TMR2
DISABLE2
CH2
VALID2
SENSE1
OUT1
CPOREF
CPO
EXTVCC
GND
OUT2
SENSE2
FAULT1
CASIN
INTVCC
CASOUT
QUAL
RETRY
SHDN
FAULT2
20
19
9
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TOP VIEW
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 70°C/W
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
CPO
CPOREF
OUT1
SENSE1
SOURCE1
GATE1
V1
UVF1
UVR1
OV1
TMR1
DISABLE1
CH1
VALID1
FAULT1
CASIN
INTVCC
CASOUT
EXTVCC
GND
OUT2
SENSE2
SOURCE2
GATE2
V2
UVF2
UVR2
OV2
TMR2
DISABLE2
CH2
VALID2
FAULT2
SHDN
RETRY
QUAL
LTC4421
3
Rev. 0
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ORDER INFORMATION
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN V1, V2 Operating Voltage Range (Note 4) l3.0 36 V
VINT(UVL) INTVCC Undervoltage Lockout Threshold Voltage l2 2.3 2.6 V
ΔVINT(HYS) INTVCC Undervoltage Lockout Hysteresis 70 mV
VINTVCC INTVCC Output Voltage IINTVCC = 0µA l3.3 3.9 4.5 V
ΔVINTVCC INTVCC Voltage Change from Zero to Full Load IINTVCC = 0 to –500µA l–35 –85 –200 mV
VCPO(UVL) CPOGOOD Threshold Voltage CPO–CPOREF l5.7 6.7 7.7 V
VCPO(HYS) CPOGOOD Hysteresis 1.4 V
ICC(TOT) Total Input Supply Current V1, V2, OUT1, OUT2, EXTVCC, CPOREF l0.53 1 mA
ICC(SHDN) Total Input Supply Current in Shutdown V1, V2, EXTVCC l5.4 12 µA
ICC(PRIO) Input Supply Current of Highest Priority Valid
Supply
Measure I(EXTVCC)l360 750 µA
ICC(VMAX) Input Supply Current of Highest Voltage Input
Supply
Measure I(V2) l25 50 µA
ICC(CPOREF) CPOREF Charge Pump Supply Current CPOREF = 11V l160 300 µA
PRIORITIZER CONTROL (V1, V2, SENSE1, SENSE2, GATE1, GATE2, SOURCE1, SOURCE2, OUT1, OUT2)
ΔVG(OFF) External N-Channel MOSFET Off Threshold
Voltage
(GATE1 – V1), (GATE2 – V2), GATE Falling l0 –0.6 –1.5 V
ΔVREV Input to Output Reverse Voltage Connect Threshold (V1– OUT1), (V2–OUT2), OUT1, OUT2 Falling l0 40 80 mV
ΔVGATE(CL) External N-Channel MOSFET Gate Drive,
(GATE – CPOREF)
CPOREF = 3.2V, EXTVCC = 3.0V, I = 0, –1µA
CPOREF = 12V, 36V, I = 0, –1µA
l
l
9
10
10.8
11.6
14
14
V
V
ISOURCE, HLD SOURCE Hold Current SOURCE = 12V, Channel Off l2.5 5 10 µA
ISOURCE, OFF SOURCE Fast Off Current SOURCE = 12V, Channel Off l0.7 1.6 3.2 mA
IGATE(ON) GATE On Pull-Up Current V(SENSE) – V(OUT) = 0V, GATE = 16V,
OUT = 10V, V1 = V2 = 12V
l–8 –16.5 –26 mA
IGATE(OFF,FWD) GATE Off Pull-Down Current, Large Forward
Sense Voltage
V(SENSE)–V(OUT) = 100mV, GATE = 16V,
OUT = 10V, V1 = V2 = 12V
l30 54 124 mA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. See the LTC4421 Data Sheet Nomenclature section for more details on pin
conditions. V1 = 12V, V2 = 13V, EXTVCC = CPOREF = OUT1 = OUT2 = SENSE1 = SENSE2 = 11V, OV1 = OV2 = TMR1 = TMR2 = OV, UVR1 =
UVR2 = UVF1 = UVF2 = DISABLE1 = DISABLE2 = SHDN = RETRY = CASIN = 4V, CPO = 23.5V, QUAL = INTVCC, unless otherwise noted.
TUBE TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4421CG#PBF LTC4421CG#TRPBF LTC4421G 36-Lead Plastic SSOP 0°C to 70°C
LTC4421IG#PBF LTC4421IG#TRPBF LTC4421G 36-Lead Plastic SSOP –40°C to 85°C
LTC4421HG#PBF LTC4421HG#TRPBF LTC4421G 36-Lead Plastic SSOP –40°C to 125°C
LTC4421CUHE#PBF LTC4421CUHE#TRPBF 4421 36-Lead Plastic QFN 0°C to 70°C
LTC4421IUHE#PBF LTC4421IUHE#TRPBF 4421 36-Lead Plastic QFN –40°C to 85°C
LTC4421HUHE#PBF LTC4421HUHE#TRPBF 4421 36-Lead Plastic QFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
LTC4421
4
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. See the LTC4421 Data Sheet Nomenclature section for more details on pin
conditions. V1 = 12V, V2 = 13V, EXTVCC = CPOREF = OUT1 = OUT2 = SENSE1 = SENSE2 = 11V, OV1 = OV2 = TMR1 = TMR2 = OV, UVR1 =
UVR2 = UVF1 = UVF2 = DISABLE1 = DISABLE2 = SHDN = RETRY = CASIN = 4V, CPO = 23.5V, QUAL = INTVCC, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IGATE(OFF,REV) GATE Off Pull-Down Current, Negative Sense
Voltage
V(SENSE)–V(OUT) = –50mV, GATE = 16V,
OUT = 10V, V1 = V2 = 12V
l30 50 92 mA
ΔVSNS Current Limit Sense Voltage,
ΔVSNS = (SENSE – OUT)
OUT = 1V, 12V, 32V
EXTVCC = 3.0V, OUT = 1V
l
l
20
20
25
25
30
30
mV
mV
ΔVSNS,FLD Current Limit Sense Voltage in Foldback,
ΔVSNS,FLD = (SENSE – OUT)
OUT = 0V l7.5 12.5 17.5 mV
VFLD,TH Foldback Threshold Voltage OUT1 l380 480 580 mV
VFLD,HYST Foldback Hysteresis 50 mV
VSNSDIS,FWD Forward Overcurrent Disconnect Voltage SENSE – OUT, Rising 50 mV
VSNSDIS,REV Reverse Current Disconnect Voltage SENSE – OUT, Falling –30 mV
ISNS SENSE Input Current SENSE = OUT = 12V l±1 μA
tG(SWITCH) Gate Break-Before-Make Time CGATE = 47nF l10.3 15 µs
tPG(DIS, OFF) Gate Turn-Off Delay from DISABLE Falling DISABLE to Gate < 12V l1.4 2.7 µs
tPG(DIS, ON) Gate Turn-On Delay from DISABLE Rising DISABLE to Gate > 12V l1.3 2.1 µs
tPG(CAS) CASIN to CASOUT Propagation Delay High-to-Low 1 μs
tPG(DIS, CAS) DISABLE to CASOUT Propagation Delay DISABLE High-to-Low 2.8 µs
CURRENT LIMIT TIMER (TMR1, TMR2)
ITMR(UP) TMR Pull-Up Current l–3 –6 –9 µA
ITMR(DN) TMR Pull-Down Current l1 2 3 µA
tTMR,FLT TMR Fault Time CTMR = 10nF l550 830 1250 µs
%TMR(COOL) TMR Cool Down Ratio to Fault Time 0.1 %
OV, UV PROTECTION CIRCUITRY (OV1, OV2, UVF1, UVF2, UVR1, UVR2, QUAL)
VTH,OVUV OV, UV Threshold Voltage OV Rising, UVF Falling, UVR Rising l490 500 510 mV
VHYST, OV OV Hysteresis l40 50 60 mV
ILK,OVUV UVR, UVF, OV Input Leakage Current V = 0.5V l±10 nA
IQUAL,SRC QUAL Source Current l–1 –2 –3 µA
IQUAL,SNK QUAL Sink Current l1 2 3 µA
tVALID OV, UV Validation Time QUAL = INTVCC
CQUAL = 470pF
l
l
1.75
5
5
7.5
8
11
µs
ms
tINVALID OV, UV Invalidation Filter Time Overdrive = 50mV l1.75 5 8 µs
DIGITAL INPUTS (DISABLE1, DISABLE2, SHDN, CASIN, RETRY)
VTH Rising Threshold Voltage l0.5 1.0 1.5 V
VHYST Hysteresis Voltage 150 mV
ILK,HV Input Leakage Current V = 36V, DISABLE, SHDN l±0.1 ±1 µA
ILK,LV Input Leakage Current V = 5.5V, CASIN
Retry = INTVCC
l
l
±0.1
±0.1
±1
±1
µA
µA
ICASIN CASIN Pull-Up Current CASIN = 0V l2.5 5 10 µA
LTC4421
5
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. See the LTC4421 Data Sheet Nomenclature section for more details on pin
conditions. V1 = 12V, V2 = 13V, EXTVCC = CPOREF = OUT1 = OUT2 = SENSE1 = SENSE2 = 11V, OV1 = OV2 = TMR1 = TMR2 = OV, UVR1 =
UVR2 = UVF1 = UVF2 = DISABLE1 = DISABLE2 = SHDN = RETRY = CASIN = 4V, CPO = 23.5V, QUAL = INTVCC, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DIGITAL OUTPUTS (CH1, CH2, VALID1, VALID2, FAULT1, FAULT2, CASOUT)
VOL,HV Output Voltage Low, CH, VALID, FAULT I = 1mA, V1 = V2 = EXTVCC = 3.0V
I = 3mA, V1 = V2 = EXTVCC = 3.0V
l
l
185
0.58
450
1.35
mV
V
IOH,HV Open Drain, Output High Leakage Current V = 36V, CH, VALID, FAULT l±1 µA
VCASO,OH CASOUT Output High Voltage I = –1µA , SHDN = 0V l2 3.4 4.5 V
VCASO,OL CASOUT Output Low Voltage I = 1mA l85 200 mV
ICASO CASOUT Pull-Up Current CASOUT = 1V l–11 –22 –40 µA
ILK,CASO CASOUT Leakage Current CASOUT = 5.5V l±1 µA
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.
Note 3. Do not drive GATE1 and GATE2 above CPO. Doing so can cause
excessive voltage on CPO.
Note 4. V1 can operate down to 0V, provided V2 ≥ 3.0V or EXTVCC ≥ 3.0V.
Likewise, V2 can operate down to 0V, provided V1 ≥ 3.0V or EXTVCC ≥ 3.0V.
The LTC4421 dedicates 13 pins per channel for the pur-
poses of monitoring each input supply and controlling
its connection to the output. Pin names having suffix “1”
apply to Channel 1, while those having suffix “2” apply to
Channel 2. When no suffix is used when referencing one
of these pins, it means that the text applies to the pins
on both channels. For example, “Connect a capacitor
CTMR from TMR to ground” means “Connect a capacitor
CTMR1 between the TMR1 pin and ground” and “Connect
a capacitor CTMR2 between the TMR2 pin and ground”.
References to multiple pin names with no suffix are meant
to describe functionality within a channel but apply to both
channels. These references occur for the following cases:
1. Connecting two pins together: “Tie FAULT to DISABLE”
means “Tie FAULT1 to DISABLE1” and “Tie FAULT2 to
DISABLE2”.
2. Referring to differential voltages: “SENSE to OUT”
means “SENSE1 to OUT1” and “SENSE2 to OUT2”.
3. Causation: “The VALID pins pull low when their V1-V2
supplies have been validated” means “The VALID1 pin
pulls low when the V1 supply has been validated” and
“The VALID2 pin pulls low when the V2 supply has
been validated”.
LTC4421 DATA SHEET NOMENCLATURE
LTC4421
6
Rev. 0
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TYPICAL PERFORMANCE CHARACTERISTICS
GATE Drive Voltage vs CPOREF
Voltage INTVCC Voltage vs EXTVCC Voltage SENSE Voltage vs Temperature
Undervoltage Threshold vs
Temperature
Overvoltage Thresholds vs
Temperature
Total Supply Current vs EXTVCC
Voltage
GATE On Pull-Up Current vs GATE
Voltage
TA = 25°C, EXTVCC = 11V, unless otherwise noted.
Shutdown Current vs EXTVCC
Voltage (V1 = 12V, V2 = 13V)
Supply Current vs EXTVCC Voltage
(V1 = 12V, V2 = 13V)
0
2
4
6
8
10
12
CPOREF VOLTAGE (V)
7
8
9
10
11
12
13
GATE-CPOREF VOLTAGE (V)
4421 G01
TRANSITION TO
Burst Mode OPERATION
EXTVCC = 3.0
EXTVCC ≥ 4.0
2
3
4
5
6
EXTVCC VOLTAGE (V)
2
3
4
5
6
VOLTAGE (V)
4421 G02
INTVCC, RLOAD = 10k
INTVCC, NO LOAD
EXTVCC
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
23
24
25
26
27
SENSE VOLTAGE (mV)
4421 G03
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
0.490
0.495
0.500
0.505
0.510
THRESHOLD VOLTAGE (V)
4421 G04
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
0.425
0.450
0.475
0.500
0.525
THRESHOLD VOLTAGE (V)
4421 G05
RISING
FALLING
0
5
10
15
20
25
30
EXTVCC VOLTAGE (V)
400
450
500
550
600
650
700
SUPPLY CURRENT (µA)
4421 G06
T = 25°C
T = 125°C
T = −40°C
0
2
4
6
8
10
12
GATE-OUT VOLTAGE (V)
−20
−15
−10
−5
0
GATE CURRENT (mA)
4421 G07
SENSE = 0mV
SENSE = 6.25mV
SENSE = 12.5mV
SENSE = 18.75mV
0
5
10
15
20
25
30
EXTVCC VOLTAGE (V)
0
1
2
3
4
5
6
V1, V2, EXTVCC CURRENT (µA)
4421 G08
V1 + V2 + EXTVCC
EXTVCC
V1
V2
0
5
10
15
20
25
30
EXTV
CC
VOLTAGE (V)
0
100
200
300
400
500
V1, V2, EXTV
CC
CURRENT (µA)
4421 G09
(V1=12V, V2=13V)
V1 + V2 + EXTV
CC
EXTV
CC
V1
V2
LTC4421
7
Rev. 0
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TYPICAL PERFORMANCE CHARACTERISTICS
VOUT Switching from Higher to
Lower Voltage
VOUT Switching from Lower to
Higher Voltage
OV, UV Validation Time vs QUAL
Capacitance
VALID, CH, FAULT Output Low
Voltage vs Pull-Up Current
GATE Break-Before-Make Time vs
Temperature
OV, UV Propagation Delay vs
Overdrive
GATE Drive vs GATE Current
TA = 25°C, EXTVCC = 11V, unless otherwise noted.
GATE Drive vs Temperature
V
OUT
C
OUT
= 100µF
I
LOAD
= 5A
30V NCH SiR158DP
50µs/DIV
V
1
4V/DIV
V
2
4V/DIV
I
V1
2A/DIV
4421 G10
0V, 0A
V
OUT
C
OUT
= 100µF
I
LOAD
= 5A
30V NCH SiR158DP
50µs/DIV
V
1
5V/DIV
V
2
5V/DIV
I
V2
2A/DIV
4421 G11
0A
0V
C
QUAL
(pF)
10
100
1000
0.1
1
10
100
TIME (ms)
4421 G12
125°C
25°C
–40°C
EXTV
CC
= 3V
PULL–UP CURRENT (mA)
0
1
2
3
4
5
0
200
400
600
800
1000
VOL (mV)
4421 G13
EXTV
CC
= 3.1V
EXTV
CC
= 11V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
9
10
11
12
13
14
TIME (µs)
4421 G14
OVERDRIVE (mV)
1
10
100
1000
0
10
20
30
40
50
t
INVALID
(µs)
4421 G15
3V
3.2V
5V
12V
36V
I
GATE
(µA)
0
2
4
6
8
10
8.0
9.0
10.0
11.0
12.0
GATE-CPOREF VOLTAGE (V)
4421 G16
CPOREF:
CPOREF
= 12V
I
GATE
= 1µA
CPOREF = 3.2V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
10.0
10.4
10.8
11.2
11.6
12.0
GATE–CPOREF VOLTAGE (V)
4421 G17
LTC4421
8
Rev. 0
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PIN FUNCTIONS
CASIN: Digital Input for Cascading. Connect to CASOUT
of another, higher priority LTC4421 when cascading.
Connect to INTVCC or drive to a supply voltage above 1V
if not used.
CASOUT: Digital Output for Cascading. Connect to the
CASIN of another, lower priority LTC4421 when cascad-
ing. Leave open if not used.
CH1: Voltage Power Source Indicator Output. This open-
drain output pulls low when V1 is powering the output
voltage and releases high otherwise. Connect a pull-up
resistor to a supply less than or equal to 36V to provide
the pull-up. Connect to ground or leave open if unused.
CH2: Voltage Power Source Indicator Output. This open-
drain output pulls low when V2 is powering the output
voltage and releases high otherwise. Connect a pull-up
resistor to a supply less than or equal to 36V to provide
the pull-up. Connect to ground or leave open if unused.
CPO: Charge Pump Output. This is the output of the charge
pump, which is used to provide overdrive to the GATE pins.
Connect a ceramic capacitor between CPO and CPOREF
whose value must be at least 10 times the combined
capacitance of the GATE compensation capacitor plus the
gate capacitance of the back-to-back external N-Channel
MOSFETs of one channel. When the (CPO–CPOREF) voltage
is lower than the CPOGOOD threshold voltage VCPO(UVL),
the input supplies are prevented from powering the output.
See the Operation section for details of the initial start-up
delay due to the time required to charge the CPO capacitor.
CPOREF: Charge Pump Reference Output. This is the
reference point for the charge pump, which is used to
provide overdrive to the GATE pins. Connect to the system
output voltage using a short PCB trace. Do not connect
to the OUT1 or OUT2 sense resistor Kelvin connections.
DISABLE1, DISABLE2: Digital Inputs for Input Disconnect
and Current Limit Fault Reset. Voltages below 1V prevent
the corresponding input V1, V2 supply from powering the
output voltage. Driving DISABLE low, then high after a cur-
rent limit fault resets the current limit timer circuitry and
releases the corresponding FAULT pin high. Connecting
DISABLE to the corresponding FAULT pin configures the
device in auto-retry mode, with a cool-down period between
retries that is 1024 times longer than the current limit fault
time. See Applications Information for more details. Tie to
INTVCC or drive to a supply voltage above 1V if not used.
EXTVCC: External High Priority Supply Input. When EXTVCC
exceeds 2.45V, an internal LDO generates a low voltage
supply rail from EXTVCC to power the low voltage inter-
nal circuitry. Most of the LTC4421’s ICC is drawn from
EXTVCC. Connect EXTVCC to a supply voltage ranging from
3.0V to 36V. Connect EXTV
CC
to the output voltage (OUT1
or OUT2) to make the output voltage provide the internal
bias current to the LTC4421. If unused, connect to ground,
and the LDO will be powered from another supply.
FAULT1, FAULT2: Current Limit Fault Indicators. These
open-drain outputs pull low when an overcurrent fault
occurs on their corresponding inputs and remain low dur-
ing the cool down cycle. Connect pull-up resistors to a
supply voltage less than or equal to 36V to provide the
pull-up. Tie to ground or leave open if unused.
GAT E1, GATE2: Gate Drives for External N-Channel
MOSFETs. Connect these pins to the gates of the exter-
nal back-to-back N-Channel MOSFETs. The charge pump
drives these pins with up to 12V of enhancement. Connect
a capacitor between each GATE pin and the sources of the
corresponding MOSFETs to compensate the current limit
regulation loop.
GND: Device Ground.
INTVCC: Internal Low Voltage Supply Decoupling Output.
An internal LDO generates a low voltage rail to power the
low voltage internal circuitry. It is capable of supplying
up to 500µA of external current. Connect a 1µF or larger
capacitor between this pin and ground to provide bypass-
ing. This pin has an undervoltage lockout threshold volt-
age of 2.3V.
OUT1, OUT2: Output Voltage Sense. The LTC4421 pre-
vents input supplies from connecting to the correspond-
ing OUT until OUT is at least 35mV below the connecting
supply. These pins are also used in conjunction with the
SENSE pins to set the current limit values for the input
supplies. Connect OUT directly to the output side of the
sense resistor with Kelvin connection.
OV1, OV2: Overvoltage Comparator Inputs. Rising input
voltages that cross above 0.5V cause an overvoltage
LTC4421
9
Rev. 0
For more information www.analog.com
event. Connect OV1 and OV2 to a resistive divider between
the respective V1, V2 and ground to set the overvoltage
threshold. See Applications Information section for con-
necting unused OV1 and OV2 pins.
QUAL: OV, UV Qualification Timer. Connect a capacitor
CQUAL from this pin to ground to set an OV, UV qualifica-
tion time of 16ms/nF. Alternatively, connect this pin to
INTVCC to set a default time of 3.5µs. Do not leave open.
RETRY: Digital Input for Retry after Current Limit Fault.
When this pin is above 1V, after a current limit fault dis-
connect occurs, the LTC4421 reconnects the input to the
output up to 6 additional times, waiting for a cool down
period between each reconnection. If current limit faults
occur in each of 6 additional reconnections, the LTC4421
keeps the input disconnected until the input’s DISABLE
pin is toggled. See the Applications section for more
details. Connect to ground if unused. Do not leave open.
SENSE1, SENSE2: Current Sense Non-Inverting Inputs.
The current limit regulation circuits control the GATE pins
to limit the sense voltages between SENSE and OUT to
25mV. If the OUT1 voltage drops below 0.45V, the regula-
tion voltage is reduced from 25mV to 12.5mV. Connect
SENSE1, SENSE2 directly to the input sides of the sense
resistors with Kelvin connections.
SHDN: Digital Input Shutdown to Disconnect Output and
Set Low Current Mode. Voltages below 1V turn off all
external MOSFETs, invalidate both channels and cause
the LTC4421 to enter a low current mode. CASOUT is
pulled high to allow a lower priority LTC4421 in a cas-
caded system to provide power to the output. All circuitry
is debiased, except for the shutdown comparator and low
voltage rail generators, and total device current is reduced
to 6µA. When SHDN is driven back above 1V, the external
MOSFETs are held off until the OV and UV comparators
revalidate. Connect to INTVCC if unused.
SOURCE1, SOURCE2: Connections to Common Sources
of External Back-to-Back N-Channel MOSFETs. Leave
open or connect to the sources of the external MOSFETs.
To minimize channel switchover time, a 5µA pull-down
current biases the MOSFETs on the edge of conduction
when their input supply is not connected to the output.
Add resistors from the MOSFET sources to ground to
PIN FUNCTIONS
increase the MOSFET VGS bias voltage and reduce swi-
tchover time.
TMR1, TMR2: Current Limit Fault Timers. Connect a capaci-
tor between each TMR pin and ground to set a 83ms/µF
duration for current limit before an overcurrent fault occurs.
When a fault occurs, the external N-Channel MOSFETs are
turned off and the corresponding FAULT pin is pulled low.
The LTC4421 can be configured to latch-off, auto-retry
indefinitely or auto-retry 6 additional times after an overcur-
rent fault. See the Applications Information for more details.
UVR1, UVR2: Undervoltage Comparator Inputs for Rising
Voltages. Rising input voltages that cross above 0.5V
are considered valid, provided that the OV pin voltage
is below 0.5V. Connect UVR1 and UVR2 to a resistive
divider between the respective V1, V2 and ground to set
the rising undervoltage threshold. Set the UVR threshold
voltage above the corresponding UVF threshold voltage
to ensure proper operation. See Applications Information
section for connecting unused UVR1 and UVR2 pins.
UVF1, UVF2: Undervoltage Comparator Inputs for
Falling Voltages. Falling input voltages that cross below
0.5V cause an undervoltage event. Connect UVF1 and
UVF2 to a resistive divider between the respective V1,
V2 and ground to set the falling undervoltage threshold.
Set the UVR threshold voltage above the corresponding
UVF threshold voltage to ensure proper operation. See
Applications Information section for connecting unused
UVF1 and UVF2 pins.
V1, V2: Input Power Supply Voltages. Typically V1 and V2
are connected to input supply voltages ranging from 3.0V
to 36V, but each supply can operate down to 0V, provided
another supply voltage ≥3.0V powers the LTC4421. In
normal operation, V1 is the higher priority supply and V2
is the lower priority supply.
VALID1, VALID2: Voltage Valid Indicator Outputs. These
open-drain outputs pull low when their corresponding V1,
V2 inputs are within their OV, UV window for the required
qualification time. Connect pull-up resistors to a supply
voltage less than or equal to 36V to provide the pull-up.
Connect to ground or leave open if unused.
Exposed Pad (Pin 37, UHE Package only): Exposed Pad
may be left open or connected to device ground.
LTC4421
10
Rev. 0
For more information www.analog.com
BLOCK DIAGRAM
6.7V/5.3V
V1
ON1
0.5V/0.45V
0.5V
CH2OFF
V1
V2
1.211V
BGGOOD
1V/0.85V
CH1OFF
FAULT1
1V/0.85V
HYS
1V/0.85V
1V/0.85V
CH1OFF
CH2OFF
2.4V/2.3V
INTVCC
CPO
INTVCC
POR
INTVCC
OUT1
OUT1
0.46V/
0.41V
1.3V
0.8V
ON1
VALID1
VREV
35mV
0.6V
25mV/12.5mV
GATE
DRIVER
+ILIM
M1
M2
20µA
ICAS
D1
M12
NMOS
0.6V
5µA
ISRC
M5
I1
2µA
I2
8µA
VSNSREV
25mV
REV
CP
Q
RD
S
VGSOFF
CP'S
ILIM
AMP
CHANNEL 1
CHANNEL 2
OV1
UVF1
UVR1
DISABLE1
TMR1
QUAL
RETRY
SHDN
EXTVCC
CASIN
V1
GATE1
SOURCE1
VALID1
SENSE1
OUT1
FAULT1
CH2
GND
INTVCC
CASOUT
LTC4421 BD
CPOREF
CPO
BG
VMAX OF 4
CASCADE
LOGIC
OV, UV
TIMER
CONNECT
LOGIC
CURRENT
LIMIT
LOGIC
COOL
DOWN
COUNTER
CHANNEL
OFF
SENSE2
FAULT2
OUT2
UVR2
UVF2
DISABLE2
OV2
GATE2
SOURCE2
V2
VALID2
TMR2
PRIORITIZED
3.9V
REGULATOR
CH1
OV CP
UV CP
FOLDBACK
CP
1
2
3
4
INTVCC
DIS CP
REVCUR
CP
SHUTDOWN CP
CASCADE CP
INTVCC GOOD CP
RETRY CP
CPOGOOD CP
CHARGE
PUMP/LDO
f = 2MHz
VMAX
OF 2
INTVCC
5μA
D2
LTC4421
11
Rev. 0
For more information www.analog.com
OPERATION
The LTC4421 is a Prioritized PowerPath™ Controller that
drives external N-Channel MOSFETs to connect one of
two input supplies to a common output based on user-
defined priority and validity. By definition, the supply con-
nected to V1 is the higher priority supply, and the supply
connected to V2 is lower priority, although this can be
changed dynamically. The V1 voltage can be lower than,
equal to or higher than the V2 voltage.
At initial power-up, the LTC4421 prevents the input sup-
plies from validating and connecting to the output until it
has enough bias voltage to function properly. Referring
to the Block Diagram, the LTC4421 prevents OV, UV
validation and connection to the output until the INTVCC
voltage exceeds 2.3V (VINT(UVL)) as detected by com-
parator INTVCC GOOD CP, the bandgap reference voltage
has reached its final regulated value as indicated by the
BGGOOD signal, and the CPO voltage exceeds the higher
of the CPOREF and INTVCC voltages by 6.7V (VCPO(UVL)) as
detected by comparator CPOGOOD CP. With a 1µF capaci-
tor connected between CPO and CPOREF, the Charge
Pump/LDO circuit can take several hundred milliseconds
to charge to 6.7V. See the Applications Information for
methods to reduce the charging time.
After initial power-up is complete, the LTC4421 moni-
tors the V1 and V2 voltages via resistive dividers to pre-
cision overvoltage (OV CP) and undervoltage (UV CP)
comparators. The UVR and UVF pins set the rising and
falling undervoltage thresholds for the UV comparators.
When an input voltage has been inside its OV, UV volt-
age window for a time (tVALID) set by the QUAL pin, it is
considered valid and is eligible to power the output. If the
input supply voltage falls out of the OV, UV window and
remains outside for at least 3.5µs (tINVALID), the supply is
disconnected from the output. Open drain output status
pins provide information regarding a channel’s validity
and connection status to the output. VALID1 and VALID2
are pulled low when V1 and V2, respectively, are valid.
CH1 and CH2 are pulled low when V1 and V2, respectively,
are powering VOUT.
The GATE DRIVER circuit provides strong sourcing and
sinking currents to external N-Channel MOSFETs to con-
nect and disconnect the input supplies to and from the
output. When turning on the MOSFETs, GATE DRIVER
sources current from the CPO pin to pull the GATE volt-
age up to the CPO voltage. A charge pump regulates the
CPO voltage 12V (VGATE(CL)) above the CPOREF voltage
to provide 12V of VGS enhancement to the MOSFETs.
Strong sinking currents ensure rapid turnoff of the
external MOSFETs when a channel is no longer valid, a
higher priority channel takes precedence or when com-
parator REVCUR CP detects a reverse voltage of –25mV
(VSNSDIS,REV) across the external sense resistor. Such a
reverse voltage occurs when an input supply powering
the output is shorted. Fast charge and discharge of the
external NMOS gates ensure fast switching between sup-
plies, minimizing droop at the output.
During channel transitions, monitoring circuitry prevents
cross conduction between input supplies and reverse cur-
rent from the output using a break-before-make archi-
tecture. Two VGS comparators (VGSOFF CPs) monitor
the disconnecting channel’s gate pin voltage (GATE1 or
GATE2). When the GATE voltage is 600mV (VGS(OFF))
lower than either the input or output voltage of the channel
turning off, the VGS comparators determine the external
N-channel MOSFETs to be off and allow the other channel
to connect to the output. The V
GS
comparator outputs are
latched in the off state; the latch is reset when the channel
is commanded to turn back on.
To prevent reverse conduction from the output to the
inputs during channel switchover, the reverse comparator
(REV CP) monitors the connecting V1, V2 supply and the
corresponding OUT1, OUT2 output. The REV comparator
prevents connection until the output droops 35mV (VREV)
below the connecting supply. The connection is latched,
resetting when the channel is commanded to disconnect.
LTC4421
12
Rev. 0
For more information www.analog.com
The current limit amplifier (ILIM AMP) monitors the load
current using the difference between the SENSE and OUT
pin voltages. The amplifier and gate driver work together
to limit the current in the load by reducing the GATE-to-
SOURCE voltage in an active control loop. The SENSE-to-
OUT differential voltage is regulated to 25mV (ΔV
SNS
). An
external sense resistor placed between SENSE and OUT
sets the current limit value for each channel. Foldback
comparator (FOLDBACK CP) reduces the SENSE-to-
OUT differential voltage from 25mV (ΔVSNS) to 12.5mV
(ΔVSNS,FLD) to conserve power when the OUT1 voltage is
low. The foldback comparator’s rising and falling thresh-
old voltages are 460mV and 410mV, respectively. If the
SENSE–OUT voltage on a channel remains in current limit
for the time programmed by the TMR pin, the LTC4421
registers a current limit fault. Additionally, pulsed output
load currents exceeding current limit and occurring at
duty cycles of 25% or higher will integrate over time and
cause a current limit fault.
When a current limit fault occurs, the LTC4421 discon-
nects the channel and drives the FAULT pin low to indicate
that a current limit fault has occurred. After a current
fault occurs, driving DISABLE low initiates a cool down
period that is 1024 times longer than the time-out period.
Driving DISABLE back high terminates the cool-down
period, resets FAULT high and allows reconnection to the
output. Alternatively, if RETRY and DISABLE are both high
when a current limit fault occurs, the LTC4421 will try
to reconnect up to 6 additional times after the first fault,
with a cool-down period between attempted connections
that is 1024 times longer than the current limit fault time.
Driving DISABLE1 and DISABLE2 low disconnects V1 and
V2, respectively, from powering the output. The CASIN
OPERATION
and CASOUT pins of multiple LTC4421’s can be config-
ured to prioritize as many input supplies as desired. The
DISABLE1, DISABLE2 and CASIN inputs are connected
to comparators having 1V (VTH) threshold and 150mV
(VTH,HYST) hysteresis. See the Applications Information
section for circuits that use the DISABLE, FAULT2 and
VALID2 pins to redefine input supply priorities in real time
and to prevent the primary input from powering the output
until a valid back-up supply is available.
Driving SHDN low causes the device to turn off the exter-
nal N-Channel MOSFETs, enter a low current state and
invalidate V1 and V2. All circuitry is debiased except the
INTVCC rail generator and shutdown comparator. The total
internal bias current is reduced dramatically to 6µA to
conserve power. The INTV
CC
voltage is reduced to 3V and
is powered from the highest of the V1, V2, EXTVCC and
OUT1 voltages. The CASOUT pin is driven high to allow
a lower priority LTC4421 in a cascading application to
power VOUT.
When SHDN is driven high, the LTC4421 reactivates all
circuits. It may take several hundred milliseconds for a
valid input to connect to the output, because the external
charge pump capacitor CCPO must charge to 6.7V before
connection is allowed.
The LTC4421 includes its own internally generated low
voltage rail (INTVCC) that provides power to the low volt-
age sections of the device. Because most of the device’s
quiescent current is provided by INTVCC, the INTVCC
power source is prioritized to minimize current draw from
lower priority sources. The INTVCC rail is powered from
one of 4 prioritized sources. These sources in order of
priority are EXTV
CC
, V1 and V2. If none of these three
inputs is valid, INTVCC is powered by the highest of the
V1, V2, EXTVCC and OUT1 voltages.
LTC4421
13
Rev. 0
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Introduction
High availability systems employ multiple input supplies
to power a single common output. When individual sup-
plies such as wall adapters and batteries are unplugged at
various points in time, output power must not brown out
as control of the output power is transferred to the other
supply. Power ORing diodes are often used in these sys-
tems, but the highest input supply voltage always pow-
ers the output. The LTC4421 powers the output from
the highest priority supply available, even if it is lower
in voltage than the lower priority supplies. When switch-
ing between supplies, output voltage droop is minimized,
and backfeeding current is prevented. A typical LTC4421
application circuit is shown in Figure1, where the primary
APPLICATIONS INFORMATION
input supply is 12V and the secondary is 28V. External
component selection is discussed in detail in the follow-
ing sections.
Setting Valid Operating Voltage Range
The LTC4421 requires an input supply remain inside a
user-defined voltage window for a user-defined amount of
time to be considered valid. The valid voltage window is
set by a resistive divider from the input supply to ground
that allows three thresholds voltages to be configured:
the UV rising threshold (VUVRISE), the UV falling thresh-
old (VUVFALL) and the OV rising threshold (VOVRISE). The
OV falling threshold is set by internal hysteresis to be
10% below the OV rising threshold. Using the 500mV
Figure1. Typical LTC4421 Application Circuit
LTC4421 F01
CINTVCC
1µF
35.7k
R1
12.7k
R2
20k
R3
1MΩ
R4
15.4k
R5
6.19k
R6
69.8k
R7
1MΩ
R8
C2
0.1µF
M1
PSMN4R8100BSE
M2
PSMN1R440YLD
M3
PSMN4R8100BSE
M4
PSMN1R440YLD
CCP0
1µF
CTMR2
47nF
CTMR1
47nF
CQUAL
470pF
COUT
220µF
D1
SMDJ36A
D2
SMDJ36A
RSENSE1
2.5mΩ
2.5mΩ
RSENSE2
GATE1
SOURCE1
OUT2
GATE2
SOURCE2
V1
EXTVCC
INTVCC
TMR1
OV1
OV2
V2
CPO
SENSE1
SENSE2
VALID1
VALID2
GND
FAULT1
FAULT2
CH1
CH2
DISABLE1
DISABLE2
SHDN
UVF1
UVF2
UVR1
UVR2
OUT1
TMR2
CASIN
CASOUT
QUAL
RETRY
CPOREF
CG2
47nF
CG1
47nF
PRIMARY
12V
VOUT
SECONDARY
28V
LTC4421
DIGITAL
STATUS
OUTPUTS
DIGITAL
CONTROL
INPUTS
UVF1 = 7.81V
UVR1 = 11.04V
OV1 = 14.96V
UVF2 = 5.97V
UVR2 = 25.28V
OV2 = 35.4V
RSN1
1.2Ω
CSN1
10µF
RSN2
2.8Ω
CSN2
10µF
ILIM1 = 10A
ILIM2 = 10A
LTC4421
14
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
comparator threshold, the resistor values can be calcu-
lated as shown in Equation 1 through Equation 5.
R
TOTAL =
R1
+
R2
+
R3
+
R4
(1)
R1=0.5 • RTOTAL
( )
VOVRISE
(2)
R2 =VOVRISE
VUVRISE
– 1
⎛
⎝
⎜⎞
⎠
⎟•R
1
(3)
R3 =VUVRISE
VUVFALL
– 1
⎛
⎝
⎜⎞
⎠
⎟•VOVRISE
VUVRISE
⎛
⎝
⎜⎞
⎠
⎟•R
1
(4)
R4 =R1• VOVRISE
0.5 – 1
⎛
⎝
⎜⎞
⎠
⎟– R3 – R2
(5)
When setting the resistor values, take into account the
tolerance of the input supply voltage, the tolerance of the
resistors, the ±2% error in the 500mV reference and the
±10nA maximum leakage of the UVR, UVF and OV pins.
To permanently invalidate a channel, connect OV, UVR
and UVF to ground.
During channel turn-on, the relatively large inrush current
causes a voltage drop across the input supply source
resistance and the parasitic resistances of PCB traces and
any cable. This voltage drop can cause UV faults that
trigger a phenomenon called UV motorboating, where
the input supply repeatedly connects and disconnects
from the output. UV motorboating can lead to compo-
nent damage and undesirable/erratic behavior. To pre-
vent UV motorboating, set the VUVRISE and VUVFALL as
far apart as possible to maximize hysteresis and prevent
channel disconnect during the inrush. Ideally, quantify the
worst-case input resistance RSRC,MAX, and set (VUVRISE-
VUVFALL) larger than (ILIM • RSRC,MAX), where ILIM is the
current limit. The OV hysteresis is fixed at 10% above the
OV threshold voltage.
For better accuracy, use one resistive divider per chan-
nel to set the UVF and UVR thresholds, and a second,
separate resistive divider to set the OV threshold. For
ease of calculation, use three individual resistive divider
strings per channel – one for OV, one for UVF and one for
UVR. However, to ensure the UVR threshold is always
higher than the UVF threshold on a given channel,
do not use separate strings for UVR and UVF when
setting their thresholds close together in voltage.
Figure2 shows these various resistive divider possibili-
ties, using Channel1 as an example.
Figure2. Three Resistive Divider Options For Setting the OV, UVR and UVF Threshold Voltages
UVF1
OV1
OV1
UVR1
OV1
UVF1
UVR1
UVR1
UVF1
0.5V
0.5V/0.45V
QUAL
V1
VALID1
VPU
R1
R2
R3
R4
R5
R6
R7
R8
M1
M2
M3
R9
R10
R11
R12
R13
R14
R15
R16
QUAL
TIMER
FEWEST
RESISTORS
ENSURES UVR1
THRESHOLD > UVF1
THRESHOLD
EASIEST TO CALCULATE
VI INPUT SUPPLY
LTC4421
LTC4421 F02
LTC4421
15
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
Current Limit Regulation and Setting the Current Limit
The LTC4421 provides independently settable current limit
values for each input. On a given channel, the LTC4421
regulates the maximum voltage across the SENSE and
OUT pins to 25mV (ΔVSNS). Connect a sense resistor
RSENSE between SENSE and OUT to set the current limit
value ILIM, is given by Equation 6.
ILIM =
25mV
RSENSE
(6)
Ensure the input supply is capable of sourcing more cur-
rent than ILIM, so that the input supply does not drop out
and cause UV motorboating. Use standard 1% resistor
values and choose RSENSE to set ILIM at least 25% higher
than the maximum output load current ILOAD(MAX) to
account for tolerances in the current limit and to provide
sufficient charging current to the output capacitor when
charging the output.
I
LIM
and C
OUT
set the rate at which the output voltage
will rise.
The minimum output rise rate is shown by Equation 7.
dVOUT
dt (min) =ILIM –ILOAD(MAX)
( )
COUT
(7)
Equation 7 assumes that the output voltage is charging
under maximum output load current conditions, so that
only the difference between the programmed current limit
current and the maximum DC load current is available to
charge C
OUT
. It is essential to set I
LIM
to ensure that
the output is fully charged before an overcurrent fault
timeout occurs.
The LTC4421 implements a stepped current limit foldback
feature. A foldback comparator monitors the voltage on the
OUT1 pin and reduces the current limit regulation voltage
from 25mV (ΔVSNS) to 12.5mV (ΔVSNS,FLD) for low OUT1
voltages, thereby cutting the current limit in half to reduce
power consumption. The comparator rising and falling
threshold voltages are 460mV (VFLD,TH) and 410mV, respec-
tively. When the OUT1 voltage is initially being powered up
from 0V, the current limit regulation voltage is 12.5mV until
OUT1 rises above 460mV, at which point it is increased
to 25mV. For output voltages below 460mV, ensure the
maximum output load current is lower than the foldback
current limit to ensure the output powers up. When the
OUT1 voltage is initially powered and then discharges, for
example due to an input or output short circuit, the current
limit regulation voltage will be 25mV until OUT1 drops below
410mV, at which point it is reduced to 12.5mV.
Use Kelvin connections from the RSENSE terminals to
the LTC4421’s SENSE and OUT pins for best accuracy.
Choose sense resistors having low inductance to mini-
mize the sense resistor’s impact on the current limit regu-
lation loop stability. A single sense resistor can be used if
the current limit is the same on both channels, as shown
in Figure3.
Figure3. Using a Single Sense Resistor RSENSE to Set the Same Current Limit for Both Channels
M1
PSMN4R060YS
M2
PSMN1R440YLD
M3
PSMN4R060YS
M4
PSMN1R440YLD
CCPO
1µF
2.5mΩ
RSENSE
CG2
LTC4421 F03
CG1
47nF
CPO
CPOREF
VOUT
V1
V2
GATE1
SOURCE1
V1
SENSE2
OUT1
LTC4421
V2
GATE2
SOURCE2
SENSE1
OUT2
LTC4421
16
Rev. 0
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Selecting the Output Capacitor
When switching connection to the output between the
two input supplies, the LTC4421 utilizes break-before-
make circuitry to ensure the first channel has completely
disconnected from the output before the second turns
on. This prevents current from flowing from one input to
the other via the output, a phenomenon known as cross-
conduction. As a result, there is a dead time during swi-
tchover when neither supply is powering the output.
Users must choose an output capacitance COUT to support
the output load current and minimize the output voltage
step and droop during switchover. When the first channel
disconnects, a voltage step occurs at the output due to
the load current flowing through COUT’s equivalent series
resistance RESR. The magnitude of the voltage step is
given by Equation 8.
VSTEP = (ILOAD • RESR )
(8)
For the duration of the dead time, the output voltage
droops as the load current discharges COUT. The maxi-
mum magnitude of the droop is given by Equation 9.
VDROOP =ILOAD(MAX) • tG(SWITCH),MAX
( )
C
OUT
(9)
Set COUT to optimize the trade-off between minimizing
output voltage droop and minimizing the time required to
fully charge the output from 0V. Set VDROOP(MAX) as high
as possible; usually, VDROOP(MAX) ≤ 0.1 • VOUT is accept-
able. Typically, using 10µF to 50µF of output capacitance
per Ampere of maximum load current achieves a reason-
able trade-off.
APPLICATIONS INFORMATION
Figure4 shows an output voltage waveform during swi-
tchover for a system having 5A output load current and
a 220µF output capacitor with 100mΩ RESR. When the
first channel is turned off, the 5A load is provided by the
220µF capacitor. With 5A flowing through the 100mΩ
R
ESR
, V
STEP
= 500mV. Following the ESR step, the output
discharges at a rate dV/dt = 5A/220µF until the second
channel is switched in.
Because of the high output currents, it is imperative
to choose capacitors having very low ESR to minimize
VSTEP. Also, consult the capacitor vendor’s curves of
capacitance versus DC bias voltage and capacitance ver-
sus temperature, and account for temperature and voltage
coefficients of COUT.
Determining the Maximum Time to Charge the Output
Voltage
Whenever the output is being charged from a lower
voltage to a higher voltage, it charges in current limit.
As a result, the overcurrent fault timer is running dur-
ing charging. It is imperative to determine the maximum
time t(CHG,MAX) required to charge the output and set the
overcurrent fault time tTMR,FLT > t(CHG,MAX). The maximum
charge time is given by Equation 10.
t(CHG,MAX) =COUT • VIN,MAX
( )
I
LIM
–I
LOAD,CHG
( )
(10)
where VIN,MAX is the highest input voltage and ILOAD,CHG
is the maximum DC load current present when COUT is
being charged. The worst case occurs when ILOAD,CHG
= ILOAD,MAX. If possible, disable the output load current
Figure4. Output Voltage ESR Step and Linear Discharge During Channel Switchover
ESR STEP
0.5/DIV
10µs/DIV
VOUT
DROOP DUE TO
SWITCHOVER DELAY
4421 F04
LTC4421
17
Rev. 0
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APPLICATIONS INFORMATION
when initially charging the output from 0V, so that
ILOAD,CHG = 0. The application circuit in Figure5 utilizes
an LTC2965 voltage monitor on the output to disable the
output DC/DC converter until VOUT rises above 9V. Once
V
OUT
rises above 9V, the DC/DC remains enabled until
VOUT drops below 1V.
N-Channel MOSFET Selection
The LTC4421 drives N-Channel MOSFETs to conduct or
block current from an input supply voltage and an output
load current. The important features of the MOSFETs are:
1. BVDSS, the absolute maximum drain-source
voltage
2. VGS,MAX, the absolute maximum VGS voltage
3. VGS(TH), the threshold voltage
4. RDS(ON), the on-resistance
5. SOA, the safe operating area
The maximum allowable drain-source voltage, BVDSS,
must be higher than all supply voltages, as there are vari-
ous scenarios where the output voltage can be at the high-
est supply voltage when the input is at 0V, and vice versa.
Additionally, it must be higher than the clamping voltage
of Transient Voltage Suppressor (TVS) diodes D1 and D2.
Supplies with high input parasitic inductance may require
additional precautions. See the Input and Output Short
Circuits and Supply Transient Protection section for more
Figure5. Load Current Hold Off. The LTC2965 Voltage Monitor Disables the DC/DC Output Load Current Until VOUT > 9V
M1
SiR158DP
M2
SiR158DP
2.5mΩ
RSENSE1
CCP0
1µF
COUT
220µF
RTH3
619k
RTH2
332k
RTH1
42.2k
CPO
CPOREF
CG1
47nF
VOUT
V1
LTC4421
12V
VIN
INH
INL
PS
RS
OUT
GND
LTC2965
DC/DC
ENABLE
LTC4421 F05
REF
GATE1
SOURCE1
V1
SENSE1
OUT1
information. Choose MOSFETs having VGS,MAX = ±20V, to
handle the LTC4421’s 14V maximum gate drive voltage.
When the back-to-back MOSFETs turn on and conduct
current to the output, large drain-source voltages can
occur on the input side MOSFET as the output is charg-
ing. However, the drain-source voltage of the output side
MOSFET is limited to about 1V due to the body diode turn-
ing on, so the output side MOSFET is always in triode. As
a result, the input side MOSFET has much more stringent
SOA requirements. A MOSFET with lower SOA and lower
V
GS(TH)
can be used on the output side to minimize power
loss in that MOSFET.
The chosen MOSFET must be able to withstand an out-
put short circuit for longer than tTMR,FLT. During output
shorts, the LTC4421 regulates the short-circuit current
using its current limit regulation circuitry and runs the
overcurrent fault timer. When the short persists longer
than the programmed tTMR,FLT time, the LTC4421 turns
off the MOSFETs. The worst-case occurs when the out-
put is resistively shorted and the output voltage, VSHORT,
remains above the foldback comparator falling threshold
voltage, which is 410mV. In this case, the power during
the short circuit is given in Equation 11.
POWER ≈VIN •ILIM =VIN • 25mV
( )
R
SENSE
(11)
where VIN is in the input voltage and VIN >> VSHORT.
LTC4421
18
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After calculating the power, refer to the SOA curves in the
MOSFET manufacturer’s data sheet. The SOA curves are
usually specified at 25°C and must be adjusted to account
for the highest operating ambient temperature T
A
as given
by Equation 12.
SOA(TA)=SOA(25°C) • TJMAX – TA
( )
T
JMAX
– 25°C
( )
(12)
Where TJMAX is the maximum allowed junction tempera-
ture of the MOSFET. Most of the recommended MOSFETs
have TJMAX =175°C. As a result, multiply the y-axis values
of the SOA curves by 0.6 for TA = 85°C, and multiply by
0.333 for TA = 125°C.
Note that MOSFET data sheets usually show a family
of 5-6 SOA curves, with each curve separated from the
next by a factor of 10 in time (e.g., 100µs, 1ms, 10ms,
etc.). To be conservative, choose the time curve closest
to and higher than tTMR,FLT and make sure the MOSFET
can handle the power in Equation 11.
When the output is hard-shorted to ground, such that the
output voltage is below 410mV, the LTC4421 implements
a stepped foldback feature, reducing the short circuit cur-
rent, and hence the power, by a factor of two. As a result,
the LTC4421 provides more SOA margin for the MOSFET
for hard shorts than resistive shorts. See procedures out-
lined in this section and the SOA curves in the chosen
MOSFET manufacturer’s data sheet to verify suitability
for the application.
APPLICATIONS INFORMATION
Overcurrent Faults and Retry
The LTC4421 features an adjustable current limit that protects
against output short circuits and excessive load current. An
overcurrent fault occurs when the current limit circuitry has
been engaged for longer than the time set by the TMR pin.
When the output load current is less than ILIM, the LTC4421
pre-biases the TMR pin voltage to its DC TMR Parking
Voltage. When the LTC4421 is regulating the output current
to I
LIM
, it sources 6µA out of the TMR pin to charge the exter-
nal TMR capacitor. When the TMR pin voltages increases
by 500mV from the TMR Parking Voltage, an overcurrent
faultoccurs. The FAULT open-drain output pull-down pin is
latched low, and the input is disconnected from the output.
Connect a capacitor CTMR between TMR and ground and use
Equation 13 to set the overcurrent fault time tTMR,FLT.
t
TMR,FLT =
C
TMR
• 83 µs/nF
[ ]
(13)
Note that pulsed current loads exceeding the programmed
current limit and having duty cycle > 25% will integrate
over time and cause a current limit fault.
After an overcurrent fault occurs, the subsequent func-
tionality depends on the configuration of the DISABLE,
FAULT and RETRY pins. Figure 6 shows a timing diagram
for an overcurrent fault occurring on Channel 1 where
the RETRY pin is set low, FAULT1 is pulled up to a supply
voltage with a 100k resistor and the user drives DISABLE1
with a digital signal. For simplicity, there is no input supply
connected to V2.
OUT1
I(R
SENSE1
)
TMR1
FAULT1
DISABLE1
t
TMR,FLT
COOL DOWN TIME = (1024 • t
TMR,FLT
)
OVERCURRENT
FAULT
OUTPUT SHORT
TO GROUND
USER
INITIATES
COOL DOWN
COOL DOWN
COMPLETE
LTC4421 F06
RECONNECT
OUTPUT SHORT
RELEASED
Figure6. Manual Retry after Overcurrent Fault on Channel 1. Conditions: RETRY = 0V,
User Driven DISABLE1 and Output Short Released During Cool Down Time
LTC4421
19
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APPLICATIONS INFORMATION
When output voltage OUT1 is shorted to ground, the
LTC4421 limits the current I(RSENSE1) flowing in the
sense resistor and simultaneously sources 6µA out the
TMR1 pin to charge the CTMR1 capacitor. At time tTMR,FLT
after the short, an overcurrent fault occurs as described
above, and the LTC4421 drives FAULT1 low. The user
detects FAULT1 being low and drives DISABLE1 low to
initiate the cool down cycle.
In this example, the short circuit is released during the cool
down cycle, as indicated in the waveforms. Because V1 is
disconnected from the output, the output voltage remains
low when the short is released. At the end of cool-down,
FAULT1 releases high and the input is allowed to reconnect
to the output. Driving DISABLE1 high reconnects Channel
1’s input to the output. With the output short removed, the
output successfully powers up, and no further faults occur.
Note: driving DISABLE1 low-to-high at any point in the
cool down cycle asynchronously terminates the cool down
cycle and allows reconnection to the output. It is strongly
recommended not to terminate the cool down cycle early,
as the MOSFETs may not have sufficient time to cool
down, and the subsequent overcurrent fault time may be
significantly shorter than the time set by the TMR pin.
Figure7 shows the functionality with RETRY = 0V, but
with the FAULT1 pin connected to DISABLE1. In this case
the user does not drive DISABLE1. When the overcur-
rent fault occurs, the FAULT1 pin is driven low. Because
FAULT1 is connected to DISABLE1, DISABLE1 also pulls
low, initiating the cool down cycle. At the end of the cool
down cycle, the LTC4421 releases FAULT1 high, which
drives DISABLE1 high, causing the V1 input supply to
reconnect to the output, a process called “auto-retry”.
This process repeats indefinitely until the output short
is removed. In this example, the output short is released
during the second cool down cycle, so the output voltage
successfully powers up on the third connection.
Figure8 shows the functionality with DISABLE1 pulled
high, FAULT1 pulled up to a supply voltage with a 100k
resistor but not connected to DISABLE1, and RETRY set
high. In this example, we are leaving the output shorted
permanently. In this case, the LTC4421 reconnects the V1
supply 6 additional times after the first overcurrent fault
occurs. Each reconnection results in an overcurrent fault,
followed by a cool down cycle. After a total of 7 faults, the
LTC4421 keeps the inputs disconnected from the output
until the DISABLE1 is toggled low, then high.
Figure7.
Auto-Retry After Overcurrent Fault on Channel 1. Conditions: RETRY = 0V, FAULT1
Connected to DISABLE1 and Output Short Released During Second Cool Down Time
Figure8. 6 Retries After Overcurrent Fault on Channel 1. Conditions: RETRY = 3V, DISABLE1 = 4V and Output Short Never Released
OUT1
I(RSENSE1)
TMR1
FAULT1
DISABLE1
tTMR,FLT
COOL DOWN TIME =
(1024 • tTMR,FLT)
OVERCURRENT
FAULT
OUTPUT SHORT
TO GROUND
LTC4421 F08
OUT1
I(RSENSE1)
TMR1
FAULT1
DISABLE1
tTMR,FLT
tTMR,FLT
COOL DOWN TIME = (1024 • tTMR,FLT)
COOL DOWN TIME = (1024 • tTMR,FLT)
OVERCURRENT
FAULT
OVERCURRENT
FAULT
OUTPUT SHORT
TO GROUND
COOL DOWN
COMPLETE
LTC4421 F07
RECONNECT
OUTPUT SHORT
RELEASED
COOL DOWN
COMPLETE
RECONNECT
INITIATE
COOL DOWN
INITIATE
COOL DOWN
LTC4421
20
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APPLICATIONS INFORMATION
The overcurrent fault times are independently settable for
each channel. Set the time to ensure the output can charge
from 0V to the maximum input voltage, as described
above. Whenever Channel 1 experiences a current limit
fault, Channel 2 is allowed to power the output, presuming
Channel 2 is valid. Channel 2 powers the output until the
fault on Channel 1 is cleared.
The RETRY count of 6 counter on a channel is reset when-
ever its input supply is invalid, its DISABLE is driven low, or
a higher priority supply becomes valid. It is also reset when
INTVCC is below the INTVCC GOOD Threshold Voltage and
CPO is below the CPOGOOD Threshold Voltage. Toggling
the RETRY pin low, then high also resets the counter.
Iterating the Application Circuit Solution for MOSFET SOA
If the selected MOSFET does not meet the SOA require-
ments imposed by the initial current limit and output
capacitor values, take one or more of the following steps:
1. Reduce t
TMR,FLT
to meet the MOSFET SOA require-
ments. This requires reducing t(CHG,MAX) from
Equation 10 to ensure tTMR,FLT > t(CHG,MAX). One
way to do this is to reduce COUT. The trade-off is
an increase in output voltage droop during channel
switchover.
2. Reduce tTMR,FLT and t(CHG,MAX) by increasing the cur
-
rent limit I
LIM
. This is only helpful if the reduction
in t(CHG,MAX) provides a larger SOA benefit than the
SOA loss caused by the increased power dissipated
in the MOSFET. For example, assume ILIM = 11A and
ILOAD,CHG = 10A. Using Equation 14.
t(CHG,MAX) =
(C
OUT
• V
IN,MAX
)
11A −10A
=
(C
OUT
• V
IN,MAX
)
1A
(14)
If ILIM is then increased from 11A to 20A, the new result is
given by Equation 15.
t(CHG,MAX) =
(C
OUT
• V
IN,MAX
)
20A −10A
=
(C
OUT
• V
IN,MAX
)
10A
(15)
With t(CHG,MAX) reduced by a factor of 10, we can
reduce tTMR,FLT by a factor of 10. By doubling ILIM,
the maximum power during output short circuits has
doubled, but t(CHG,MAX) has decreased by a factor of
10, so there is a net reduction in the SOA stress. Be
sure the input power supply is capable of sourcing
more current than the new, higher value of I
LIM
. Also,
ensure the new ILIM does not cause UV motorboating.
3. Choose a MOSFET with higher SOA. Look for
MOSFET’s having high BVDSS, as they usually have
better SOA performance.
Charge Pump and Gate Driver Circuitry
The gate drive is provided by a charge pump circuit
that powers CPO. A curve of GATE pin voltage versus
output voltage is shown in the Typical Performance
Characteristics curves. For output voltages less than 4V,
the minimum gate drive voltage is 9V. When the output
voltage is higher than 5V, the gate drive is at least 10V.
A burst mode comparator ensures the gate drive never
exceeds 14V.
When an input supply is invalid, the LTC4421 drives the
GATE pin voltage close to ground using a 50mA pull-
down current. When a supply is valid but turned off, gate
driver parking circuitry regulates the GATE voltage to
1V below the lower of the channel input voltage and the
output voltage. This is called the GATE Parking Voltage.
The LTC4421 also sinks 5µA from the SOURCE pin to
bias the external MOSFETs at their threshold voltages,
to minimize the ΔVGS and hence the turn-on time during
channel switchover when the MOSFETs are turned back
on. If possible, choose a lower threshold MOSFET for
the output MOSFET to preferentially draw the SOURCE
current from VOUT instead of the input supply of the off
channel, and add a resistor from SOURCE to ground to
increase current and hence the VGS.
CPO Charge Pump Capacitor Selection
Connect a reservoir capacitor CCPO between CPO and
CPOREF to provide the charge necessary to turn on the
MOSFETs quickly. The recommended value is approxi-
mately 10× the combined input CISS capacitances of the
two back-to-back MOSFETs on one channel, plus any dis-
crete GATE-to-SOURCE capacitor CG that has been added
to stabilize the current limit loop. A larger CCPO capacitor
LTC4421
21
Rev. 0
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takes a correspondingly longer time to charge up by the
internal charge pump, resulting in longer delays from ini-
tial power-up of the first input supply to first connection
to the output. A smaller capacitor suffers more voltage
drop during a channel turn-on event as it shares charge
with C
G
and the MOSFET C
ISS
capacitances. Given the
limited charging capability of the charge pump, continu-
ously changing channels at rates higher than 80Hz (typi-
cal) eventually depletes the CCPO capacitor, causing dis-
connection of both inputs from the output. At that point,
the charge pump charges the CCPO capacitor above 6.7V,
the inputs are then allowed to reconnect to the output, and
the process repeats.
Analog Current Limit Loop Stability
The active current limit loop is compensated by adding a
capacitor CG between the gate and source of the external
MOSFETs. Choosing 47nF for CG ensures stability for all
recommended MOSFETs. In addition, add a snubber from
the input supply to ground consisting of resistor R
SN
in
series with capacitor CSN. Choose RSN using Equation 16.
RSN =
V
IN
I
LIM
(16)
where VIN is the maximum input supply voltage and ILIM
is the current limit being set by RSENSE. Setting CSN to
10µF works well for all applications. Applications having
small input inductance and low output load current may
use values as low as 1µF for CSN.
Setting Qualification Time for Validity
The QUAL pin sets the amount of time a supply must
be inside the OV, UV voltage window to be valid.
Connect a capacitor CQUAL from QUAL to ground and
use Equation 17 to set the validation time:
t
VALID
= C
QUAL
• 16[ms/nF
]
(17)
where tVALID is the validation time. Note that the validation
time is the same for both channels. To set a fixed qualifi-
cation time of 3.5µs, connect QUAL to INTVCC instead of
connecting a capacitor to ground.
APPLICATIONS INFORMATION
If possible, set a qualification time on the order of 10ms
or longer. This allows the LTC4421’s gate driver parking
circuitry to pre-bias the GATE1 voltage to its GATE Parking
Voltage when hot-plugging the V1 input supply. This will
reduce switchover time and hence output voltage droop
when switching from Channel 2 to Channel 1.
Optional Charge Pump Pre-Charge Circuit
The LTC4421 prevents the input supplies from being
validated and powering the output until the external CCPO
capacitor voltage is charged to 6.7V (V
CPO(UVL)
) above the
higher of the CPOREF and INTVCC voltages. With a typical
CCPO capacitor of 1µF, the charge pump voltage may take
several hundred milliseconds to charge to 6.7V. For input
supplies ≥ 12V, this time can be shortened by pre-charging
the CPO pin with the circuit shown in Figure9. The 12V
Zener diode Z1 and NPN transistor Q1 are used to quickly
charge the CPO voltage to about 10.8V above ground. For
V1, V2 voltages below 12V, the circuit pre-charges CPO
to a voltage approximately 1.8V below the higher of the
V1 and V2 voltages. Diode D3 prevents reverse current
conduction when an input supply is connected to VOUT
and causes the CPO voltage to rise above 9V. Diodes D1
and D2 form a diode-OR circuit that powers the Z1 and Q1
from the higher of the V1 and V2 input supply voltages.
Figure9. Optional CPO Pre-Charge. The Higher Voltage of Input
Supplies V1 and V2 Pre-Charges the CPO Voltage to Reduce
System Power-Up Time
CPO
CPOREF
CCPO
1µF
12V
Z1
BZX84C12L
R1
1k
D1
1N4148
COUT
220µF
D2
1N4148
R2
100k
D3
1N4148
D4
1N4148
Q1
2N2222
VOUT
LTC4421
LTC4421 F09
V1
V2
LTC4421
22
Rev. 0
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APPLICATIONS INFORMATION
Minimizing Bias Current Draw from Lower Priority
Supplies
In order to minimize current draw from lower priority
power sources, the LTC4421 draws the vast majority of
its supply current from the highest priority available sup-
ply. When SHDN is high and EXTVCC is connected to the
system output voltage, the LTC4421 consumes 600µA
from the supply powering the output and only 10µA to
26µA from the other supplies. When SHDN is low, the 6µA
(typical) is drawn from the highest of the V1, V2, EXTVCC
and OUT1 voltages, and the supply current in each of the
other, lower voltage pins is a miniscule 250nA.
Digital Status Outputs VALID1, VALID2, CH1, CH2
The LTC4421 provides open-drain pull-down digital out-
puts to provide system status information. The VALID1
and VALID2 pins pull low when their respective V1 and V2
input supplies have been validated. The CH1 and CH2 pins
pull low when their input supply is connected to the output
voltage. Connect large value pull-up resistors between
these pins and INTVCC to provide the logic high, taking
care not to exceed the 500µA maximum current draw
from INTVCC. The pull-downs are capable of driving low
power LED’s, but they cannot be pulled up to INTVCC in
that case due to the LED current required. When using
LED’s, power the pull-up from a supply voltage up to 36V.
These outputs can be used in conjunction with the DISABLE
pins in a variety of application circuits to change V1, V2 pri-
ority over time. For example, consider what happens when
CH2 is connected to DISABLE1. Once V2 is connected to
the output, it will continue to power the output regardless of
V1’s validity. In effect, V2 became the higher priority supply,
but only after it connected to the output. This configuration
can be used in systems where, after switching to the sec-
ondary supply, it is desirable to run the secondary supply
to full discharge before re-connecting to the primary. For
proper operation at power up, it is essential that Channel 1
becomes valid before Channel 2.
In Figure10, logic gates U1 and U2 disable channel 1
whenever V2 is valid, enabled and does not have a latched
overcurrent fault. Disabling channel 1 disconnects V1
from the output and allows V2 to connect to the output.
This configuration permanently flips V1 and V2 priority,
so that V2 is always the higher priority input.
In Figure11, inverter U1 is used to connect the logically
inverted VALID2 signal to DISABLE1. This configuration
prevents Channel 1 from connecting to the output when-
ever Channel 2 is invalid. This prevents the primary input
from powering the output unless a valid secondary supply
is available to power the output when the primary fails.
Input and Output Short Circuits and Supply Transient
Protection
When an input supply powering the output is shorted
to ground, the LTC4421 senses reverse current through
the sense resistor. When the reverse voltage developed
DIS2
VALID2
FAULT2
DISABLE1
DISABLE2
RFLT2
100k
RVLD2
100k
LTC4421
LTC4421 F10
5V
U1
U2
RVLD2
100k
DISABLE1
VALID2
LTC4421
LTC4421 F11
5V
Figure10. Flip Priority. Two External Logic Gates Are Used to
Flip Priorities of Channel 1 and Channel 2
Figure11. Valid Secondary Required. Preventing the Primary
Input Supply from Powering the Output Unless a Valid Secondary
Supply Is Present
LTC4421
23
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across the sense resistor exceeds 30mV, the LTC4421
sinks 50mA from the GATE pin of the shorted channel to
turn off the N-Channel MOSFETs, thereby disconnecting
the input from the output. Assuming the input is still valid,
reconnection occurs when the output voltage drops 35mV
below the input.
When the output is shorted to ground, the voltage across
the sense resistor may exceed 25mV until the current
limit loop enters regulation. When the forward voltage
across the sense resistors exceeds 50mV, the LTC4421
sinks 50mA from the GATE pin to quickly reduce the VGS
of the N-Channel MOSFETs. The 50mA sink current is
turned off when the voltage across the sense resistor falls
below 25mV.
When the output is shorted to ground, the current limit
circuitry will regulate the current to ILIM. When the cur-
rent limit circuitry has been engaged for longer than the
time set by the TMR pin, a current limit fault is registered.
The input is disconnected from the output, and FAULT is
driven low.
For large input and output inductances, rapid changes
in current during short circuit events and channel turn-
off can cause transient voltages that exceed the Absolute
Maximum ratings of the input and output pins and/or vio-
late the BVDSS limits of the external MOSFETs. To minimize
APPLICATIONS INFORMATION
such transients, use wider PCB traces and heavier trace
plating to reduce power trace inductance. External to
the PCB, twist the power and ground wires together to
minimize inductance. Although the input snubber helps
dissipate the input inductive energy at channel turn-off,
transient voltage suppressor (TVS) D1 is still needed to
clamp the peak input voltage, as shown in Figure12.
When selecting transient voltage suppressors, ensure the
reverse standoff voltage (VR) is equal to or greater than
the application operating voltage, the peak pulse current
(IPP) is higher than the peak transient voltage divided by
the source impedance, and the maximum clamping volt-
age (VCLAMP) at the rated IPP is less than the Absolute
Maximum ratings of the LTC4421 and the BVDSS of the
external MOSFETs. The LTC4421’s Absolute Maximum
Voltage Ratings of V1 and V2 allow it to withstand supply
side inductive voltage spikes up to 60V. A range of TVS’s
can be used accommodating V
R
ratings up to 36V and
VCLAMP ratings up to 60V.
Cascading
Multiple LTC4421’s can be cascaded to prioritize more
than two input supplies. To prioritize three or four sup-
plies, use two LTC4421’s with their OUT pins connected
together, and connect CASOUT of the higher priority
M1
PSMN4R060YS
M2
PSMN1R440YLD
2.5mΩ
RSENSE
CG1
47nF
RSN
CSN
COUT1
220µF
D1
SMDJ36A
VOUT
V1
INPUT
PARASITIC
INDUCTANCE
LTC4421 F12
GATE1
SOURCE1
V1
SENSE1
OUT1
LTC4421
Figure12. Supply Voltage Transient Suppression Circuitry
LTC4421
24
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APPLICATIONS INFORMATION
master LTC4421 to CASIN of the lower priority slave
LTC4421, as shown in Figure13.
When both master input supplies are invalid, the master
verifies that it has disconnected both supplies from the
output before driving its CASOUT pin high. This ensures
the reverse conduction paths from the output back to the
master inputs are blocked before the slave is allowed to
power the output. The master LTC4421 pulls CASOUT
up to INTVCC using a 20µA current source, allowing the
slave LTC4421 to connect its highest priority valid supply
to the output.
When the slave is powering the output and one of the
master’s inputs becomes valid, the master simultane-
ously connects its valid channel to the output and drives
its CASOUT pin low to force the slave to disconnect its
inputs. To prevent cross conduction, make the connection
between the master’s CASOUT and slave’s CASIN as short
as possible. This minimizes the capacitance of the con-
nection and hence the turn-off delay of the slave channel.
This scheme can be extended to prioritize as many input
supplies as necessary. Connect each additional lower
priority LTC4421’s OUT pins to the common output volt-
age and connect its CASIN pin to the CASOUT pin of the
next higher priority LTC4421. Note that driving the mas-
ter LTC4421’s CASIN pin low disconnects all input sup-
plies in the system. Driving the master’s DISABLE1 and
DISABLE2 pins low disconnects the master’s inputs from
the output and allows the slave LTC4421’s to connect to
the output.
Figure13. Using Two LTC4421’s in a Cascading Application to Prioritize Four Input
Supplies. (The Master and Slave V2 Power Paths are Omitted for Clarity)
CG1
M1
SiR158DP
M2
SiR158DP
2.5mΩ
RSENSE1
47nF
GATE1
SOURCE1
CASIN
CASOUT
V1
SENSE1
OUT1
DISABLE1
DISABLE2
M5
SiR158DP
M6
SiR158DP
2.5mΩ
RSENSE3
CG3
47nF
CASIN
SHDN
CASOUT
VOUT
V1
V3
LTC4421
MASTER
LTC4421
LTC4421 F13
SLAVE
L = DISCONNECT ALL CHANNELS
H = CONNECT HIGHEST PRIORITY VALID CHANNEL
L = DISABLE MASTER, ENABLE SLAVE
CONNECT HIGH
GATE1
SOURCE1
V1
SENSE1
OUT1
LTC4421
25
Rev. 0
For more information www.analog.com
Design Example
As a design example, take the following specifications for
the circuit in Figure14. For simplicity, the same specifica-
tions and hence the same component values are used for
each channel. The application is rated for an input voltage
of 12V, maximum output load current of 8A, UV rising =
11V, UV falling = 8V, OV Rising = 15V and maximum output
voltage drop during switchover = 1.2V (10% of the input
supply voltages). The minimum and maximum operating
ambient temperatures are –40°C and 85°C, respectively.
Start by setting the current limit to 16A, so that the out-
put voltage can be charged at full DC load conditions in
a reasonable amount of time as shown by Equation 18
(from Equation 6).
RSENSE =
25mV
16A
=1.5625mΩ
(18)
APPLICATIONS INFORMATION
The nearest standard value sense resistor is 1.5mΩ,
which results in a current limit of 16.7A.
Choose an electrolytic output capacitor having
RESR=50mΩ. During switchover is given by Equation 19
(from Equation 8).
V
STEP
= (8A • 50mΩ) = 400mV
(19)
To keep the total output voltage drop during switchover
to less than 1.2V, the maximum droop must be ≤ 800mV.
Therefore is given by Equation 20 (from Equation 9).
COUT ≥8A • 15µs
( )
800mV
=150µF
(20)
so we choose COUT = 220µF for margin.
Figure14. Dual 12V, 8A Application Circuit for Design Example
CINTVCC
1µF
CTMR2
6.8nF
CTMR1
6.8nF
CQUAL
1nF
931k
R4
RSN1
1.2Ω
CSN1
10µF
16.9k
R3
12.1k
R2
33.2k
R1
931k
R8
16.9k
R7
12.1k
R6
33.2k
R5
C2
0.1µF
M1
PSMN4R060YS
M2
PSMN1R440YLD
ILIM1 = 16.7A
ILIM2 = 16.7A
M3
PSMN4R060YS
M4
PSMN1R440YLD
CCP0
1µF
COUT
220µF
1.5mΩ
RSENSE1
1.5mΩ
RSENSE2
EXTVCC
INTVCC
TMR1
OV1
OV2
VALID1
VALID2
GND
FAULT1
FAULT2
CH1
CH2
DISABLE1
DISABLE2
SHDN
UVF1
UVF2
UVR1
UVR2
TMR2
CASIN
CASOUT
QUAL
RETRY
47nF
CG1
CG2
47nF
D1
SMBJ24CA
D2
SMBJ24CA
PRIMARY
12V
VOUT
8A
SECONDARY
12V
LTC4421
LTC4421 F14
DIGITAL
STATUS
OUTPUTS
DIGITAL
CONTROL
INPUTS
VUVFALL1 = 8V
VUVRISE1 = 11V
VOVRISE1 = 15V
VUVFALL2 = 8V
VUVRISE2 = 11V
VOVRISE = 15V
RSN2
1.2Ω
CSN2
10µF
GATE1
SOURCE1
OUT2
GATE2
SOURCE2
V1
V2
CPO
SENSE1
SENSE2
OUT1
CPOREF
LTC4421
26
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
Next, calculate the time it takes to charge the output volt-
age from 0V to 12V at the maximum DC load current as
shown in Equation 21 (from Equation 10).
tCHG(MAX) =
(220µF • 12V)
(16.7A – 8A) = 303µs
(21)
To ensure the output will fully charge before trigger-
ing an overcurrent fault time-out, choose C
TMR1
to set
tTMR,FLT = 450µs. See Equation 22 (from Equation 13).
CTMR1 = 450µs
83[µs/nF]
⎛
⎝
⎜⎞
⎠
⎟= 5.4nF
(22)
Using the nearest standard value and accounting for tol-
erance, we choose 6.8nF, which yields tTMR,FLT = 564µs.
The power dissipation during short circuits is given by
Equation 23 (from Equation 11).
Power = (12V • 16.7A) = 200W
(23)
Referring to the SOA curves in the PSMN4R060YS data
sheet, the MOSFET can withstand 720W for 1ms at 25°C
and 12V. Derating the SOA for the maximum operating
temperature is given by Equation 24 (from Equation 12).
SOA(85°C) = 720W •
(175 – 85)
(175 – 25)= 432W at 1ms
(24)
Our overcurrent fault time-out will occur for 200W at
564µs, so the requirement is satisfied.
Next, select 47nF capacitors CG1 and CG2 to compensate
the current limit regulation loops of channels 1 and 2,
respectively. D1 and D2 are bidirectional Transient Voltage
Suppression (TVS) diodes that clamp the input voltages
below 40V at channel turn-off, thereby protecting the
LTC4421 and the N-Channel MOSFETs.
The OV, UV monitoring resistors should be chosen to yield
a total divider resistance of between 1MΩ and 2MΩ for
both low power and good transient response time. Using
Equation 1 through Equation 4 and rounding up to the
nearest 1% accurate standard resistor values, R1-R4 are
calculated by Equation 25.
Choose R1 + R2 + R3 + R4 = 1000kΩ
(25)
From Equation 2, R1 = (0.5/15) • 1000kΩ = 33.3kΩ. The
nearest standard resistor value is 33.2kΩ.
From Equation 3, R2 = (15/11 – 1) • 33.2kΩ = 12.07kΩ.
The nearest standard value is 12.1kΩ.
From Equation 4, R3 = (11/8 – 1) • (15/11) • 33.2kΩ =
16.98kΩ. The nearest standard value is 16.9kΩ.
From Equation 5, R4 = (15/0.5 – 1) • 33.2kΩ – 12.1kΩ –
16.9kΩ = 933.8kΩ. The nearest standard value is 931kΩ.
From Equation 17, CQUAL is set to 1nF to set an OV, UV
validation time of 16ms. This gives the LTC4421 time to
pre-charge the GATE1 voltage to minimize turn-on time
when V2 is powering the output and the V1 input supply
is plugged in.
PCB Layout Considerations
To achieve accurate current sensing, Kelvin connections
are recommended for the sense resistors. The PCB lay-
out for the sense resistors should be balanced and sym-
metrical to minimize wiring errors. In addition, the PCB
layout for the sense resistors and power MOSFETs should
include good thermal management techniques for opti-
mal device power dissipation. Small resistances add up
quickly in high current applications. Note that 1oz copper
exhibits a sheet resistance of about 530µΩ/square. The
minimum trace width for 1oz copper is 0.02" per amp
(0.5mm per amp) to make sure the trace stays at a rea-
sonable temperature. Using 0.03” per amp (0.8mm per
amp) is recommended.
To improve noise immunity, put the OV, UVR, UVF resis-
tive dividers close to the LTC4421 and keep traces to GND
pin and the input supply pin short. It is also important to
put CINTVCC, the bypass capacitor for the INTVCC pin, as
close as possible between INTVCC and GND. Place CCPO,
the charge pump reservoir capacitor, as close as possible
between the CPO and CPOREF pins. Transient voltage sup-
pressors D1 and D2 are located close to the LTC4421 and
are connected between the input supply and ground using
wide traces. Figure15 shows a recommended PCB layout
for a 2-layer board.
LTC4421
27
Rev. 0
For more information www.analog.com
Preventing Input Hold-Up During Unplug Events
Figure16 includes a backplane connector with a kelvin
sense. The resistive divider network that sets the OV
and UV thresholds is connected to the kelvin sense.
Disconnecting the supply powering V1 causes a nearly
immediate UV fault, because there is no hold-up capaci-
tance on the OV1, UVF1 or UVR1 pins. The output volt-
age discharges minimally before the UV fault occurs, as
the output discharge rate is very slow compared to the
UV fault time. Without a kelvin sense connection, upon
input supply disconnection the resistive divider would
stay connected to the drain of M1. The output, OV1, UVF1
and UVR1 pin voltages would all fall at the rate dictated
by the output discharge, and the channel would not be
disconnected until the output voltage dropped below the
UVF1 threshold voltage.
APPLICATIONS INFORMATION
SOA Doubler
Multiple LTC4421’s can be used to control parallel MOSFET
pathways from each input to the output, as shown in Figure17.
This is valuable in very high current applications to cut the
SOA and load current carrying burdens of each MOSFET in
half. LTC4421 #1 acts as a master and performs all monitor-
ing functions, including OV, UV, fault and reverse current. After
LTC4421 #2 drives the VALID12 and VALID22 signals low to
indicate that it has successfully powered up, it acts as a slave
to LTC4421#1, turning its external MOSFETs on and off at
LTC4421#1’s command. Connecting LTC4421 #1’s CH1 and
CH2 outputs through inverters U3 and U4 to LTC4421 #2’s
DISABLE1 and DISABLE2 inputs, respectively, synchronizes
channel turn-on and turn-off of the two LTC4421’s. NOR gates
U1 and U2 prevent LTC4421 #1 from turning on its MOSFETs
until LTC4421 #2’s inputs are validated. This ensures that
LTC4421 #1 never turns on its MOSFETs when LTC4421 #2
is unable to turn on its MOSFETs.
Figure15. Recommended 2-Layer PCB Layout
GATE1
UVF1
UVR1
FAULT1
CASIN
INTVCC
CASOUT
QUAL
UVR2
UVF2
V2
GATE2
EXTVCC
CPO
CPOREF
OUT1
SENSE1
SOURCE1
SOURCE2
1
2
4
5
11
12
13
14
15
24
25
27
28
32
33
34
35
36
37
FROM V1
INPUT SOURCE
M1
M2
RETRY
SHDN
FAULT2
17
18
SENSE2
OUT2
29
30
TMR1
DISABLE1
CH1
VALID1
OV1
6
7
8
9
10
VALID2
CH2
DISABLE2
TMR2
OV2
19
20
21
22
23
RSENSE1
RSN1
CSN1
RSN2
CSN2
0.03" PER
AMPERE
D1
TRANSIENT
VOLTAGE
SUPPRESSOR
R2
CCPO
CTMR1
CINTVCC
GND
GND
LTC4421 F15
NOT TO SCALE
G
FROM V2
INPUT SOURCE
M3
M4
RSENSE2
0.03" PER
AMPERE
D2
TRANSIENT
VOLTAGE
SUPPRESSOR
CTMR2
Layer 1
Layer 2
VOUT
METAL
D
S
G
S
G
D
D
S
G
S
D
3
V1
26
R2
R4
R7
R1
R5
R6
R8
R3
16
GND
31
LTC4421
28
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
M1
PSMN4R060YS
M2
PSMN1R440YLD
2.5mΩ
RSENSE1
CCPO
1µF
COUT
220µF
ILOAD
R1
35.7k
R2
12.7k
R3
20k
R4
1MΩ
CG1
47nF
GATE1
SOURCE1
CPO
CPOREF
UVF1
V1
UVR1
OV1
SENSE1
OUT1
VOUT
VIN
LTC4421 F16
CONNECTOR1
CONNECTOR2
KELVIN
GND
LTC4421
Figure16. Preventing Input Hold-Up During Unplug Events with a Staggered
Connector to Decouple OV and UV Pins from VOUT
LTC4421
29
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure17. SOA Doubler. Using Two LTC4421’s in a Master–Slave Configuration to Split
Current and SOA Burden Between Parallel Pairs of MOSFETs in High Current Applications
C2
0.1µF
M1
PSMN4R8100BSE
M2
PSMN1R440YLD
M3
PSMN4R8100BSE
M4
PSMN1R440YLD
COUT1
470µF
D1
SMDJ36A
D2
SMDJ36A
RSENSE1
2.5mΩ
RSENSE2
2.5mΩ
CG2
CG1
47nF
MAIN
12V
VOUT
RESERVE
28V
COUT2
470µF
ILIM1(TOT) = 20A
ILIM2(TOT) = 20A
CCPO1
1µF
VPULLUP
VPULLUP
ENABLE1
ENABLE2
CINTVCC1
1µF
R1
35.7k
R2
12.7k
R3
20k
R4
1MΩ
R5
15.4k
R6
6.19k
R7
69.8k
R8
1MΩ
CTMR2
47nF
CTMR1
47nF
CQUAL
470pF
EXTVCC
INTVCC
TMR1
OV1
OV2
VALID1
VALID2
GND
FAULT1
FAULT2
CH1
CH2
DISABLE1
DISABLE2
SHDN
UVF1
UVF2
UVR1
UVR2
TMR2
CASIN
CASOUT
QUAL
RETRY
47nF
M5
PSMN4R8100BSE
M6
PSMN1R440YLD
M7
PSMN4R8100BSE
M8
PSMN1R440YLD
RSENSE3
2.5mΩ
RSENSE4
2.5m
10k
RVLD1
10k
RCH1
10k
RVLD2
D5
1N4148
D6
1N4148
100k
RLIM2
D7
1N750
10k
RLIM1
CPULL
1µF
10k
RCH2
10k
RFLT2
10k
RFLT1
Q1
2N2222
LTC4421 #1
MASTER
UV1FALLING = 7.81V
UV1RISING = 11.04V
OV1RISING = 14.96V
UV2FALLING = 5.97V
UV2RISING = 25.28V
OV2RISING = 35.4V
U1
U2
RSN1
0.6Ω
CSN1
10µF
C
INTV
CC2
1µF
LTC4421 F17
RSN2
1.4Ω
CSN2
10µF
VPULLUP
VALID12
VALID22
CH1
CH2
0.1µF
CCPO2
1µF
EXTVCC
INTVCC
TMR1
OV1
OV2
VALID1
VALID2
GND
FAULT1
FAULT2
CH1
CH2
DISABLE1
DISABLE2
SHDN
UVF1
UVF2
UVR1
UVR2
TMR2
CASIN
CASOUT
QUAL
RETRY
CG3
47nF
CG4
47nF
10k
RVLD4
10k
RVLD3
LTC4421 #2
SLAVE
U3
U4
GATE1
SOURCE1
OUT2
GATE2
SOURCE2
V1
V2
CPO
SENSE1
SENSE2
OUT1
CPOREF
GATE1
SOURCE1
OUT2
GATE2
SOURCE2
V1
V2
CPO
SENSE1
SENSE2
OUT1
CPOREF
LTC4421
30
Rev. 0
For more information www.analog.com
PACKAGE DESCRIPTION
5.00 ±0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
1
10
20
28
1119
3629
BOTTOM VIEW—EXPOSED PAD
4.50 REF
6.00 ±0.10
R = 0.125
TYP
0.25 ±0.05
4.60 ±0.10
3.60
±0.10
(UHE36) QFN 0410 REV Ø
0.50 BSC
4.60 ±0.05
3.60 ±0.05
0.75 ±0.05
0.00 – 0.05
0.200 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.50 REF
0.40 ±0.10
0.70 ±0.05
0.50 BSC
4.50 REF
3.50 REF
4.10 ±0.05
5.50 ±0.05
5.10 ±0.05
6.50 ±0.05
0.25 ±0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP
OR 0.35 × 45°
CHAMFER
R = 0.10
TYP
UHE Package
36-Lead Plastic QFN (5mm × 6mm)
(Reference LTC DWG # 05-08-1876 Rev Ø)
LTC4421
31
Rev. 0
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PACKAGE DESCRIPTION
G36 SSOP 0204
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
7.40 – 8.20
(.291 – .323)
12345678 9 10 11 12 14 15 16 17 1813
12.50 – 13.10*
(.492 – .516)
2526 22 21 20 19232427282930313233343536
2.0
(.079)
MAX
0.05
(.002)
MIN
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
LTC4421
32
Rev. 0
ANALOG DEVICES, INC. 2019
11/19
www.analog.com
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
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LTC4418 Dual Prioritized PowerPath Controller 2.5V to 40V Operation; Ext P-Channel MOSFET; –42V Reverse Protection
LTC4419 Dual Prioritized PowerPath Controller 1.8V to 18V Operation; 0.5A Switches; Freshness Seal
LTC4420 Dual Prioritized PowerPath Controller 1.8V to 18V Operation; 0.5A Switches; Freshness Seal; Backup Disconnect
LTC4411 Single 2.6A Ideal Diode 2.6V to 5.5V Operation; 140mΩ RON; 40µA IQ
LTC4358 Single 5A Ideal Diode 9V to 26.5V Operation; 20mΩ RON; 780µA IQ
LTC4413 Dual 2.6A Ideal Diode 2.5V to 5.5V Operation; 140mΩ RON; 25µA IQ
LTC4415 Dual 4A Ideal Diode 1.7V to 5.5V Operation; 50mΩ RON; 44µA IQ
Secondary Supply Run Down to 500mV Using LTC3119 to Power EXTVCC
C7
0.1µF
R14
100k
C9
0.1µF
C10
220µF
R9
78.7k
R12
100k
R13
316k
C11
820pF
VOUT
3.3V
L1
4.7µH
CINTVCC
1µF
35.7k
R1
12.7k
R2
20k
R3
1MΩ
R4
35.7k
R5
12.7k
R6
1.02M
R7
C2
0.1µF
M1
PSMN4R060YS
M2
PSMN1R440YLD
M3
PSMN4R060YS
M4
PSMN1R440YLD
CCPO
1µF
CTMR2
47nF
CTMR1
47nF
CQUAL
470pF
COUT1
220µF
RSENSE1
1.5mΩ
RSENSE2
1.5mΩ
C8
4.7µF
R10
162k
D1
SMBJ24CA
D2
SMBJ24CA
CG1
47nF
GATE1
SOURCE1
OUT2
GATE2
SOURCE2
V1
EXTVCC
INTVCC
TMR1
OV1
OV2
V2
CPO
SENSE1
SENSE2
VALID1
VALID2
GND
FAULT1
FAULT2
CH1
CH2
DISABLE1
DISABLE2
SHDN
UVF1
UVF2
UVR1
UVR2
OUT1
TMR2
CASIN
CASOUT
QUAL
RETRY
CPOREF
CG2
47nF
PRIMARY
12V
SECONDARY
12V
LTC4421
LTC4421 TA02
DIGITAL
STATUS
OUTPUTS
DIGITAL
CONTROL
INPUTS
UVR1 = 11.04V
UVF1 = 7.81V
OV1 = 14.96V
UVR2 = 11.04V
UVF2 = 500mV
OV2 = 14.96V
BST1
SW2
SW1
BST2
PVIN
VIN
RUN
PWM/SYNC
VCC
SVCC
MPPC
RT
PGND
GND
VC
PGOOD
PVOUT
FB
LTC3119
RSN2
1.2Ω
CSN2
10µF
RSN1
1.2Ω
CSN1
10µF
D3