LTC4421 High Power Prioritized PowerPath Controller FEATURES DESCRIPTION 0V to 36V Wide Operating Range (60V Tolerant) n Drives Large External N-Channel MOSFETs for High Output Current Applications n Accurately Limits Inrush Current n Connects Highest Priority Valid Supply to Output Load n Changes Channel Priority in Real Time n 2% OV, UV Input Comparators n Individually Adjustable Current Limit Time-Out for Each Channel n Adjustable Input Validation Time n Fast Switchover Minimizes V OUT Droop n 36-Lead 5mm x 6mm QFN and SSOP Packages The LTC(R)4421 connects one of two input supplies to a common output based on user-defined priority and validity. By definition, the supply connected to V1 is the higher priority supply, although this can be changed dynamically. External resistive dividers set the undervoltage and overvoltage thresholds that bound the valid voltage window. APPLICATIONS External sense resistors set the maximum inrush and current limit currents. During current limiting, the LTC4421 controls the N-channel MOSFET gate to regulate 25mV across the sense resistor. When the sense resistor voltage has been regulated to 25mV for a user-settable time, the channel is disconnected and a fault is set. n Strong gate drivers switch the large external N-channel MOSFETs quickly. Fast switchover circuitry minimizes output droop when changing channels while preventing reverse and cross conduction. A fast comparator detects input short circuits and quickly turns off the N-channel MOSFETs to minimize disruption. High Reliability Systems Server Based Back-Up Systems n Industrial Handheld Instruments n Battery Back-Up Systems n n All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION ILIM1 = 10A 2.5m PRIMARY 12V VOUT 1.21 220F 1F SECONDARY 28V ILIM2 = 10A 2.5m 2.8 1F 1M V1 47nF 47nF 1F GATE1 SOURCE1 SENSE1 OUT1 CPO CPOREF V2 GATE2 SOURCE2 SENSE2 OUT2 EXTVCC UVF1 0.1F 20k UVR1 12.7k OV1 35.7k LTC4421 1M UVF2 8.06k UV1FALLING = 7.81V UV1RISING = 11.04V OV1RISING = 14.96V UV2FALLING = 18.1V UV2RISING = 25.2V OV2RISING = 31.2V UVR2 3.92k OV2 16.5k GND QUAL TMR1 470pF TMR2 47nF INTVCC 47nF 1F VALID1 VALID2 CH1 CH2 FAULT1 FAULT2 CASOUT DIGITAL STATUS OUTPUTS RETRY DISABLE1 DISABLE2 SHDN CASIN DIGITAL CONTROL INPUTS 4421 TA01 Rev. 0 Document Feedback For more information www.analog.com 1 LTC4421 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltages V1, V2, EXTVCC.........................................-10V to 60V OUT1, OUT2, CPOREF...............................-10V to 45V Input Voltages DISABLE1, DISABLE2, SHDN.................. -0.3V to 60V CASIN....................................................... -0.3V to 6V SENSE1, SENSE2, SOURCE1, SOURCE2...-10V to 45V UVF1, UVF2, UVR1, UVR2, OV1, OV2..... -0.3V to 60V RETRY, TMR1, TMR2, QUAL....-0.3V to INTVCC+0.3V Output Voltages VALID1, VALID2, CH1, CH2, FAULT1, FAULT2, CPO.............................. -0.3V to 60V INTVCC...................................................... -0.3V to 6V GATE1, GATE2 (Note 3) ..............................-0.3V to CPO CASOUT....................................................... -0.3V to 6V Output Currents FAULT1, FAULT2, CH1, CH2, VALID1, VALID2, CASOUT................................................................5mA Operating Ambient Temperature Range LTC4421C................................................. 0C to 70C LTC4421I..............................................-40C to 85C LTC4421H........................................... -40C to 125C Storage Temperature Range................... -65C to 150C PIN CONFIGURATION TOP VIEW SENSE2 OUT2 GND EXTVCC CPO CPOREF OUT1 SENSE1 TOP VIEW 36 35 34 33 32 31 30 29 SOURCE1 1 37 OV1 6 TMR1 7 32 SOURCE2 GATE1 6 31 GATE2 V1 7 30 V2 24 UVR2 UVF1 8 29 UVF2 23 OV2 UVR1 9 28 UVR2 21 DISABLE2 CH1 9 20 CH2 19 VALID2 VALID1 10 FAULT2 SHDN RETRY QUAL CASOUT INTVCC CASIN 11 12 13 14 15 16 17 18 FAULT1 34 OUT2 33 SENSE2 22 TMR2 DISABLE1 8 OUT1 5 25 UVF2 UVR1 5 35 GND 3 4 26 V2 UVF1 4 36 EXTVCC 2 SENSE1 27 GATE2 V1 3 1 SOURCE1 28 SOURCE2 GATE1 2 CPO CPOREF UHE PACKAGE 36-LEAD (5mm x 6mm) PLASTIC QFN TJMAX = 150C, JA = 43C/W, JC = 5C/W EXPOSED PAD (Pin 37), PCB GND CONNECTION OPTIONAL OV1 10 TMR1 11 DISABLE1 12 CH1 13 27 OV2 26 TMR2 25 DISABLE2 24 CH2 VALID1 14 23 VALID2 FAULT1 15 22 FAULT2 CASIN 16 21 SHDN INTVCC 17 20 RETRY CASOUT 18 19 QUAL G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 150C, JA = 70C/W Rev. 0 2 For more information www.analog.com LTC4421 ORDER INFORMATION TUBE TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4421CG#PBF LTC4421CG#TRPBF LTC4421G 36-Lead Plastic SSOP 0C to 70C LTC4421IG#PBF LTC4421IG#TRPBF LTC4421G 36-Lead Plastic SSOP -40C to 85C LTC4421HG#PBF LTC4421HG#TRPBF LTC4421G 36-Lead Plastic SSOP -40C to 125C LTC4421CUHE#PBF LTC4421CUHE#TRPBF 4421 36-Lead Plastic QFN 0C to 70C LTC4421IUHE#PBF LTC4421IUHE#TRPBF 4421 36-Lead Plastic QFN -40C to 85C LTC4421HUHE#PBF LTC4421HUHE#TRPBF 4421 36-Lead Plastic QFN -40C to 125C Contact the factory for parts specified with wider operating temperature ranges. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. See the LTC4421 Data Sheet Nomenclature section for more details on pin conditions. V1 = 12V, V2 = 13V, EXTVCC = CPOREF = OUT1 = OUT2 = SENSE1 = SENSE2 = 11V, OV1 = OV2 = TMR1 = TMR2 = OV, UVR1 = UVR2 = UVF1 = UVF2 = DISABLE1 = DISABLE2 = SHDN = RETRY = CASIN = 4V, CPO = 23.5V, QUAL = INTVCC, unless otherwise noted. SYMBOL PARAMETER CONDITIONS VIN V1, V2 Operating Voltage Range (Note 4) VINT(UVL) INTVCC Undervoltage Lockout Threshold Voltage VINT(HYS) INTVCC Undervoltage Lockout Hysteresis VINTVCC INTVCC Output Voltage VINTVCC MIN TYP MAX 36 V 2 2.3 2.6 V l 3.3 3.9 4.5 IINTVCC = 0 to -500A l -35 -85 -200 CPO-CPOREF l 5.7 6.7 7.7 l 3.0 l IINTVCC = 0A INTVCC Voltage Change from Zero to Full Load VCPO(UVL) CPOGOOD Threshold Voltage VCPO(HYS) CPOGOOD Hysteresis 70 UNITS mV 1.4 V mV V V ICC(TOT) Total Input Supply Current V1, V2, OUT1, OUT2, EXTVCC, CPOREF l 0.53 1 mA ICC(SHDN) Total Input Supply Current in Shutdown V1, V2, EXTVCC l 5.4 12 A ICC(PRIO) Input Supply Current of Highest Priority Valid Supply Measure I(EXTVCC) l 360 750 A ICC(VMAX) Input Supply Current of Highest Voltage Input Supply Measure I(V2) l 25 50 A ICC(CPOREF) CPOREF Charge Pump Supply Current CPOREF = 11V l 160 300 A -0.6 -1.5 V PRIORITIZER CONTROL (V1, V2, SENSE1, SENSE2, GATE1, GATE2, SOURCE1, SOURCE2, OUT1, OUT2) VG(OFF) External N-Channel MOSFET Off Threshold Voltage (GATE1 - V1), (GATE2 - V2), GATE Falling l 0 VREV Input to Output Reverse Voltage Connect Threshold (V1- OUT1), (V2-OUT2), OUT1, OUT2 Falling l 0 40 80 mV VGATE(CL) External N-Channel MOSFET Gate Drive, (GATE - CPOREF) CPOREF = 3.2V, EXTVCC = 3.0V, I = 0, -1A CPOREF = 12V, 36V, I = 0, -1A l l 9 10 10.8 11.6 14 14 V V ISOURCE, HLD SOURCE Hold Current SOURCE = 12V, Channel Off l 2.5 5 10 A ISOURCE, OFF SOURCE Fast Off Current SOURCE = 12V, Channel Off l 0.7 1.6 3.2 mA IGATE(ON) GATE On Pull-Up Current V(SENSE) - V(OUT) = 0V, GATE = 16V, OUT = 10V, V1 = V2 = 12V l -8 -16.5 -26 mA V(SENSE)-V(OUT) = 100mV, GATE = 16V, OUT = 10V, V1 = V2 = 12V l 30 54 124 mA IGATE(OFF,FWD) GATE Off Pull-Down Current, Large Forward Sense Voltage Rev. 0 For more information www.analog.com 3 LTC4421 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. See the LTC4421 Data Sheet Nomenclature section for more details on pin conditions. V1 = 12V, V2 = 13V, EXTVCC = CPOREF = OUT1 = OUT2 = SENSE1 = SENSE2 = 11V, OV1 = OV2 = TMR1 = TMR2 = OV, UVR1 = UVR2 = UVF1 = UVF2 = DISABLE1 = DISABLE2 = SHDN = RETRY = CASIN = 4V, CPO = 23.5V, QUAL = INTVCC, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX IGATE(OFF,REV) GATE Off Pull-Down Current, Negative Sense Voltage V(SENSE)-V(OUT) = -50mV, GATE = 16V, OUT = 10V, V1 = V2 = 12V l 30 50 92 mA VSNS Current Limit Sense Voltage, VSNS = (SENSE - OUT) OUT = 1V, 12V, 32V EXTVCC = 3.0V, OUT = 1V l l 20 20 25 25 30 30 mV mV VSNS,FLD Current Limit Sense Voltage in Foldback, VSNS,FLD = (SENSE - OUT) OUT = 0V l 7.5 12.5 17.5 mV OUT1 l 380 480 580 mV VFLD,TH Foldback Threshold Voltage VFLD,HYST Foldback Hysteresis VSNSDIS,FWD Forward Overcurrent Disconnect Voltage SENSE - OUT, Rising VSNSDIS,REV Reverse Current Disconnect Voltage SENSE - OUT, Falling ISNS SENSE Input Current SENSE = OUT = 12V l UNITS 50 mV 50 mV -30 mV 1 A tG(SWITCH) Gate Break-Before-Make Time CGATE = 47nF l 10.3 15 s tPG(DIS, OFF) Gate Turn-Off Delay from DISABLE Falling DISABLE to Gate < 12V l 1.4 2.7 s tPG(DIS, ON) Gate Turn-On Delay from DISABLE Rising DISABLE to Gate > 12V l 1.3 2.1 s tPG(CAS) CASIN to CASOUT Propagation Delay High-to-Low tPG(DIS, CAS) DISABLE to CASOUT Propagation Delay DISABLE High-to-Low 1 s 2.8 s CURRENT LIMIT TIMER (TMR1, TMR2) ITMR(UP) TMR Pull-Up Current l -3 -6 -9 A ITMR(DN) TMR Pull-Down Current l 1 2 3 A tTMR,FLT TMR Fault Time l 550 830 1250 s CTMR = 10nF %TMR(COOL) TMR Cool Down Ratio to Fault Time 0.1 % OV, UV PROTECTION CIRCUITRY (OV1, OV2, UVF1, UVF2, UVR1, UVR2, QUAL) VTH,OVUV OV, UV Threshold Voltage VHYST, OV OV Hysteresis ILK,OVUV UVR, UVF, OV Input Leakage Current IQUAL,SRC QUAL Source Current IQUAL,SNK QUAL Sink Current tVALID OV, UV Validation Time tINVALID OV, UV Invalidation Filter Time OV Rising, UVF Falling, UVR Rising l 490 500 510 mV l 40 50 60 mV 10 nA l -1 -2 -3 A l 1 2 3 A QUAL = INTVCC CQUAL = 470pF l l 1.75 5 5 7.5 8 11 s ms Overdrive = 50mV l 1.75 5 8 s l 0.5 1.0 1.5 V V = 0.5V l DIGITAL INPUTS (DISABLE1, DISABLE2, SHDN, CASIN, RETRY) VTH Rising Threshold Voltage VHYST Hysteresis Voltage ILK,HV Input Leakage Current V = 36V, DISABLE, SHDN l 0.1 1 A ILK,LV Input Leakage Current V = 5.5V, CASIN Retry = INTVCC l l 0.1 0.1 1 1 A A ICASIN CASIN Pull-Up Current CASIN = 0V l 5 10 A 150 2.5 mV Rev. 0 4 For more information www.analog.com LTC4421 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. See the LTC4421 Data Sheet Nomenclature section for more details on pin conditions. V1 = 12V, V2 = 13V, EXTVCC = CPOREF = OUT1 = OUT2 = SENSE1 = SENSE2 = 11V, OV1 = OV2 = TMR1 = TMR2 = OV, UVR1 = UVR2 = UVF1 = UVF2 = DISABLE1 = DISABLE2 = SHDN = RETRY = CASIN = 4V, CPO = 23.5V, QUAL = INTVCC, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 185 0.58 450 1.35 mV V 1 A DIGITAL OUTPUTS (CH1, CH2, VALID1, VALID2, FAULT1, FAULT2, CASOUT) VOL,HV Output Voltage Low, CH, VALID, FAULT I = 1mA, V1 = V2 = EXTVCC = 3.0V I = 3mA, V1 = V2 = EXTVCC = 3.0V l l IOH,HV Open Drain, Output High Leakage Current V = 36V, CH, VALID, FAULT l VCASO,OH CASOUT Output High Voltage I = -1A , SHDN = 0V l VCASO,OL CASOUT Output Low Voltage I = 1mA l ICASO CASOUT Pull-Up Current CASOUT = 1V l ILK,CASO CASOUT Leakage Current CASOUT = 5.5V l Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. 2 -11 3.4 4.5 V 85 200 mV -22 -40 A 1 A Note 3. Do not drive GATE1 and GATE2 above CPO. Doing so can cause excessive voltage on CPO. Note 4. V1 can operate down to 0V, provided V2 3.0V or EXTVCC 3.0V. Likewise, V2 can operate down to 0V, provided V1 3.0V or EXTVCC 3.0V. LTC4421 DATA SHEET NOMENCLATURE The LTC4421 dedicates 13 pins per channel for the purposes of monitoring each input supply and controlling its connection to the output. Pin names having suffix "1" apply to Channel 1, while those having suffix "2" apply to Channel 2. When no suffix is used when referencing one of these pins, it means that the text applies to the pins on both channels. For example, "Connect a capacitor CTMR from TMR to ground" means "Connect a capacitor CTMR1 between the TMR1 pin and ground" and "Connect a capacitor CTMR2 between the TMR2 pin and ground". References to multiple pin names with no suffix are meant to describe functionality within a channel but apply to both channels. These references occur for the following cases: 1. Connecting two pins together: "Tie FAULT to DISABLE" means "Tie FAULT1 to DISABLE1" and "Tie FAULT2 to DISABLE2". 2. Referring to differential voltages: "SENSE to OUT" means "SENSE1 to OUT1" and "SENSE2 to OUT2". 3.Causation: "The VALID pins pull low when their V1-V2 supplies have been validated" means "The VALID1 pin pulls low when the V1 supply has been validated" and "The VALID2 pin pulls low when the V2 supply has been validated". Rev. 0 For more information www.analog.com 5 LTC4421 TYPICAL PERFORMANCE CHARACTERISTICS GATE Drive Voltage vs CPOREF Voltage 13 6 SENSE VOLTAGE (mV) 5 VOLTAGE (V) TRANSITION TO Burst Mode OPERATION 9 4 3 8 7 EXTVCC = 3.0 EXTVCC 4.0 0 2 4 6 8 10 2 12 2 3 CPOREF VOLTAGE (V) 4 5 26 25 24 23 -50 6 -25 EXTVCC VOLTAGE (V) 50 75 100 0.505 0.500 Total Supply Current vs EXTVCC Voltage 700 650 RISING SUPPLY CURRENT (A) 0.525 THRESHOLD VOLTAGE (V) 0.510 125 4421 G03 Overvoltage Thresholds vs Temperature 0.495 25 4421 G02 Undervoltage Threshold vs Temperature 0.500 0 TEMPERATURE (C) 4421 G01 THRESHOLD VOLTAGE (V) 27 INTVCC, RLOAD = 10k INTVCC, NO LOAD EXTVCC 11 10 SENSE Voltage vs Temperature INTVCC Voltage vs EXTVCC Voltage 12 GATE-CPOREF VOLTAGE (V) TA = 25C, EXTVCC = 11V, unless otherwise noted. 0.475 FALLING 0.450 T = 25C T = 125C T = -40C 600 550 500 450 0.490 -50 -25 0 25 50 75 100 125 0.425 -50 -25 TEMPERATURE (C) 0 25 50 75 100 -15 2 4 6 8 10 12 GATE-OUT VOLTAGE (V) 20 25 500 5 4 3 V1 + V2 + EXTVCC EXTVCC V1 V2 2 1 0 30 Supply Current vs EXTVCC Voltage (V1 = 12V, V2 = 13V) (V1=12V, V2=13V) 0 5 10 15 20 25 30 EXTVCC VOLTAGE (V) 4421 G07 V1, V2, EXTVCC CURRENT (A) V1, V2, EXTVCC CURRENT (A) GATE CURRENT (mA) SENSE = 0mV SENSE = 6.25mV SENSE = 12.5mV SENSE = 18.75mV 15 4421 G06 6 -5 10 EXTVCC VOLTAGE (V) Shutdown Current vs EXTVCC Voltage (V1 = 12V, V2 = 13V) 0 0 5 4421 G05 GATE On Pull-Up Current vs GATE Voltage -10 0 TEMPERATURE (C) 4421 G04 -20 400 125 400 300 V1 + V2 + EXTVCC EXTVCC V1 V2 200 100 0 0 5 10 15 20 25 30 EXTVCC VOLTAGE (V) 4421 G08 4421 G09 Rev. 0 6 For more information www.analog.com LTC4421 TYPICAL PERFORMANCE CHARACTERISTICS VOUT Switching from Higher to Lower Voltage V2 5V/DIV V2 4V/DIV OV, UV Validation Time vs QUAL Capacitance VOUT Switching from Lower to Higher Voltage 100 VOUT VOUT V1 5V/DIV 10 TIME (ms) V1 4V/DIV 0V IV1 2A/DIV 0V, 0A IV2 2A/DIV 0A 4421 G10 50s/DIV COUT = 100F ILOAD = 5A 30V NCH SiR158DP 1000 0.1 10 4421 G12 40 EXTVCC = 3.1V t INVALID (s) TIME (s) 400 1000 50 13 -40C 100 CQUAL (pF) OV, UV Propagation Delay vs Overdrive 14 800 600 4421 G11 GATE Break-Before-Make Time vs Temperature 25C 125C 1 50s/DIV COUT = 100F ILOAD = 5A 30V NCH SiR158DP VALID, CH, FAULT Output Low Voltage vs Pull-Up Current 12 11 30 20 EXTVCC = 11V 200 EXTVCC = 3V 0 1 2 3 4 PULL-UP CURRENT (mA) 9 -50 5 -25 0 25 50 75 TEMPERATURE (C) 100 4421 G13 12.0 CPOREF: 3V 3.2V 5V 12V 36V 10.0 9.0 8.0 0 2 4 6 IGATE (A) 1 10 100 OVERDRIVE (mV) 8 1000 4421 G15 GATE Drive vs Temperature GATE Drive vs GATE Current 12.0 11.0 0 125 4421 G14 10 GATE-CPOREF VOLTAGE (V) 0 10 10 GATE-CPOREF VOLTAGE (V) VOL (mV) TA = 25C, EXTVCC = 11V, unless otherwise noted. IGATE = 1A 11.6 CPOREF = 12V 11.2 10.8 CPOREF = 3.2V 10.4 10.0 -50 4421 G16 -25 0 25 50 75 TEMPERATURE (C) 100 125 4421 G17 Rev. 0 For more information www.analog.com 7 LTC4421 PIN FUNCTIONS CASIN: Digital Input for Cascading. Connect to CASOUT of another, higher priority LTC4421 when cascading. Connect to INTVCC or drive to a supply voltage above 1V if not used. CASOUT: Digital Output for Cascading. Connect to the CASIN of another, lower priority LTC4421 when cascading. Leave open if not used. CH1: Voltage Power Source Indicator Output. This opendrain output pulls low when V1 is powering the output voltage and releases high otherwise. Connect a pull-up resistor to a supply less than or equal to 36V to provide the pull-up. Connect to ground or leave open if unused. CH2: Voltage Power Source Indicator Output. This opendrain output pulls low when V2 is powering the output voltage and releases high otherwise. Connect a pull-up resistor to a supply less than or equal to 36V to provide the pull-up. Connect to ground or leave open if unused. CPO: Charge Pump Output. This is the output of the charge pump, which is used to provide overdrive to the GATE pins. Connect a ceramic capacitor between CPO and CPOREF whose value must be at least 10 times the combined capacitance of the GATE compensation capacitor plus the gate capacitance of the back-to-back external N-Channel MOSFETs of one channel. When the (CPO-CPOREF) voltage is lower than the CPOGOOD threshold voltage VCPO(UVL), the input supplies are prevented from powering the output. See the Operation section for details of the initial start-up delay due to the time required to charge the CPO capacitor. CPOREF: Charge Pump Reference Output. This is the reference point for the charge pump, which is used to provide overdrive to the GATE pins. Connect to the system output voltage using a short PCB trace. Do not connect to the OUT1 or OUT2 sense resistor Kelvin connections. DISABLE1, DISABLE2: Digital Inputs for Input Disconnect and Current Limit Fault Reset. Voltages below 1V prevent the corresponding input V1, V2 supply from powering the output voltage. Driving DISABLE low, then high after a current limit fault resets the current limit timer circuitry and releases the corresponding FAULT pin high. Connecting DISABLE to the corresponding FAULT pin configures the device in auto-retry mode, with a cool-down period between retries that is 1024 times longer than the current limit fault time. See Applications Information for more details. Tie to INTVCC or drive to a supply voltage above 1V if not used. EXTVCC: External High Priority Supply Input. When EXTVCC exceeds 2.45V, an internal LDO generates a low voltage supply rail from EXTVCC to power the low voltage internal circuitry. Most of the LTC4421's ICC is drawn from EXTVCC. Connect EXTVCC to a supply voltage ranging from 3.0V to 36V. Connect EXTVCC to the output voltage (OUT1 or OUT2) to make the output voltage provide the internal bias current to the LTC4421. If unused, connect to ground, and the LDO will be powered from another supply. FAULT1, FAULT2: Current Limit Fault Indicators. These open-drain outputs pull low when an overcurrent fault occurs on their corresponding inputs and remain low during the cool down cycle. Connect pull-up resistors to a supply voltage less than or equal to 36V to provide the pull-up. Tie to ground or leave open if unused. GATE1, GATE2: Gate Drives for External N-Channel MOSFETs. Connect these pins to the gates of the external back-to-back N-Channel MOSFETs. The charge pump drives these pins with up to 12V of enhancement. Connect a capacitor between each GATE pin and the sources of the corresponding MOSFETs to compensate the current limit regulation loop. GND: Device Ground. INTVCC: Internal Low Voltage Supply Decoupling Output. An internal LDO generates a low voltage rail to power the low voltage internal circuitry. It is capable of supplying up to 500A of external current. Connect a 1F or larger capacitor between this pin and ground to provide bypassing. This pin has an undervoltage lockout threshold voltage of 2.3V. OUT1, OUT2: Output Voltage Sense. The LTC4421 prevents input supplies from connecting to the corresponding OUT until OUT is at least 35mV below the connecting supply. These pins are also used in conjunction with the SENSE pins to set the current limit values for the input supplies. Connect OUT directly to the output side of the sense resistor with Kelvin connection. OV1, OV2: Overvoltage Comparator Inputs. Rising input voltages that cross above 0.5V cause an overvoltage Rev. 0 8 For more information www.analog.com LTC4421 PIN FUNCTIONS event. Connect OV1 and OV2 to a resistive divider between the respective V1, V2 and ground to set the overvoltage threshold. See Applications Information section for connecting unused OV1 and OV2 pins. QUAL: OV, UV Qualification Timer. Connect a capacitor CQUAL from this pin to ground to set an OV, UV qualification time of 16ms/nF. Alternatively, connect this pin to INTVCC to set a default time of 3.5s. Do not leave open. RETRY: Digital Input for Retry after Current Limit Fault. When this pin is above 1V, after a current limit fault disconnect occurs, the LTC4421 reconnects the input to the output up to 6 additional times, waiting for a cool down period between each reconnection. If current limit faults occur in each of 6 additional reconnections, the LTC4421 keeps the input disconnected until the input's DISABLE pin is toggled. See the Applications section for more details. Connect to ground if unused. Do not leave open. SENSE1, SENSE2: Current Sense Non-Inverting Inputs. The current limit regulation circuits control the GATE pins to limit the sense voltages between SENSE and OUT to 25mV. If the OUT1 voltage drops below 0.45V, the regulation voltage is reduced from 25mV to 12.5mV. Connect SENSE1, SENSE2 directly to the input sides of the sense resistors with Kelvin connections. SHDN: Digital Input Shutdown to Disconnect Output and Set Low Current Mode. Voltages below 1V turn off all external MOSFETs, invalidate both channels and cause the LTC4421 to enter a low current mode. CASOUT is pulled high to allow a lower priority LTC4421 in a cascaded system to provide power to the output. All circuitry is debiased, except for the shutdown comparator and low voltage rail generators, and total device current is reduced to 6A. When SHDN is driven back above 1V, the external MOSFETs are held off until the OV and UV comparators revalidate. Connect to INTVCC if unused. SOURCE1, SOURCE2: Connections to Common Sources of External Back-to-Back N-Channel MOSFETs. Leave open or connect to the sources of the external MOSFETs. To minimize channel switchover time, a 5A pull-down current biases the MOSFETs on the edge of conduction when their input supply is not connected to the output. Add resistors from the MOSFET sources to ground to increase the MOSFET VGS bias voltage and reduce switchover time. TMR1, TMR2: Current Limit Fault Timers. Connect a capacitor between each TMR pin and ground to set a 83ms/F duration for current limit before an overcurrent fault occurs. When a fault occurs, the external N-Channel MOSFETs are turned off and the corresponding FAULT pin is pulled low. The LTC4421 can be configured to latch-off, auto-retry indefinitely or auto-retry 6 additional times after an overcurrent fault. See the Applications Information for more details. UVR1, UVR2: Undervoltage Comparator Inputs for Rising Voltages. Rising input voltages that cross above 0.5V are considered valid, provided that the OV pin voltage is below 0.5V. Connect UVR1 and UVR2 to a resistive divider between the respective V1, V2 and ground to set the rising undervoltage threshold. Set the UVR threshold voltage above the corresponding UVF threshold voltage to ensure proper operation. See Applications Information section for connecting unused UVR1 and UVR2 pins. UVF1, UVF2: Undervoltage Comparator Inputs for Falling Voltages. Falling input voltages that cross below 0.5V cause an undervoltage event. Connect UVF1 and UVF2 to a resistive divider between the respective V1, V2 and ground to set the falling undervoltage threshold. Set the UVR threshold voltage above the corresponding UVF threshold voltage to ensure proper operation. See Applications Information section for connecting unused UVF1 and UVF2 pins. V1, V2: Input Power Supply Voltages. Typically V1 and V2 are connected to input supply voltages ranging from 3.0V to 36V, but each supply can operate down to 0V, provided another supply voltage 3.0V powers the LTC4421. In normal operation, V1 is the higher priority supply and V2 is the lower priority supply. VALID1, VALID2: Voltage Valid Indicator Outputs. These open-drain outputs pull low when their corresponding V1, V2 inputs are within their OV, UV window for the required qualification time. Connect pull-up resistors to a supply voltage less than or equal to 36V to provide the pull-up. Connect to ground or leave open if unused. Exposed Pad (Pin 37, UHE Package only): Exposed Pad may be left open or connected to device ground. Rev. 0 For more information www.analog.com 9 LTC4421 BLOCK DIAGRAM V1 V2 GATE1 GATE2 SOURCE1 SOURCE2 CHANNEL OFF 0.6V VGSOFF CP'S CH1OFF CPO 0.6V OUT1 5A ISRC GATE DRIVER +ILIM CH1 CH2OFF CONNECT LOGIC M1 ON1 CH2 OV CP 0.5V/0.45V VALID1 OV1 VALID1 OV, UV TIMER OV2 UVR1 ILIM AMP UV CP 0.5V UVF1 HYS Q UVF2 RD UVR2 DISABLE2 ON1 VALID2 25mV/12.5mV REV CP S SENSE1 FOLDBACK CP 0.46V/ 0.41V V1 SENSE2 OUT1 VREV OUT2 35mV DIS CP DISABLE1 M5 1V/0.85V CURRENT LIMIT LOGIC INTVCC I2 8A REVCUR CP VSNSREV COOL DOWN COUNTER 1.3V 25mV FAULT1 TMR1 M2 FAULT1 0.8V FAULT2 I1 2A CHANNEL 1 TMR2 CHANNEL 2 QUAL RETRY CP RETRY 1V/0.85V INTVCC VMAX OF 2 CHARGE PUMP/LDO f = 2MHz CPO CPOGOOD CP POR 6.7V/5.3V INTVCC GOOD CP INTVCC CPOREF SHUTDOWN CP 2.4V/2.3V SHDN GND BG 1.211V BGGOOD 1V/0.85V EXTVCC 1 PRIORITIZED 2 3.9V 3 REGULATOR 4 V1 V2 INTVCC 5A D2 VMAX OF 4 CASCADE CP OUT1 CASIN 1V/0.85V CH1OFF CH2OFF CASCADE LOGIC INTVCC 20A ICAS D1 INTVCC CASOUT M12 NMOS LTC4421 BD Rev. 0 10 For more information www.analog.com LTC4421 OPERATION The LTC4421 is a Prioritized PowerPathTM Controller that drives external N-Channel MOSFETs to connect one of two input supplies to a common output based on userdefined priority and validity. By definition, the supply connected to V1 is the higher priority supply, and the supply connected to V2 is lower priority, although this can be changed dynamically. The V1 voltage can be lower than, equal to or higher than the V2 voltage. At initial power-up, the LTC4421 prevents the input supplies from validating and connecting to the output until it has enough bias voltage to function properly. Referring to the Block Diagram, the LTC4421 prevents OV, UV validation and connection to the output until the INTVCC voltage exceeds 2.3V (VINT(UVL)) as detected by comparator INTVCC GOOD CP, the bandgap reference voltage has reached its final regulated value as indicated by the BGGOOD signal, and the CPO voltage exceeds the higher of the CPOREF and INTVCC voltages by 6.7V (VCPO(UVL)) as detected by comparator CPOGOOD CP. With a 1F capacitor connected between CPO and CPOREF, the Charge Pump/LDO circuit can take several hundred milliseconds to charge to 6.7V. See the Applications Information for methods to reduce the charging time. After initial power-up is complete, the LTC4421 monitors the V1 and V2 voltages via resistive dividers to precision overvoltage (OV CP) and undervoltage (UV CP) comparators. The UVR and UVF pins set the rising and falling undervoltage thresholds for the UV comparators. When an input voltage has been inside its OV, UV voltage window for a time (tVALID) set by the QUAL pin, it is considered valid and is eligible to power the output. If the input supply voltage falls out of the OV, UV window and remains outside for at least 3.5s (tINVALID), the supply is disconnected from the output. Open drain output status pins provide information regarding a channel's validity and connection status to the output. VALID1 and VALID2 are pulled low when V1 and V2, respectively, are valid. CH1 and CH2 are pulled low when V1 and V2, respectively, are powering VOUT. The GATE DRIVER circuit provides strong sourcing and sinking currents to external N-Channel MOSFETs to connect and disconnect the input supplies to and from the output. When turning on the MOSFETs, GATE DRIVER sources current from the CPO pin to pull the GATE voltage up to the CPO voltage. A charge pump regulates the CPO voltage 12V (VGATE(CL)) above the CPOREF voltage to provide 12V of VGS enhancement to the MOSFETs. Strong sinking currents ensure rapid turnoff of the external MOSFETs when a channel is no longer valid, a higher priority channel takes precedence or when comparator REVCUR CP detects a reverse voltage of -25mV (VSNSDIS,REV) across the external sense resistor. Such a reverse voltage occurs when an input supply powering the output is shorted. Fast charge and discharge of the external NMOS gates ensure fast switching between supplies, minimizing droop at the output. During channel transitions, monitoring circuitry prevents cross conduction between input supplies and reverse current from the output using a break-before-make architecture. Two VGS comparators (VGSOFF CPs) monitor the disconnecting channel's gate pin voltage (GATE1 or GATE2). When the GATE voltage is 600mV (VGS(OFF)) lower than either the input or output voltage of the channel turning off, the VGS comparators determine the external N-channel MOSFETs to be off and allow the other channel to connect to the output. The VGS comparator outputs are latched in the off state; the latch is reset when the channel is commanded to turn back on. To prevent reverse conduction from the output to the inputs during channel switchover, the reverse comparator (REV CP) monitors the connecting V1, V2 supply and the corresponding OUT1, OUT2 output. The REV comparator prevents connection until the output droops 35mV (VREV) below the connecting supply. The connection is latched, resetting when the channel is commanded to disconnect. Rev. 0 For more information www.analog.com 11 LTC4421 OPERATION The current limit amplifier (ILIM AMP) monitors the load current using the difference between the SENSE and OUT pin voltages. The amplifier and gate driver work together to limit the current in the load by reducing the GATE-toSOURCE voltage in an active control loop. The SENSE-toOUT differential voltage is regulated to 25mV (VSNS). An external sense resistor placed between SENSE and OUT sets the current limit value for each channel. Foldback comparator (FOLDBACK CP) reduces the SENSE-toOUT differential voltage from 25mV (VSNS) to 12.5mV (VSNS,FLD) to conserve power when the OUT1 voltage is low. The foldback comparator's rising and falling threshold voltages are 460mV and 410mV, respectively. If the SENSE-OUT voltage on a channel remains in current limit for the time programmed by the TMR pin, the LTC4421 registers a current limit fault. Additionally, pulsed output load currents exceeding current limit and occurring at duty cycles of 25% or higher will integrate over time and cause a current limit fault. and CASOUT pins of multiple LTC4421's can be configured to prioritize as many input supplies as desired. The DISABLE1, DISABLE2 and CASIN inputs are connected to comparators having 1V (VTH) threshold and 150mV (VTH,HYST) hysteresis. See the Applications Information section for circuits that use the DISABLE, FAULT2 and VALID2 pins to redefine input supply priorities in real time and to prevent the primary input from powering the output until a valid back-up supply is available. When a current limit fault occurs, the LTC4421 disconnects the channel and drives the FAULT pin low to indicate that a current limit fault has occurred. After a current fault occurs, driving DISABLE low initiates a cool down period that is 1024 times longer than the time-out period. Driving DISABLE back high terminates the cool-down period, resets FAULT high and allows reconnection to the output. Alternatively, if RETRY and DISABLE are both high when a current limit fault occurs, the LTC4421 will try to reconnect up to 6 additional times after the first fault, with a cool-down period between attempted connections that is 1024 times longer than the current limit fault time. When SHDN is driven high, the LTC4421 reactivates all circuits. It may take several hundred milliseconds for a valid input to connect to the output, because the external charge pump capacitor CCPO must charge to 6.7V before connection is allowed. Driving DISABLE1 and DISABLE2 low disconnects V1 and V2, respectively, from powering the output. The CASIN Driving SHDN low causes the device to turn off the external N-Channel MOSFETs, enter a low current state and invalidate V1 and V2. All circuitry is debiased except the INTVCC rail generator and shutdown comparator. The total internal bias current is reduced dramatically to 6A to conserve power. The INTVCC voltage is reduced to 3V and is powered from the highest of the V1, V2, EXTVCC and OUT1 voltages. The CASOUT pin is driven high to allow a lower priority LTC4421 in a cascading application to power VOUT. The LTC4421 includes its own internally generated low voltage rail (INTVCC) that provides power to the low voltage sections of the device. Because most of the device's quiescent current is provided by INTVCC, the INTVCC power source is prioritized to minimize current draw from lower priority sources. The INTVCC rail is powered from one of 4 prioritized sources. These sources in order of priority are EXTVCC, V1 and V2. If none of these three inputs is valid, INTVCC is powered by the highest of the V1, V2, EXTVCC and OUT1 voltages. Rev. 0 12 For more information www.analog.com LTC4421 APPLICATIONS INFORMATION Introduction High availability systems employ multiple input supplies to power a single common output. When individual supplies such as wall adapters and batteries are unplugged at various points in time, output power must not brown out as control of the output power is transferred to the other supply. Power ORing diodes are often used in these systems, but the highest input supply voltage always powers the output. The LTC4421 powers the output from the highest priority supply available, even if it is lower in voltage than the lower priority supplies. When switching between supplies, output voltage droop is minimized, and backfeeding current is prevented. A typical LTC4421 application circuit is shown in Figure1, where the primary RSENSE1 M1 M2 PSMN4R8100BSE PSMN1R440YLD 2.5m PRIMARY 12V D1 Setting Valid Operating Voltage Range The LTC4421 requires an input supply remain inside a user-defined voltage window for a user-defined amount of time to be considered valid. The valid voltage window is set by a resistive divider from the input supply to ground that allows three thresholds voltages to be configured: the UV rising threshold (VUVRISE), the UV falling threshold (VUVFALL) and the OV rising threshold (VOVRISE). The OV falling threshold is set by internal hysteresis to be 10% below the OV rising threshold. Using the 500mV ILIM1 = 10A RSN1 1.2 CSN1 10F SMDJ36A SECONDARY 28V input supply is 12V and the secondary is 28V. External component selection is discussed in detail in the following sections. COUT 220F ILIM2 = 10A M3 M4 RSENSE2 PSMN4R8100BSE PSMN1R440YLD 2.5m RSN2 2.8 CSN2 10F D2 SMDJ36A R4 1M VOUT CG1 47nF V1 GATE1 CG2 47nF CCP0 1F SOURCE1 SENSE1 OUT1 CPO CPOREF V2 GATE2 SOURCE2 UVR1 R2 12.7k R1 35.7k OV1 VALID1 VALID2 CH1 CH2 FAULT1 FAULT2 CASOUT LTC4421 R8 1M UVF2 UVF1 = 7.81V UVR1 = 11.04V OV1 = 14.96V UVF2 = 5.97V UVR2 = 25.28V OV2 = 35.4V R7 69.8k R6 6.19k R5 15.4k RETRY DISABLE1 DISABLE2 SHDN CASIN UVR2 OV2 OUT2 EXTVCC UVF1 R3 20k SENSE2 GND QUAL TMR1 TMR2 INTVCC C2 0.1F DIGITAL STATUS OUTPUTS DIGITAL CONTROL INPUTS LTC4421 F01 CQUAL 470pF CTMR1 47nF CTMR2 47nF CINTVCC 1F Figure1. Typical LTC4421 Application Circuit Rev. 0 For more information www.analog.com 13 LTC4421 APPLICATIONS INFORMATION comparator threshold, the resistor values can be calculated as shown in Equation 1 through Equation 5. (1) R = R1+R2+R3+R4 TOTAL R1= (0.5 * RTOTAL ) VOVRISE During channel turn-on, the relatively large inrush current causes a voltage drop across the input supply source resistance and the parasitic resistances of PCB traces and any cable. This voltage drop can cause UV faults that trigger a phenomenon called UV motorboating, where the input supply repeatedly connects and disconnects from the output. UV motorboating can lead to component damage and undesirable/erratic behavior. To prevent UV motorboating, set the VUVRISE and VUVFALL as far apart as possible to maximize hysteresis and prevent channel disconnect during the inrush. Ideally, quantify the worst-case input resistance RSRC,MAX, and set (VUVRISEVUVFALL) larger than (ILIM * RSRC,MAX), where ILIM is the current limit. The OV hysteresis is fixed at 10% above the OV threshold voltage. (2) V R2 = OVRISE - 1 * R1 VUVRISE (3) V V R3 = UVRISE - 1 * OVRISE * R1 VUVFALL VUVRISE (4) V R4 = R1* OVRISE - 1 - R3 - R2 0.5 (5) For better accuracy, use one resistive divider per channel to set the UVF and UVR thresholds, and a second, separate resistive divider to set the OV threshold. For ease of calculation, use three individual resistive divider strings per channel - one for OV, one for UVF and one for UVR. However, to ensure the UVR threshold is always higher than the UVF threshold on a given channel, do not use separate strings for UVR and UVF when setting their thresholds close together in voltage. Figure2 shows these various resistive divider possibilities, using Channel1 as an example. When setting the resistor values, take into account the tolerance of the input supply voltage, the tolerance of the resistors, the 2% error in the 500mV reference and the 10nA maximum leakage of the UVR, UVF and OV pins. To permanently invalidate a channel, connect OV, UVR and UVF to ground. VI INPUT SUPPLY VPU V1 R4 UVF1 M3 R11 R13 R15 R9 R3 R7 UVR1 R16 LTC4421 0.5V VALID1 M2 UVF1 UVF1 R10 UVR1 R12 OV1 R14 OV1 QUAL TIMER R2 R6 M1 0.5V/0.45V R8 UVR1 R5 OV1 R1 QUAL EASIEST TO CALCULATE ENSURES UVR1 THRESHOLD > UVF1 THRESHOLD FEWEST RESISTORS LTC4421 F02 Figure2. Three Resistive Divider Options For Setting the OV, UVR and UVF Threshold Voltages Rev. 0 14 For more information www.analog.com LTC4421 APPLICATIONS INFORMATION Current Limit Regulation and Setting the Current Limit The LTC4421 provides independently settable current limit values for each input. On a given channel, the LTC4421 regulates the maximum voltage across the SENSE and OUT pins to 25mV (VSNS). Connect a sense resistor RSENSE between SENSE and OUT to set the current limit value ILIM, is given by Equation 6. ILIM = 25mV RSENSE (6) Ensure the input supply is capable of sourcing more current than ILIM, so that the input supply does not drop out and cause UV motorboating. Use standard 1% resistor values and choose RSENSE to set ILIM at least 25% higher than the maximum output load current ILOAD(MAX) to account for tolerances in the current limit and to provide sufficient charging current to the output capacitor when charging the output. ILIM and COUT set the rate at which the output voltage will rise. The minimum output rise rate is shown by Equation 7. dVOUT (ILIM - ILOAD(MAX) ) (min) = dt COUT (7) Equation 7 assumes that the output voltage is charging under maximum output load current conditions, so that only the difference between the programmed current limit V1 current and the maximum DC load current is available to charge COUT. It is essential to set ILIM to ensure that the output is fully charged before an overcurrent fault timeout occurs. The LTC4421 implements a stepped current limit foldback feature. A foldback comparator monitors the voltage on the OUT1 pin and reduces the current limit regulation voltage from 25mV (VSNS) to 12.5mV (VSNS,FLD) for low OUT1 voltages, thereby cutting the current limit in half to reduce power consumption. The comparator rising and falling threshold voltages are 460mV (VFLD,TH) and 410mV, respectively. When the OUT1 voltage is initially being powered up from 0V, the current limit regulation voltage is 12.5mV until OUT1 rises above 460mV, at which point it is increased to 25mV. For output voltages below 460mV, ensure the maximum output load current is lower than the foldback current limit to ensure the output powers up. When the OUT1 voltage is initially powered and then discharges, for example due to an input or output short circuit, the current limit regulation voltage will be 25mV until OUT1 drops below 410mV, at which point it is reduced to 12.5mV. Use Kelvin connections from the RSENSE terminals to the LTC4421's SENSE and OUT pins for best accuracy. Choose sense resistors having low inductance to minimize the sense resistor's impact on the current limit regulation loop stability. A single sense resistor can be used if the current limit is the same on both channels, as shown in Figure3. RSENSE 2.5m M1 M2 PSMN4R060YS PSMN1R440YLD M3 PSMN4R060YS V2 CG1 47nF VOUT M4 PSMN1R440YLD CG2 CCPO 1F V1 GATE1 SOURCE1 V2 GATE2 SOURCE2 SENSE1 SENSE2 OUT1 OUT2 CPOREF CPO LTC4421 LTC4421 F03 Figure3. Using a Single Sense Resistor RSENSE to Set the Same Current Limit for Both Channels For more information www.analog.com Rev. 0 15 LTC4421 APPLICATIONS INFORMATION Selecting the Output Capacitor When switching connection to the output between the two input supplies, the LTC4421 utilizes break-beforemake circuitry to ensure the first channel has completely disconnected from the output before the second turns on. This prevents current from flowing from one input to the other via the output, a phenomenon known as crossconduction. As a result, there is a dead time during switchover when neither supply is powering the output. Users must choose an output capacitance COUT to support the output load current and minimize the output voltage step and droop during switchover. When the first channel disconnects, a voltage step occurs at the output due to the load current flowing through COUT's equivalent series resistance RESR. The magnitude of the voltage step is given by Equation 8. (8) VSTEP = (ILOAD * R ESR ) For the duration of the dead time, the output voltage droops as the load current discharges COUT. The maximum magnitude of the droop is given by Equation 9. VDROOP = (I LOAD(MAX) * tG(SWITCH),MAX ) COUT (9) Set COUT to optimize the trade-off between minimizing output voltage droop and minimizing the time required to fully charge the output from 0V. Set VDROOP(MAX) as high as possible; usually, VDROOP(MAX) 0.1 * VOUT is acceptable. Typically, using 10F to 50F of output capacitance per Ampere of maximum load current achieves a reasonable trade-off. Figure4 shows an output voltage waveform during switchover for a system having 5A output load current and a 220F output capacitor with 100m RESR. When the first channel is turned off, the 5A load is provided by the 220F capacitor. With 5A flowing through the 100m RESR, VSTEP = 500mV. Following the ESR step, the output discharges at a rate dV/dt = 5A/220F until the second channel is switched in. Because of the high output currents, it is imperative to choose capacitors having very low ESR to minimize VSTEP. Also, consult the capacitor vendor's curves of capacitance versus DC bias voltage and capacitance versus temperature, and account for temperature and voltage coefficients of COUT. Determining the Maximum Time to Charge the Output Voltage Whenever the output is being charged from a lower voltage to a higher voltage, it charges in current limit. As a result, the overcurrent fault timer is running during charging. It is imperative to determine the maximum time t(CHG,MAX) required to charge the output and set the overcurrent fault time tTMR,FLT > t(CHG,MAX). The maximum charge time is given by Equation 10. t(CHG,MAX) = (COUT * VIN,MAX ) (ILIM- ILOAD,CHG ) (10) where VIN,MAX is the highest input voltage and ILOAD,CHG is the maximum DC load current present when COUT is being charged. The worst case occurs when ILOAD,CHG = ILOAD,MAX. If possible, disable the output load current VOUT ESR STEP 0.5/DIV DROOP DUE TO SWITCHOVER DELAY 10s/DIV 4421 F04 Figure4. Output Voltage ESR Step and Linear Discharge During Channel Switchover Rev. 0 16 For more information www.analog.com LTC4421 APPLICATIONS INFORMATION when initially charging the output from 0V, so that ILOAD,CHG = 0. The application circuit in Figure5 utilizes an LTC2965 voltage monitor on the output to disable the output DC/DC converter until VOUT rises above 9V. Once VOUT rises above 9V, the DC/DC remains enabled until VOUT drops below 1V. information. Choose MOSFETs having VGS,MAX = 20V, to handle the LTC4421's 14V maximum gate drive voltage. When the back-to-back MOSFETs turn on and conduct current to the output, large drain-source voltages can occur on the input side MOSFET as the output is charging. However, the drain-source voltage of the output side MOSFET is limited to about 1V due to the body diode turning on, so the output side MOSFET is always in triode. As a result, the input side MOSFET has much more stringent SOA requirements. A MOSFET with lower SOA and lower VGS(TH) can be used on the output side to minimize power loss in that MOSFET. N-Channel MOSFET Selection The LTC4421 drives N-Channel MOSFETs to conduct or block current from an input supply voltage and an output load current. The important features of the MOSFETs are: 1.BVDSS, the absolute maximum drain-source voltage The chosen MOSFET must be able to withstand an output short circuit for longer than tTMR,FLT. During output shorts, the LTC4421 regulates the short-circuit current using its current limit regulation circuitry and runs the overcurrent fault timer. When the short persists longer than the programmed tTMR,FLT time, the LTC4421 turns off the MOSFETs. The worst-case occurs when the output is resistively shorted and the output voltage, VSHORT, remains above the foldback comparator falling threshold voltage, which is 410mV. In this case, the power during the short circuit is given in Equation 11. 2.VGS,MAX, the absolute maximum VGS voltage 3.VGS(TH), the threshold voltage 4.RDS(ON), the on-resistance 5. SOA, the safe operating area The maximum allowable drain-source voltage, BVDSS, must be higher than all supply voltages, as there are various scenarios where the output voltage can be at the highest supply voltage when the input is at 0V, and vice versa. Additionally, it must be higher than the clamping voltage of Transient Voltage Suppressor (TVS) diodes D1 and D2. Supplies with high input parasitic inductance may require additional precautions. See the Input and Output Short Circuits and Supply Transient Protection section for more M1 SiR158DP V1 12V M2 SiR158DP POWER VIN *ILIM = VOUT GATE1 CCP0 1F SOURCE1 (11) DC/DC COUT 220F V1 RSENSE where VIN is in the input voltage and VIN >> VSHORT. RSENSE1 2.5m CG1 47nF ( VIN * 25mV ) SENSE1 OUT1 CPOREF CPO ENABLE VIN REF RTH3 619k INH LTC2965 RTH2 332k LTC4421 OUT INL LTC4421 F05 RTH1 42.2k PS RS GND Figure5. Load Current Hold Off. The LTC2965 Voltage Monitor Disables the DC/DC Output Load Current Until VOUT > 9V Rev. 0 For more information www.analog.com 17 LTC4421 APPLICATIONS INFORMATION After calculating the power, refer to the SOA curves in the MOSFET manufacturer's data sheet. The SOA curves are usually specified at 25C and must be adjusted to account for the highest operating ambient temperature TA as given by Equation 12. SOA(TA ) = SOA(25C) * (TJMAX - TA ) (TJMAX - 25C) (12) Where TJMAX is the maximum allowed junction temperature of the MOSFET. Most of the recommended MOSFETs have TJMAX =175C. As a result, multiply the y-axis values of the SOA curves by 0.6 for TA = 85C, and multiply by 0.333 for TA = 125C. Note that MOSFET data sheets usually show a family of 5-6 SOA curves, with each curve separated from the next by a factor of 10 in time (e.g., 100s, 1ms, 10ms, etc.). To be conservative, choose the time curve closest to and higher than tTMR,FLT and make sure the MOSFET can handle the power in Equation 11. When the output is hard-shorted to ground, such that the output voltage is below 410mV, the LTC4421 implements a stepped foldback feature, reducing the short circuit current, and hence the power, by a factor of two. As a result, the LTC4421 provides more SOA margin for the MOSFET for hard shorts than resistive shorts. See procedures outlined in this section and the SOA curves in the chosen MOSFET manufacturer's data sheet to verify suitability for the application. OUT1 Overcurrent Faults and Retry The LTC4421 features an adjustable current limit that protects against output short circuits and excessive load current. An overcurrent fault occurs when the current limit circuitry has been engaged for longer than the time set by the TMR pin. When the output load current is less than ILIM, the LTC4421 pre-biases the TMR pin voltage to its DC TMR Parking Voltage. When the LTC4421 is regulating the output current to ILIM, it sources 6A out of the TMR pin to charge the external TMR capacitor. When the TMR pin voltages increases by 500mV from the TMR Parking Voltage, an overcurrent faultoccurs. The FAULT open-drain output pull-down pin is latched low, and the input is disconnected from the output. Connect a capacitor CTMR between TMR and ground and use Equation 13 to set the overcurrent fault time tTMR,FLT. (13) t TMR,FLT = CTMR * 83 [s/nF ] Note that pulsed current loads exceeding the programmed current limit and having duty cycle > 25% will integrate over time and cause a current limit fault. After an overcurrent fault occurs, the subsequent functionality depends on the configuration of the DISABLE, FAULT and RETRY pins. Figure 6 shows a timing diagram for an overcurrent fault occurring on Channel 1 where the RETRY pin is set low, FAULT1 is pulled up to a supply voltage with a 100k resistor and the user drives DISABLE1 with a digital signal. For simplicity, there is no input supply connected to V2. OUTPUT SHORT RELEASED OUTPUT SHORT TO GROUND I(RSENSE1) TMR1 FAULT1 OVERCURRENT FAULT COOL DOWN COMPLETE USER INITIATES COOL DOWN DISABLE1 tTMR,FLT RECONNECT LTC4421 F06 COOL DOWN TIME = (1024 * tTMR,FLT) Figure6. Manual Retry after Overcurrent Fault on Channel 1. Conditions: RETRY = 0V, User Driven DISABLE1 and Output Short Released During Cool Down Time Rev. 0 18 For more information www.analog.com LTC4421 APPLICATIONS INFORMATION When output voltage OUT1 is shorted to ground, the LTC4421 limits the current I(RSENSE1) flowing in the sense resistor and simultaneously sources 6A out the TMR1 pin to charge the CTMR1 capacitor. At time tTMR,FLT after the short, an overcurrent fault occurs as described above, and the LTC4421 drives FAULT1 low. The user detects FAULT1 being low and drives DISABLE1 low to initiate the cool down cycle. In this example, the short circuit is released during the cool down cycle, as indicated in the waveforms. Because V1 is disconnected from the output, the output voltage remains low when the short is released. At the end of cool-down, FAULT1 releases high and the input is allowed to reconnect to the output. Driving DISABLE1 high reconnects Channel 1's input to the output. With the output short removed, the output successfully powers up, and no further faults occur. Note: driving DISABLE1 low-to-high at any point in the cool down cycle asynchronously terminates the cool down cycle and allows reconnection to the output. It is strongly recommended not to terminate the cool down cycle early, as the MOSFETs may not have sufficient time to cool down, and the subsequent overcurrent fault time may be significantly shorter than the time set by the TMR pin. OUT1 Figure7 shows the functionality with RETRY = 0V, but with the FAULT1 pin connected to DISABLE1. In this case the user does not drive DISABLE1. When the overcurrent fault occurs, the FAULT1 pin is driven low. Because FAULT1 is connected to DISABLE1, DISABLE1 also pulls low, initiating the cool down cycle. At the end of the cool down cycle, the LTC4421 releases FAULT1 high, which drives DISABLE1 high, causing the V1 input supply to reconnect to the output, a process called "auto-retry". This process repeats indefinitely until the output short is removed. In this example, the output short is released during the second cool down cycle, so the output voltage successfully powers up on the third connection. Figure8 shows the functionality with DISABLE1 pulled high, FAULT1 pulled up to a supply voltage with a 100k resistor but not connected to DISABLE1, and RETRY set high. In this example, we are leaving the output shorted permanently. In this case, the LTC4421 reconnects the V1 supply 6 additional times after the first overcurrent fault occurs. Each reconnection results in an overcurrent fault, followed by a cool down cycle. After a total of 7 faults, the LTC4421 keeps the inputs disconnected from the output until the DISABLE1 is toggled low, then high. OUTPUT SHORT RELEASED OUTPUT SHORT TO GROUND I(RSENSE1) TMR1 FAULT1 DISABLE1 OVERCURRENT FAULT COOL DOWN COMPLETE OVERCURRENT FAULT COOL DOWN COMPLETE INITIATE COOL DOWN RECONNECT INITIATE COOL DOWN RECONNECT tTMR,FLT COOL DOWN TIME = (1024 * tTMR,FLT) tTMR,FLT COOL DOWN TIME = (1024 * tTMR,FLT) LTC4421 F07 Figure7. Auto-Retry After Overcurrent Fault on Channel 1. Conditions: RETRY = 0V, FAULT1 Connected to DISABLE1 and Output Short Released During Second Cool Down Time OUT1 OUTPUT SHORT TO GROUND I(RSENSE1) TMR1 OVERCURRENT FAULT FAULT1 DISABLE1 LTC4421 F08 COOL DOWN TIME = (1024 * tTMR,FLT) tTMR,FLT Figure8. 6 Retries After Overcurrent Fault on Channel 1. Conditions: RETRY = 3V, DISABLE1 = 4V and Output Short Never Released Rev. 0 For more information www.analog.com 19 LTC4421 APPLICATIONS INFORMATION The overcurrent fault times are independently settable for each channel. Set the time to ensure the output can charge from 0V to the maximum input voltage, as described above. Whenever Channel 1 experiences a current limit fault, Channel 2 is allowed to power the output, presuming Channel 2 is valid. Channel 2 powers the output until the fault on Channel 1 is cleared. The RETRY count of 6 counter on a channel is reset whenever its input supply is invalid, its DISABLE is driven low, or a higher priority supply becomes valid. It is also reset when INTVCC is below the INTVCC GOOD Threshold Voltage and CPO is below the CPOGOOD Threshold Voltage. Toggling the RETRY pin low, then high also resets the counter. Iterating the Application Circuit Solution for MOSFET SOA If the selected MOSFET does not meet the SOA requirements imposed by the initial current limit and output capacitor values, take one or more of the following steps: 1. Reduce tTMR,FLT to meet the MOSFET SOA requirements. This requires reducing t(CHG,MAX) from Equation 10 to ensure tTMR,FLT > t(CHG,MAX). One way to do this is to reduce COUT. The trade-off is an increase in output voltage droop during channel switchover. 2. Reduce tTMR,FLT and t(CHG,MAX) by increasing the current limit ILIM. This is only helpful if the reduction in t(CHG,MAX) provides a larger SOA benefit than the SOA loss caused by the increased power dissipated in the MOSFET. For example, assume ILIM = 11A and ILOAD,CHG = 10A. Using Equation 14. t(CHG,MAX) = (COUT * VIN,MAX ) (COUT * VIN,MAX ) = 11A - 10A 1A (14) If ILIM is then increased from 11A to 20A, the new result is given by Equation 15. t(CHG,MAX) = (COUT * VIN,MAX ) (COUT * VIN,MAX ) = 20A - 10A 10A (15) With t(CHG,MAX) reduced by a factor of 10, we can reduce tTMR,FLT by a factor of 10. By doubling ILIM, the maximum power during output short circuits has doubled, but t(CHG,MAX) has decreased by a factor of 10, so there is a net reduction in the SOA stress. Be sure the input power supply is capable of sourcing more current than the new, higher value of ILIM. Also, ensure the new ILIM does not cause UV motorboating. 3. Choose a MOSFET with higher SOA. Look for MOSFET's having high BVDSS, as they usually have better SOA performance. Charge Pump and Gate Driver Circuitry The gate drive is provided by a charge pump circuit that powers CPO. A curve of GATE pin voltage versus output voltage is shown in the Typical Performance Characteristics curves. For output voltages less than 4V, the minimum gate drive voltage is 9V. When the output voltage is higher than 5V, the gate drive is at least 10V. A burst mode comparator ensures the gate drive never exceeds 14V. When an input supply is invalid, the LTC4421 drives the GATE pin voltage close to ground using a 50mA pulldown current. When a supply is valid but turned off, gate driver parking circuitry regulates the GATE voltage to 1V below the lower of the channel input voltage and the output voltage. This is called the GATE Parking Voltage. The LTC4421 also sinks 5A from the SOURCE pin to bias the external MOSFETs at their threshold voltages, to minimize the VGS and hence the turn-on time during channel switchover when the MOSFETs are turned back on. If possible, choose a lower threshold MOSFET for the output MOSFET to preferentially draw the SOURCE current from VOUT instead of the input supply of the off channel, and add a resistor from SOURCE to ground to increase current and hence the VGS. CPO Charge Pump Capacitor Selection Connect a reservoir capacitor CCPO between CPO and CPOREF to provide the charge necessary to turn on the MOSFETs quickly. The recommended value is approximately 10x the combined input CISS capacitances of the two back-to-back MOSFETs on one channel, plus any discrete GATE-to-SOURCE capacitor CG that has been added to stabilize the current limit loop. A larger CCPO capacitor Rev. 0 20 For more information www.analog.com LTC4421 APPLICATIONS INFORMATION takes a correspondingly longer time to charge up by the internal charge pump, resulting in longer delays from initial power-up of the first input supply to first connection to the output. A smaller capacitor suffers more voltage drop during a channel turn-on event as it shares charge with CG and the MOSFET CISS capacitances. Given the limited charging capability of the charge pump, continuously changing channels at rates higher than 80Hz (typical) eventually depletes the CCPO capacitor, causing disconnection of both inputs from the output. At that point, the charge pump charges the CCPO capacitor above 6.7V, the inputs are then allowed to reconnect to the output, and the process repeats. Analog Current Limit Loop Stability The active current limit loop is compensated by adding a capacitor CG between the gate and source of the external MOSFETs. Choosing 47nF for CG ensures stability for all recommended MOSFETs. In addition, add a snubber from the input supply to ground consisting of resistor RSN in series with capacitor CSN. Choose RSN using Equation 16. R SN = VIN ILIM (16) where VIN is the maximum input supply voltage and ILIM is the current limit being set by RSENSE. Setting CSN to 10F works well for all applications. Applications having small input inductance and low output load current may use values as low as 1F for CSN. If possible, set a qualification time on the order of 10ms or longer. This allows the LTC4421's gate driver parking circuitry to pre-bias the GATE1 voltage to its GATE Parking Voltage when hot-plugging the V1 input supply. This will reduce switchover time and hence output voltage droop when switching from Channel 2 to Channel 1. Optional Charge Pump Pre-Charge Circuit The LTC4421 prevents the input supplies from being validated and powering the output until the external CCPO capacitor voltage is charged to 6.7V (VCPO(UVL)) above the higher of the CPOREF and INTVCC voltages. With a typical CCPO capacitor of 1F, the charge pump voltage may take several hundred milliseconds to charge to 6.7V. For input supplies 12V, this time can be shortened by pre-charging the CPO pin with the circuit shown in Figure9. The 12V Zener diode Z1 and NPN transistor Q1 are used to quickly charge the CPO voltage to about 10.8V above ground. For V1, V2 voltages below 12V, the circuit pre-charges CPO to a voltage approximately 1.8V below the higher of the V1 and V2 voltages. Diode D3 prevents reverse current conduction when an input supply is connected to VOUT and causes the CPO voltage to rise above 9V. Diodes D1 and D2 form a diode-OR circuit that powers the Z1 and Q1 from the higher of the V1 and V2 input supply voltages. V1 R1 1k VOUT Setting Qualification Time for Validity COUT 220F The QUAL pin sets the amount of time a supply must be inside the OV, UV voltage window to be valid. Connect a capacitor CQUAL from QUAL to ground and use Equation 17 to set the validation time: (17) t VALID = C QUAL * 16[ms/nF] where tVALID is the validation time. Note that the validation time is the same for both channels. To set a fixed qualification time of 3.5s, connect QUAL to INTVCC instead of connecting a capacitor to ground. V2 D1 1N4148 CCPO 1F CPOREF Q1 2N2222 D2 1N4148 R2 100k D4 1N4148 D3 1N4148 12V Z1 BZX84C12L CPO LTC4421 LTC4421 F09 Figure9. Optional CPO Pre-Charge. The Higher Voltage of Input Supplies V1 and V2 Pre-Charges the CPO Voltage to Reduce System Power-Up Time Rev. 0 For more information www.analog.com 21 LTC4421 APPLICATIONS INFORMATION Minimizing Bias Current Draw from Lower Priority Supplies In order to minimize current draw from lower priority power sources, the LTC4421 draws the vast majority of its supply current from the highest priority available supply. When SHDN is high and EXTVCC is connected to the system output voltage, the LTC4421 consumes 600A from the supply powering the output and only 10A to 26A from the other supplies. When SHDN is low, the 6A (typical) is drawn from the highest of the V1, V2, EXTVCC and OUT1 voltages, and the supply current in each of the other, lower voltage pins is a miniscule 250nA. from the output and allows V2 to connect to the output. This configuration permanently flips V1 and V2 priority, so that V2 is always the higher priority input. In Figure11, inverter U1 is used to connect the logically inverted VALID2 signal to DISABLE1. This configuration prevents Channel 1 from connecting to the output whenever Channel 2 is invalid. This prevents the primary input from powering the output unless a valid secondary supply is available to power the output when the primary fails. 5V RFLT2 100k Digital Status Outputs VALID1, VALID2, CH1, CH2 The LTC4421 provides open-drain pull-down digital outputs to provide system status information. The VALID1 and VALID2 pins pull low when their respective V1 and V2 input supplies have been validated. The CH1 and CH2 pins pull low when their input supply is connected to the output voltage. Connect large value pull-up resistors between these pins and INTVCC to provide the logic high, taking care not to exceed the 500A maximum current draw from INTVCC. The pull-downs are capable of driving low power LED's, but they cannot be pulled up to INTVCC in that case due to the LED current required. When using LED's, power the pull-up from a supply voltage up to 36V. These outputs can be used in conjunction with the DISABLE pins in a variety of application circuits to change V1, V2 priority over time. For example, consider what happens when CH2 is connected to DISABLE1. Once V2 is connected to the output, it will continue to power the output regardless of V1's validity. In effect, V2 became the higher priority supply, but only after it connected to the output. This configuration can be used in systems where, after switching to the secondary supply, it is desirable to run the secondary supply to full discharge before re-connecting to the primary. For proper operation at power up, it is essential that Channel 1 becomes valid before Channel 2. In Figure10, logic gates U1 and U2 disable channel 1 whenever V2 is valid, enabled and does not have a latched overcurrent fault. Disabling channel 1 disconnects V1 DIS2 DISABLE2 RVLD2 100k FAULT2 LTC4421 U2 DISABLE1 VALID2 U1 LTC4421 F10 Figure10. Flip Priority. Two External Logic Gates Are Used to Flip Priorities of Channel 1 and Channel 2 Input and Output Short Circuits and Supply Transient Protection When an input supply powering the output is shorted to ground, the LTC4421 senses reverse current through the sense resistor. When the reverse voltage developed 5V RVLD2 100k DISABLE1 LTC4421 VALID2 LTC4421 F11 Figure11. Valid Secondary Required. Preventing the Primary Input Supply from Powering the Output Unless a Valid Secondary Supply Is Present Rev. 0 22 For more information www.analog.com LTC4421 APPLICATIONS INFORMATION across the sense resistor exceeds 30mV, the LTC4421 sinks 50mA from the GATE pin of the shorted channel to turn off the N-Channel MOSFETs, thereby disconnecting the input from the output. Assuming the input is still valid, reconnection occurs when the output voltage drops 35mV below the input. When the output is shorted to ground, the voltage across the sense resistor may exceed 25mV until the current limit loop enters regulation. When the forward voltage across the sense resistors exceeds 50mV, the LTC4421 sinks 50mA from the GATE pin to quickly reduce the VGS of the N-Channel MOSFETs. The 50mA sink current is turned off when the voltage across the sense resistor falls below 25mV. When the output is shorted to ground, the current limit circuitry will regulate the current to ILIM. When the current limit circuitry has been engaged for longer than the time set by the TMR pin, a current limit fault is registered. The input is disconnected from the output, and FAULT is driven low. For large input and output inductances, rapid changes in current during short circuit events and channel turnoff can cause transient voltages that exceed the Absolute Maximum ratings of the input and output pins and/or violate the BVDSS limits of the external MOSFETs. To minimize INPUT PARASITIC INDUCTANCE such transients, use wider PCB traces and heavier trace plating to reduce power trace inductance. External to the PCB, twist the power and ground wires together to minimize inductance. Although the input snubber helps dissipate the input inductive energy at channel turn-off, transient voltage suppressor (TVS) D1 is still needed to clamp the peak input voltage, as shown in Figure 12. When selecting transient voltage suppressors, ensure the reverse standoff voltage (VR) is equal to or greater than the application operating voltage, the peak pulse current (IPP) is higher than the peak transient voltage divided by the source impedance, and the maximum clamping voltage (VCLAMP) at the rated IPP is less than the Absolute Maximum ratings of the LTC4421 and the BVDSS of the external MOSFETs. The LTC4421's Absolute Maximum Voltage Ratings of V1 and V2 allow it to withstand supply side inductive voltage spikes up to 60V. A range of TVS's can be used accommodating VR ratings up to 36V and VCLAMP ratings up to 60V. Cascading Multiple LTC4421's can be cascaded to prioritize more than two input supplies. To prioritize three or four supplies, use two LTC4421's with their OUT pins connected together, and connect CASOUT of the higher priority M1 PSMN4R060YS V1 D1 M2 RSENSE PSMN1R440YLD 2.5m COUT1 220F RSN SMDJ36A VOUT CSN CG1 47nF V1 GATE1 SOURCE1 SENSE1 OUT1 LTC4421 LTC4421 F12 Figure12. Supply Voltage Transient Suppression Circuitry Rev. 0 For more information www.analog.com 23 LTC4421 APPLICATIONS INFORMATION master LTC4421 to CASIN of the lower priority slave LTC4421, as shown in Figure13. When both master input supplies are invalid, the master verifies that it has disconnected both supplies from the output before driving its CASOUT pin high. This ensures the reverse conduction paths from the output back to the master inputs are blocked before the slave is allowed to power the output. The master LTC4421 pulls CASOUT up to INTVCC using a 20A current source, allowing the slave LTC4421 to connect its highest priority valid supply to the output. When the slave is powering the output and one of the master's inputs becomes valid, the master simultaneously connects its valid channel to the output and drives M1 SiR158DP V1 M2 SiR158DP RSENSE1 2.5m its CASOUT pin low to force the slave to disconnect its inputs. To prevent cross conduction, make the connection between the master's CASOUT and slave's CASIN as short as possible. This minimizes the capacitance of the connection and hence the turn-off delay of the slave channel. This scheme can be extended to prioritize as many input supplies as necessary. Connect each additional lower priority LTC4421's OUT pins to the common output voltage and connect its CASIN pin to the CASOUT pin of the next higher priority LTC4421. Note that driving the master LTC4421's CASIN pin low disconnects all input supplies in the system. Driving the master's DISABLE1 and DISABLE2 pins low disconnects the master's inputs from the output and allows the slave LTC4421's to connect to the output. VOUT CG1 47nF V1 GATE1 SOURCE1 SENSE1 OUT1 CASIN LTC4421 MASTER DISABLE1 L = DISCONNECT ALL CHANNELS H = CONNECT HIGHEST PRIORITY VALID CHANNEL L = DISABLE MASTER, ENABLE SLAVE DISABLE2 CASOUT M5 SiR158DP V3 M6 SiR158DP RSENSE3 2.5m CG3 47nF V1 GATE1 SOURCE1 LTC4421 SLAVE SENSE1 OUT1 CASIN SHDN CONNECT HIGH CASOUT LTC4421 F13 Figure13. Using Two LTC4421's in a Cascading Application to Prioritize Four Input Supplies. (The Master and Slave V2 Power Paths are Omitted for Clarity) Rev. 0 24 For more information www.analog.com LTC4421 APPLICATIONS INFORMATION Design Example As a design example, take the following specifications for the circuit in Figure14. For simplicity, the same specifications and hence the same component values are used for each channel. The application is rated for an input voltage of 12V, maximum output load current of 8A, UV rising = 11V, UV falling = 8V, OV Rising = 15V and maximum output voltage drop during switchover = 1.2V (10% of the input supply voltages). The minimum and maximum operating ambient temperatures are -40C and 85C, respectively. Start by setting the current limit to 16A, so that the output voltage can be charged at full DC load conditions in a reasonable amount of time as shown by Equation 18 (from Equation 6). RSENSE = PRIMARY 12V 25mV = 1.5625m 16A The nearest standard value sense resistor is 1.5m, which results in a current limit of 16.7A. Choose an electrolytic output capacitor having RESR=50m. During switchover is given by Equation 19 (from Equation 8). (19) VSTEP = (8A * 50m) = 400mV To keep the total output voltage drop during switchover to less than 1.2V, the maximum droop must be 800mV. Therefore is given by Equation 20 (from Equation 9). COUT (8A * 15s) = 150F 800mV (20) so we choose COUT = 220F for margin. (18) ILIM1 = 16.7A RSENSE1 M1 M2 PSMN4R060YS PSMN1R440YLD 1.5m VOUT 8A RSN1 1.2 CSN1 10F D1 SMBJ24CA ILIM2 = 16.7A RSENSE2 M3 M4 PSMN4R060YS PSMN1R440YLD 1.5m SECONDARY 12V D2 SMBJ24CA RSN2 1.2 CSN2 10F COUT 220F CG2 47nF CG1 47nF CCP0 1F R4 931k V1 GATE1 SOURCE1 SENSE1 OUT1 CPO CPOREF V2 GATE2 SOURCE2 R3 16.9k UVR1 R2 12.1k R1 33.2k VUVFALL1 = 8V VUVRISE1 = 11V VOVRISE1 = 15V VUVFALL2 = 8V VUVRISE2 = 11V VOVRISE = 15V OV1 LTC4421 R8 931k R7 16.9k R6 12.1k R5 33.2k UVF2 UVR2 OV2 SENSE2 OUT2 EXTVCC UVF1 GND QUAL TMR1 CQUAL 1nF TMR2 CTMR1 6.8nF INTVCC CTMR2 6.8nF CINTVCC 1F C2 0.1F VALID1 VALID2 CH1 CH2 FAULT1 FAULT2 CASOUT DIGITAL STATUS OUTPUTS RETRY DISABLE1 DISABLE2 SHDN CASIN DIGITAL CONTROL INPUTS LTC4421 F14 Figure14. Dual 12V, 8A Application Circuit for Design Example Rev. 0 For more information www.analog.com 25 LTC4421 APPLICATIONS INFORMATION Next, calculate the time it takes to charge the output voltage from 0V to 12V at the maximum DC load current as shown in Equation 21 (from Equation 10). tCHG(MAX) = (220F * 12V) = 303s (16.7A - 8A) (21) To ensure the output will fully charge before triggering an overcurrent fault time-out, choose CTMR1 to set tTMR,FLT = 450s. See Equation 22 (from Equation 13). 450s CTMR1 = = 5.4nF 83[s/nF] (22) Using the nearest standard value and accounting for tolerance, we choose 6.8nF, which yields tTMR,FLT = 564s. The power dissipation during short circuits is given by Equation 23 (from Equation 11). (23) Power = (12V * 16.7A) = 200W Referring to the SOA curves in the PSMN4R060YS data sheet, the MOSFET can withstand 720W for 1ms at 25C and 12V. Derating the SOA for the maximum operating temperature is given by Equation 24 (from Equation 12). SOA(85C) = 720W * (175 - 85) = 432W at 1ms (24) (175 - 25) Our overcurrent fault time-out will occur for 200W at 564s, so the requirement is satisfied. Next, select 47nF capacitors CG1 and CG2 to compensate the current limit regulation loops of channels 1 and 2, respectively. D1 and D2 are bidirectional Transient Voltage Suppression (TVS) diodes that clamp the input voltages below 40V at channel turn-off, thereby protecting the LTC4421 and the N-Channel MOSFETs. The OV, UV monitoring resistors should be chosen to yield a total divider resistance of between 1M and 2M for both low power and good transient response time. Using Equation 1 through Equation 4 and rounding up to the nearest 1% accurate standard resistor values, R1-R4 are calculated by Equation 25. (25) Choose R1 + R2 + R3 + R4 = 1000k From Equation 2, R1 = (0.5/15) * 1000k = 33.3k. The nearest standard resistor value is 33.2k. From Equation 3, R2 = (15/11 - 1) * 33.2k = 12.07k. The nearest standard value is 12.1k. From Equation 4, R3 = (11/8 - 1) * (15/11) * 33.2k = 16.98k. The nearest standard value is 16.9k. From Equation 5, R4 = (15/0.5 - 1) * 33.2k - 12.1k - 16.9k = 933.8k. The nearest standard value is 931k. From Equation 17, CQUAL is set to 1nF to set an OV, UV validation time of 16ms. This gives the LTC4421 time to pre-charge the GATE1 voltage to minimize turn-on time when V2 is powering the output and the V1 input supply is plugged in. PCB Layout Considerations To achieve accurate current sensing, Kelvin connections are recommended for the sense resistors. The PCB layout for the sense resistors should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistors and power MOSFETs should include good thermal management techniques for optimal device power dissipation. Small resistances add up quickly in high current applications. Note that 1oz copper exhibits a sheet resistance of about 530/square. The minimum trace width for 1oz copper is 0.02" per amp (0.5mm per amp) to make sure the trace stays at a reasonable temperature. Using 0.03" per amp (0.8mm per amp) is recommended. To improve noise immunity, put the OV, UVR, UVF resistive dividers close to the LTC4421 and keep traces to GND pin and the input supply pin short. It is also important to put CINTVCC, the bypass capacitor for the INTVCC pin, as close as possible between INTVCC and GND. Place CCPO, the charge pump reservoir capacitor, as close as possible between the CPO and CPOREF pins. Transient voltage suppressors D1 and D2 are located close to the LTC4421 and are connected between the input supply and ground using wide traces. Figure15 shows a recommended PCB layout for a 2-layer board. Rev. 0 26 For more information www.analog.com LTC4421 APPLICATIONS INFORMATION VOUT METAL RSENSE2 RSENSE1 FROM V1 INPUT SOURCE G S M1 D D M2 G G S S G M4 D S FROM V2 INPUT SOURCE D M3 RSN1 RSN2 CCPO R4 4 UVF1 5 UVR1 6 OV1 31 30 29 OUT2 3 V1 32 SENSE2 GATE1 33 GND 2 34 CPO SOURCE1 35 EXTVCC 1 36 OUT1 CSN1 D1 TRANSIENT VOLTAGE SUPPRESSOR CPOREF 0.03" PER AMPERE SENSE1 0.03" PER AMPERE CSN2 GATE2 27 V2 26 UVF2 25 R3 TMR1 TMR2 22 CTMR2 8 DISABLE1 9 CH1 R5 Layer 1 Layer 2 FAULT2 13 SHDN 12 RETRY 11 QUAL CH2 20 CASOUT 10 VALID1 DISABLE2 21 INTVCC CTMR1 7 R6 OV2 23 CASIN R1 R8 R7 UVR2 24 37 FAULT1 R2 R2 D2 TRANSIENT VOLTAGE SUPPRESSOR SOURCE2 28 14 15 16 17 18 VALID2 19 CINTVCC GND GND NOT TO SCALE LTC4421 F15 Figure15. Recommended 2-Layer PCB Layout Preventing Input Hold-Up During Unplug Events SOA Doubler Figure16 includes a backplane connector with a kelvin sense. The resistive divider network that sets the OV and UV thresholds is connected to the kelvin sense. Disconnecting the supply powering V1 causes a nearly immediate UV fault, because there is no hold-up capacitance on the OV1, UVF1 or UVR1 pins. The output voltage discharges minimally before the UV fault occurs, as the output discharge rate is very slow compared to the UV fault time. Without a kelvin sense connection, upon input supply disconnection the resistive divider would stay connected to the drain of M1. The output, OV1, UVF1 and UVR1 pin voltages would all fall at the rate dictated by the output discharge, and the channel would not be disconnected until the output voltage dropped below the UVF1 threshold voltage. Multiple LTC4421's can be used to control parallel MOSFET pathways from each input to the output, as shown in Figure17. This is valuable in very high current applications to cut the SOA and load current carrying burdens of each MOSFET in half. LTC4421 #1 acts as a master and performs all monitoring functions, including OV, UV, fault and reverse current. After LTC4421 #2 drives the VALID12 and VALID22 signals low to indicate that it has successfully powered up, it acts as a slave to LTC4421#1, turning its external MOSFETs on and off at LTC4421#1's command. Connecting LTC4421 #1's CH1 and CH2 outputs through inverters U3 and U4 to LTC4421 #2's DISABLE1 and DISABLE2 inputs, respectively, synchronizes channel turn-on and turn-off of the two LTC4421's. NOR gates U1 and U2 prevent LTC4421 #1 from turning on its MOSFETs until LTC4421 #2's inputs are validated. This ensures that LTC4421 #1 never turns on its MOSFETs when LTC4421 #2 is unable to turn on its MOSFETs. Rev. 0 For more information www.analog.com 27 LTC4421 APPLICATIONS INFORMATION RSENSE1 M1 M2 PSMN4R060YS PSMN1R440YLD 2.5m VOUT COUT 220F CONNECTOR2 CONNECTOR1 VIN ILOAD CG1 47nF CCPO 1F KELVIN R4 1M UVF1 V1 GATE1 SOURCE1 SENSE1 OUT1 CPOREF CPO R3 20k UVR1 R2 12.7k LTC4421 OV1 R1 35.7k LTC4421 F16 GND Figure16. Preventing Input Hold-Up During Unplug Events with a Staggered Connector to Decouple OV and UV Pins from VOUT Rev. 0 28 For more information www.analog.com VPULLUP Q1 2N2222 RLIM1 10k RESERVE 28V MAIN 12V CPULL 1F D5 1N4148 D7 1N750 RLIM2 100k D6 1N4148 RSN2 1.4 CSN2 10F R1 35.7k R2 12.7k R3 20k R4 1M UV2FALLING = 5.97V UV2RISING = 25.28V OV2RISING = 35.4V UV1FALLING = 7.81V UV1RISING = 11.04V OV1RISING = 14.96V RSN1 0.6 CSN1 10F For more information www.analog.com R5 15.4k R6 6.19k R7 69.8k R8 1M GND QUAL SOURCE1 OV2 UVR2 UVF2 OV1 UVR1 UVF1 V1 GATE1 GND QUAL SOURCE1 CG3 47nF CCPO1 1F 47nF CG2 CQUAL 470pF TMR1 CTMR1 47nF CINTVCC1 1F LTC4421 #2 SLAVE TMR2 OUT2 VALID1 VALID2 CH1 CH2 FAULT1 FAULT2 CASOUT EXTVCC RETRY DISABLE1 DISABLE2 SHDN CASIN SENSE2 CG4 47nF 1F CINTVCC2 INTVCC VALID1 VALID2 CH1 CH2 FAULT1 FAULT2 CASOUT EXTVCC OUT2 LTC4421 F17 RETRY DISABLE1 DISABLE2 SHDN CASIN SENSE2 M8 M7 RSENSE4 PSMN4R8100BSE PSMN1R440YLD 2.5m CTMR2 47nF INTVCC OUT1 CPO CPOREF V2 GATE2 SOURCE2 TMR1 SENSE1 CCPO2 1F TMR2 LTC4421 #1 MASTER SENSE1 OUT1 CPO CPOREF V2 GATE2 SOURCE2 M6 M5 RSENSE3 PSMN4R8100BSE PSMN1R440YLD 2.5m OV2 UVR2 UVF2 OV1 UVR1 UVF1 V1 GATE1 CG1 47nF RSENSE2 M3 M4 PSMN4R8100BSE PSMN1R440YLD 2.5m 0.1F U2 U1 C2 0.1F VALID12 VALID22 ENABLE2 ENABLE1 RVLD1 10k RVLD3 10k U4 U3 CH2 CH1 RVLD4 10k RCH2 10k VPULLUP COUT2 470F RCH1 10k VPULLUP RVLD2 10k COUT1 470F Figure17. SOA Doubler. Using Two LTC4421's in a Master-Slave Configuration to Split Current and SOA Burden Between Parallel Pairs of MOSFETs in High Current Applications D2 SMDJ36A D1 SMDJ36A RSENSE1 M1 M2 PSMN4R8100BSE PSMN1R440YLD 2.5m RFLT1 10k RFLT2 10k ILIM1(TOT) = 20A ILIM2(TOT) = 20A VOUT LTC4421 APPLICATIONS INFORMATION Rev. 0 29 LTC4421 PACKAGE DESCRIPTION UHE Package 36-Lead Plastic QFN (5mm x 6mm) (Reference LTC DWG # 05-08-1876 Rev O) 0.70 0.05 5.50 0.05 4.10 0.05 3.50 REF PACKAGE OUTLINE 3.60 0.05 4.60 0.05 0.25 0.05 0.50 BSC 4.50 REF 5.10 0.05 6.50 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 0.10 0.00 - 0.05 0.200 REF 3.50 REF R = 0.10 TYP 29 36 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 28 6.00 0.10 1 4.50 REF 4.60 0.10 3.60 0.10 20 10 (UHE36) QFN 0410 REV O 0.75 0.05 19 0.25 0.05 11 R = 0.125 TYP 0.50 BSC BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev. 0 30 For more information www.analog.com LTC4421 PACKAGE DESCRIPTION G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.50 - 13.10* (.492 - .516) 1.25 0.12 7.8 - 8.2 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 5.3 - 5.7 0.42 0.03 7.40 - 8.20 (.291 - .323) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 RECOMMENDED SOLDER PAD LAYOUT 2.0 (.079) MAX 5.00 - 5.60** (.197 - .221) 0 - 8 0.09 - 0.25 (.0035 - .010) 0.55 - 0.95 (.022 - .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 0.65 (.0256) BSC 0.22 - 0.38 (.009 - .015) TYP 0.05 (.002) MIN G36 SSOP 0204 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 31 LTC4421 TYPICAL APPLICATION Secondary Supply Run Down to 500mV Using LTC3119 to Power EXTVCC L1 4.7H C7 0.1F M1 M2 RSENSE1 PSMN4R060YS PSMN1R440YLD 1.5m PRIMARY 12V D1 SMBJ24CA RSN1 1.2 CSN1 10F COUT1 220F R14 100k D2 SMBJ24CA RSN2 1.2 CSN2 10F PVOUT SENSE1 OUT1CPO V1 GATE1 SOURCE1 LTC3119 FB PGOOD SVCC VC RT C8 4.7F SOURCE2 SENSE2 R13 316k PWM/SYNC CG2 47nF CPOREF V2 GATE2 VOUT 3.3V C10 220F RUN VCC CCPO 1F R4 1M PVIN MPPC CG1 47nF C9 0.1F SW2 BST2 VIN M3 RSENSE2 M4 PSMN4R060YS PSMN1R440YLD 1.5m SECONDARY 12V SW1 BST1 R10 162k PGND GND OUT2 R12 100k R9 78.7k C11 820pF UVF1 R3 20k UVR1 R2 12.7k OV1 LTC4421 R1 35.7k R7 1.02M UVR1 = 11.04V UVF1 = 7.81V OV1 = 14.96V UVR2 = 11.04V UVF2 = 500mV OV2 = 14.96V R6 12.7k R5 35.7k UVF2 UVR2 OV2 GND QUAL TMR1 CQUAL 470pF TMR2 CTMR1 47nF DIGITAL STATUS OUTPUTS RETRY DISABLE1 DISABLE2 SHDN CASIN DIGITAL CONTROL INPUTS EXTVCC INTVCC CTMR2 47nF D3 VALID1 VALID2 CH1 CH2 FAULT1 FAULT2 CASOUT CINTVCC 1F LTC4421 TA02 C2 0.1F RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC4417 Triple Prioritized PowerPath Controller 2.5V to 36V Operation; Ext P-Channel MOSFET; -42V Reverse Protection LTC4418 Dual Prioritized PowerPath Controller 2.5V to 40V Operation; Ext P-Channel MOSFET; -42V Reverse Protection LTC4419 Dual Prioritized PowerPath Controller 1.8V to 18V Operation; 0.5A Switches; Freshness Seal LTC4420 Dual Prioritized PowerPath Controller 1.8V to 18V Operation; 0.5A Switches; Freshness Seal; Backup Disconnect LTC4411 Single 2.6A Ideal Diode 2.6V to 5.5V Operation; 140m RON; 40A IQ LTC4358 Single 5A Ideal Diode 9V to 26.5V Operation; 20m RON; 780A IQ LTC4413 Dual 2.6A Ideal Diode 2.5V to 5.5V Operation; 140m RON; 25A IQ LTC4415 Dual 4A Ideal Diode 1.7V to 5.5V Operation; 50m RON; 44A IQ Rev. 0 32 11/19 www.analog.com ANALOG DEVICES, INC. 2019