M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
DESCRIPTION
These are single-chip microcomputers designed with high-perfor-
mance CMOS silicon gate technology, including the internal flash
memory. These microcomputers support the 7900 Series instruction
set, which are enhanced and expanded instruction set and are up-
per-compatible with the 7700/7751 Series instruction set.
The CPU of these microcomputers is a 16-bit parallel processor that
can also be switched to perform 8-bit parallel processing. Also, the
bus interface unit of these microcomputers enhances the memory
access efficiency to execute instructions fast. Therefore, these mi-
crocomputers are suitable for office, business, and industrial equip-
ment controller that require high-speed processing of large data.
For the internal flash memory, single-power-supply programming
and erasure, using a PROM programmer or the control by the cen-
tral processing unit (CPU), is supported. Also, each of these micro-
computers has the memory area dedicated for storing a certain
software which controls programming and erasure (reprogramming
control software). Therefore, on these microcomputers, the program
can easily be changed even after they are mounted on the board.
DISTINCTIVE FEATURES
<Microcomputer mode>
•Number of basic machine instructions .................................... 203
•Memory
[M37902FCMHP]
Flash memory (User ROM area) ................................. 120 Kbytes
RAM .............................................................................4096 bytes
[M37902FGMHP]
Flash memory (User ROM area) ................................. 248 Kbytes
RAM .............................................................................6144 bytes
[All of the above computers]
Flash memory (Boot ROM area) ................................... 16 Kbytes
•Instruction execution time
The fastest instruction at 20 MHz frequency ........................ 50 ns
•Single power supply ................................................. 3.3 V ± 0.3 V
•Interrupts ........... 6 external sources, 16 internal sources, 7 levels
•Multi-functional 16-bit timer ................................................... 5 + 3
•Serial I/O (UART or Clock synchronous)..................................... 2
•10-bit A-D converter ............................................8-channel inputs
•8-bit D-A converter ............................................ 3-channel outputs
•Real-time output
....4 bits × 2 channels, or 6 bits × 1 channel + 2 bits × 1 channel
•12-bit watchdog timer
•Programmable input/output (ports P0–P8, P10, P11) ............... 84
<Flash memory mode>
•Power supply voltage ............................................... 3.3 V ± 0.3 V
•Programming/Erase voltage..................................... 3.3 V ± 0.3 V
•Programming method............ Programming in a unit of 256 bytes
•Erase method ............................................
Block erase or Total erase
(Data protection per block is enabled.)
•Programming/Erase control by software command
•Maximum number of reprograms ............................................ 100
APPLICATION
Control devices for personal computer peripheral equipment such as
CD-ROM drives, DVD-ROM drives, hard disk drives, high density
FDD, printers
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
2
M37902FxMHP PIN CONFIGURATION (TOP VIEW)
Outline 100P6Q-A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P6
4
/INT
2
↔
P6
3
/INT
1
↔
P6
2
/INT
0
↔
P6
1
/TA4
IN
↔
P6
0
/TA4
OUT
↔
P5
5
/TA2
IN
/RTP1
1
/KI
1
↔
P5
4
/TA2
OUT
/RTP1
0
/KI
0
↔
P5
3
/TA1
IN
/RTP0
3
↔
P5
2
/TA1
OUT
/RTP0
2
↔
P5
1
/TA0
IN
/RTP0
1
↔
P5
0
/TA0
OUT
/RTP0
0
↔
P4
7
/CS
3
↔
P4
6
/CS
2
↔
P4
5
/CS
1
↔
P4
4
/CS
0
↔
P4
3
/HOLD ↔
P4
0
/ALE ↔
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P4
2
/HLDA ↔
P4
1
/φ
1
↔
P6
5
/TB0
IN
↔
P6
6
/TB1
IN
↔
P6
7
/TB2
IN
↔
P7
0
/AN
0
↔
↔ P3
0
/RDY
↔ P3
1
/RD
↔ P3
2
/BLW
↔ P3
3
/BHW
←
BYTE
V
CONT
←
RESET
←
MD0
V
SS
↔ P2
5
/D
13
↔ P2
4
/D
12
↔ P2
6
/D
14
←
X
IN
→
X
OUT
V
CC
↔ P2
7
/D
15
↔ P2
3
/D
11
↔ P2
2
/D
10
↔ P2
1
/D
9
↔ P2
0
/D
8
↔ P1
7
/D
7
/LA
7
↔ P1
6
/D
6
/LA
6
↔ P1
5
/D
5
/LA
5
↔ P1
0
/D
0
/LA
0
↔ P1
1
/D
1
/LA
1
↔ P1
2
/D
2
/LA
2
V
SS
↔ P10
5
/A
5
↔ P10
4
/A
4
↔ P10
7
/A
7
↔ P10
6
/A
6
↔ P11
0
/A
8
↔ P11
2
/A
10
↔ P11
1
/A
9
↔ P11
3
/A
11
↔ P11
5
/A
13
↔ P11
4
/A
12
↔ P11
6
/A
14
↔ P0
0
/A
16
↔ P11
7
/A
15
↔ P0
1
/A
17
↔ P0
2
/A
18
↔ P0
4
/A
20
↔ P0
3
/A
19
↔ P0
5
/A
21
↔ P0
7
/A
23
←
MD1
↔ P0
6
/A
22
↔ P1
4
/D
4
/LA
4
↔ P1
3
/D
3
/LA
3
P10
0
/A
0
↔
P8
7
/T
X
D
1
↔
P8
6
/R
X
D
1
↔
P8
5
/CTS
1
/CLK
1
↔
P8
4
/CTS
1
/RTS
1
/INT
4
↔
P8
3
/T
X
D
0
↔
P10
3
/A
3
↔
P10
2
/A
2
↔
P10
1
/A
1
↔
P8
2
/R
X
D
0
↔
V
CC
AV
CC
V
REF
→
AV
SS
V
SS
P7
7
/AN
7
/AD
TRG
/DA
1
/(INT
2
) ↔
P7
6
/AN
6
/DA
0
↔
P7
5
/AN
5
/(INT
4
) ↔
P7
4
/AN
4
/(INT
3
) ↔
P7
3
/AN
3
↔
P7
2
/AN
2
↔
P7
1
/AN
1
↔
P8
0
/CTS
0
/RTS
0
/DA
2
/INT
3
↔
NMI →
P8
1
/CTS
0
/CLK
0
↔M37902FCMHP
M37902FGMHP
P5
7
/TA3
IN
/RTP1
3
/KI
3
↔
P5
6
/TA3
OUT
/RTP1
2
/KI
2
↔
3
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
BLOCK DIAGRAM
Data bank Register DT (8)
Program Counter PC (16)
Incrementer/Decrementer (24)
Program Bank Register PG (8)
Input Buffer Register IB (16)
Direct Page Register DPR0 (16)
Stack Pointer S (16)
Index Register Y (16)
Index Register X (16)
Arithmetic Logic
Unit (16)
Accumulator B (16)
Accumulator A (16)
Instruction register (8)
Central Processing Unit (CPU)
Incrementer (24)
Program Address Register PA (24)
Data Address Register DA (24)
Bus
Interface
Unit
(BIU)
RESET MD1
Reference
voltage input
V
REF
(0V)
AV
SS
AVcc
Vcc
External data bus width
select input
BYTE
Clock Generating Circuit
Clock input
X
IN
V
CONT
X
OUT
Data Buffer DQ
0
(8)
Instruction Queue Buffer Q
0
(8)
Data Bus (Odd)
Address Bus
A-D converter (10)
UART1 (9)
UART0 (9)
Watchdog timer
Timer TB1 (16)
Timer TB2 (16)
Timer TB0 (16)
D-A
1
converter (8)
D-A
2
converter (8)
Timer TA1 (16)
Timer TA2 (16)
Timer TA3 (16)
Timer TA4 (16)
Timer TA0 (16)
RAM
(Note)
P8(8)
Input/Output
port P8
P7(8)
Input/Output
port P7 Input/Output
port P4
P4(8)
P10(8)
Input/Output
port P10
P6(8)
Input/Output
port P6
P5(8)
Input/Output
port P5
P11(8)
Input/Output
port P11
P1(8)
Input/Output
port P1
P2(8)
Input/Output
port P2
P3(4)
Input/Output
port P3
P0(8)
Input/Output
port P0
MD0
(0V)
Vss
Processor Status Register PS (11)
NMI
Flash memory
(Note) D-A
0
converter (8)
Data Bus (Even)
Data Buffer DQ
1
(8)
Data Buffer DQ
2
(8)
Data Buffer DQ
3
(8)
Instruction Queue Buffer Q
1
(8)
Instruction Queue Buffer Q
2
(8)
Instruction Queue Buffer Q
3
(8)
Instruction Queue Buffer Q
4
(8)
Instruction Queue Buffer Q
5
(8)
Instruction Queue Buffer Q
6
(8)
Instruction Queue Buffer Q
7
(8)
Instruction Queue Buffer Q
8
(8)
Instruction Queue Buffer Q
9
(8)
Direct Page Register DPR1 (16)
Direct Page Register DPR2 (16)
Direct Page Register DPR3 (16)
Clock output Reset input
Note:
Flash memory RAM
M37902FCMHP 120 Kbytes 4096 bytes
M37902FGMHP 248 Kbytes 6144 bytes
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
4
203
50 ns (the fastest instruction at f(fsys) = 20 MHz)
20 MHz (Max.)
20 MHz (Max.)
(Note)
(Note)
16 Kbytes
8-bit ✕ 10
4-bit ✕ 1
16-bit ✕ 5
16-bit ✕ 3
(UART or Clock synchronous serial I/O) ✕ 2
10-bit successive approximation method ✕ 1 (8 channels)
8-bit ✕ 3
12-bit ✕ 1
Chip select area ✕ 4 (CS0–CS3). A bus cycle type and bus width
can be set for each chip select area.
4 bits ✕ 2 channels; or 6 bits ✕ 1 channel + 2 bits ✕ 1 channel
5 external types, 13 internal types. Each interrupt can be set to a
priority level within the range of 0–7 by software.
1 external type, 3 internal types.
Built-in (externally connected to a ceramic resonator or quartz
crystal resonator).
The following multiplication methods are available: double, triple,
and quadruple.
3.3 V±0.3 V
39.6 mW (at f(fsys) = 20 MHz, Typ., PLL frequency multiplier
stopped)
3.3 V
5 mA
Up to 16 Mbytes. Note that bank FF16 is a reserved area.
–20 to 85 °C
CMOS high-performance silicon gate process
100-pin plastic molded QFP
FUNCTIONS (Microcomputer mode)
FunctionsParameter
Number of basic machine instructions
Instruction execution time
External clock input frequency f(XIN)
System clock frequency fsys
Memory size
Programmable input/output
ports
Multi-functional timers
Serial I/O
A-D converter
D-A converter
Watchdog timer
Chip-select wait control
Real-time output
Interrupts
Clock generating circuit
PLL frequency multiplier
Input/Output withstand voltage
Output current
Flash memory (User ROM area)
RAM
Flash memory (Boot ROM area)
P0–P2, P4–P8, P10, P11
P3
TA0–TA4
TB0–TB2
UART0 and UART1
Power supply voltage
Power dissipation
Ports’ input/output
characteristics
Memory expansion
Operating ambient temperature range
Device structure
Package
Maskable interrups
Non-maskable interrups
Flash memory M37902FCMHP 120 Kbytes
(User ROM area) M37902FGMHP 248 Kbytes
RAM M37902FCMHP 4096 bytes
M37902FGMHP 6144 bytes
Note:
5
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3.3 V±0.3 V
3.3 V±0.3 V
3 modes: parallel I/O, serial I/O, and CPU reprogramming modes
(Note 1)
1 block (16 Kbytes ✕ 1) (Note 2)
Programmed per page (in a unit of 256 Kbytes)
User ROM area + Boot ROM area
User ROM area
User ROM area
Total erase/Block erase
User ROM area + Boot ROM area
User ROM area
User ROM area
Programming/Erase control by software commands
Protected per block, by using a lock bit.
8 commands
100
FUNCTIONS (Flash memory mode)
FunctionsParameter
Power supply voltage
Programming/Erase voltage
Flash memory mode
Block division for erasure
Programming method
Erase method
Programming/Erase control
Data protection method
Number of commands
Maximum number of reprograms
User ROM area
Boot ROM area
Flash memory parallel I/O mode
Flash memory serial I/O mode
Flash memory CPU reprogramming mode
Flash memory parallel I/O mode
Flash memory serial I/O mode
Flash memory CPU reprogramming mode
2: On shipment,
our reprogramming control firmware
for the flash memory serial I/O mode has been stored into the boot ROM area.
Note that the boot ROM area can be erased/programmed only in the flash memory parallel I/O mode.
User ROM area
M37902FCMHP 5 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 1), total 120 Kbytes
M37902FGMHP 7 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 3), total 248 Kbytes
Notes 1:
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
6
Vcc, Vss
MD0
MD1
RESET
XIN
XOUT
BYTE
VCONT
AVcc,
AVss
VREF
P00–P07
P10–P17
P20–P27
P30–P33
P40–P47
Power supply input
MD0
MD1
Reset input
Clock input
Clock output
External data bus width
select input
Filter circuit connection
Analog power supply input
Reference voltage input
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
—
Input
Input
Input
Input
Output
Input
—
—
Input
I/O
I/O
I/O
I/O
I/O
Apply 3.3 V±0.3 V to Vcc, and 0 V to Vss.
This pin controls the processor mode. Connect this pin to VSS for the single-chip
mode or memory expansion mode, and Vcc for the microprocessor mode.
Connect this pin to Vss.
The microcomputer is reset when “L” level is applied to this pin.
These are input and output pins of the internal clock generating circuit. Connect a
ceramic or quartz- crystal resonator between the XIN and XOUT pins. When an
external clock is used, the clock source should be connected to the XIN pin, and the
XOUT pin should be left open.
This pin determines whether the external data bus has an 8-bit width or 16-bit width
for the memory expansion mode or microprocessor mode. The width is 16 bits when
“L” signal is input, and 8 bits when “H” signal is input. When BYTE = Vss level, by
the register setting, the external data bus for each of areas CS1 to CS3 can have a
width of 8 bits.
When using the PLL frequency multiplier, connect this pin to the filter circuit. When
not using, this pin should be left open.
Power supply input pins for the A-D converter and the D-A converter. Connect AVcc
to Vcc, and AVss to Vss externally.
This is the reference voltage input pin for the A-D converter and the D-A converter.
■ In single-chip mode
Port P0 is an 8-bit I/O port. This port has an I/O direction register, and each pin
can be programmed for input or output. These pins enter the input mode at
reset.
■ In memory expansion and microprocessor modes
Address (A16–A23) is output. These pins also function as I/O port pins according
to the register setting.
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion and microprocessor modes
The low-order 8 bits of data (D0–D7) are input/output. When the external data bus
has an 8-bit width, address (LA0–LA7) output and data (D0–D7) input/output can
be performed with the time-sharing method, according to the register setting.
■ In single-chip mode or When 8-bit external data bus is used in memory expansion
mode and microprocessor mode
These pins have the same functions as port P0.
■ When the 16-bit external data bus is used in memory expansion or microproce-
ssor mode
The high-order 8 bits of data (D8–D15) are input or output.
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion mode
P30 functions as an I/O port pin; and P31, P32, and P33 function as the output
pins of RD, BLW, BHW, respectively. P30 also functions as an output pin of RDY
according to the register setting. When the external data bus has a width of 8 bits,
the BHW pin functions as an I/O port pin (P33).
■ In microprocessor mode
P30 functions as an input pin of RDY; and P31,P32, P33 function as the output
pins of RD, BLW, BHW , respectively. P30 also functions as an I/O port pin accord-
ing to the register setting. When the external data bus has a width of 8 bits,
the BHW pin functions as an I/O port pin (P33).
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion mode
P40–P47 function as I/O port pins. According to the register setting, these pins
function as output pins or input pins of ALE, φ1, HLDA, HOLD, CS0–CS3, respec-
tively.
■ In microprocessor mode
P40–P44 function as output or input pins of ALE, φ1, HLDA, HOLD, CS0, and
P45–P47 as I/O port pins, respectively. According to the register setting, P40–P43
also function as I/O port pins, and P45–P47 as output pins of CS1–CS3.
PIN DESCRIPTION (MICROCOMPUTER MODE)
Functions
Input/
Output
NamePin
7
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
I/O
I/O
I/O
I/O
I/O
I/O
Input
Functions
Input/
Output
NamePin
P50–P57
P60–P67
P70–P77
P80–P87
P100–P107
P110–P117
NMI
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as I/O pins for timers A0–A3, output pins for the real-time output,
and input pins for the key-input interrupt.
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as I/O pins for timer A4, input pins for external interrupt inputs
INT0–INT2, and input pins for timers B0–B2.
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as input pins for the A-D converter, output pins for the D-A
converter, and input pins for INT2, INT3, and INT4.
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as I/O pins for UART0, UART1, output pins for D-A converter,
and input pins for INT3 and INT4.
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion and microprocessor modes
Address (A0–A7) is output.
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion and microprocessor modes
Address (A8–A15) is output. Also, these pins function as I/O port pins according to
the register setting.
This pin is for a non-maskable interrupt.
I/O port P5
I/O port P6
I/O port P7
I/O port P8
I/O port P10
I/O port P11
Non-maskable interrupt
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
8
PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE)
VCC, VSS
MD0
MD1
_____
RESET
XIN
XOUT
BYTE
VCONT
A Vcc, A Vss
VREF
P00–P07
P10–P17
P20–P27
P30–P33
P40,
P44– P47
P41
P42
P43
P50–P57
P60–P67
P70–P77
P80–P87
P100–P107
P110–P117
NMI
Pin
Power supply input
MD0
MD1
Reset input
Clock input
Clock output
BYTE
Filter circuit connection
Analog supply input
Reference voltage input
Input port P0
Input port P1
Input port P2
Input port P3
Input port P4
SCLK input
SDA I/O
BUSY output
Input port P5
Input port P6
Input port P7
Input port P8
Input port P10
Input port P11
Non-maskable interrupt
Name
—
Input
Input
Input
Input
Output
Input
—
—
Input
Input
Input
Input
Input
Input
Input
I/O
Output
Input
Input
Input
Input
Input
Input
Input
Input
/Output
Functions
Apply 3.3 V ± 0.3 V to Vcc, and 0 V to Vss.
Connect this pin to Vss.
Connect this pin to Vss via a resistor of 10 kΩ to 100 kΩ.
The reset input pin.
Connect a ceramic resonator between the XIN and XOUT pins, or input an external
clock from the XIN pin with the XOUT pin left open.
Connect this pin to Vcc or Vss. (This is not used in the flash memory serial I/O mode.)
Connect this pin to the filter circuit, or leave this pin open. (This is not used in the flash memory serial I/O mode.)
Connect AVcc to Vcc, and AVss to Vss.
Input an arbitrary level within the range of V
SS
–V
CC
.(This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
I
nput “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
This is an input pin for a serial clock.
This is an I/O pin for serial data. Connect this pin to VCC via a resistor (about 1 kΩ).
This is an output pin for the BUSY signal.
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H”, or leave this pin open.
9
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
BASIC FUNCTION BLOCKS
These microcomputers have the same functions as the
M37902FCCHP.
Therefore, refer to the datasheet of the M37902FCCHP.
MEMORY
Figures 1 and 2 show the memory maps. The address space is 16
Mbytes from address 016 to FFFFFF16. The address space is di-
vided into 64-Kbyte units called banks. The banks are numbered
from 016 to FF16. Bank FF16 is a reserved area for the development
support tool. Therefore, do not use bank FF16.
Internal flash memory and internal RAM are assigned as shown in
Figures 1 and 2.
Addresses FFC016 to FFFF16 contain the RESET and the interrupt
vector addresses, and the interrupt vectors are stored there.
For details, refer to the section on interrupts.
Assigned to addresses 016 to FF16 are peripheral devices such as
I/O ports, A-D converter, D-A converter , UAR T, timers, interrupt con-
trol registers, etc. Figures 7 and 8 show the location of SFRs. For the
flash memory in the boot ROM area, refer to the section on the flash
memory mode.
Fig. 1 Memory map of M37902FCMHP (Single-chip mode)
;;
;;
;;
INT4
A-D conversion
Reserved area
Reserved area
Address matching detect
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Interrupt vector table
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
Watchdog timer
BRK instruction
Zero divide
INT3
INT2
INT1
INT0
NMI
RESET
DBC
00000016
Bank 016
FFFFFF16
FE000016
00FFFF16
01000016
01FFFF16
Bank FE16
00000016
00080016
0000FF16
00FFFE16
00FFC016
Internal RAM
4096 bytes
Internal flash memory
120 Kbytes
(User ROM area)
Peripheral devices
control registers
001FFF16
00200016
FEFFFF16
FF000016
0017FF16
00180016
00FFFF16
00FFC016
Bank 116
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bank FF16 Reserved area
for development
support tool
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
10
Fig. 2 Memory map of M37902FGMHP (Single-chip mode)
;;
;;
;;
INT
4
A-D conversion
Reserved area
Reserved area
Address matching detect
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Interrupt vector table
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
Watchdog timer
BRK instruction
Zero divide
INT
3
INT
2
INT
1
INT
0
NMI
RESET
DBC
000000
16
Bank 0
16
FFFFFF
16
FE0000
16
00FFFF
16
010000
16
01FFFF
16
Bank FE
16
000000
16
000800
16
0000FF
16
00FFFE
16
00FFC0
16
Internal RAM
6144 bytes
Internal flash memory
248 Kbytes
(User ROM area)
Peripheral devices
control registers
001FFF
16
002000
16
FEFFFF
16
FF0000
16
00FFFF
16
00FFC0
16
Bank 1
16
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bank FF
16
020000
16
02FFFF
16
Bank 2
16
030000
16
03FFFF
16
Bank 3
16
Reserved area
for development
support tool
11
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 7 Location of SFRs (1)
000000
16
000001
16
000002
16
000003
16
000004
16
000005
16
000006
16
000007
16
000008
16
000009
16
00000A
16
00000B
16
00000C
16
00000D
16
00000E
16
00000F
16
000010
16
000011
16
000012
16
000013
16
000014
16
000015
16
000016
16
000017
16
000018
16
000019
16
00001A
16
00001B
16
00001C
16
00001D
16
00001E
16
00001F
16
000020
16
000021
16
000022
16
000023
16
000024
16
000025
16
000026
16
000027
16
000028
16
000029
16
00002A
16
00002B
16
00002C
16
00002D
16
00002E
16
00002F
16
000030
16
000031
16
000032
16
000033
16
000034
16
000035
16
000036
16
000037
16
000038
16
000039
16
00003A
16
00003B
16
00003C
16
00003D
16
00003E
16
00003F
16
Port P2 register
Port P3 register
Port P1 direction register
Port P0 direction register
Port P1 register
Port P0 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P8 direction register
Port P10 register
Port P11 register
Port P10 direction register
Port P11 direction register
A-D control register 0
A-D control register 1
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
UART0 transmit/receive mode register
UART0 baud rate register (BRG0)
UART0 transmit buffer register
UART0 transmit/receive control register 1
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 baud rate register (BRG1)
UART1 transmit buffer register
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 receive buffer register
Address (Hexadecimal notation) 000040
16
000041
16
000042
16
000043
16
000044
16
000045
16
000046
16
000047
16
000048
16
000049
16
00004A
16
00004B
16
00004C
16
00004D
16
00004E
16
00004F
16
000050
16
000051
16
000052
16
000053
16
000054
16
000055
16
000056
16
000057
16
000058
16
000059
16
00005A
16
00005B
16
00005C
16
00005D
16
00005E
16
00005F
16
000060
16
000061
16
000062
16
000063
16
000064
16
000065
16
000066
16
000067
16
000068
16
000069
16
00006A
16
00006B
16
00006C
16
00006D
16
00006E
16
00006F
16
000070
16
000071
16
000072
16
000073
16
000074
16
000075
16
000076
16
000077
16
000078
16
000079
16
00007A
16
00007B
16
00007C
16
00007D
16
00007E
16
00007F
16
Address (Hexadecimal notation)
Count start register
One-shot start register
Timer A clock division select register
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Timer A1 mode register
Timer A0 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register 1
Watchdog timer register
Particular function select register 0
Particular function select register 1
Debug control register 0
INT
3
interrupt control register
UART0 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B2 interrupt control register
INT
1
interrupt control register
Watchdog timer frequency select register
Debug control register 1
INT
4
interrupt control register
UART1 transmit interrupt control register
Timer A2 interrupt control register
Timer B1 interrupt control register
INT
2
interrupt control register
Address comparison register 0
Address comparison register 1
Particular function select register 2
Reserved area (Note)
Note: Do not write to this address.
UART0 transmit/receive control register 0
Up-down register
Processor mode register 0
A-D conversion interrupt control register
UART0 receive interrupt control register
INT
0
interrupt control register
Reserved area (Note)
Reserved area (Note)
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
12
Fig. 8 Location of SFRs (2)
0000C0
16
0000C1
16
0000C2
16
0000C3
16
0000C4
16
0000C5
16
0000C6
16
0000C7
16
0000C8
16
0000C9
16
0000CA
16
0000CB
16
0000CC
16
0000CD
16
0000CE
16
0000CF
16
0000D0
16
0000D1
16
0000D2
16
0000D3
16
0000D4
16
0000D5
16
0000D6
16
0000D7
16
0000D8
16
0000D9
16
0000DA
16
0000DB
16
0000DC
16
0000DD
16
0000DE
16
0000DF
16
0000E0
16
0000E1
16
0000E2
16
0000E3
16
0000E4
16
0000E5
16
0000E6
16
0000E7
16
0000E8
16
0000E9
16
0000EA
16
0000EB
16
0000EC
16
0000ED
16
0000EE
16
0000EF
16
0000F0
16
0000F1
16
0000F2
16
0000F3
16
0000F4
16
0000F5
16
0000F6
16
0000F7
16
0000F8
16
0000F9
16
0000FA
16
0000FB
16
0000FC
16
0000FD
16
0000FE
16
0000FF
16
0000A0
16
0000A1
16
0000A2
16
0000A3
16
0000A4
16
0000A5
16
0000A6
16
0000A7
16
0000A8
16
0000A9
16
0000AA
16
0000AB
16
0000AC
16
0000AD
16
0000AE
16
0000AF
16
0000B0
16
0000B1
16
0000B2
16
0000B3
16
0000B4
16
0000B5
16
0000B6
16
0000B7
16
0000B8
16
0000B9
16
0000BA
16
0000BB
16
0000BC
16
0000BD
16
0000BE
16
0000BF
16
Real-time output control register
Pulse output data register 0
Pulse output data register 1
Serial I/O pin control register
000080
16
000081
16
000082
16
000083
16
000084
16
000085
16
000086
16
000087
16
000088
16
000089
16
00008A
16
00008B
16
00008C
16
00008D
16
00008E
16
00008F
16
000090
16
000091
16
000092
16
000093
16
000094
16
000095
16
000096
16
000097
16
000098
16
000099
16
00009A
16
00009B
16
00009C
16
00009D
16
00009E
16
00009F
16
Address (Hexadecimal notation)
CS
0
control register L
CS
0
control register H
CS
1
control register L
CS
1
control register H
CS
2
control register L
CS
2
control register H
CS
3
control register L
CS
3
control register H
Area CS
0
start address register
Area CS
1
start address register
Area CS
2
start address register
Area CS
3
start address register
Reserved area (Note)
Reserved area (Note)
Port function control register
External interrupt input control register
External interrupt input read-out register
D-A control register
D-A register 0
D-A register 1
D-A register 2
Flash memory control register
Note: Do not write to this address.
Clock control register
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Address (Hexadecimal notation)
Reserved area (Note)
Reserved area (Note)
13
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
FLASH MEMORY MODE
These microcomputers contain the DINOR (DIvided bit line NOR)-
type flash memory; and single-power-supply reprogramming is avail-
able to this. These microcomputers have the following three modes,
enabling reading/programming/erasure for the flash memory:
• Flash memory parallel I/O mode and Flash memory serial I/O
mode, where the flash memory is handled by using an external pro-
grammer.
• CPU reprogramming mode, where the flash memory is handled by
the central processing unit (CPU).
For each modes, refer to the datasheet M37902FCCHP.
Figures 9 and 10 shows the block configuration of the internal flash
memory of each microcomputer.
These microcomputers have the same functions as the
M37902FCCHP except for the following:
(1) Power supply voltage (3.3 V ± 0.3 V)
(2) Electrical characteristics
Therefore, for the flash memory mode except for the above, refer to
the datasheet M37902FCCHP.
Fig 9. M37902FCMHP: block configuration of internal flash memory
16 Kbytes
001FFF16
Boot ROM areaUser ROM area
32 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
01FFFF16
003FFF16
005FFF16
00600016
007FFF16
00FFFF16
01000016
00800016
00FFFF16
001FFF16
002FFF16
00300016
003FFF16
007FFF16
00800016
00400016
00200016
00400016
00100016
00200016
Byte Address Word Address 00000016
003FFF16
00000016
Byte Addresses Word Addresses
64 Kbytes
Total 120 Kbytes
Notes 1: In the flash memory mode, the read/programming/erase
operation cannot be performed for areas except for the
internal flash memory area.
2: The boot ROM area can be reprogrammed only in the
flash memory parallel I/O mode. When the boot ROM
area is read out by the CPU, these addresses are shifted
to addresses 00C00016–00FFFF16 (byte addresses).
3: The reserved area for the serial programmer is assigned
to addresses FFB016–FFBF16 (byte addresses). When
the flash memory serial I/O mode is used, do not
program to this area.
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
14
Fig 10. M37902FGMHP: block configuration of internal flash memory
Notes 1: In the flash memory mode, the read/programming/erase
operation cannot be performed for areas except for the
internal flash memory area.
2: The boot ROM area can be reprogrammed only in the
flash memory parallel I/O mode. When the boot ROM
area is read out by the CPU, these addresses are shifted
to addresses 00C000
16
–00FFFF
16
(byte addresses).
3: The reserved area for the serial programmer is assigned
to addresses FFB0
16
–FFBF
16
(byte addresses). When
the flash memory serial I/O mode is used, do not
program to this area.
16 Kbytes
001FFF
16
Boot ROM areaUser ROM area
32 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
01FFFF
16
003FFF
16
005FFF
16
006000
16
007FFF
16
00FFFF
16
010000
16
008000
16
00FFFF
16
001FFF
16
002FFF
16
003000
16
003FFF
16
007FFF
16
008000
16
004000
16
002000
16
004000
16
001000
16
002000
16
Byte Address Word Address
000000
16
003FFF
16
000000
16
Byte Addresses Word Addresses
64 Kbytes
Total 248 Kbytes
64 Kbytes
64 Kbytes
02FFFF
16
020000
16
017FFF
16
010000
16
03FFFF
16
030000
16
01FFFF
16
018000
16
15
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
AC Electrical Characteristics (VCC = 3.3 V ± 0.3 V, Ta = 0 to 60 °C, f(fsys) = 20 MHz (Note))
The limits of parameters other than the above are same as those in the microcomputer mode.
Note: f(fsys) indicates the system clock (fsys) frequency.
Parameter
Page programming time
Block erase time
Erase all unlocked block time
Lock bit programming time
Limits Unit
Min. Typ. Max.
8
50
50 ✕ n
8
120
600
600 ✕ n
120
ms
ms
ms
ms
n = Number of blocks to be erased
Symbol Parameter Limits Unit
Icc1
Icc2
Icc3
Icc4
Min. Typ. Max.
VCC power source current (at read)
VCC power source current (at write)
VCC power source current (at programming)
VCC power source current (at erasing)
19 40
40
48
48
DC Electrical Characteristics (VCC = 3.3 V ± 0.3 V, Ta = 0 to 60 °C, f(f sys) = 20 MHz (Note))
Limits of VIH, VIL, VOH, VOL, IIH, and IIL for each pin are the same as those in the microcomputer mode.
Note: f(fsys) indicates the system clock (fsys) frequency.
mA
mA
mA
mA
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
16
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
MHz
MHz
Max.
3.6
Vcc
VCC
Vcc
Vcc
Vcc
Vcc
Vcc
0.2 VCC
0.2 VCC
0.2 VCC
0.16 VCC
0.22 VCC
0.16 VCC
0.16 VCC
–10
–5
10
5
20
20
Parameter
Power source voltage
Analog power source voltage
Power source voltage
Analog power source voltage
High-level input voltage XIN, RESET, BYTE, MD0, MD1
High-level input voltage P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117
High-level input voltage P00–P07 (When the port P0 input level select bit = “0”)
High-level input voltage P00–P07 (When the port P0 input level select bit = “1”)
High-level input voltage D0–D7, D8–D15
High-level input voltage RDY, HOLD, TA0IN–TA4IN, TA0OUT–TA4OUT,
TB0IN–TB2IN, KI0–KI3, INT0–INT4, NMI, ADTRG, CTS0,
CTS1, CLK0, CLK1, RxD0, RxD1
High-level input voltage SCLK, SDA (Note 1)
Low-level input voltage XIN, RESET, BYTE, MD0, MD1
Low-level input voltage P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117
Low-level input voltage P00–P07 (When the port P0 input level select bit = “0”)
Low-level input voltage P00–P07 (When the port P0 input level select bit = “1”)
Low-level input voltage D0–D7, D8–D15
Low-level input voltage RDY, HOLD, TA0IN–TA4IN, TA0OUT–TA4OUT,
TB0IN–TB2IN, KI0–KI3, INT0–INT4, NMI, ADTRG, CTS0,
CTS1, CLK0, CLK1, RxD0, RxD1
Low-level input voltage SCLK, SDA (Note 1)
High-level peak output current P00–P07, P10–P17, P20–P27, P30–P33, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87,
P100–P107, P110–P117
High-level average output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
Low-level peak output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
Low-level average output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
External clock input frequency (Note 2)
System clock frequency
Symbol
VCC
AVCC
VSS
AVSS
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
VIL
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
f(XIN)
f(fsys)
Parameter
Power source voltage
Analog power source voltage
Input voltage P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117,
VREF, XIN, RESET, BYTE, MD0, MD1, NMI, VCONT
Output voltage P00–P07, P10–P17, P20–P27, P30–P33, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87, P100–P107,
P110–P117, XOUT
Power dissipation
Operating ambient temperature
Storage temerature
Symbol
VCC
AVCC
VI
VO
Pd
Topr
Tstg
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS (Vcc = 3.3 V, Ta = –20 to 85 °C, unless otherwise noted)
Notes 1: Pins SCLK and SDA are used only in the flash memory serial I/O mode.
2: When using the PLL frequency multiplier, be sure that f(fsys) = 20 MHz or less.
3: Average output current is the average value of an interval of 100 ms.
4: The sum of IOL(peak) for ports P0–P2, P8, P10, and P11 must be 80 mA or less, the sum of IOH(peak) for ports P0–P2, P8, P10, and P11 must be 80
mA or less, the sum of IOL(peak) for ports P3–P7 must be 80 mA or less, the sum of IOH(peak) for ports P3–P7 must be 80 mA or less.
Unit
V
V
V
V
mW
°C
°C
Ratings
–0.3 to 4.6
–0.3 to 4.6
–0.3 to VCC+0.3
–0.3 to VCC+0.3
400
–20 to 85
–40 to 150
Limits
Min.
3.0
0.8 Vcc
0.7 VCC
0.7 Vcc
0.5 Vcc
0.5 Vcc
0.5 Vcc
0.5 Vcc
0
0
0
0
0
0
0
Typ.
3.3
VCC
0
0
17
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Unit
V
V
V
V
V
V
V
V
µ
A
f(fsys) = 20 MHz.
CPU operates.
Ta = 25 °C when
clock is stopped.
Ta = 85 °C when
clock is stopped.
Test conditions
IOH = –1 mA
IOH = –1 mA
IOL = 1 mA
IOL = 1 mA
VI = 3.3 V
VI = 0 V
VI = 0 V, No pullup transistor
VI = 0 V, Pullup transistor used
When clock is stoped.
Parameter
High-level output voltage P00–P07, P10–P17,
P20–P27, P30, P40–P47,
P50–P57, P60–P67,
P70–P77, P80–P87,
P100–P107, P110–P117
High-level output voltage P31–P33
Low-level output voltage P00–P07, P10–P17,
P20–P27, P30, P40–P47,
P50–P57, P60–P67,
P70–P77, P80–P87,
P100–P107, P110–P117
Low-level output voltage P31–P33
Hysteresis RDY, HOLD, TA0IN–TA4IN,
TA0OUT–TA4OUT, TB0IN–TB2IN,
KI0–KI3, INT0–INT4, NMI, ADTRG,
CTS0, CTS1, CLK0, CLK1, RxD0, RxD1
Hysteresis RESET
Hysteresis XIN
High-level input current
P00–P07, P10–P17,
P2
0
–P2
7
, P3
0
–P3
3
, P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
0
–P7
7
,
P80–P87, P100–P107,
P110–P117, XIN, RESET,
BYTE, MD0, MD1, NMI
Low-level input current
P00–P07, P10–P17,
P2
0
–P2
7
, P3
0
–P3
3
, P4
0
–P4
3
,
P5
0
–P5
3
, P6
0
–P6
7
, P7
0
–P7
7
,
P80–P87, P100–P107,
P110–P117, XIN, RESET,
BYTE, MD0, MD1
Low-level input current
P4
4
–P4
7
,
P54–P57, NMI
RAM hold voltage
Power source current
Symbol
VOH
VOH
VOL
VOL
VT+ —VT–
VT+ —VT–
VT+ —VT–
IIH
IIL
IIL
VRAM
ICC
Min.
2.5
2.6
0.08
Limits
Typ.
–0.36
12
Max.
0.5
0.4
0.5
1
0.26
4
–4
–4
–0.54
24
1
20
Output-only pins
are open, and the
other pins are con-
nected to Vss or
Vcc. An external
square-waveform
clock is input. (Pin
X
OUT
is open.) The
PLL frequency
multiplier stops its
operation.
DC ELECTRICAL CHARACTERISTICS (Vcc = 3.3 V, Vss = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz (Note))
–0.20
2
0.3
0.05
µ
A
mA
V
mA
µ
A
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
18
Resolution
Absolute accuracy
Ladder resistance
Conversion time
Reference voltage
Analog input voltage
—————
—————
RLADDER
tCONV
VREF
VIA
VREF = VCC
VREF = VCC
VREF = VCC
f(fsys) ≤ 20 MHz
Max.
A-D CONVERTER CHARACTERISTICS
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
UnitParameterSymbol Test conditions Limits
Min.
10-bit resolution mode
8-bit resolution mode
10-bit resolution mode
8-bit resolution mode
5
5.90
2.45 (Note)
2.7
0
10
± 3
± 2
VCC
VREF
Bits
LSB
LSB
kΩ
µ
s
V
V
Note: This is applied when A-D conversion freguency (
φ
AD) = f1.
D-A CONVERTER CHARACTERISTICS
(VCC = 3.3 V, VSS = AVSS = 0 V, VREF = 3.3 V, Ta = –20 to 85 °C, unless otherwise noted)
UnitParameterSymbol Limits
Typ.Min. Max.
Test conditions
Resolution
Absolute accuracy
Set time
Output resistance
Reference power source input current
——
——
tsu
RO
IVREF (Note) 1 2.5
8
± 1.0
3
4
3.2
Bits
%
µ
s
kΩ
mA
Note: The test conditions are as follows:
• One D-A converter is used.
• The D-A register value of the unused D-A converter is “0016.”
• The reference power source input current for the ladder resistance of the A-D converter is excluded.
µ
s
RESET input low-level pulse width
tw(RESETL)
Symbol Parameter Min. Limits Unit
RESET INPUT
Reset input timing requirements (VCC = 3.3 V ± 0.3 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
2
Max.Typ.
RESET input t
w(RESETL)
19
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
tc(TA)
tw(TAH)
tw(TAL)
f(fsys)
≤
20 MHz
f(fsys)
≤
20 MHz
f(fsys)
≤
20 MHz
PERIPHERAL DEVICE INPUT/OUTPUT TIMING
(VCC = 3.3 V±0.3 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz unless otherwise noted)
∗For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(fsys) = 20 MHz are shown in ( ).
Timer A input (Up-down input and Count input in event counter mode)
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
Symbol
TAiOUT input cycle time
TAiOUT input high-level pulse width
TAiOUT input low-level pulse width
TAiOUT input setup time
TAiOUT input hold time
Parameter Limits
Min.
2000
1000
1000
400
400
Max. ns
ns
ns
ns
ns
Unit
Timer A input (External trigger input in pulse width modulation mode)
tw(TAH)
tw(TAL)
Symbol
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Parameter Min.
80
80
Limits Max. ns
ns
Unit
Limits
Symbol Parameter Min. Max. Unit
8 × 109
f(fsys)(400)
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
ns
ns
ns
80
80
Timer A input (External trigger input in one-shot pulse mode)
Limits
Symbol Parameter Min. Max. Unit
16 × 109
f(fsys)
8 × 109
f(fsys)
8 × 109
f(fsys)
(800)
(400)
(400)
tc(TA)
tw(TAH)
tw(TAL)
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
ns
ns
ns
Timer A input (Gating input in timer mode)
Note :The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys)
≤
20 MHz.
Timer A input (Count input in event counter mode)
tc(TA)
tw(TAH)
tw(TAL)
Symbol
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Parameter Min.
80
40
40
Limits Max. ns
ns
ns
Unit
f(fsys) ≤ 20 MHz
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
20
tc(TA)
tsu(TAjIN-TAjOUT)
tsu(TAjOUT-TAjIN)
Symbol Parameter Min.
800
200
200
Limits Max. ns
ns
ns
Unit
Timer A input (Two-phase pulse input in event counter mode)
TAiIN input cycle time
TAjIN input setup time
TAjOUT input setup time
TAi
IN
input
TAi
OUT
input
(Up-down input)
TAi
OUT
input
(Up-down input)
TAi
IN
input
(When count by falling)
TAi
IN
input
(When count by rising)
TAj
IN
input
TAj
OUT
input
Test conditions
• V
CC
= 3.3 V±0.3 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
= 0.53 V, VIH = 1.65 V
• Up-down and Count input in event counter mode
• Two-phase pulse input in event counter mode
• Gating input in timer mode
• Count input in event counter mode
• External trigger input in one-shot pulse mode
• External trigger input in pulse width modulation mode tc
(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
h(T
IN
-UP)
t
su(TAj
IN
-TAj
OUT
)
t
su(TAj
IN
-TAj
OUT
)
t
su(TAj
OUT
-TAj
IN
)
t
su(TAj
OUT
-TAj
IN
)
t
c(TA)
t
su(UP-T
IN
)
21
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
f(fsys) ≤ 20 MHz
f(fsys) ≤ 20 MHz
f(fsys) ≤ 20 MHz
f(fsys) ≤ 20 MHz
f(fsys) ≤ 20 MHz
f(fsys) ≤ 20 MHz
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Timer B input (Count input in event counter mode)
Symbol
TBiIN input cycle time (one edge count)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edge count)
TBiIN input high-level pulse width (both edge count)
TBiIN input low-level pulse width (both edge count)
Parameter Limits
Min.
80
40
40
160
80
80
Max. ns
ns
ns
ns
ns
ns
Unit
Limits
Symbol Parameter Min. Max. Unit
16 × 109
f(fsys)
8 × 109
f(fsys)
8 × 109
f(fsys)
(800)
(400)
(400)
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input cycle time
TBiIN input high-level pulse width
TBiIN input low-level pulse width
ns
ns
ns
Timer B input (Pulse period measurement mode)
Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz.
Limits
Symbol Parameter Min. Max. Unit
16 × 109
f(fsys)
8 × 109
f(fsys)
8 × 109
f(fsys)
(800)
(400)
(400)
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input cycle time
TBiIN input high-level pulse width
TBiIN input low-level pulse width
ns
ns
ns
Timer B input (Pulse width measurement mode)
Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz.
tc(AD)
tw(ADL)
Symbol
ADTRG input cycle time (minimum allowable trigger)
ADTRG input low-level pulse width
Parameter Min.
1000
125
Limits Max. ns
ns
Unit
A-D trigger input
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
22
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Serial I/O
Symbol
CLKi input cycle time
CLKi input high-level pulse width
CLKi input low-level pulse width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Parameter Limits
Min.
200
100
100
0
20
90
Max.
80
ns
ns
ns
ns
ns
ns
ns
Unit
tw(INH)
tw(INL)
Symbol
INTi input/NMI input/KIi input high-level pulse width
INTi input/NMI input/KIi input low-level pulse width
Parameter Min.
250
250
Limits Max. ns
ns
Unit
External interrupt (INTi) input, NMI input, Key input interrupt (KIi) input
tc(TB)
tw(TBH)
tw(TBL)
tc(CK)
tw(CKH)
tw(CKL) th(C - Q)
td(C - Q) tsu(D - C)
tw(INH)
tw(INL)
th(C - D)
tc(AD)
tw(ADL)
TBiIN input
INTi input,
ADTRG input
CLKi input
TxDi output
RxDi input
NMI input,
KIi input
Test conditions
• Vcc = 3.3 V±0.3 V, Ta = –20 to 85°C
• Input timing voltage : VIL = 0.53 V, VIH = 1.65 V
•Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF
23
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
td(
φ
1-HLDAL)
td(RDH-HLDAL)
t
d(BXWH-HLDAL)
t
pxz(HLDAL-RDZ)
t
pxz(HLDAL-BXWZ)
t
pxz(HLDAL-CSiZ)
t
pxz(HLDAL-ALEZ)
tpxz(HLDAL-AZ)
t
pzx(HLDAL-RDZ)
t
pzx(HLDAL-BXWZ)
t
pzx(HLDAL-CSiZ)
t
pzx(HLDAL-ALEZ)
tpzx(HLDAL-AZ)
tsu(RDY-
φ
1)
tsu(HOLD-
φ
1)
th(
φ
1-RDY)
th(
φ
1-HOLD)
Symbol
RDY input setup time
HOLD input setup time
RDY input hold time
HOLD input hold time
Parameter Limits
Min.
40
40
0
0
Max. ns
ns
ns
ns
Unit
Switching characteristics (VCC = 3.3 V±0.3 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz, unless otherwise noted)
Symbol
HLDA output delay time
HLDA low-level output delay time after read
HLDA low-level output delay time after write
Floating start delay time
Floating start delay time
Floating start delay time
Floating start delay time
Floating start delay time
Floating release delay time
Floating release delay time
Floating release delay time
Floating release delay time
Floating release delay time
Parameter Min.
tc –15 (Note)
tc –15 (Note)
–15
–15
–15
–15
–15
0
0
0
0
0
Limits Max.
20
10
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Note: tc = 1/f(fsys).
READY, HOLD TIMING
Timing requirements (VCC = 3.3 V±0.3 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz, unless otherwise noted)
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
24
φ1
RDY input
t
su (RDY-φ1)
RD,
BLW,
BHW
: Wait inserted by software (The above is applied when bus cycle = 1φ + 2φ)
: Wait inserted by ready function
RDY input
t
h (φ1-RDY)
Test conditions
• V
CC
= 3.3 V ± 0.3 V, Ta= –20 to 85 °C
• RDY input, HOLD input:V
IL
= 0.53 V, V
IH
= 1.65 V
• HLDA output : V
OL
= 0.8V, V
OH
= 2.0 V, C
L
= 50 pF
φ1
HOLD input
t
su (HOLD-φ1)
t
d (φ1-HLDAL)
t
pxz (HLDAL-RDZ)
t
pxz (HLDAL-BXWZ)
t
pxz (HLDAL-CSiZ)
t
pxz (HLDAL-AZ)
t
h (φ1-HOLD)
t
d (φ1-HLDAL)
t
pzx (HLDAL-RDZ)
t
pzx (HLDAL-BXWZ)
t
pzx (HLDAL-CSiZ)
t
pzx (HLDAL-ALEZ)
t
pzx (HLDAL-AZ)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
HOLD input
HLDA output
RD
BLW
BHW
CSi
A0–A23 output
t
d (RDH-HLDAL)
t
d (BXWH-HLDAL)
t
pxz (HLDAL-ALEZ)
ALE
25
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
tc(in)
tw(half)
tw(H)
tw(L)
tr
tf
ta(A-D)
ta(A-D)
ta(CSiL-D)
ta(RDL-D)
tsu(D-RDL)
th(RDH-D)
ta(BA-D)
th(BA-D)
ta(LA-D)
Max.
0.55 tc
(WH + WL) tc-45
(WH + WL-0.5) tc-35
(WH + WL-0.5) tc-35
WL ✕ tc-30
WL ✕ tc-35
Min.
50
0.45 tc
0.5 tc – 6
0.5 tc – 6
6
6
15
0
8
(W
H
+ W
L
-0.5)tc-35 (Note)
External clock input cycle time
External clock input pulse width with half input-volage
External clock input high-level pulse width
External clock input low-level pulse width
External clock input rise time
External clock input fall time
Address access time (the address output select bit = 0)
Address access time (the address output select bit = 1)
Chip select access time
Read access time
Read data setup time
Data input hold time after read
Address access time at burst ROM access
Data hold time after address at burst ROM access
Address access time (the multiplexed bus select bit = 1)
1
φ
+1
φ
1
φ
+2
φ
1
φ
+3
φ
2
φ
+2
φ
Limits
External bus timing
For limits depending on f(fsys), their calculation formulas are shown below.
Symbol Parameter
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
External clock input trtf
tw(L) tw(H) tw(half)
XIN
tc(in)
Test conditions
• Vcc = 3.3 V ± 0.3 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 0.66 V, VIH = 2.64 V (tw(H), tw(L), tr, tf)
• Output timing voltage : 1.65 V (tc(in), tw(half))
Bus cycle WHWL
1
1
1
2
1
2
3
2
Bus cycle WHWL
2
φ
+3
φ
2
φ
+4
φ
3
φ
+3
φ
3
φ
+4
φ
2
2
3
3
3
4
3
4
tc = 1/f(fsys).
Timing Requirements (VCC = 3.3 V±0.3 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted)
Note: This is independent of the value of the address output select bit’s contents.
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
26
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bus cycle = 2φ + 2φ
Bus cycle = 3φ + 3φ, 3φ + 4φ
td(φ1-RDL)
td(φ1-RDH)
td(φ1-BXWL)
td(φ1-BXWH)
td(φ1L-CSiL)
td(φ1L-CSiH)
td(φ1H-A)
td(φ1L-A)
tw(ALEH)
td(A-ALEL)
tw(RDL)
tw(RDH)
td(RDH-BXWH)
td(A-RDH)
td(A-RDH)
th(RDH-A)
th(RDH-A)
td(RDH-ALEL)
td(ALEL-RDH)
td(CSiL-RDH)
td(CSiL-RDL)
th(RDH-CSiL)
td(RDH-D)
tw(BXWL)
tw(BXWH)
td(BXWH-RDH)
td(A-BXWH)
td(A-BXWH)
th(BXWH-A)
th(BXWH-A)
td(BXWH-ALEL)
td(ALEL-BXWH)
td(CSiL-BXWH)
td(CSiL-BXWL)
th(BXWH-CSiL)
td(D-BXWL)
th(BXWH-D)
tpxz(BXWH-DZ)
Parameter
Switching characteristics (VCC = 3.3 V±0.3 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz, unless otherwise noted)
Max.
0
0
0
0
0
10
25
16
20
20
0.5tc + 10
Min.
–18
–18
–18
–18
–20
–22
–5
–20
0.5tc-19
tc-20
1.5tc-20
tc-30
1.5tc-30
2tc-30
0.5tc-19
tc-20
1.5tc-20
WL ✕ tc-15
WH ✕ tc-15
tc-15
WH ✕ tc-30
(WH-0.5)tc-19
8
0.5tc-10
0.5tc-19
tc-15
(WH-0.5)tc-19
(W
H
+ W
L
-0.5)tc-20
0.5tc-14
tc-15
WL ✕ tc-15
WH ✕ tc-15
tc-15
WH ✕ tc-30
(WH-0.5)tc-19
8
0.5tc-10
0.5tc-19
tc-15
(WH-0.5)tc-19
(WH + WL-0.5)tc-20
0.5tc-14
WL ✕ tc-20
0.5tc-10
Read low-level output delay time
Read high-level output delay time
Write low-level output delay time
Write high-level output delay time
Chip select low-level output delay time
Chip select high-level output delay time
Address output delay time (the address output select bit = 0)
Address output delay time (the address output select bit = 1)
ALE pulse width
ALE completion delay time
after address stabilization
(when the address output
select bit = 0)
ALE completion delay time
after address stabilization
(when the address output
select bit = 1)
Read output pulse width
Read output high-level width (Note 1)
Write disable valid time after read (Note 2)
Address valid time before read (when the address output select bit = 0)
Address valid time before read (when the address output select bit = 1)
Address hold time after read (when the address output select bit = 0) (Note 2)
Address hold time after read (when the address output select bit = 1) (Note 2)
ALE completion delay time after read start
Read disable valid time
after ALE completion
Limits
Symbol Unit
Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Notes 1:
When the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.).
2:
When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.).
3: This parameter is extended by tc (ns) when both of the following conditions are satisfied:
• When accessing the area where the recovery cycle insertion is selected.
• When two recovery cycles are inserted.
Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Chip select valid time before read
Chip select output valid time before read completion
Chip select hold time after read
Next write cycle data output delay time after read (Note 2)
Write output pulse width
Write output high-level width (Note 1)
Read disable valid time after write (Note 2)
Address valid time before write (when the address output select bit = 0)
Address valid time before write (when the address output select bit = 1)
Address hold time after write (when the address output select bit = 0) (Note 2)
Address hold time after write (when the address output select bit = 1) (Note 2)
ALE completion delay time after write start
Write disable valid time
after ALE completion
Chip select valid time before write
Chip select output valid time before write completion
Chip select hold time after write
Data output valid time before write completion
Data hold time after write (Note 3)
Floating start delay time after write (Note 3)
27
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
td(LA-RDH)
td(LA-ALEL)
th(ALEL-LA)
tpxz(RDH-LAZ)
td(LA-BXWH)
tpzx(RDH-DZ)
Address valid time before read
ALE completion delay time
after address stabilization
Address hold time after
ALE completion
Floating start delay time
Address valid time before write
Floating release delay time
Bus cycle = 2φ + 2φ
Bus cycle = 3φ + 3φ, 3φ + 4φ
Bus cycle = 2φ + 2φ
Bus cycle = 3φ + 3φ, 3φ + 4φ
Switching characteristics (VCC = 3.3 V±0.3 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz, unless otherwise noted)
Parameter Max.
5
Min.
(W
H
-0.5)tc-19 (Note)
tc-20 (Note)
1.5tc-20 (Note)
0.5tc-19
tc-15
(W
H
-0.5)tc-19 (Note)
0.5tc-19 (Note)
Limits
Symbol
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Note: This is independent of the address output select bit’s contents.
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
28
Bus cycle
t
h(RDH-D)
t
h(RDH-A)
t
w(RDL)
t
a(CSiL-D)
t
a(RDL-D)
t
a(A-D)
t
d(CSiL-RDL)
t
su(D-RDL)
t
w(ALEH)
t
d(RDH-ALEL)
t
c
t
d(A-ALEL)
t
w(RDH)
t
d(RDH-D)
t
d(φ1-RDL)
t
h(RDH-A)
t
d(A-RDH)
t
d(CSiL-RDH)
t
a(A-D)
t
d(A-ALEL)
t
d(φ1H-A)
t
d(φ1L-A)
t
d(φ1L-CSiL)
t
d(φ1L-CSiH)
t
d(φ1-RDH)
t
h(RDH-CSiL)
t
d(RDH-BXWH)
t
d(A-RDH)
CS
i
RD
ALE
φ
1
f
sys
BLW
BHW
<At read>
Normal access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ+ 3φ,
2φ + 3φ, or 2φ + 4φ
A
0
–A
23
(when the address output select bit = 0)
A
0
–A
23
(when the address output select bit = 1)
D
0
–D
7
, D
8
–D
15
Test conditions
• V
CC
= 3.3 V ±0.3 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
=0.53 V, V
IH
=1.65 V
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=15 pF (CS
i
)
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=50 pF (except for CS
i
)
29
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
th(BXWH-A)
td(CSiL-BXWL)
tw(BXWL)
td(BXWH-ALEL)
td(D-BXWL) th(BXWH-D)
tpxz(BXWH-DZ)
Bus cycle
td(φ1-BXWL)
th(BXWH-A)
td(A-BXWH)
td(CSiL-BXWH)
tc
td(A-ALEL)
tw(ALEH)
td(φ1H-A)
td(φ1L-CSiL) td(φ1L-CSiH)
td(BXWH-RDH)
td(φ1-BXWH)
th(BXWH-CSiL)
td(A-ALEL)
tw(BXWH)
td(A-BXWH)
td(φ1L-A)
CS
i
RD
ALE
BLW
BHW
φ
1
f
sys
<At write>
Normal access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ,
2φ + 3φ, or 2φ + 4φ
A
0
–A
23
(when the address output select bit = 0)
A
0
–A
23
(when the address output select bit = 1)
D
0
–D
7
, D
8
–D
15
Test conditions
• VCC = 3.3 V ±0.3 V, Ta = –20 to 85 °C
• Input timing voltage : VIL=0.53 V, VIH=1.65 V
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, C
L
=15 pF (CSi)
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, C
L
=50 pF (except for CSi)
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
30
t
d(A-RDH)
Bus cycle
t
d(CSiL-RDL)
t
d(A-ALEL)
t
h(RDH-D)
t
h(RDH-A)
t
w(RDL)
t
a(CSiL-D)
t
a(RDL-D)
t
a(A-D)
t
su(D-RDL)
t
w(ALEH)
t
c
t
w(RDH)
t
d(RDH-D)
t
d(ALEL-RDH)
t
d(φ1-RDL)
t
d(φ1-RDH)
t
h(RDH-D)
t
a(LA-D)
t
a(RDL-D)
t
d(LA-RDH)
t
su(D-RDL)
t
pzx(RDH-DZ)
t
d(LA-ALEL)
t
h(ALEL-LA)
t
pxz(RDH-LAZ)
t
h(RDH-A)
t
d(A-RDH)
t
d(CSiL-RDH)
t
a(A-D)
Address Input data Address
t
d(φ1H-A)
t
d(φ1L-CSiL)
t
d(φ1L-CSiH)
t
d(RDH-BXWH)
t
h(RDH-CSiL)
t
d(A-ALEL)
t
d(φ1L-A)
CS
i
RD
ALE
BLW
BHW
fsys
φ
1
Note: Valid only when area CS2 is accessed with the external data bus width = 8 bits.
<At read>
Normal access: bus cycle = 2φ + 2φ, 3φ + 3φ, 3φ + 4φ
A0–A23
(when the address output
select bit = 0)
D0–D7, D8–D15
(when the multiplexed
bus select bit = 0)
LA0/D0–LA7/D7
(when the multiplexed
bus select bit = 1, Note)
A0–A23
(when the address output
select bit = 1)
Test conditions
• V
CC
= 3.3 V ±0.3 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
=0.53 V, V
IH
=1.65 V
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, CL=15 pF (CS
i
)
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, CL=50 pF (except for CS
i
)
31
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
t
d(CSiL-BXWL)
t
h(BXWH-A)
t
d(A-BXWH)
t
w(ALEH)
t
w(BXWL)
t
d(D-BXWL)
t
h(BXWH-D)
t
pxz(BXWH-DZ)
t
d(A-ALEL)
t
w(BXWH)
t
d(ALEL-BXWH)
Bus cycle
t
d(φ1-BXWL)
t
h(BXWH-D)
t
pxz(BXWH-DZ)
t
d(D-BXWL)
t
h(ALEL-LA)
t
d(LA-ALEL)
t
d(LA-BXWH)
t
c
t
h(BXWH-A)
t
d(A-BXWH)
t
d(CSiL-BXWH)
Address Output data
t
d(φ1-BXWH)
t
d(φ1H-A)
t
d(φ1L-CSiL)
t
d(φ1L-CSiH)
t
d(A-ALEL)
t
h(BXWH-CSiL)
t
d(BXWH-RDH)
t
d(φ1L-A)
CS
i
RD
ALE
BLW
BHW
f
sys
φ
1
Note: Valid only when area CS
2
is accessed with the external data bus width = 8 bits.
<At write>
Normal access: bus cycle = 2φ + 2φ, 3φ + 3φ, 3φ + 4φ
A
0
–A
23
(when the address output
select bit = 0)
D
0
–D
7
, D
8
–D
15
(when the multiplexed
bus select bit = 0)
LA
0
/D
0
–LA
7
/D
7
(when the multiplexed
bus select bit = 1, Note)
A
0
–A
23
(when the address output
select bit = 1)
Test conditions
• V
CC
= 3.3 V ±0.3 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
=0.53 V, V
IH
=1.65 V
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=15 pF (CS
i
)
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=50 pF (except for CS
i
)
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
32
t
h(BA-D)
t
d(RDH-BXWH)
BLW
BHW
RD
t
a(RDL-D)
t
d(A-RDH)
CS
i
t
h(RDH-A)
t
a(CSiL-D)
t
a(A-D)
t
a(BA-D)
t
h(BA-D)
t
h(BA-D)
t
h(RDH-D)
t
a(BA-D)
t
a(BA-D)
t
h(RDH-CSiL)
t
d(CSiL-RDH)
t
d(A-ALEL)
t
w(ALEH)
ALE
t
d(RDH-ALEL)
t
w(RDH)
t
d(A-RDH)
t
h(RDH-A)
t
a(A-D)
Burst ROM access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, 2φ + 3φ, 2φ + 4φ
D
0
–D
7
, D
8
–D
15
Test conditions
• V
CC
= 3.3 V±0.3 V, Ta = –20 to 85°C
• Input timing voltage : V
IL
=0.53 V, V
IH
=1.65 V
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=15 pF (CS
i
)
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=50 pF (except for CS
i
)
A
0
–A
23
(when the address output select bit = 0)
A
0
–A
23
(when the address output select bit = 1)
t
d(A-ALEL)
M37902FCMHP, M37902FGMHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PACKAGE OUTLINE
LQFP100-P-1414-0.50 Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225 ––
I
2
1.0 ––
M
D
14.4 ––
M
E
14.4
10°0°0.1
1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4
01.7
e
e
e
E
c
H
E
1
76
75
51
50
26
25
H
D
D
M
D
M
E
A
F
b
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
100
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit
application examples contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to
change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these
inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
• When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making
a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 2000 MITSUBISHI ELECTRIC CORP.
New publication, effective Jun., 2000.
Specifications subject to change without notice.
Keep safety first in your circuit designs!
•Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Rev. Rev.
No. date
1.0 First Edition 990305
2.0 Refer to Corrections and Supplementary Explanation for “M37902FxM Datasheet (REV.A)”. 990625
3.0 The following are revised/added points in this edition: 990917
• Page 20; RECOMMENDED OPERATING CONDITIONS
<Error>
f(fsys) External clock input frequency (Note 2) •••••••••••
<Correction>
f(XIN) External clock input frequency (Note 2) •••••••••••
• Page 21; the maximum value of ICC is revised.
<Error> Ta = 25 °C when clock is stopped : —
Ta = 85 °C when clock is stopped : —
<Correction> Ta = 25 °C when clock is stopped : 1
Ta = 85 °C when clock is stopped : 20
4.0 Refer to Corrections and Supplementary Explanation for “M37902FxM Datasheet (REV.B)”. 000609
Notes 1: ★ represents the new information added in Rev.4.0.
2: The revised/added points informed in Rev.3.0 are included in Corrections and
Supplementary Explanation for “M37902FxM Datasheet (REV.B)”.
Revision History M37902FxMHP Datasheet
(1/1)
Revision Description
Corrections and
Supplement
ar
y
Explanation
for M37902FxM Dat
asheet
(
REV.
B) NO.1
Page Erro
r Correction
(1/5)
Page 3
,
B
LO
C
K
DIAGRA
M
,
No
t
e
:
Note: R
AM
2048 bytes
4096 bytes
6144 bytes
6144 bytes
12288 bytes
12288 bytes
M37902F8MHP
M37902FCMHP
M37902FEMHP
M37902FGMHP
M37902FHMHP
M37902FJMHP
Flash memory
60 Kbytes
120 Kbytes
184 Kbytes
248 Kbytes
370 Kbytes
498 Kbytes
Note: RAM
4096 bytes
6144 bytes
M37902F
C
MHP
M37902FGMHP
Flash memory
120 Kbytes
248 Kbytes
Pa
ge 4
,
Ch
ip-selec
t
wait control
★All pages,
Heade
r
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(Deleted)
P63/
INT2 P64/
INT2
Page 2,
PIN
CONFIGURATION
★
M37902F8MHP
,
M37902F
M
H
P,
M37902F
EMHP,
M37902FGMHP, M
37
902FHMHP
,
M37902FJMHP M37902F
C
M
HP
,
M37902F
G
MHP
[M
379
02F8MHP]
Fl
ash
memor
y (User
R
O
M ar
ea
)
..
....
....
...
....
....
.60 Kbytes
RA
M
...
....
....
....
...
....
....
....
...
....
....
....
....
...
....
....
....
.2048 bytes (Deleted)
[M
379
02FEMHP
]
Fl
ash
memor
y (User
R
O
M ar
ea
)
..
....
....
...
....
...184 Kbytes
RA
M
...
....
....
....
...
....
....
....
...
....
....
....
....
...
....
....
....
.6144 bytes (Deleted)
[M
379
02FHMHP
]
Fl
ash
memor
y (User
R
O
M ar
ea
)
..
....
....
...
....
...370 Kbytes
RA
M
...
....
....
....
...
....
....
....
...
....
....
....
....
...
....
....
...12288 byt
e
s(Deleted)
[M37902FJMHP]
Flash memory (User ROM area) ....................498 Kbytes
RAM...............................................................12288 bytes (Deleted)
Page 1,
DISTI
N
CTI
VE
FEAT
U
RES
;
M
emor
y
★
The fastest instruction at 26 MHz frequency .............38 ns The fastest instruction at 20 MHz frequency .............50 n
s
Page 1,
DISTI
N
CTI
VE
FEAT
U
RES
;
Instruction
execution t
i
m
e
★
Page 1,
APPLICATION
ontrol devices for personal computer peripheral equip-
ment such as CD-ROM drives, DVD-ROM drives, hard
disk drives, high density FDD, printers
Control devices for office equipment such as copiers and
facsimiles
Control devices for industrial equipment such as commu-
nication and measuring instruments
C
ontrol devices for personal computer peripheral equip-
ment such as CD-ROM drives, DVD-ROM drives, hard
disk drives, high density FDD, printers
★
M37902F8MHP
M37902FCMHP
M37902FEMHP
M37902FGMHP
M37902FHMHP
M37902FJMHP
M37902F
C
MHP
M37902FGMHP
(Type) (Type)
★
C
hi
p
sel
ect
area ✕ 4 (
C
S0–
C
S3)
. A wai
t
number
an
d
bus width can be set
for each
ch
ip select ar
ea.
C
hip select area ✕ 4 (
C
S0–
C
S3). A bus cycle type
and bus width can be set for each chip select area.
Pa
ge 4
,
I
nstruction
executio
n
time
38 ns (the fastest instruction at f(fsys) = 26 MHz) 50 ns (the fastest instruction at f(fsys) = 20 MHz)
Pa
ge 4
,
Ext
ern
al clock
inp
ut
frequency
f(XIN),
System clock
f
req
uency
fsys
26 M
H
z
(Max.
) 20 MHz (Max.)
★
★
Corrections and
Supplement
ar
y
Explanation
for M37902FxM Dat
asheet
(
REV.
B) NO.2
Page
Page 9,
Fig. 1
Erro
r Correction
(2/5)
00FF
C016
Internal
f
l
ash memory
120 Kbytes
(User ROM area)
00FFFF16
00200016
00FFC016
Internal
f
l
ash memory
120 Kbytes
(User ROM area)
00FFFF16
00200016
Pa
ge 4
,
Operating
temperatur
e
rang
e
★
Page 6,
P40–P4
7
•••••••••••••••
■ In microprocessor mode
•••••••• According to the register setting, P40–P44
also ••••••••••
•••••••••••••••
■ In microprocessor mode
•••••••• According to the register setting, P40–P43
also ••••••••••
★
Operating temperature rang
eOperating ambi
ent
temper
at
u
re
r
ange
Pa
ge 4
,
Powe
r
dissi
pation
★51.5 m
W (at
f(
fsys)
= 26 MHz,
T
yp.
, ••••• 39.6 mW (at f(fsys) = 20 MHz, Typ., •••••
Page 4,
No
t
e: Note:
RAM 2048 bytes
4096 bytes
6144 bytes
6144 bytes
12288 bytes
12288 bytes
M37902F8MH
P
M37902FC
MHP
M37902FEMH
P
M37902FGMHP
M37902FH
MHP
M37902FJMH
P
Flash memory
(User ROM
area)
60 Kbytes
120 Kbytes
184 Kbytes
248 Kbytes
370 Kbytes
498 Kbytes
M37902F8MH
P
M37902FCMHP
M37902FEMHP
M37902FGMHP
M37902FHMHP
M37902FJMHP
Note:
RAM 4096 bytes
M37902F
C
MH
P
Flash memory
(User ROM
area)
120 Kbytes
M37902F
C
MH
P
M37902F
G
MH
P
M37902F
G
MH
P
248 Kbytes
6144 bytes
★
Page 5,
N
ot
e
s
1:
★User
R
O
M
area M37902F8MH
P 4 blocks •••••
•
M37902FCMHP 5 blocks ••••••
M37902FEMH
P 6 blocks •••••
•
M37902FGMHP 7 blocks •••••
•
M37902FHMHP 9 blocks ••••••
M37902FJMH
P 11 blocks •••••
User
R
O
M
area M37902FC
MHP 5 blocks •••••
•
M37902FGMHP 7 blocks••••••
Fig. 2. Memory map of M37902F
C
MHP (Single-chip
mode) Fig. 1. Memory map of M37902F
C
MHP (Single-chip
mode)
Mem
ory m
ap of M
379
02F8MHP (Sing
le-
ch
ip m
ode) (Deleted)
★
Mem
ory m
ap of M
379
02FEMHP
(Si
ngle-chip mode)
★(Deleted)
Mem
ory m
ap of M
379
02FHMHP
(Si
ngle-chip m
od
e) (Deleted)
Mem
ory m
ap of M
379
02FJMHP (Singl
e-
chi
p m
ode) (Deleted)
★
Corrections and
Supplement
ar
y
Explanation
for M37902FxM Dat
asheet
(
REV.
B) NO.3
Page Erro
r Correction
(3/5)
Page 10,
Fig.
2
00FF
C016
Internal
f
l
ash memory
248 Kbytes
(User ROM area)
00
FFFF16
00380016
00FFC016
Internal
flash memory
248 Kbytes
(User ROM area)
00FFFF16
00380016
Page 11,
Fig.
7
Port 011 direction re
g
ister
00001916
00001A16
Port P11 direction re
g
ister
00001916
00001A16
00000016
00000116
00000016
00000116
Reserved area
(
Note
)
Reserved area
(
Note
)
address
0016, 0116
address
1916
★
Fi
g. 4. M
emory
map of
M37902F
G
MHP
(Si
ngle-chip
mode) Fi
g. 2. M
emory
map of
M37902F
G
MHP
(Si
ngle-chip
mode)
★
Page 12,
Fig.
8
Serial
I/O
control r
e
g
i
st
e
r
0
000AC16
0000AD16
Serial I/O
p
in control re
g
ister
0
000AC16
0000AD16
Reserved area
(
Note
)
0000A616
0000A716
(
Deleted
)
address
A616
★
address
AC16, AD16
M37902F8MHP
: block configuration of
i
nter
nal
flash
mem
ory (Deleted)
★
Fig. 10. M37902F
C
MHP : block configuration of internal
flash memory Fig. 9. M37902F
C
MHP : block configuration of inter-
nal flash memory
Page 13,
Fig.
9
★
M37902FEMHP : block configuration of internal flash
memory (Deleted)
Fi
g.
12. M
37
902F
G
M
H
P :
bl
ock
co
nf
i
gur
ation
of internal
flash m
e
m
ory Fig. 10. M37902F
G
MHP : block configuration of inter-
nal flash memory
Page 14,
Fig. 1
0
★
M37902FH
M
HP
:
block configu
r
ation of inter
na
l f
l
ash
mem
ory (Deleted)
★
M37902FJMHP
: block configuration of
i
nt
e
r
nal
flash
mem
ory (Deleted)
Corrections and
Supplement
ar
y
Explanation
for M37902FxM Dat
asheet
(
REV.
B) NO.4
Page Erro
r Correction
(4/5)
Page 16,
RECOMMEND
ED
OPE
R
AT
ING
C
O
N
DITI
ONS
★
Page 17,
DC ELECTRICAL
CHARACTERISTICS
Ta = 25 °
C
•••••••
•
–
–
Ta = 85 °
C
••••••••
µA
–
–
•••••••
•
Icc •••••••
•
Ta = 25 °
C
•••••••• 1
Ta = 85 °
C
••••••••
µA
20
•••••••
•
Icc •••••••
•
Page 16,
AB
SOLUT
E
MAX
IM
UM
RA
TINGS 300
Ratings
S
ymbol
P
d
P
ower di
sspat
i
on
P
arameter Unit
mW 400
Rating
s
S
ymbol
P
d
P
ower di
sspat
i
on
P
arameter Uni
t
mW
Topr
O
perating t
em
perature Topr
O
perating ambien
t
temperature
Page 1
5
DC
Electri
cal
C
haracteristics;
AC
Electri
cal
Ch
aract
er
istic
s
(Vcc = 3.3 V ± 0.3 V, Ta = 0 to 60 °
C
, f(fsys) = 26 MHz
(Note)) (Vcc = 3.3 V ± 0.3 V, Ta = 0 to 60 °
C
, f(fsys) = 20 MHz
(Note))
★
2:
••••••••,
be sure
that f
(fsys)
= 26 M
Hz or less. 2:
••••••••,
be sure
that f
(fsys)
= 20 M
Hz or less.
26
Lim
its
S
ymbol
f
(XIN) Ext
e
rnal clcok input
f
r
equency
(N
o
te
2)
P
arameter
f
(sys)
S
yst
e
m
cl
cok
f
requen
cy
Typ. Min.Max.
26
20
Limits
S
ymbol
f
(XIN) Ext
e
rnal clcok input
f
r
equency
(N
o
te
2)
P
arameter
f
(
f
sys)
S
yst
e
m
cl
cok
f
requen
cy
Typ. Mi
n.Max.
20
★
Min.
31.2
Limits Max.Typ.
S
ymbol
ICC 15.6
f
(
f
sys)
= 26MHz,
CPU
oper
at
es.
Test
condi
t
i
ons
(Vcc =
3.3 V, Vss =
0
V
,
••••••
f(fsys) =
26
MHz (N
ote)
) (Vcc =
3.3 V, Vss =
0
V
,
••••••
f(fsys) =
20
MHz (N
ote)
)
Min.
24
Lim
its Max.Typ.
S
ymbol
ICC 12
f
(
f
sys)
= 20MHz,
CPU
oper
at
es.
Test
conditions
★
★
Min.
1.89
(Note)
Limits
Max.
S
ymbol
tC
O
N
V4.54
f(fsys) ≤ 26MHz
Test conditions
•••••••
•
•••••••
•
Mi
n.
2.45
(Note)
Lim
its
Max.
S
ymbol
tCONV 5.90
f
(
f
sys) ≤ 20MHz
Test conditions
•••••••
•
•••••••
•
Page 18,
A
-
D
C
O
N
VE
RTE
R
CH
ARA
CTE
RISTICS;
the
mini
um
val
ue
of
tC
O
N
V
★
Page 1
9
PERIPHERAL
DEVICE
INPUT/OUTPU
T
TIMING
(Vcc =
3.3 V ± 0.3
V
,
••••••
f(fsys)
=
26
MHz, unless othr
e-
wi
se
noted)
✽ •
•
•
•
•
•
a
t
f
(
fsys)
=
2
6
M
H
z
a
r
e
s
h
o
w
n
i
n
(
)
.
(Vcc =
3.3 V ± 0.3
V
,
••••••
f(fsys)
=
20
MHz, unless othr
e-
wi
se
noted)
✽ •••••
• at f
(fsys)
= 20
MHz are shown in (
).
Corrections and
Supplement
ar
y
Explanation
for M37902FxM Dat
asheet
(
REV.
B) NO.5
Page Erro
r Correction
(5/5)
Page 19,
T
im
e
r
A inpu
t
;
(Gating input in
t
i
mer mode) Mi
n.
f
(
f
sys)
Limits Max.
S
ymbol
tc(TA
)16✕10
f
(
f
sys)
≤
26MH
z
P
arameter
9(615)
•••••••
•
f
(
f
sys)
tw
(TAH
)8✕10
f
(
f
sys)
≤
26MH
z9(307)
•••••••
•
f
(
f
sys)
tw
(TAL) 8✕10
f
(
f
sys)
≤
26MH
z9(307)
•••••••
•
No
t
e: ••
•••• the
co
unt
source =
f2 at
f(fsys) ≤
2
6
MHz.
Page 19,
T
im
e
r
A inpu
t
;
(Ext
erna
l t
ri
gge
r
inpu
t
in one-sho
t
pul
se mode) tc(TA) ••••••••
Page 21,
T
im
e
r
B inpu
t
;
(Pul
se
per
iod
measurement
mode), (Pulse
w
idth
me
asure-
ment mode)
tc(TB)
f
(
f
sys)
≤
26MH
z
•••••••
•
tw
(TBH
)
f
(
f
sys) ≤ 26MHz
•••••••
•
tw
(TBL)
f
(
f
sys) ≤ 26MHz
•••••••
•
Note: •••••• the count source = f2 at f(fsys) ≤ 26 MHz.
Page 23,
READY, HOLD
TIMING; Timing
requirements,
Switching
characteristic
s
(Vcc =
3.3 V ± 0.3
V
,
••••••
f(fsys)
=
26
MHz, unless othr
e-
wi
se
noted)
Pag
es
25,26,27
,
External bus
timi
ng;
(Tim
ing
r
equireme
nt
s),
(Swi
t
ch
ing
char
act
eri
st
i
cs)
Min.
f
(
f
sys)
Limits Max.
S
ymbol
tc(TA
)16✕10
f
(
f
sys)
≤
20MH
z
P
arameter
9(800)
•••••••
•
f
(
f
sys)
tw
(TAH
)8✕10
f
(
f
sys)
≤
20MH
z9(400)
•••••••
•
f
(
f
sys)
tw
(TAL) 8✕10
f
(
f
sys)
≤
20MH
z9(400)
•••••••
•
★
No
t
e: ••
•••• the
co
unt
source =
f2 at
f(fsys) ≤
2
0
MHz.
Mi
n.Limits Max.
S
ymbol
P
arameter
f
(
f
sys)
8✕10
f
(
f
sys)
≤
26MH
z9(307) tc(TA) •••••••• Mi
n.Lim
its Max.
S
ymbol
P
arameter
f
(
f
sys)
8✕10
f
(
f
sys)
≤
20MH
z9(400)
★
Min.Limits Max.
S
ymbol
P
arameter
f
(
f
sys)
16✕109(615)
f
(
f
sys)
8✕109(307)
f
(
f
sys)
8✕109(307)
tc(TB)
f
(
f
sys)
≤
20MH
z
•••••••
•
tw
(TBH
)
f
(
f
sys) ≤ 20MHz
•••••••
•
tw
(TBL)
f
(
f
sys) ≤ 20MHz
•••••••
•
Min.Limits Max.
S
ymbol
P
arameter
f
(
f
sys)
16✕109(800)
f
(
f
sys)
8✕109(400)
f
(
f
sys)
8✕109(400)
Note: •••••• the count source = f2 at f(fsys) ≤ 20 MHz.
★
(Vcc = 3.3 V ± 0.3 V, •••••• f(fsys) = 20 MHz, unless othre-
wise noted)
Page 26,
External bu
s
timing; (Timin
g
requirements
)
tc(in) External clock •••••••• 38
Mi
n. Limits Max.
S
ymbol
P
arameter
tc(in) External clock •••••••• 50
Mi
n. Lim
its Max.
S
ymbol
P
arameter
★
★
★