3VoltIntel®Advanced+BootBlock
FlashMemory(C3)Stacked-ChipScale
PackageFamily
Datasheet
ProductFeatures
The3VoltIntel®
Advanced+BootBlockFlashMemory(C3)Stacked-ChipScalePackage
(Stacked-CSP)devicedeliversafeature-richsolutionforlow-powerapplications.TheC3
Stacked-CSPmemorydeviceincorporatesflashmemoryandstaticRAMinonepackagewith
lowvoltagecapabilitytoachievethesmallestsystemmemorysolutionform-factortogetherwith
high-speed,low-poweroperations.TheC3Stacked-CSPmemorydeviceoffersaprotection
registerandflexibleblocklockingtoenablenextgenerationsecuritycapability.Combinedwith
theIntel®FlashDataIntegrator(Intel®FDI)software,theC3Stacked-CSPmemorydevice
providesacost-effective,flexible,codeplusdatastoragesolution.
■FlashMemoryPlusSRAM
—ReducesMemoryBoardSpace
Required,SimplifyingPCBDesign
Complexity
■Stacked-ChipScalePackage(Stacked-
CSP)Technology
—SmallestMemorySubsystemFootprint
—Area:8x10mmfor16Mbit(0.13µm)
Flash+2Mbitor4MbitSRAM
—Area:8x12mmfor32Mbit(0.13µm)
Flash+4Mbitor8MbitSRAM
—Height:1.20mmfor16Mbit(0.13µm)
Flash+2Mbitor4MbitSRAMand
32Mbit(0.13um)Flash+8MbitSRAM
—Height:1.40mmfor32Mbit(0.13µm)
Flash+4MbitSRAM
—ThisFamilyalsoincludes0.25µmand
0.18µmtechnologies
■AdvancedSRAMTechnology
—70nsAccessTime
—LowPowerOperation
—LowVoltageDataRetentionMode
■Intel®FlashDataIntegrator(FDI)
Software
—Real-TimeDataStorageandCode
ExecutionintheSameMemoryDevice
—FullFlashFileManagerCapability
■Advanced+BootBlockFlashMemory
—70nsAccessTimeat2.7V
—Instant,IndividualBlockLocking
—128bitProtectionRegister
—12VProductionProgramming
—UltraFastProgramandEraseSuspend
—ExtendedTemperature–25°Cto+85°C
■BlockingArchitecture
—BlockSizesforCode+DataStorage
—4-KwordParameterBlocks(fordata)
—64-KbyteMainBlocks(forcode)
—100,000EraseCyclesperBlock
■LowPowerOperation
—AsyncReadCurrent:9mA(Flash)
—StandbyCurrent:7µA(Flash)
—AutomaticPowerSavingMode
■FlashTechnologies
—0.25µmETOX™VI,0.18µmETOX™
VIIand0.13µmETOX™VIIIFlash
Technologies
—28F160xC3,28F320xC3
252636-001
February,2003
Notice:Thisdocumentcontainsinformationonnewproductsinproduction.Thespecifications
aresubjecttochangewithoutnotice.VerifywithyourlocalIntelsalesofficethatyouhavethelat-
estdatasheetbeforefinalizingadesign.
2Datasheet
INFORMATIONINTHISDOCUMENTISPROVIDEDINCONNECTIONWITHINTEL®PRODUCTS.NOLICENSE,EXPRESSORIMPLIED,BY
ESTOPPELOROTHERWISE,TOANYINTELLECTUALPROPERTYRIGHTSISGRANTEDBYTHISDOCUMENT.EXCEPTASPROVIDEDIN
INTEL'STERMSANDCONDITIONSOFSALEFORSUCHPRODUCTS,INTELASSUMESNOLIABILITYWHATSOEVER,ANDINTELDISCLAIMS
ANYEXPRESSORIMPLIEDWARRANTY,RELATINGTOSALEAND/ORUSEOFINTELPRODUCTSINCLUDINGLIABILITYORWARRANTIES
RELATINGTOFITNESSFORAPARTICULARPURPOSE,MERCHANTABILITY,ORINFRINGEMENTOFANYPATENT,COPYRIGHTOROTHER
INTELLECTUALPROPERTYRIGHT.Intelproductsarenotintendedforuseinmedical,lifesaving,orlifesustainingapplications.
Intelmaymakechangestospecificationsandproductdescriptionsatanytime,withoutnotice.
The3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamilymaycontaindesigndefectsorerrorsknownaserratawhichmaycause
theproducttodeviatefrompublishedspecifications.Currentcharacterizederrataareavailableonrequest.
MPEGisaninternationalstandardforvideocompression/decompressionpromotedbyISO.ImplementationsofMPEGCODECs,orMPEGenabled
platformsmayrequirelicensesfromvariousentities,includingIntelCorporation.
ContactyourlocalIntelsalesofficeoryourdistributortoobtainthelatestspecificationsandbeforeplacingyourproductorder.
Copiesofdocumentswhichhaveanorderingnumberandarereferencedinthisdocument,orotherIntelliteraturemaybeobtainedbycalling1-800-
548-4725orbyvisitingIntel'swebsiteathttp://www.intel.com.AdditionalinformationonthisproductfamilycanbeobtainedbyaccessingtheIntel®
Flashwebsite:http://www.intel.com/design/flash.
Copyright©2003IntelCorporation.
*Othernamesandbrandsmaybeclaimedasthepropertyofothers.
Datasheet 3
Contents
Contents
1.0 Introduction....................................................................................................................................7
1.1 DocumentConventions ........................................................................................................7
1.2 ProductOverview .................................................................................................................7
1.3 PackageBallout....................................................................................................................8
1.4 SignalDefinitions..................................................................................................................9
2.0 PrinciplesofOperation...............................................................................................................11
2.1 BusOperation.....................................................................................................................11
2.1.1 Read ......................................................................................................................11
2.1.2 OutputDisable.......................................................................................................12
2.1.3 Standby..................................................................................................................12
2.1.4 FlashReset............................................................................................................13
2.1.5 Write ......................................................................................................................13
3.0 FlashMemoryModesofOperation............................................................................................13
3.1 ReadArray(FFh)................................................................................................................13
3.2 ReadIdentifier(90h)...........................................................................................................13
3.3 ReadStatusRegister(70h) ................................................................................................14
3.3.1 ClearStatusRegister(50h) ...................................................................................14
3.4 CFIQuery(98h)..................................................................................................................15
3.5 WordProgram(40h/10h)....................................................................................................15
3.5.1 SuspendingandResumingProgram(B0h/D0h)....................................................15
3.6 BlockErase(20h)...............................................................................................................16
3.6.1 SuspendingandResumingErase(B0h/D0h)........................................................16
3.7 BlockLocking......................................................................................................................18
3.7.1 BlockLockingOperationSummary........................................................................19
3.7.2 LockedState..........................................................................................................19
3.7.3 UnlockedState ......................................................................................................19
3.7.4 Lock-DownState ...................................................................................................19
3.7.5 ReadingaBlock’sLockStatus ..............................................................................20
3.7.6 LockingOperationduringEraseSuspend.............................................................20
3.7.7 StatusRegisterErrorChecking .............................................................................20
3.8 128BitProtectionRegister.................................................................................................21
3.8.1 ReadingtheProtectionRegister............................................................................21
3.8.2 ProgrammingtheProtectionRegister(C0h)..........................................................21
3.8.3 LockingtheProtectionRegister.............................................................................22
4.0 PowerandResetConsiderations ..............................................................................................23
4.1 Power-Up/DownCharacteristics.........................................................................................23
4.2 AdditionalFlashFeatures...................................................................................................23
4.2.1 Improved12 VoltProductionProgramming...........................................................23
4.2.2 F-VPP<VPPLKforCompleteProtection..............................................................23
5.0 ElectricalSpecifications .............................................................................................................24
5.1 AbsoluteMaximumRatings................................................................................................24
5.2 OperatingConditions..........................................................................................................25
5.3 Capacitance........................................................................................................................25
Contents
4Datasheet
5.4 DCCharacteristics..............................................................................................................26
5.5 FlashACCharacteristics....................................................................................................29
5.6 FlashACCharacteristics—WriteOperations......................................................................31
5.7 FlashEraseandProgramTimings(1).................................................................................31
5.8 FlashResetOperations......................................................................................................34
5.9 SRAMACCharacteristics—ReadOperations....................................................................35
5.10 SRAMACCharacteristics—WriteOperations....................................................................37
5.11 SRAMDataRetentionCharacteristics—ExtendedTemperature.......................................39
6.0 MigrationGuideInformation ......................................................................................................40
7.0 SystemDesignConsiderations..................................................................................................41
7.1 Background.........................................................................................................................41
7.1.1 Flash+SRAMFootprintIntegration ......................................................................41
7.1.2 Advanced+BootBlockFlashMemoryFeatures ...................................................41
7.2 FlashControlConsiderations .............................................................................................41
7.2.1 F-RP#ConnectedtoSystemReset.......................................................................42
7.2.2 F-VCC,F-VPPandF-RP#Transition....................................................................42
7.3 NoiseReduction .................................................................................................................43
7.4 SimultaneousOperation.....................................................................................................44
7.4.1 SRAMOperationduringFlash“Busy” ...................................................................45
7.4.2 SimultaneousBusOperations...............................................................................45
7.5 PrintedCircuitBoardNotes................................................................................................45
7.6 SystemDesignNotesSummary.........................................................................................45
AppendixAProgram/EraseFlowcharts.............................................................................................46
AppendixBCFIQueryStructure ........................................................................................................52
AppendixCWord-WideMemoryMapDiagrams ...............................................................................59
AppendixDDeviceIDTable................................................................................................................62
AppendixEProtectionRegisterAddressing.....................................................................................63
AppendixFMechanicalandShippingMediaDetails........................................................................64
AppendixGAdditionalInformation....................................................................................................68
AppendixHOrderingInformation.......................................................................................................69
Datasheet 5
Contents
RevisionHistory
Dateof
Revision Version Description
02/11/03 -001 Initialrelease,Stacked-ChipScalePackage
Contents
6Datasheet
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 7
1.0 Introduction
Thisdocumentcontainsthespecificationsforthe3VoltIntel®
Advanced+BootBlockFlash
Memory(C3)Stacked-ChipScalePackage(Stacked-CSP)device.Stackedmemorysolutionsare
offeredinthefollowingcombinations:32-Mbitflash+8-MbitSRAM,32-Mbitflash+4-Mbit
SRAM,16-Mbitflash+4-MbitSRAM,or16-Mbitflashmemory+2-MbitSRAM.
1.1 DocumentConventions
Throughoutthisdocument,thefollowingconventionshavebeenadopted.
•Voltages:“2.7V”referstothefullvoltagerange,2.7V–3.3V;12Vrefersto11.4Vto12.6V
•Mainblock(s):32-Kwordblock
•Parameterblock(s):4-Kwordblock
1.2 ProductOverview
TheC3Stacked-CSPdevicecombinesflashandSRAMintoasinglepackage,andprovidessecure
low-voltagememorysolutionsforportableapplications.Thismemoryfamilycombinestwo
memorytechnologies,flashmemoryandSRAM,inonepackage.Theflashmemorydelivers
enhancedsecurityfeatures,ablocklockingcapabilitythatallowsinstantlocking/unlockingofany
flashblockwithzero-latency,anda128-bitprotectionregisterthatenableuniquedevice
identification,tomeettheneedsofnextgenerationportableapplications.Improved12 V
productionprogrammingcanbeusedtoimprovefactorythroughput.
Theflashmemoryisasymmetrically-blockedtoenablesystemintegrationofcodeanddatastorage
inasingledevice.Eachflashblockcanbeerasedindependentlyoftheothersupto100,000times.
Theflashhaseight8-KBparameterblockslocatedateitherthetop(denotedby-Tsuffix)orthe
bottom(-Bsuffix)oftheaddressmapinordertoaccommodatedifferentmicroprocessorprotocols
forkernelcodelocation.Theremainingflashmemoryisgroupedinto32-Kwordmainblocks.Any
individualflashblockcanbelockedorunlockedinstantlytoprovidecompleteprotectionforcode
ordata(seeSection5.7,“FlashEraseandProgramTimings(1)”onpage 31fordetails).
TheflashcontainsbothaCommandUserInterface(CUI)andaWriteStateMachine(WSM).The
CUIservesastheinterfacebetweenthemicrocontrollerandtheinternaloperationoftheflash
memory.TheinternalWSMautomaticallyexecutesthealgorithmsandtimingsnecessaryfor
Table1. BlockOrganization(x16)
MemoryDevice Kwords
32-MbitFlash 2048
16-MbitFlash 1024
2-MbitSRAM 128
4-MbitSRAM 256
8-MbitSRAM 512
NOTE: Allwordsare16bitseach.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
8Datasheet
programanderaseoperations,includingverification,therebyunburdeningthemicroprocessoror
microcontroller.Theflash’sstatusregisterindicatesthestatusoftheWSMbysignifyingblock
eraseorwordprogramcompletionandstatus.
Flashprogramanderaseautomationallowsprogramanderaseoperationstobeexecutedusingan
industry-standardtwo-writecommandsequencetotheCUI.Programoperationsareperformedin
wordincrements.Eraseoperationserasealllocationswithinablocksimultaneously.Bothprogram
anderaseoperationscanbesuspendedbythesystemsoftwareinordertoreadfromanyotherflash
block.Inaddition,datacanbeprogrammedtoanotherflashblockduringanerasesuspend.
TheC3Stacked-CSPmemorydeviceofferstwolow-powersavingsfeatures:AutomaticPower
Savings(APS)forflashmemoryandstandbymodeforflashandSRAM.Thedeviceautomatically
entersAPSmodefollowingthecompletionofareadcyclefromtheflashmemory.Standbymode
isinitiatedwhenthesystemdeselectsthedevicebydrivingF-CE#andS-CS1#or
S-CS2inactive.Powersavingsfeaturessignificantlyreducepowerconsumption.
TheflashmemorycanberesetbyloweringF-RP#toGND.ThisprovidesCPU-memoryreset
synchronizationandadditionalprotectionagainstbusnoisethatmayoccurduringsystemresetand
power-up/-downsequences.
1.3 PackageBallout
72-
NOTES:
1. FlashupgradeballsareshownuptoA21(64-Mbitflash)andA22(128-Mbitflash).InallflashandSRAM
combinations,66ballsarepopulatedonlowerdensitydevices.(Upperaddressballsarenotpopulated).Ball
locationA10is“NC”on16/2devicesonly.
Figure1.66-BallStackedChipScalePackage
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
H
NC A
20
A
11
A
15
A
14
A
13
A
12
A
16
A
8
A
10
A
9
DQ
15
S-WE#
F-WE# NC A
21
DQ
13
DQ
6
S-V
SS
F-WP# A
19
DQ
11
DQ
10
S-LB# S-UB# S-OE# DQ
9
DQ
8
A
18
A
17
A
7
A
6
A
3
A
2
NC NC A
5
A
4
A
0
F-CE# F-V
SS
F-RP# A
22
DQ
12
S-CS
2
910 11 12
F-V
SS
NC
DQ
14
DQ
7
DQ
4
DQ
5
DQ
2
DQ
3
DQ
0
DQ
1
A
1
S-CS
1
#
F-OE# NC NC
S-V
CC
F-V
CC
TopView,BallsDown
F-V
CCQ
F-V
PP
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 9
2. TomaintaincompatibilitywithallJEDECVariationBoptionsforthisballlocationC6,thisC6landpadshould
beconnecteddirectlytothelandpadforballG4(A17).
1.4 SignalDefinitions
Table2.definesthesignaldefinitionsshowninthepreviousballout.
Table2. 3VoltIntel®Advanced+BootBlockStacked-CSPBallDescriptions(Sheet1of2)
Symbol Type NameandFunction
A[20:0] INPUT
ADDRESSINPUTSformemoryaddresses.Addressesareinternallylatchedduringaprogramor
erasecycle.
2-Mbit:A[16:0]
4-Mbit:A[18:0]
16-Mbit:A[19:0]
32-MbitA[20:0]
DQ[15:0] INPUT/
OUTPUT
DATAINPUTS/OUTPUTS:InputsarraydataforSRAMwriteoperationsandonthesecondF-CE#
andF-WE#cycleduringaflashprogramcommand.Inputscommandstotheflash’sCommand
UserInterfacewhenF-CE#andF-WE#areasserted.Dataisinternallylatched.Outputsarray,
configurationandstatusregisterdata.Thedataballsfloattotri-statewhenthechipisde-selected
ortheoutputsaredisabled.
F-CE# INPUT FLASHCHIPENABLE:Activatestheflashinternalcontrollogic,inputbuffers,decodersand
senseamplifiers.F-CE#isactivelow.F-CE#highde-selectstheflashmemorydeviceandreduces
powerconsumptiontostandbylevels.
S-CS1# INPUT SRAMCHIPSELECT1:ActivatestheSRAMinternalcontrollogic,inputbuffers,decodersand
senseamplifiers.S-CS1#isactivelow.S-CS1#highde-selectstheSRAMmemorydeviceand
reducespowerconsumptiontostandbylevels.
S-CS2 INPUT SRAMCHIPSELECT2:ActivatestheSRAMinternalcontrollogic,inputbuffers,decodersand
senseamplifiers.S-CS2isactivehigh.S-CS2lowde-selectstheSRAMmemorydeviceand
reducespowerconsumptiontostandbylevels.
F-OE# INPUT FLASHOUTPUTENABLE:Enablesflash’soutputsthroughthedatabuffersduringaread
operation.F-OE#isactivelow.
S-OE# INPUT SRAMOUTPUTENABLE:EnablesSRAM’soutputsthroughthedatabuffersduringaread
operation.S-OE#isactivelow.
F-WE# INPUT FLASHWRITEENABLE:Controlswritestoflash’scommandregisterandmemoryarray.F-WE#
isactivelow.AddressesanddataarelatchedontherisingedgeofthesecondF-WE#pulse.
S-WE# INPUT SRAMWRITEENABLE:ControlswritestotheSRAMmemoryarray.S-WE#isactivelow.
S-UB# INPUT SRAMUPPERBYTEENABLE:EnablestheupperbyteforSRAM(DQ8–DQ15).
S-UB#isactivelow.
S-LB# INPUT SRAMLOWERBYTEENABLE:EnablesthelowerbyteforSRAM(DQ0–DQ7).
S-LB#isactivelow.
F-RP# INPUT
FLASHRESET/DEEPPOWER-DOWN:Usestwovoltagelevels(VIL,VIH)tocontrolreset/deep
power-downmode.
WhenF-RP#isatlogiclow,thedeviceisinreset/deeppower-downmode,whichdrivesthe
outputstoHigh-Z,resetstheWriteStateMachine,andminimizescurrentlevels(ICCD).
WhenF-RP#isatlogichigh,thedeviceisinstandardoperation.WhenF-RP#transitionsfrom
logic-lowtologic-high,thedeviceresetsallblockstolockedanddefaultstothereadarraymode.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
10 Datasheet
F-WP# INPUT
FLASHWRITEPROTECT:Controlsthelock-downfunctionoftheflexibleLockingfeature.
WhenF-WP#isalogiclow,thelock-downmechanismisenabledandblocksmarkedlock-
downcannotbeunlockedthroughsoftware.
WhenF-WP#islogichigh,thelock-downmechanismisdisabledandblockspreviously
locked-downarenowlockedandcanbeunlockedandlockedthroughsoftware.AfterF-WP#goes
low,anyblockspreviouslymarkedlock-downreverttothatstate.
SeeSection7.0,“SystemDesignConsiderations”onpage 41fordetailsonblocklocking.
F-VCC SUPPLY FLASHPOWERSUPPLY:[2.7 V–3.3 V]Suppliespowerfordevicecoreoperations.
F-VCCQ SUPPLY FLASHI/OPOWERSUPPLY:[2.7 V–3.3 V]SuppliespowerfordeviceI/Ooperations.
S-VCC SUPPLY SRAMPOWERSUPPLY:[2.7 V–3.3 V]Suppliespowerfordeviceoperations.
SeeSection7.2.2,“F-VCC,F-VPPandF-RP#Transition”onpage 42fordetailsofpower
connections.
F-VPP INPUT/
SUPPLY
FLASHPROGRAM/ERASEPOWERSUPPLY:[1.65 V–3.3 Vor11.4 V–12.6 V]Operatesasan
inputatlogiclevelstocontrolcompleteflashprotection.Suppliespowerforacceleratedflash
programanderaseoperationsin12 V±5%range.Thisballcannotbeleftfloating.
LowerF-VPP≤VPPLK,toprotectallcontentsagainstProgramandErasecommands.
SetF-VPP =F-V
CCforin-systemread,programanderaseoperations.Inthisconfiguration,
F-VPPcandropaslowas1.65 Vtoallowforresistorordiodedropfromthesystemsupply.Note
thatifF-VPPisdrivenbyalogicsignal,VIH = 1.65 V.Thatis,F-VPP
mustremainabove1.65 Vto
performin-systemflashmodifications.
RaiseF-VPPto12V±5%forfasterprogramanderaseinaproductionenvironment.Applying
12 V±5%toF-VPP
canonlybedoneforamaximumof1000cyclesonthemainblocksand2500
cyclesontheparameterblocks.
F-VPPmaybeconnectedto12 Vforatotalof80hoursmaximum.
F-VSS SUPPLY FLASHGROUND:Forallinternalcircuitry.Allgroundinputsmustbeconnected.
S-VSS SUPPLY SRAMGROUND:Forallinternalcircuitry.Allgroundinputsmustbeconnected.
NC NOTCONNECTED:Internallydisconnectedwithinthedevice.
Table2. 3VoltIntel®Advanced+BootBlockStacked-CSPBallDescriptions(Sheet2of2)
Symbol Type NameandFunction
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 11
2.0 PrinciplesofOperation
TheflashmemoryutilizesaCUIandautomatedalgorithmstosimplifyprogramanderase
operations.TheWSMautomatesprogramanderaseoperationsbyhandlingdataandaddress
latches,WE#,andsystemstatusrequests.
.
2.1 BusOperation
AllbuscyclestoorfromtheStacked-CSPconformtostandardmicrocontrollerbuscycles.Four
controlsignalsdictatethedataflowinandoutoftheflashcomponent:F-CE#,F-OE#,F-WE#and
F-RP#.FourseparatecontrolsignalshandlethedataflowinandoutoftheSRAMcomponent:
S-CS1#,S-CS2,S-OE#,andS-WE#.ThesebusoperationsaresummarizedinTable2andTable3.
2.1.1 Read
Theflashmemoryhasfourreadmodes:readarray,readidentifier,readstatusandCFIquery.These
flashmemoryreadmodesarenotdependentontheF-VPPvoltage.Uponinitialdevicepower-upor
afterexitfromreset,theflashdeviceautomaticallydefaultstoreadarraymode.F-CE#andF-OE#
mustbeassertedtoobtaindatafromtheflashcomponent.
TheSRAMhasonereadmodeavailable.S-CS1#,S-CS2,andS-OE#mustbeassertedtoobtain
datafromtheSRAMdevice.SeeTable 3,“3VoltIntelAdvanced+BootBlockFlashMemory
Stacked-CSPBusOperations”onpage 12forasummaryofoperations.
Figure2.3VoltIntel®Advanced+BootBlockStackedChipScalePackageBlockDiagram
F-VCC
F-OE#
F-CE#
A[Max:0]
2-,4-or8-Mbit
SRAM
28F160C3
or
28F320C3
Flash
S-VCC
F-VCCQ
S-CS1
S-CS2
S-OE#
S-WE#
S-UB#
S-LB#
F-VPP
F-WE#
F-VSS
S-VSS
D[15:0]
F-WP#
F-RP#
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
12 Datasheet
2.1.2 OutputDisable
WithF-OE#andS-OE#deasserted,theStacked-CSPoutputssignalsareplacedinahigh-
impedancestate.
2.1.3 Standby
WithF-CE#andS-CS1#orS-CS2deasserted,theStacked-CSPentersastandbymode,which
substantiallyreducesdevicepowerconsumption.Instandby,outputsareplacedinahigh-
impedancestateindependentofF-OE#andS-OE#.Iftheflashisdeselectedduringaprogramor
eraseoperation,theflashcontinuestoconsumeactivepoweruntiltheprogramoreraseoperationis
complete.
Table3. 3VoltIntelAdvanced+BootBlockFlashMemoryStacked-CSPBusOperations
Modes
FlashSignals SRAMSignals MemoryOutput
Notes
F-RP#
F-CE#
F-OE1#
F-WE#
S-CS1#
S-CS2
S-OE1#
S-WE#
S-UB#,S-LB#(1)
MemoryBusControl
D0–
D15
FLASH
Read H L L H SRAMmustbeinHighZFlash DOUT 2,3,4
Write H L H L Flash DIN 2,4
Standby H H X X
AnySRAMmodeisallowable
Other HighZ5,6
OutputDisable H L H H Other HighZ5,6
Reset L X X X Other HighZ5,6
SRAM
Read FLASHmustbeinHighZLHLHLSRAMD
OUT 2,4
Write L H H L L SRAM DIN 2,4
Standby
AnyFLASHmodeisallowable
HXXXX
Other HighZ 4,5,6
XLXXX
OutputDisable L H H H X Other HighZ 4,5,6
DataRetention sameasastandby Other HighZ 4,5,7
NOTES:
1. Twodevicesmaynotdrivethememorybusatthesametime.
2. TheSRAMmaybeplacedintodataretentionmodebyloweringtheS-VCCtotheVDRrange,asspecified.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 13
2.1.4 FlashReset
ThedeviceentersaresetmodewhenRP#isdrivenlow.Inresetmode,internalcircuitryisturned
offandoutputsareplacedinahigh-impedancestate.
Afterreturnfromreset,atimetPHQVisrequireduntiloutputsarevalid,andadelay(tPHWLor
tPHEL)isrequiredbeforeawritesequencecanbeinitiated.Afterthiswake-upinterval,normal
operationisrestored.Thedevicedefaultstoreadarraymode,thestatusregisterissetto80h,and
thereadconfigurationregisterdefaultstoasynchronousreads.
IfRP#istakenlowduringablockeraseorprogramoperation,theoperationwillbeabortedandthe
memorycontentsattheabortedlocationarenolongervalid.
2.1.5 Write
WritestoflashtakeplacewhenbothF-CE#andF-WE#areassertedandF-OE#isdeasserted.
WritestoSRAMtakeplacewhenbothS-CS1#andS-WE#areassertedandS-OE#andS-CS2are
deasserted.Commandsarewrittentotheflashmemory’sCommandUserInterface(CUI)using
standardmicroprocessorwritetimingstocontrolflashoperations.TheCUIdoesnotoccupyan
addressablememorylocationwithintheflashcomponent.Theaddressanddatabusesarelatched
ontherisingedgeofthesecondF-WE#orF-CE#pulse,whicheveroccursfirst.(SeeFigure6and
Figure7forreadandwritewaveforms.)
3.0 FlashMemoryModesofOperation
Theflashmemoryhasfourreadmodes:readarray,readconfiguration,readstatus,andCFIquery.
Thewritemodesareprogramanderase.Threeadditionalmodes(erasesuspendtoprogram,erase
suspendtoreadandprogramsuspendtoread)areavailableonlyduringsuspendedoperations.
ThesemodesarereachedusingthecommandssummarizedinTable 5,“FlashMemoryCommand
Definitions”onpage 17.
3.1 ReadArray(FFh)
WhenF-RP#transitionsfromVIL(reset)toVIH,thedevicedefaultstoreadarraymodeandwill
respondtothereadcontrolinputswithoutanyadditionalCUIcommands.
Inaddition,theaddressofthedesiredlocationmustbeappliedtotheaddressballs.Ifthedeviceis
notinreadarraymode,aswouldbethecaseafteraprogramoreraseoperation,theReadArray
command(FFh)mustbewrittentotheCUIbeforearrayreadscantakeplace.
3.2 ReadIdentifier(90h)
Thereadconfigurationmodeoutputsthemanufacturer/deviceidentifier.Thedeviceisswitchedto
thismodebywritingthereadconfigurationcommand(90h).Onceinthismode,readcyclesfrom
addressesshowninTable 4,“ReadConfigurationTable”onpage 14retrievethespecified
information.Toreturntoreadarraymode,writetheReadArraycommand(FFh).
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
14 Datasheet
TheReadConfigurationmodeoutputsthreetypesofinformation:themanufacturer/device
identifier,theblocklockingstatus,andtheprotectionregister.Thedeviceisswitchedtothismode
bywritingtheReadConfigurationcommand(90h).Onceinthismode,readcyclesfromaddresses
showninTable4retrievethespecifiedinformation.Toreturntoreadarraymode,writetheRead
Arraycommand(FFh).
OtherlocationswithintheconfigurationaddressspacearereservedbyIntelforfutureuse.
3.3 ReadStatusRegister(70h)
Thestatusregisterindicatesthestatusofdeviceoperations,andthesuccess/failureofthat
operation.TheReadStatusRegister(70h)commandcausessubsequentreadstooutputdatafrom
thestatusregisteruntilanothercommandisissued.Toreturntoreadingfromthearray,issuea
ReadArray(FFh)command.
ThestatusregisterbitsareoutputonDQ[7:0].Theupperbyte,DQ[15:8],outputs00hduringa
ReadStatusRegistercommand.
ThecontentsofthestatusregisterarelatchedonthefallingedgeofF-OE#orF-CE#,whichever
occurslast.Thispreventspossiblebuserrorswhichmightoccurifstatusregistercontentschange
whilebeingread.F-CE#orF-OE#mustbetoggledwitheachsubsequentstatusread,orthestatus
registerwillnotindicatecompletionofaprogramoreraseoperation.
WhentheWSMisactive,SR7willindicatethestatusoftheWSM;theremainingbitsinthestatus
registerindicatewhethertheWSMwassuccessfulinperformingthedesiredoperation(see
Table 6,“FlashMemoryStatusRegisterDefinition”onpage 18).
3.3.1 ClearStatusRegister(50h)
TheWSMsetsstatusbits1through7to“1,”andclearsbits2,6and7to“0,”butcannotclear
statusbits1or3through5to“0.”Becausebits1,3,4and5indicatevariouserrorconditions,these
bitscanonlybeclearedthroughtheuseoftheClearStatusRegister(50h)command.Byallowing
thesystemsoftwaretocontroltheresettingofthesebits,severaloperationsmaybeperformed
Table4. ReadConfigurationTable
Item Address Data Notes
ManufacturerCode(x16) 0x00000 0x0089
DeviceID(SeeAppendixD) 0x00001 ID
BlockLockConfiguration 0xXX002 LOCK 1,2
•BlockIsUnlocked DQ0=0
•BlockIsLocked DQ0=1
•BlockIsLocked-Down DQ1=1
ProtectionRegisterLock 0x80 PR-LK 3
ProtectionRegister(x16) 0x81-0x88 PR
NOTES:
1. SeeSection3.7forvalidlockstatusoutputs.
2. “XX”specifiestheblockaddressoflockconfigurationbeingread.
3. SeeSection3.8forprotectionregisterinformation.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 15
(suchascumulativelyprogrammingseveraladdressesorerasingmultipleblocksinsequence)
beforereadingthestatusregistertodetermineifanerroroccurredduringthatseries.Clearthe
statusregisterbeforebeginninganothercommandorsequence.NotethattheReadArraycommand
mustbeissuedbeforedatacanbereadfromthememoryarray.Resettingthedevicealsoclearsthe
statusregister.
3.4 CFIQuery(98h)
TheCFIquerymodeoutputsCommonFlashInterface(CFI)datawhenthedeviceisread.Thiscan
beaccessedbywritingtheCFIQueryCommand(98h).TheCFIdatastructurecontains
informationsuchasblocksize,density,commandsetandelectricalspecifications.Onceinthis
mode,readcyclesfromaddressesshowninAppendixBretrievethespecifiedinformation.To
returntoreadarraymode,writetheReadArraycommand(FFh).
3.5 WordProgram(40h/10h)
Programmingisexecutedusingatwo-writesequence.TheProgramSetupcommand(40h)is
writtentotheCUIfollowedbyasecondwritewhichspecifiestheaddressanddatatobe
programmed.TheWSMwillexecuteasequenceofinternallytimedeventstoprogramdesiredbits
oftheaddressedlocation,thenverifythebitsaresufficientlyprogrammed.Programmingthe
memoryresultsinspecificbitswithinanaddresslocationbeingchangedtoa“0.”Iftheuser
attemptstoprogram“1”s,thememorycellcontentsdonotchangeandnoerroroccurs.
Thestatusregisterindicatesprogrammingstatus:whiletheprogramsequenceexecutes,statusbit7
is“0.”ThestatusregistercanbepolledbytogglingeitherF-CE#orF-OE#.Whileprogramming,
theonlyvalidcommandsareReadStatusRegister,ProgramSuspend,andProgramResume.
Whenprogrammingiscomplete,theprogramstatusbitsshouldbechecked.Iftheprogramming
operationwasunsuccessful,bitSR.4ofthestatusregisterissettoindicateaprogramfailure.If
SR.3issetthenF-VPPwasnotwithinacceptablelimits,andtheWSMdidnotexecutetheprogram
command.IfSR.1isset,aprogramoperationwasattemptedonalockedblockandtheoperation
wasaborted.
Thestatusregistershouldbeclearedbeforeattemptingthenextoperation.AnyCUIinstructioncan
followafterprogrammingiscompleted;however,topreventinadvertentstatusregisterreads,be
suretoresettheCUItoreadarraymode.
3.5.1 SuspendingandResumingProgram(B0h/D0h)
TheProgramSuspendcommandhaltsanin-progressprogramoperationsothatdatacanberead
fromotherlocationsofmemory.Oncetheprogrammingprocessstarts,writingtheProgram
SuspendcommandtotheCUIrequeststhattheWSMsuspendtheprogramsequence(at
predeterminedpointsintheprogramalgorithm).Thedevicecontinuestooutputstatusregisterdata
aftertheProgramSuspendcommandiswritten.PollingstatusregisterbitsSR.7andSR.2will
determinewhentheprogramoperationhasbeensuspended(bothwillbesetto“1”).tWHRH1/
tEHRH1specifytheprogramsuspendlatency.
AReadArraycommandcanbewrittentotheCUItoreaddatafromanyblockotherthanthe
suspendedblock.Theonlyothervalidcommands,whileprogramissuspended,areReadStatus
Register,ReadConfiguration,CFIQuery,andProgramResume.AftertheProgramResume
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
16 Datasheet
commandiswrittentotheflashmemory,theWSMwillcontinuewiththeprogrammingprocess
andstatusregisterbitsSR.2andSR.7willautomaticallybecleared.Thedeviceautomatically
outputsstatusregisterdatawhenread(seeAppendixA,ProgramSuspend/ResumeFlowcharts)
aftertheProgramResumecommandiswritten.F-VPPmustremainatthesameF-VPPlevelused
forprogramwhileinprogramsuspendmode.F-RP#mustalsoremainatVIH.
3.6 BlockErase(20h)
Toeraseablock,writetheEraseSet-upandEraseConfirmcommandstotheCUI,alongwithan
addressidentifyingtheblocktobeerased.ThisaddressislatchedinternallywhentheErase
Confirmcommandisissued.Blockerasureresultsinallbitswithintheblockbeingsetto“1.”Only
oneblockcanbeerasedatatime.TheWSMwillexecuteasequenceofinternallytimedeventsto
programallbitswithintheblockto“0,”eraseallbitswithintheblockto“1,”thenverifythatall
bitswithintheblockaresufficientlyerased.Whiletheeraseexecutes,statusbit7isa“0.”
Whenthestatusregisterindicatesthaterasureiscomplete,checktheerasestatusbittoverifythat
theeraseoperationwassuccessful.IftheEraseoperationwasunsuccessful,SR.5ofthestatus
registerwillbesettoa“1,”indicatinganerasefailure.IfF-VPPwasnotwithinacceptablelimits
aftertheEraseConfirmcommandwasissued,theWSMwillnotexecutetheerasesequence;
instead,SR.5ofthestatusregisterissettoindicateaneraseerror,andSR.3issettoa“1”to
identifythatF-VPPsupplyvoltagewasnotwithinacceptablelimits.
Afteraneraseoperation,clearthestatusregister(50h)beforeattemptingthenextoperation.Any
CUIinstructioncanfollowaftererasureiscompleted;however,topreventinadvertentstatus
registerreads,itisadvisabletoplacetheflashinreadarraymodeaftertheeraseiscomplete.
3.6.1 SuspendingandResumingErase(B0h/D0h)
Aneraseoperationcantakeseveralsecondstocomplete,therefore,theEraseSuspendcommandis
providedtoallowerase-sequenceinterruptioninordertoreaddatafrom,orprogramdatato,
anotherblockinmemory.Onceanerasesequencehasstarted,writingtheEraseSuspendcommand
totheCUIcausesthedevicetosuspendtheerasesequenceatapredeterminedpointintheerase
algorithm.BlockeraseissuspendedwhenStatusRegisterbitsSR[7,6]areset.Suspendlatencyis
specifiedinSection5.7,“FlashEraseandProgramTimings”onpage31.
Whenaneraseoperationhasbeensuspended,aWordProgramorReadoperationcanbeperformed
withinanyblock,excepttheblockthatisinanerasesuspendstate.Aneraseoperationcannotbe
nestedwithinanothererasesuspendoperation.
Asuspendederaseoperationcannotresumeuntilthenestedprogramoperationhascompleted.
ReadArray,ReadStatusRegister,ClearStatusRegister,ReadIdentifier,CFIQuery,Erase
Resume,areallvalidcommandsduringEraseSuspend.Additionally,Program,ProgramSuspend,
ProgramResume,LockBlock,UnlockBlockandLock-DownBlockarevalidcommandsduring
EraseSuspend.
Toresumeanerasesuspendoperation,issuetheResumecommand.TheResumecommandcanbe
writtentoanydeviceaddress.WhenaprogramoperationisnestedwithinanEraseSuspend
operationandtheProgramSuspendcommandisissued,thedevicewillsuspendtheprogram
operation.Whentheresumecommandisissued,thedevicewillresumetheprogramoperation
first.Oncethenestedprogramoperationiscompleted,anadditionalResumecommandisrequired
tocompletetheblockoperation.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 17
Table5. FlashMemoryCommandDefinitions
Command Note FirstBusCycle SecondBusCycle
Operation Address Data Operation Address Data
ReadArray 1 Write X FFh
ReadIdentifier 1,2 Write X 90h Read IA ID
CFIQuery 1,2 Write X 98h Read QA QD
ReadStatusRegister 1 Write X 70h Read X SRD
ClearStatusRegister 1 Write X 50h
WordProgram 1,3 Write X 40h/10h Write PA PD
BlockErase/Confirm 1 Write X 20h Write BA D0h
Program/EraseSuspend 1 Write X B0h
Program/EraseResume 1 Write X D0h
LockBlock 1 Write X 60h Write BA 01h
UnlockBlock 1,4Write X 60hWriteBA D0h
Lock-DownBlock 1 Write X 60h Write BA 2Fh
ProtectionRegisterProgram 1 Write X C0h Write PA PD
LockProtectionRegister 1 Write X C0h Write PA FFFD
X = Don’tCare PA = ProgramAddress BA = BlockAddress IA = IdentifierAddress QA = QueryAddress
SRD = StatusRegisterData PD = ProgramData ID = IdentifierData QD = QueryData
NOTES:
1. Whenwritingcommands,theupperdatabus[DQ8–DQ15]shouldbeeitherVILorVIH,tominimizecurrentdraw.
2. FollowingtheReadConfigurationorCFIQuerycommands,readoperationsoutputdeviceconfigurationorCFIquery
information,respectively.
3. Either40hor10hcommandisvalid,buttheIntelstandardis40h.
4. Whenunlockingablock,WP#mustbeheldforthreeclockcycles(1clockcycleafterthesecondcommandbuscycle).
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
18 Datasheet
3.7 BlockLocking
Theinstant,individualblocklockingfeaturethatallowsanyflashblocktobelockedorunlocked
withnolatency,whichenablesinstantcodeanddataprotection.
Thislockingofferstwolevelsofprotection.Thefirstlevelallowssoftware-onlycontrolofblock
locking(usefulfordatablocksthatchangefrequently),whilethesecondlevelrequireshardware
interactionbeforelockingcanbechanged(usefulforcodeblocksthatchangeinfrequently).
Thefollowingsectionswilldiscusstheoperationofthelockingsystem.Theterm“state[XYZ]”
willbeusedtospecifylockingstates;e.g.,“state[001],”whereX=valueofWP#,Y = bitDQ1of
theBlockLockstatusregister,andZ = bitDQ0oftheBlockLockstatusregister.Table 8,“Block
LockingStateTransitions”onpage 21definesallofthesepossiblelockingstates.
Table6. FlashMemoryStatusRegisterDefinition
WSMS ESS ES PS VPPS PSS BLS R
76543210
NOTES:
SR.7WRITESTATEMACHINESTATUS
1 = Ready(WSMS)
0=Busy
CheckWriteStateMachinebitfirsttodetermineWordProgramor
BlockErasecompletion,beforecheckingProgramorEraseStatus
bits.
SR.6 = ERASE-SUSPENDSTATUS(ESS)
1=EraseSuspended
0=EraseInProgress/Completed
WhenEraseSuspendisissued,WSMhaltsexecutionandsets
bothWSMSandESSbitsto“1.”ESSbitremainssetto“1”untilan
EraseResumecommandisissued.
SR.5 = ERASESTATUS(ES)
1 = ErrorInBlockErase
0 = SuccessfulBlockErase
Whenthisbitissetto“1,”WSMhasappliedthemax.numberof
erasepulsesandisstillunabletoverifysuccessfulblockerasure.
SR.4 = PROGRAMSTATUS(PS)
1 = ErrorinProgramming
0 = SuccessfulProgramming
Whenthisbitissetto“1,”WSMhasattemptedbutfailedto
programaword/byte.
SR.3 = F-VPPSTATUS(VPPS)
1=F-V
PPLowDetect,OperationAbort
0=F-V
PPOK
TheF-VPP
statusbitdoesnotprovidecontinuousindicationofVPP
level.TheWSMinterrogatesF-VPPlevelonlyaftertheProgramor
Erasecommandsequenceshavebeenentered,andinformsthe
systemifF-VPPhasnotbeenswitchedon.TheF-VPPisalso
checkedbeforetheoperationisverifiedbytheWSM.TheF-VPP
statusbitisnotguaranteedtoreportaccuratefeedbackbetween
VPPLKandVPP1
min.
SR.2 = PROGRAMSUSPENDSTATUS(PSS)
1=ProgramSuspended
0=PrograminProgress/Completed
WhenProgramSuspendisissued,WSMhaltsexecutionandsets
bothWSMSandPSSbitsto“1.”PSSbitremainssetto“1”untila
ProgramResumecommandisissued.
SR.1 = BLOCKLOCKSTATUS
1=Prog/Eraseattemptedonalockedblock;Operation
aborted.
0=Nooperationtolockedblocks
Ifaprogramoreraseoperationisattemptedtooneofthelocked
blocks,thisbitissetbytheWSM.Theoperationspecifiedis
abortedandthedeviceisreturnedtoreadstatusmode.
SR.0 = RESERVEDFORFUTUREENHANCEMENTS(R) Thisbitisreservedforfutureuseandshouldbemaskedoutwhen
pollingthestatusregister.
NOTE: ACommandSequenceErrorisindicatedwhenSR.4,SR.5andSR.7areset.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 19
3.7.1 BlockLockingOperationSummary
Thefollowingconciselysummarizesthelockingfunctionality.
Allblocksarelockedwhenpowered-up,andcanbeunlockedorlockedwiththeUnlockandLock
commands.
•TheLock-DowncommandlocksablockandpreventsitfrombeingunlockedwhenWP# = 0.
•WhenWP# = 1,Lock-Downisoverriddenandcommandscanunlock/locklocked-down
blocks.
•WhenWP#returnsto0,locked-downblocksreturntoLock-Down.
•Lock-Downisclearedonlywhenthedeviceisresetorpowered-down.
ThelockingstatusofeachblockcansettoLocked,Unlocked,andLock-Down,eachofwhichwill
bedescribedinthefollowingsections.Acomprehensivestatetableforthelockingfunctionsis
showninTable8onpage 21,andaflowchartforlockingoperationsisshowninFigure19on
page 50.
3.7.2 LockedState
Thedefaultstatusofallblocksuponpower-uporresetislocked(states[001]or[101]).Locked
blocksarefullyprotectedfromalteration.Anyprogramoreraseoperationsattemptedonalocked
blockwillreturnanerroronbitSR.1ofthestatusregister.Thestatusofalockedblockcanbe
changedtoUnlockedorLock-Downusingtheappropriatesoftwarecommands.Unlockedblocks
canbelockedissuingthe“Lock”commandsequence,60hfollowedby01h.
3.7.3 UnlockedState
Unlockedblocks(states[000],[100],[110])canbeprogrammedorerased.Allunlockedblocks
returntotheLockedstatewhenthedeviceisresetorpowereddown.Thestatusofanunlocked
blockcanbechangedtoLockedorLocked-Downusingtheappropriatesoftwarecommands.A
LockedblockcanbeunlockedbywritingtheUnlockcommandsequence,60hfollowedbyD0h.
3.7.4 Lock-DownState
BlocksthatareLocked-Down(state[011])areprotectedfromprogramanderaseoperations(just
likeLockedblocks),buttheirprotectionstatuscannotbechangedusingsoftwarecommandsalone.
ALockedorUnlockedblockcanbeLocked-downbywritingtheLock-Downcommandsequence,
60hfollowedby2Fh.Locked-DownblocksreverttotheLockedstatewhenthedeviceisresetor
powereddown.
TheLock-DownfunctionisdependentontheWP#inputball.WhenWP# = 0,blocksinLock-
Down[011]areprotectedfromprogram,erase,andlockstatuschanges.WhenWP# = 1,theLock-
Downfunctionisdisabled([111])andlocked-downblockscanbeindividuallyunlockedby
softwarecommandtothe[110]state,wheretheycanbeerasedandprogrammed.Theseblockscan
thenbere-locked[111]andunlocked[110]asdesiredwhileWP#remainshigh.WhenWP#goes
low,blocksthatwerepreviouslylocked-downreturntotheLock-Downstate[011]regardlessof
anychangesmadewhileWP#washigh.Deviceresetorpower-downresetsallblocks,including
thoseinLock-Down,toLockedstate.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
20 Datasheet
3.7.5 ReadingaBlock’sLockStatus
Thelockstatusofeveryblockcanbereadintheconfigurationreadmodeofthedevice.Toenter
thismode,write90htothedevice.SubsequentreadsatBlockAddress+00002willoutputthelock
statusofthatblock.Thelockstatusisrepresentedbytheleastsignificantoutputs,DQ0andDQ1.
DQ0indicatestheBlockLock/UnlockstatusandissetbytheLockcommandandclearedbythe
Unlockcommand.ItisalsoautomaticallysetwhenenteringLock-Down.DQ1indicatesLock-
DownstatusandissetbytheLock-Downcommand.Itcannotbeclearedbysoftware,onlyby
deviceresetorpower-down.
3.7.6 LockingOperationduringEraseSuspend
Changestoblocklockstatuscanbeperformedduringanerasesuspendbyusingthestandard
lockingcommandsequencestounlock,lock,orlock-downablock.Thisisusefulinthecasewhen
anotherblockneedstobeupdatedwhileaneraseoperationisinprogress.
Tochangeblocklockingduringaneraseoperation,firstwritetheerasesuspendcommand(B0h),
thencheckthestatusregisteruntilitindicatesthattheeraseoperationhasbeensuspended.Next
writethedesiredlockcommandsequencetoablockandthelockstatuswillbechanged.After
completinganydesiredlock,read,orprogramoperations,resumetheeraseoperationwiththe
EraseResumecommand(D0h).
Ifablockislockedorlocked-downduringasuspendederaseofthesameblock,thelockingstatus
bitswillbechangedimmediately,butwhentheeraseisresumed,theeraseoperationwillcomplete.
Lockingoperationscannotbeperformedduringaprogramsuspend.
3.7.7 StatusRegisterErrorChecking
Usingnestedlockingorprogramcommandsequencesduringerasesuspendcanintroduce
ambiguityintostatusregisterresults.
Sincelockingchangesareperformedusingatwocyclecommandsequence,e.g.,60hfollowedby
01htolockablock,followingtheConfigurationSetupcommand(60h)withaninvalidcommand
willproducealockcommanderror(SR.4andSR.5willbesetto1)inthestatusregister.Ifalock
commanderroroccursduringanerasesuspend,SR.4andSR.5willbesetto1,andwillremainat1
aftertheeraseisresumed.Wheneraseiscomplete,anypossibleerrorduringtheerasecannotbe
detectedviathestatusregisterbecauseofthepreviouslockingcommanderror.
Asimilarsituationhappensifanerroroccursduringaprogramoperationerrornestedwithinan
erasesuspend.
Table7. BlockLockStatus
Item Address Data
BlockLockConfiguration XX002 LOCK
•BlockIsUnlocked DQ0=0
•BlockIsLocked DQ0=1
•BlockIsLocked-Down DQ1=1
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 21
3.8 128BitProtectionRegister
The3 VoltIntel®
Advanced+Stacked-CSParchitectureincludesa128-bitprotectionregisterthan
canbeusedtoincreasethesecurityofasystemdesign.Forexample,thenumbercontainedinthe
protectionregistercanbeusedto“mate”theflashcomponentwithothersystemcomponentssuch
astheCPUorASIC,preventingdevicesubstitution.
3.8.1 ReadingtheProtectionRegister
Theprotectionregisterisreadintheconfigurationreadmode.Thedeviceisswitchedtothismode
bywritingtheReadConfigurationcommand(90h).Onceinthismode,readcyclesfromaddresses
showninAppendixEretrievethespecifiedinformation.Toreturntoreadarraymode,writethe
ReadArraycommand(FFh).
3.8.2 ProgrammingtheProtectionRegister(C0h)
Theprotectionregisterbitsareprogrammedusingthetwo-cycleProtectionProgramcommand.
The64-bitnumberisprogrammed16bitsatatimeforword-wideparts.FirstwritetheProtection
ProgramSetupcommand,C0h.Thenextwritetothedevicewilllatchinaddressanddataand
programthespecifiedlocation.TheallowableaddressesareshowninAppendixE.SeeFigure20,
“ProtectionRegisterProgrammingFlowchart”onpage 51.
Table8. BlockLockingStateTransitions
CurrentState Erase/
Program
Allowed?
NextStateafterCommandInput
WP# DQ1DQ0Name Lock Unlock Lock-Down
0 0 0 Unlocked Yes GoTo[001] – GoTo[011]
1 0 0 Unlocked Yes GoTo[101] – GoTo[111]
0 0 1 Locked(Default) No – GoTo[000] GoTo[011]
1 0 1 Locked No – GoTo[100] GoTo[111]
0 1 1 Locked-Down No – – –
110 Lock-Down
Disabled Yes GoTo[111] – GoTo[111]
111 No - GoTo[110] –
NOTES:
1. “–”indicatesnochangeinthecurrentstate.
2. Inthistable,thenotation[XYZ]denotesthelockingstateofablock,whereX=WP#,Y=DQ
1,andZ=DQ
0.Thecurrent
lockingstateofablockisdefinedbythestateofWP#andthetwobitsoftheblocklockstatus(DQ0,DQ1).DQ0indicatesifa
blockislocked(1)orunlocked(0).DQ1indicatesifablockhasbeenlocked-down(1)ornot(0).
3. Atpower-upordevicereset,allblocksdefaulttoLockedstate[001](ifWP# = 0).holdingWP# = 0istherecommended
default.
4. The“Erase/ProgramAllowed?”columnshowswhethereraseandprogramoperationsareenabled(Yes)ordisabled(No)in
thatblock’scurrentlockingstate.
5. The“LockCommandInputResult[NextState]”columnshowstheresultofwritingthethreelockingcommands(Lock,Unlock,
Lock-Down)inthecurrentlockingstate.Forexample,“GoesTo[001]”wouldmeanthatwritingthecommandtoablockinthe
currentlockingstatewouldchangeitto[001].
6. The128bitsoftheprotectionregisteraredividedintotwo64-bitsegments.OneofthesegmentsisprogrammedattheIntel
factorywithaunique64bitnumber,whichisunchangeable.Theothersegmentisleftblankforcustomerdesignstoprogram
asdesired.Oncethecustomersegmentisprogrammed,itcanbelockedtopreventreprogramming.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
22 Datasheet
AnyattempttoaddressProtectionProgramcommandsoutsidethedefinedprotectionregister
addressspacewillresultinastatusregistererror(programerrorbitSR.4willbesetto1).
Attemptingtoprogramortoapreviouslylockedprotectionregistersegmentwillresultinastatus
registererror(programerrorbitSR.4andlockerrorbitSR.1willbesetto1).
3.8.3 LockingtheProtectionRegister
Theuser-programmablesegmentoftheprotectionregisterislockablebyprogrammingBit1ofthe
PR-LOCKlocationto0.Bit0ofthislocationisprogrammedto0attheIntelfactorytoprotectthe
uniquedevicenumber.ThisbitissetusingtheProtectionProgramcommandtoprogramFFFDhto
thePR-LOCKlocation.Afterthesebitshavebeenprogrammed,nofurtherchangescanbemadeto
thevaluesstoredintheprotectionregister.AProtectionProgramcommandtolockedwordswill
resultinastatusregistererror(programerrorbitSR.4andLockErrorbitSR.1willbesetto1).
Theprotectionregisterlockoutstateisnotreversible.
0645_05
Figure3.ProtectionRegisterMemoryMap
4Words
FactoryProgrammed
4Words
UserProgrammed
PR-LOCK
88H
85H
84H
81H
80H
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 23
4.0 PowerandResetConsiderations
4.1 Power-Up/DownCharacteristics
Inordertopreventanyconditionthatmayresultinaspuriouswriteoreraseoperation,itis
recommendedtopower-upF-VCC,F-VCCQandS-VCCtogether.Conversely,F-VCC,F-VCCQand
S-VCCmustpower-downtogether.Itisalsorecommendedtopower-upF-VPPwithorslightlyafter
F-VCC.Conversely,F-VPPmustpowerdownwithorslightlybeforeF-VCC.
IfF-VCCQand/orF-VPParenotconnectedtotheF-VCCsupply,thenF-VCCshouldattainF-
VCCMinbeforeapplyingF-VCCQandF-VPP.Deviceinputsshouldnotbedrivenbeforesupply
voltage=F-VCCMin.PowersupplytransitionsshouldonlyoccurwhenF-RP#islow.
4.2 AdditionalFlashFeatures
Intel3VoltAdvanced+Stacked-CSPproductsprovidein-systemprogramminganderaseinthe
1.65 V–3.3 Vrange.Forfastproductionprogramming,italsoincludesalow-cost,backward-
compatible12 Vprogrammingfeature.
4.2.1 Improved12 VoltProductionProgramming
WhenF-VPPisbetween1.65 Vand3.3 V,allprogramanderasecurrentisdrawnthroughthe
F-VCCsignal.NotethatifF-VPPisdrivenbyalogicsignal,VIH min=1.65 V.Thatis,F-VPP
must
remainabove1.65 Vtoperformin-systemflashmodifications.WhenF-VPPisconnectedtoa12 V
powersupply,thedevicedrawsprogramanderasecurrentdirectlyfromtheF-VPPsignal.This
eliminatestheneedforanexternalswitchingtransistortocontrolthevoltageF-VPP.Figure12,
“ExamplePowerSupplyConfigurations”onpage 42showsexamplesofhowtheflashpower
suppliescanbeconfiguredforvarioususagemodels.
The12 VF-VPPmodeenhancesprogrammingperformanceduringtheshortperiodoftime
typicallyfoundinmanufacturingprocesses;however,itisnotintendedforextendeduse.12 Vmay
beappliedtoF-VPPduringprogramanderaseoperationsforamaximumof1000cyclesonthe
mainblocksand2500cyclesontheparameterblocks.F-VPPmaybeconnectedto12 Vforatotal
of80hoursmaximum.Stressingthedevicebeyondtheselimitsmaycausepermanentdamage.
4.2.2 F-VPP≤ VPPLKforCompleteProtection
Inadditiontotheflexibleblocklocking,theF-VPPprogrammingvoltagecanbeheldlowfor
absolutehardwarewriteprotectionofallblocksintheflashdevice.WhenF-VPPisbelowVPPLK,
anyprogramoreraseoperationwillresultinaerror,promptingthecorrespondingstatusregisterbit
(SR.3)tobeset.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
24 Datasheet
5.0 ElectricalSpecifications
5.1 AbsoluteMaximumRatings
Warning: Stressingthedevicebeyondthe“AbsoluteMaximumRatings”maycausepermanentdamage.
Thesearestressratingsonly.Operationbeyondthe“OperatingConditions”isnotrecommended
andextendedexposurebeyondthe“OperatingConditions”mayaffectdevicereliability.
NOTICE:Thisdatasheetcontainsinformationonproductsinfullproduction.Thespecificationsaresubjectto
changewithoutnotice.VerifywithyourlocalIntelSalesofficethatyouhavethelatestdatasheetbeforefinalizinga
design.
Table9. AbsoluteMaximumRatings
Parameter MaximumRating Notes
ExtendedOperatingTemperature
–25°Cto+85°C
DuringRead
DuringFlashBlockEraseandProgram
TemperatureunderBias
StorageTemperature –65°Cto+125°C
VoltageonAnyBall(exceptF-VCC
/F-VCCQ
/S-VCC
andF-VPP)with
RespecttoGND –0.5 Vto+3.3 V 1
F-VPPVoltage(forBlockEraseandProgram)withRespecttoGND –0.5Vto+13.5 V 1,2,4
F-VCC
/F-VCCQ
/S-VCC
SupplyVoltagewithRespecttoGND –0.2Vto+3.3 V
OutputShortCircuitCurrent 100mA 3
NOTES:
1. MinimumDCvoltageis–0.5 Voninput/outputballs.Duringtransitions,thislevelmayundershootto–
2.0 Vforperiods<20 ns.MaximumDCvoltageoninput/outputballsisF-VCC
/F-VCCQ
/S-VCC
+0.5 V
which,duringtransitions,mayovershootto
F-VCC
/F-VCCQ
/S-VCC
+2.0 Vforperiods< 20ns.
2. MaximumDCvoltageonF-VPPmayovershootto+14.0 Vforperiods<20ns.
3. F-VPPvoltageisnormally1.65 V–3.3 V.Connectiontosupplyof11.4 V–12.6 Vcanonlybedonefor
1000cyclesonthemainblocksand2500cyclesontheparameterblocksduringprogram/erase.F-VPP
maybeconnectedto12 Vforatotalof80hoursmaximum.SeeSection4.2.1fordetails
4. Outputshortedfornomorethanonesecond.
Nomorethanoneoutputshortedatatime.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 25
5.2 OperatingConditions
5.3 Capacitance
TCASE=+25°C,f=1MHz
Table10.TemperatureandVoltageOperatingConditions
Symbol Parameter Notes Min Max Units
TCASE OperatingTemperature –25 +85 °C
VCC
/VCCQ F-VCC
/F-VCCQ
/S-VCCSupply
Voltage 12.73.3Volts
VPP1 SupplyVoltage 1 1.65 3.3 Volts
VPP2 1,2 11.4 12.6 Volts
Cycling BlockEraseCycling 2 100,000 Cycles
NOTES:
1. F-VCC/F-VCCQmustsharethesamesupply.F-VCC/S-VCCmustsharethesamesupplywhennotindata
retention.
2. ApplyingF-VPP = 11.4 V–12.6 Vduringaprogram/erasecanonlybedoneforamaximumof1000cycles
onthemainblocksand2500cyclesontheparameterblocks.F-VPPmaybeconnectedto12 Vforatotal
of80hoursmaximum.SeeSection4.2.1fordetails.
Sym Parameter Notes Typ Max Units Conditions
CIN InputCapacitance 1 16 18 pF VIN =0V
COUT OutputCapacitance 1 20 22 pF VOUT =0V
NOTE: Sampled,not100%tested.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
26 Datasheet
5.4 DCCharacteristics
Table11.DCCharacteristics(Sheet1of2)
Symbol Parameter Device Note 2.7V–3.3VUnit TestConditions
Typ Max
ILI InputLoadCurrent Flash/
SRAM 1±2µA
F-VCC/S-VCC =V
CC
Max
VIN =V
CCMaxorGND
ILO OutputLeakageCurrent Flash/
SRAM 10.2±10 µA F-VCC/S-VCC =V
CC
Max
VIN =V
CC
MaxorGND
ICCS VCC
StandbyCurrent
0.25µm
Flash 11025
µA
F-VCC =V
CC
Max
F-CE# = F-RP# = VCC
F-WP# = VCCorGND
VIN =V
CC
MaxorGND
0.13µm
and
0.18µm
Flash
1715
2-Mb
SRAM 1-10µA
S-VCC =V
CC
Max
S-CS1#=VCC,S-CS2 =VCC
orS-CS2 =GND
VIN =V
CC
MaxorGND
4-Mb
SRAM 1-15µA
8-Mb
SRAM 1-25µA
ICCD VCCDeepPower-DownCurrent
0.25µm
Flash 1725
µA F-VCC =V
CCMax
VIN =V
CC
MaxorGND
F-RP# = GND±0.2 V
0.13µm
and
0.18µm
Flash
1715
ICC OperatingPowerSupplyCurrent
(cycletime=1µs)
2-Mb
SRAM 1-7mA
IIO =0mA,S-CS1# = VIL
S-CS2 =S-WE#=V
IH
VIN =V
ILorVIH
4-Mb
SRAM 1-10mA
8-Mb
SRAM 1-10mA
ICC2 OperatingPowerSupplyCurrent
(mincycletime)
2-Mb
SRAM 1-40mA
Cycletime=Min,100%duty,
IIO =0mA,S-CS1# =VIL,
S-CS2= VIH,VIN=V
ILorVIH
4-Mb
SRAM 1-45mA
8-Mb
SRAM 1-50mA
ICCR VCCReadCurrent
0.25µm
Flash 1,2 10 18 mA F-VCC =V
CCMax
F-OE# = VIH,F-CE# = VIL
f=5MHz,IOUT =0mA
VIN =V
ILorVIH
0.13µm
and
0.18µm
Flash
1,2 9 18 mA
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 27
ICCW VCCProgramCurrent Flash 1,3
18 55 mA F-VPP =V
PP1
PrograminProgress
822mA
F-VPP =V
PP2(12 V)
PrograminProgress
ICCE VCCEraseCurrent Flash 1,3
16 45 mA F-VPP =V
PP1
EraseinProgress
815mA
F-VPP =V
PP2
(12 V)
EraseinProgress
ICCES VCCEraseSuspendCurrent Flash 1,3,4 7 15 µA F-CE# = VCC,EraseSuspend
inProgress
ICCWS VCCProgramSuspendCurrent
0.25µm
Flash 1,3,4 10 25
µA F-CE# = VCC,Program
SuspendinProgress
0.13µm
and
0.18µm
Flash
1,3,4 7 15
IPPD F-VPPDeepPower-DownCurrent Flash 1 0.2 5 µA F-RP# = GND±0.2 V
F-VPP
≤VCC
IPPS F-VPPStandbyCurrent Flash 1 0.2 5 µA F-VPP
≤VCC
IPPR F-VPPReadCurrent Flash 12±15 µA F-VPP
≤VCC
1,2 50 200 µA F-VPP
≥VCC
IPPW F-VPPProgramCurrent Flash 1,2
0.05 0.1 mA F-VPP =VPP1
PrograminProgress
822mA
F-VPP =V
PP2
(12 V)
PrograminProgress
IPPE F-VPPEraseCurrent Flash 1,2 0.05 0.1 ma F-VPP =V
PP1
EraseinProgress
IPPES F-VPPEraseSuspendCurrent Flash 1,2
0.2 5 µA F-VPP =V
PP1
EraseSuspendinProgress
50 200 µA F-VPP =V
PP2
(12 V)
EraseSuspendinProgress
IPPWS F-VPPProgramSuspendCurrent Flash 1,2 0.2 5 µA F-VPP =V
PP1
ProgramSuspendinProgress
50 200 µA F-VPP =V
PP2
(12 V)
ProgramSuspendinProgress
NOTES:
1. AllcurrentsareinRMSunlessotherwisenoted.TypicalvaluesatnominalF-VCC/S-VCC,TCASE =+25°C.
2. AutomaticPowerSavings(APS)reducesICCRtoapproximatelystandbylevelsinstaticoperation(CMOSinputs).
3. Sampled,not100%tested.
4. ICCESandICCWSarespecifiedwithdevicede-selected.Ifdeviceisreadwhileinerasesuspend,currentdrawissumofICCES
andICCR.Ifthedeviceisreadwhileinprogramsuspend,currentdrawisthesumofICCWSandICCR.
Table11.DCCharacteristics(Sheet2of2)
Symbol Parameter Device Note 2.7V–3.3VUnit TestConditions
Typ Max
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
28 Datasheet
0645_07
0666_05
NOTE: CLincludesjigcapacitance.
Table12.DCCharacteristics
Symbol Parameter Device Note 2.7V–3.3VUnits TestConditions
Min Max
VIL InputLowVoltage Flash/
SRAM –0.2 0.6 V
VIH InputHighVoltage Flash/
SRAM 2.3 VCC
+0.2 V
VOL OutputLowVoltage Flash/
SRAM –0.10 0.10 V F-VCC/S-VCC =V
CC
Min
IOL =100µA
VOH OutputHighVoltage Flash/
SRAM VCC–
0.1 V
F-VCC/S-VCC =V
CC
Min
IOH = –100µA
VPPLK F-VPPLock-OutVoltage Flash 1 1.0 V CompleteWriteProtection
VPP1 F-VPPduringProgram/Erase Flash 1 1.65 3.3 V
VPP2 Operations 1,2 11.4 12.6
VLKO VCC
Prog/EraseLockVoltage Flash 1.5 V
VLKO2 VCCQ
Prog/EraseLockVoltage Flash 1.2 V
NOTES:
1. EraseandProgramareinhibitedwhenF-Vpp<VPPLKandnotguaranteedoutsidethevalidF-VpprangesofVPP1andVPP2.
2. ApplyingF-Vpp=11.4V–12.6Vduringprogram/erasecanonlybedoneforamaximumof1000cyclesonthemainblocksand
2500cyclesontheparameterblocks.F-Vppmaybeconnectedto12Vforatotalof80hoursmaximum.SeeSection4.2.1for
details.
Figure4.Input/OutputReferenceWaveform
NOTE: ACtestinputsaredrivenatVCCQforalogic“1”and0.0Vforalogic“0.”Inputtimingbegins,andoutput
timingends,atVCCQ/2.Inputriseandfalltimes(10%–90%)<10ns.Worstcasespeedconditionsare
whenVCCQ
=VCCQMin.
INPUT OUTPUT
TESTPOINTS
VCC
0.0
VCC
2VCC
2
Figure5.TestConfiguration
Device
UnderTest Out
CL
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 29
5.5 FlashACCharacteristics.
FlashTestConfigurationComponentValuesTable
TestConfiguration CL(pF)
2.7 V–3.3 VStandardTest 50
Table13.FlashACCharacteristics—ReadOperations
# Sym Parameter
Density 16-Mbit 32-Mbit
Unit
Product -70 -90 -110 -70 -90
VoltageRange 2.7V-3.3V
Note Min Max Min Max Min Max Min Max Min Max
R1 tAVAV ReadCycleTime 70 90 110 70 90 ns
R2 tAVQV AddresstoOutputDelay 70 90 110 70 90 ns
R3 tELQV F-CE#toOutputDelay 1 70 90 110 70 90 ns
R4 tGLQV F-OE#toOutputDelay 1 20 30 30 20 20 ns
R5 tPHQV F-RP#toOutputDelay 150 150 150 150 150 ns
R6 tELQX F-CE#toOutputinLowZ 200000ns
R7 tGLQX F-OE#toOutputinLowZ 200000ns
R8 tEHQZ F-CE#toOutputinHighZ 2 20 25 25 20 20 ns
R9 tGHQZ F-OE#toOutputinHighZ 2 20 20 20 20 20 ns
R10 tOH
OutputHoldfromAddress
F-CE#,orF-OE#Change,
WhicheverOccursFirst 200000ns
NOTES:
1. F-OE#maybedelayeduptotELQV–tGLQVafterthefallingedgeofCE#withoutimpactontELQV
2. Sampled,butnot100%tested.
3. SeeFigure6,“ACWaveform:FlashReadOperations”onpage 30.
4. SeeFigure4,“Input/OutputReferenceWaveform”onpage28fortimingmeasurementsandmaximumallowableinputslew
rate.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
30 Datasheet
Figure6.ACWaveform:FlashReadOperations
A
ddress Stable
Device and
A
ddress Selection
IH
V
IL
V
A
DDRESSES (
A
)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
CE# (E)
OE# (G)
WE# (W)
D
A
T
A
(D/Q)
IH
V
IL
V
RP#(P)
OL
V
OH
VHigh Z Valid Output
Data
Valid Standby
High Z
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 31
5.6 FlashACCharacteristics—WriteOperations
SeeFigure4,“Input/OutputReferenceWaveform”onpage 28fortimingmeasurementsandmaximum
allowableinputslewrate.
SeeFigure7,“ACWaveform:FlashProgramandEraseOperations”onpage 33.
5.7 FlashEraseandProgramTimings(1)
Table14.FlashACCharacteristics—WriteOperations
# Sym Parameter
Density 16-Mbit 32-Mbit
Unit
Product -70 -90 -110 -70 -90
VoltageRange 2.7V-3.3V
Note Min Min Min Min Min
W1 tPHWLtPHEL F-RP#HighRecoverytoF-WE#(F-CE#)GoingLow 150 150 150 150 150 ns
W2 tELWLtWLEL F-CE#(F-WE#)SetuptoF-WE#(F-CE#)GoingLow 0 0 0 0 0 ns
W3 tELEHtWLWH F-WE#(F-CE#)PulseWidth 1 45 60 70 45 60 ns
W4 tDVWHtDVEH DataSetuptoF-WE#(F-CE#)GoingHigh 2 40 50 60 40 40 ns
W5 tAVWHtAVEH AddressSetuptoF-WE#(F-CE#)GoingHigh 2 50 60 70 50 60 ns
W6 tWHEHtEHWH F-CE#(F-WE#)HoldTimefromF-WE#(F-CE#)High 0 0 0 0 0 ns
W7 tWHDXtEHDX DataHoldTimefromF-WE#(F-CE#)High 2 0 0 0 0 0 ns
W8 tWHAXtEHAX AddressHoldTimefromF-WE#(F-CE#)High 2 0 0 0 0 0 ns
W9 tWHWL
tEHEL F-WE#(F-CE#)PulseWidthHigh 1 25 30 30 25 30 ns
W10 tVPWHtVPEH F-VPPSetuptoF-WE#(F-CE#)GoingHigh 3 200 200 200 200 200 ns
W11 tQVVL F-VPP
HoldfromValidSRD 3 00000ns
NOTES:
1. Writepulsewidth(tWP)isdefinedfromF-CE#orF-WE#goinglow(whichevergoeslowlast)
toF-CE#or
F-WE#goinghigh(whichevergoeshighfirst).Hence,tWP=t
WLWH =t
ELEH =t
WLEH=t
ELWH.Similarly,writepulsewidthhigh
(tWPH)isdefinedfromF-CE#orF-WE#goinghigh(whichevergoeshighfirst)
toF-CE#or
F-WE#goinglow(whichevergoeslowfirst).Hence,tWPH =t
WHWL=t
EHEL =t
WHEL=t
EHWL.
2. RefertoTable 5,“FlashMemoryCommandDefinitions”onpage 17forvalidAINorDIN.
3. Sampled,butnot100%tested.
Table15.FlashEraseandProgramTimings(Sheet1of2)
Symbol Parameter F-VPP 1.65V–3.3V 11.4V–12.6VUnit
Note Typ(1) Max Typ(1) Max
tBWPB 4-KWParameterBlockProgramTime(Word) 2,30.100.300.030.12 s
tBWMB 32-KWMainBlockProgramTime(Word) 2,3 0.8 2.4 0.24 1 s
tWHQV1
/tEHQV1 0.25µmWordProgramTime 2,322200 8 185µs
0.13µmand0.18µmWordProgramTime 2,312200 8 185
tWHQV2/tEHQV2 4-KWParameterBlockEraseTime(Word) 2,30.540.44 s
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
32 Datasheet
tWHQV3/tEHQV3 32-KWMainBlockEraseTime(Word) 2,31 50.65 s
tWHRH1/tEHRH1 ProgramSuspendLatency 3 5 10 5 10 µs
tWHRH2/tEHRH2 EraseSuspendLatency 3 5 20 5 20 µs
NOTES:
1. TypicalvaluesmeasuredatTCASE =+25°Candnominalvoltages.
2. Excludesexternalsystem-leveloverhead.
3. Sampled,butnot100%tested.
Table15.FlashEraseandProgramTimings(Sheet2of2)
Symbol Parameter F-VPP 1.65V–3.3V 11.4V–12.6VUnit
Note Typ(1) Max Typ(1) Max
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 33
NOTES:
1. F-CE#mustbetoggledlowwhenreadingStatusRegisterData.F-WE#mustbeinactive(high)whenreading
StatusRegisterData.
A. F-VCC
Power-UpandStandby.
B. WriteProgramorEraseSetupCommand.
C. WriteValidAddressandData(forProgram)orEraseConfirmCommand.
D. AutomatedProgramorEraseDelay.
E. ReadStatusRegisterData(SRD):reflectscompletedprogram/eraseoperation.
F. WriteReadArrayCommand.
Figure7.ACWaveform:FlashProgramandEraseOperations
ADDRESSES[A]
CE#(WE#)[E(W)]
OE#[G]
WE#(CE#)[W(E)]
DATA[D/Q]
RP#[P]
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IL
V
IL
V
IN
D
IN
AIN
A
Valid
SRD
IN
D
IH
V
HighZ
IH
V
IL
V
V[V]
PP
PPH
V
PPLK
VPPH
V1
2
WP# IL
V
IH
V
IN
D
AB C D E F
W8
W6
W9
W3
W4
W7
W1
W5
W2
W10 W11
(Note1)
(Note1)
ADDRESSES[A]
CE#(WE#)[E(W)]
OE#[G]
WE#(CE#)[W(E)]
DATA[D/Q]
RP#[P]
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IL
V
IL
V
IN
D
IN
AIN
A
Valid
SRD
IN
D
IH
V
HighZ
IH
V
IL
V
V[V]
PP
PPH
V
PPLK
VPPH
V1
2
WP# IL
V
IH
V
IN
D
AB C D E F
W8
W6
W9
W3
W4
W7
W1
W5
W2
W10 W11
(Note1)
(Note1)
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
34 Datasheet
5.8 FlashResetOperations
Figure8.ACWaveform:ResetOperation
Table16.ResetSpecifications(1)
Symbol Parameter Note F-VCC2.7V–3.3VUnit
Min Max
tPLPH F-RP#LowtoResetduringRead(IfF-RP#istied
toVCC,thisspecificationisnotapplicable) 2,4 100 ns
tPLRH1 F-RP#LowtoResetduringBlockErase 3,4 22 µs
tPLRH2 F-RP#LowtoResetduringProgram 3,4 12 µs
NOTES:
1. SeeSection2.1.4,“FlashReset”onpage 13forafulldescriptionoftheseconditions.
2. IftPLPHis<100nsthedevicemaystillresetbutthisisnotguaranteed.
3. IfF-RP#isassertedwhileablockeraseor
wordprogramoperationisnotexecuting,theresetwillcomplete
within100ns.
4. Sampled,butnot100%tested.
IH
V
IL
V
RP#(P)
PLPH
t
IH
V
IL
V
RP#(P)
PLPH
t
(A)ResetduringReadMode
Abort
Complete PHQV
tPHWL
tPHEL
t
PHQV
tPHWL
tPHEL
t
(B)ResetduringProgramorBlockErase,<
PLPH
tPLR
H
t
PLRH
t
IH
V
IL
V
RP#(P)
PLPH
t
Abort
Complete PHQV
tPHWL
tPHEL
t
PLRH
t
Deep
Power-
Down
(C)ResetProgramorBlockErase,>
PLPH
tPLRH
t
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 35
5.9 SRAMACCharacteristics—ReadOperations
Table17.SRAMACCharacteristics—ReadOperations(1)
#Sym Parameter
Density 2/4/8-Mbit
UnitVoltageRange 2.7V–3.3V
Note Min Max
R1 tRC ReadCycleTime 70 – ns
R2 tAA AddresstoOutputDelay – 70 ns
R3 tCO1,tCO2 S-CS1#,S-CS2toOutputDelay – 70 ns
R4 tOE S-OE#toOutputDelay – 35 ns
R5 tBA S-UB#,LB#toOutputDelay – 70 ns
R6 tLZ1,tLZ2 S-CS1#,S-CS2toOutputinLowZ2,35–ns
R7 tOLZ S-OE#toOutputinLowZ30–ns
R8 tHZ1,tHZ2 S-CS1#,S-CS2toOutputinHighZ 2,3,4 0 25 ns
R9 tOHZ S-OE#toOutputinHighZ3,4025ns
R10 tOH OutputHoldfromAddress,S-CS1#,
S-CS2,orS-OE#Change,WhicheverOccurs
First 0–ns
R11 tBLZ S-UB#,S-LB#toOutputinLowZ30–ns
R12 tBHZ S-UB#,S-LB#toOutputinHighZ3025ns
NOTE:
1. SeeFigure9,“ACWaveform:SRAMReadOperations”onpage 36.
2. Atanygiventemperatureandvoltagecondition,tHZ(Max)islessthanandtLZ(Max)bothforagiven
deviceandfromdevicetodeviceinterconnection.
3. Sampled,butnot100%tested.
4. TimingsoftHZandtOHZaredefinedasthetimeatwhichtheoutputsachievetheopencircuitconditions
andarenotreferencedtooutputvoltagelevels.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
36 Datasheet
Figure9.ACWaveform:SRAMReadOperations
HighZ
ValidOutput
AddressStable
DataValid
Device
AddressSelection
Standby
ADDRESSES(A)
V
IH
V
IL
V
IH
V
IL
CS
1
#(E
1
)
V
IH
V
IL
V
OH
V
OL
V
IH
OE#(G)
WE#(W)
DATA(D/Q)
UB#,LB#
HighZ
V
IH
V
IL
R1
R2
R4
R3
R6
R7
R8
R9
R10
CS
2
(E
2
)
V
IH
V
IL
V
IH
R5
R11 R12
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 37
5.10 SRAMACCharacteristics—WriteOperations
Table18.SRAMACCharacteristics—WriteOperations(1,2)
#Sym Parameter
Density 2/4/8-Mbit
UnitVolt 2.7V–3.3V
Note Min Max
W1 tWC WriteCycleTime 70 – ns
W2 tAS AddressSetuptoS-WE#(S-CS1#)andS-UB#,
S-LB#GoingLow 30–
ns
W3 tWP S-WE#(S-CS1#)PulseWidth 4 55 – ns
W4 tDW DatatoWriteTimeOverlap 30 – ns
W5 tAW AddressSetuptoS-WE#(S-CS1#)GoingHigh 60 – ns
W6 tCW S-CE#(S-WE#)SetuptoS-WE#(S-CS1#)Going
High 60 – ns
W7 tDH DataHoldTimefromS-WE#(S-CS1#)High 0 – ns
W8 tWR WriteRecovery 5 0 – ns
W9 tBW S-UB#,S-LB#SetuptoS-WE#(S-CS1#)Going
High 60 – ns
NOTES:
1. SeeFigure10,“ACWaveform:SRAMWriteOperations”onpage 38.
2. Awriteoccursduringtheoverlap(tWP)oflowS-CS1#andlowS-WE#.AwritebeginswhenS-CS1#goes
lowandS-WE#goeslowwithassertingS-UB#orS-LB#forsinglebyteoperationorsimultaneously
asserting
S-UB#andS-LB#fordoublebyteoperation.AwriteendsattheearliesttransitionwhenS-CS1#goeshigh
andS-WE#goeshigh.ThetWPismeasuredfromthebeginningofwritetotheendofwrite.
3. tASismeasuredfromtheaddressvalidtothebeginningofwrite.
4. tWPismeasuredfromS-CS1#goinglowtoendofwrite.
5. tWRismeasuredfromtheendofwritetotheaddresschange.tWRappliedincaseawriteendsasS-CS1#
orS-WE#goinghigh.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
38 Datasheet
Figure10.ACWaveform:SRAMWriteOperations
HighZ
DataIn
AddressStable
Device
AddressSelection
Standby
ADDRESSES(A)
V
IH
V
IL
V
IH
V
IL
CS
1
#(E
1
)
V
IH
V
IL
V
OH
V
OL
V
IH
OE#(G)
WE#(W)
DATA(D/Q)
UB#,LB#
HighZ
V
IH
V
IL
W1
W8
CS
2
(E
2
)
V
IH
V
IL
V
IH
W9
W6
W5
W2
W3
W4 W7
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 39
5.11 SRAMDataRetentionCharacteristics—Extended
Temperature
Table19.SRAMDataRetentionCharacteristics(1)—ExtendedTemperature
Sym Parameter Note Min Typ Max Unit TestConditions
VDR S-VCCforDataRetention
2
1.5 – 3.3 V CS1#≥VCC–0.2 V
IDR
DeepRetentionCurrent-
8-Mbit ––6µA
S-VCC=1.5V
CS1#≥VCC–0.2 V
DeepRetentionCurrent-
4-Mbit ––5µA
DeepRetentionCurrent-
2-Mbit ––4µA
tSDR DataRetentionSet-upTime 0 – – ns SeeDataRetentionWaveform
tRDR RecoveryTime tRC ––ns
NOTES:
1. TypicalvaluesatnominalS-VCC,TCASE =+25°C.
2. S-CS1#≥ VCC–0.2 V,S-CS2≥ VCC–0.2 V(S-CS1#controlled)orS-CS2≤0.2 V(S-CS2controlled).
Figure11.SRAMDataRetentionWaveform
V
CC
3.0/2.7V
CS
1
#(E
1
)
2.2V
V
DR
CS
2
(E
2
)
GND
V
CC
3.0/2.7V
0.4V
V
DR
GND
CS
1
#Controlled
CS
2
Controlled
DataRetentionModet
SDR
t
RDR
DataRetentionMode
t
SDR
t
RDR
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
40 Datasheet
6.0 MigrationGuideInformation
Typically,itisimportanttodiscussfootprintmigrationcompatibilitybetweenanewproductand
existingproducts.Inthisspecificcase,theStacked-CSPallowsthesystemdesignertoremovetwo
separatememoryfootprintsforindividualflashandSRAMandreplacethemwithasingle
footprint,thusresultinginanoverallreductioninboardspacerequired.Thisimpliesthatanew
printedcircuitboardwouldbeusedtotakeadvantageofthisfeature.
SincetheflashinStacked-CSPsharesthesamefeaturesastheAdvanced+BootBlockFeatures,
conversionsfromtheAdvancedBootBlockaredescribedinAP-658DesigningforUpgradetothe
Advanced+BootBlockFlashMemory,ordernumber292216.
PleasecontactyourlocalIntelrepresentationfordetailedinformationaboutspecificFlash+
SRAMsystemmigrations.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 41
7.0 SystemDesignConsiderations
Thissectioncontainsinformationthatwouldhavebeencontainedinaproductdesignguidein
earliergenerations.Inanefforttosimplifytheamountofdocumentation,relevantsystemdesign
considerationshavebeencombinedintothisdocument.
7.1 Background
TheIntelAdvanced+BootBlockStackedchipscalepackagecombinesthefeaturesofthe
Advanced+BootBlockflashmemoryarchitecturewithalow-powerSRAMtoachieveanoverall
reductioninsystemboardspace.Thisenablesapplicationstointegratesecuritywithsimple
softwareandhardwareconfigurations,whilealsocombiningthesystemSRAMandflashintoone
commonfootprint.Thissectiondiscusseshowtotakefulladvantageofthe3VoltAdvanced+Boot
BlockStackedChipScalePackage.
7.1.1 Flash+SRAMFootprintIntegration
TheStackedChipScalePackagememorysolutioncanbeusedtoreplaceasubsetofthememory
subsystemwithinadesign.Whereapreviousdesignmayhaveusedtwoseparatefootprintsfor
SRAMandFlash,youcannowreplacewiththeindustry-standardI-balloutoftheStacked-CSP
device.Thisallowsforanoverallreductioninboardspace,whichallowsthedesigntointegrate
boththeflashandtheSRAMintoonecomponent.
7.1.2 Advanced+BootBlockFlashMemoryFeatures
Advanced+BootBlockaddsthefollowingnewfeaturestoIntelAdvancedBootBlock
architecture:
•Instant,individualblocklockingprovidessoftware/hardwarecontrolled,independentlocking/
unlockingofanyblockwithzerolatencytoprotectcodeanddata.
•A128-bitProtectionRegisterenablessystemsecurityimplementations.
•Improved12 Vproductionprogrammingsimplifiesthesystemconfigurationrequiredto
implement12 Vfastprogramming.
•CommonFlashInterface(CFI)providescomponentinformationonthechiptoallowsoftware-
independentdeviceupgrades.
FormoreinformationonspecificadvantagesoftheAdvanced+BootBlockFlashMemory,please
seeAP-658DesigningwiththeAdvanced+BootBlockFlashMemoryArchitecture.
7.2 FlashControlConsiderations
Theflashdeviceisprotectedagainstaccidentalblockerasureorprogrammingduringpower
transitions.Powersupplysequencingisnotrequired,since thedeviceisindifferentastowhich
powersupply,F-VPPorF-VCC,powers-upfirst.Exampleflashpowersupplyconfigurationsare
showninFigure12,“ExamplePowerSupplyConfigurations”onpage 42.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
42 Datasheet
7.2.1 F-RP#ConnectedtoSystemReset
TheuseofF-RP#duringsystemresetisimportantwithautomatedprogram/erasedevicessincethe
systemexpectstoreadfromtheflashmemorywhenitcomesoutofreset.IfaCPUresetoccurs
withoutaflashmemoryreset,properCPUinitializationwillnotoccurbecausetheflashmemory
maybeprovidingstatusinformationinsteadofarraydata.IntelrecommendsconnectingF-RP#to
thesystemCPURESET#signaltoallowproperCPU/flashinitializationfollowingsystemreset.
SystemdesignersmustguardagainstspuriouswriteswhenF-VCCvoltagesareaboveVLKO.Since
bothF-WE#andF-CE#mustbelowforacommandwrite,drivingeithersignaltoVIHwillinhibit
writestothedevice.TheCUIarchitectureprovidesadditionalprotectionsincealterationof
memorycontentscanonlyoccuraftersuccessfulcompletionofthetwo-stepcommandsequences.
ThedeviceisalsodisableduntilF-RP#isbroughttoVIH,regardlessofthestateofitscontrol
inputs.
Byholdingthedeviceinreset(F-RP#connectedtosystemPowerGood)duringpower-up/down,
invalidbusconditionsduringpower-upcanbemasked,providingyetanotherlevelofmemory
protection.
7.2.2 F-VCC,F-VPPandF-RP#Transition
TheCUIlatchescommandsasissuedbysystemsoftwareandisnotalteredbyF-VPPorF-CE#
transitionsorWSMactions.Itsdefaultstateuponpower-up,afterexitfromresetmodeorafter
F-VCCtransitionsaboveVLKO(Lockoutvoltage),isreadarraymode.
Afteranyprogramorblockeraseoperationiscomplete(evenafterF-VPPtransitionsdownto
VPPLK),theCUImustberesettoreadarraymodeviatheReadArraycommandifaccesstothe
flashmemoryarrayisdesired.
NOTE: 1.AresistorcanbeusediftheF-VCCsupplycansinkadequatecurrentbasedonresistorvalue.
Figure12.ExamplePowerSupplyConfigurations
V
CC
V
PP
12VFastProgramming
AbsoluteWriteProtectionWithV
PP
≤
V
PPLK
SystemSupply
12VSupply
10
≤
K
Ω
V
CC
V
PP
SystemSupply
12VSupply
LowVoltageand12VFastProgramming
V
CC
V
PP
SystemSupply
Prot#
(LogicSignal)
V
CC
V
PP
SystemSupply
Low-VoltageProgramming
Low-VoltageProgramming
AbsoluteWriteProtectionviaLogicSignal
(Note1)
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 43
7.3 NoiseReduction
Stacked-CSPmemory’spowerswitchingcharacteristicsrequirecarefuldevicedecoupling.System
designersshouldconsiderthreesupplycurrentissuesforboththeflashandSRAM:
1. Standbycurrentlevels(ICCS)
2. Readcurrentlevels(ICCR)
3. TransientpeaksproducedbyfallingandrisingedgesofF-CE#,S-CS1#,andS-CS2.
Transientcurrentmagnitudesdependonthedeviceoutputs’capacitiveandinductiveloading.Two-
linecontrolandproperdecouplingcapacitorselectionwillsuppressthesetransientvoltagepeaks.
Eachdeviceshouldhaveacapacitorsbetweenindividualpower(F-VCC,F-VCCQ,
F-VPP,
S-VCC)andground(GND)signals.High-frequency,inherentlylow-inductancecapacitorsshould
beplacedascloseaspossibletothepackageleads.
Noiseissueswithinasystemcancausedevicestooperateerraticallyifitisnotadequatelyfiltered.
Inordertoavoidanynoiseinteractionissueswithinasystem,itisrecommendedthatthedesign
containtheappropriatenumberofdecouplingcapacitorsinthesystem.Noiseissuescanalsobe
reducedifleadstothedevicearekeptveryshort,inordertoreduceinductance.
DecouplingcapacitorsbetweenVCCandVSSreducevoltagespikesbysupplyingtheextracurrent
neededduringswitching.Placingthesecapacitorsasclosetothedeviceaspossiblereducesline
inductance.Thecapacitorsshouldbelowinductancecapacitors;surfacemountcapacitorstypically
exhibitlowerinductance.
Itishighlyrecommendedthatsystemsusea0.1
µfcapacitorforeachoftheD9,D10,A10andE4
gridballoutlocations(seeFigure1,“66-BallStackedChipScalePackage”onpage 8forballout).
Thesecapacitorsarenecessarytoavoidundesiredconditionscreatedbyexcessnoise.Smaller
capacitorscanbeusedtodecouplehigherfrequencies.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
44 Datasheet
NOTES:
1. SubstrateconnectionsrefertoballoutlocationsshowninFigure1,“66-BallStackedChipScalePackage”on
page 8.
2. 0.1µfcapacitorsshouldbeusedwithD9,D10,A10andE4.
3. SomeSRAMdevicesdonothaveaS-VSSQ;inthiscase,thispadisaS-VSS.
4. SomeSRAMdevicesdonothaveaS-VSSQ;inthiscase,thispadisaVCC.
7.4 SimultaneousOperation
ThetermsimultaneousoperationinusedtodescribetheabilitytoreadorwritetotheSRAMwhile
alsoprogrammingorerasingflash.Inaddition,F-CE#,S-CS1#andS-CS2shouldnotbeenabledat
thesametime.(SeeTable 2,“3VoltIntel®Advanced+BootBlockStacked-CSPBall
Descriptions”onpage 9forasummaryofrecommendedoperatingmodes.)Simultaneous
operationofthecanbesummarizedbythefollowing:
•SRAMread/writeareduringaFlashProgramorEraseOperationareallowed.
•SimultaneousBusOperationsbetweentheFlashandSRAMarenotallowed(becauseofbus
contention).
Figure13.TypicalFlash+SRAMSubstratePowerandGroundConnections
S-V
SSQ
D10
SRAMDIE
FLASHDIE
SUBSTRATE
XX
S-X
F-X
Substrateconnectiontopackageball
SRAMdiebondpadconnection
Flashdiebondpadconnection
S-V
CCQ
S-V
CC
S-V
SS
F-V
PP
F-V
SSQ
F-V
CC
F-V
CCQ
F-V
SS
H8
A9
D9
E4
D3
A10
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 45
7.4.1 SRAMOperationduringFlash“Busy”
ThisfunctionalityprovidestheabilitytouseboththeflashandtheSRAM“atthesametime”
withinasystem,similartotheoperationoftwodeviceswithseparatefootprints.Thisoperationcan
beachievedbyfollowingtheappropriatetimingconstraintswithinasystem.
7.4.2 SimultaneousBusOperations
OperationsthatrequireboththeSRAMandFlashtobeinactivemodearedisallowed.Anexample
ofthesecaseswouldincludesimultaneousreadsonboththeflashandSRAM,whichwouldresult
incontentionforthedatabus.Finally,areadofonedevicewhileattemptingtowritetotheother
(similartotheconditionsofdirectmemoryaccess(DMA)operation)arealsonotwithinthe
recommendedoperatingconditions.Basically,onlyonememorycandrivetheoutputsoutthe
deviceatonegivenpointintime.
7.5 PrintedCircuitBoardNotes
TheIntelStacked-CSPwillsavesignificantspaceonyourPCBbycombiningtwochipsintoone
BGAstylepackage.IntelStacked-CSPhasa0.8mmpitchthatcanberoutedonyourPrinted
CircuitBoardwithconventionaldesignrules.Tracewidthsof0.127mm(0.005inches)aretypical.
Unusedballsinthecenterofthepackagearenotpopulatedtofurtherincreasetheroutingoptions.
StandardsurfacemountprocessandequipmentcanbeusedfortheIntelStacked-CSP.
NOTE: TopView
7.6 SystemDesignNotesSummary
TheAdvanced+BootBlockStacked-CSPallowshigherlevelsofmemorycomponentintegration.
Differentpowersupplyconfigurationscanbeusedwithinthesystemtoachievedifferent
objectives.Atleastthreedifferent0.1µfcapacitorsshouldbeusedtodecouplethedeviceswithina
system.SRAMreadsorwritesduringaflashprogramorerasearesupportedoperations.Standard
printedcircuitboardtechnologycanbeused.
Figure14.StandardPCBDesignRulesCanbeUsedwithStacked-CSPDevice
LandPadDiameter:0.35mm(0.0138in)
SolderMaskOpening:0.50mm(0.0198in)
TraceWidth:0.127mm(0.005in)
TraceSpaces:0.160mm(0.00625in)
ViaCapturePad:0.51mm(0.020in)
ViaDrillSize:0.25mm(0.010in)
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
46 Datasheet
AppendixAProgram/EraseFlowcharts
Figure15.AutomatedWordProgrammingFlowchart
Start
Write40H
ProgramAddress/Data
ReadStatusRegister
SR.7=1?
FullStatus
CheckifDesired
ProgramComplete
ReadStatusRegister
Data(SeeAbove)
V
PP
RangeError
ProgrammingError
AttemptedProgramto
LockedBlock-Aborted
ProgramSuccessful
SR.3=
SR.4=
SR.1=
FULLSTATUSCHECKPROCEDURE
BusOperation
Write
Write
Standby
Repeatforsubsequentprogrammingoperations.
SRFullStatusCheckcanbedoneaftereachprogramorafterasequenceof
programoperations.
WriteFFHafterthelastprogramoperationtoresetdevicetoreadarraymode.
BusOperation
Standby
Standby
SR.3MUSTbecleared,ifsetduringaprogramattempt,beforefurther
attemptsareallowedbytheWriteStateMachine.
SR.1,SR.3andSR.4areonlyclearedbytheClearStausRegisterCommand,
incaseswheremultiplebytesareprogrammedbeforefullstatusischecked.
Ifanerrorisdetected,clearthestatusregisterbeforeattemptingretryorother
errorrecovery.
No
Yes
1
0
1
0
1
0
Command
ProgramSetup
Program
Comments
Data=40H
Data=DatatoProgram
Addr=LocationtoProgram
CheckSR.7
1=WSMReady
0=WSMBusy
Command Comments
CheckSR.3
1=V
PP
LowDetect
CheckSR.1
1=AttemptedProgramto
LockedBlock-Program
Aborted
Read StatusRegisterDataToggle
CE#orOE#toUpdateStatus
RegisterData
Standby CheckSR.4
1=V
PP
ProgramError
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 47
0645_13
Figure16.ProgramSuspend/ResumeFlowchart
Start
WriteB0H
ReadStatusRegister
No
Comments
Data=B0H
Addr=X
Data=FFH
Addr=X
SR.7=
SR.2=
1
WriteFFH
ReadArrayData
ProgramCompleted
Done
Reading
Yes
WriteFFHWriteD0H
ProgramResumed ReadArrayData
0
1
Readarraydatafromblock
otherthantheonebeing
programmed.
StatusRegisterDataToggle
CE#orOE#toUpdateStatus
RegisterData
Addr=X
CheckSR.7
1=WSMReady
0=WSMBusy
CheckSR.2
1=ProgramSuspended
0=ProgramCompleted
Data=D0H
Addr=X
Bus
Operation Command
0
Write70H
StatusRegisterDataToggle
CE#orOE#toUpdateStatus
RegisterData
Addr=X
Write
Write
Write
Read
Read
Standby
Standby
Write
Data=70H
Addr=X
Command
Program
Suspend
ReadStatus
ReadArray
Program
Resume
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
48 Datasheet
0645_14
Figure17.AutomatedBlockEraseFlowchart
Start
Write20H
WriteD0Hand
BlockAddress
ReadStatusRegister
SR.7=
FullStatus
CheckifDesired
BlockEraseComplete
FULLSTATUSCHECKPROCEDURE
BusOperation
Write
Write
Standby
Repeatforsubsequentblockerasures.
FullStatusCheckcanbedoneaftereachblockeraseorafterasequenceof
blockerasures.
WriteFFHafterthelastwriteoperationtoresetdevicetoreadarraymode.
BusOperation
Standby
SR.1and3MUSTbecleared,ifsetduringaneraseattempt,beforefurther
attemptsareallowedbytheWriteStateMachine.
SR.1,3,4,5areonlyclearedbytheClearStausRegisterCommand,incases
wheremultiplebytesareerasedbeforefullstatusischecked.
Ifanerrorisdetected,clearthestatusregisterbeforeattemptingretryorother
errorrecovery.
No Yes
SuspendErase
Suspend
EraseLoop
1
0
Standby
Command
EraseSetup
EraseConfirm
Comments
Data=20H
Addr=WithinBlocktoBe
Erased
Data=D0H
Addr=WithinBlocktoBe
Erased
CheckSR.7
1=WSMReady
0=WSMBusy
Command Comments
CheckSR.3
1=V
PP
LowDetect
CheckSR.4,5
Both1=CommandSequence
Error
ReadStatusRegister
Data(SeeAbove)
V
PP
RangeError
CommandSequence
Error
BlockErase
Successful
SR.3=
SR.4,5=
1
0
1
0
BlockEraseErrorSR.5=1
0
AttemptedEraseof
LockedBlock-Aborted
SR.1=1
0
Read StatusRegisterDataToggle
CE#orOE#toUpdateStatus
RegisterData
Standby CheckSR.5
1=BlockEraseError
Standby CheckSR.1
1=AttemptedEraseof
LockedBlock-EraseAborted
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 49
0645_15
Figure18.EraseSuspend/ResumeFlowchart
Start
WriteB0H
ReadStatusRegister
No
Comments
Data=B0H
Addr=X
Data=FFH
Addr=X
SR.7=
SR.6=
1
WriteFFH
ReadArrayData
EraseCompleted
Done
Reading
Yes
WriteFFHWriteD0H
EraseResumed ReadArrayData
0
1
Readarraydatafromblock
otherthantheonebeing
erased.
StatusRegisterDataToggle
CE#orOE#toUpdateStatus
RegisterData
Addr=X
CheckSR.7
1=WSMReady
0=WSMBusy
CheckSR.6
1=EraseSuspended
0=EraseCompleted
Data=D0H
Addr=X
Bus
Operation
Write
Standby
Write
Read
Standby
Read
Command
0
Write70H
StatusRegisterDataToggle
CE#orOE#toUpdateStatus
RegisterData
Addr=X
Write
Write
Data=70H
Addr=X
Command
EraseSuspend
ReadStatus
ReadArray
EraseResume
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
50 Datasheet
0645_16
Figure19.LockingOperationsFlowchart
Start
Write60H
(ConfigurationSetup)
No
Comments
Data=60H
Addr=X
Write90H
(ReadConfiguration)
ReadBlockLockStatus
Locking
Change
Confirmed?
LockingChange
Complete
Bus
Operation
Write
Command
Write
01H,D0H,or2FH
Write
Write
Data=01H(LockBlock)
D0H(UnlockBlock)
2FH(LockdownBlock)
Addr=Withinblocktolock
Command
Config.Setup
Lock,Unlock,
orLockdown
Data=90H
Addr=X
Write
(Optional) Read
Configuration
BlockLockStatusData
Addr=Secondaddrofblock
Read
(Optional) BlockLock
Status
ConfirmLockingChangeon
DQ
1
,DQ
0
.(SeeBlockLocking
StateTableforvalid
combinations.)
Standby
(Optional)
Optional
WriteFFh
(ReadArray)
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 51
0645_17
Figure20.ProtectionRegisterProgrammingFlowchart
Start
WriteC0H
(ProtectionReg.
ProgramSetup)
WriteProtect.Register
Address/Data
ReadStatusRegister
SR.7=1?
FullStatus
CheckifDesired
ProgramComplete
ReadStatusRegister
Data(SeeAbove)
V
PP
RangeError
ProtectionRegister
ProgrammingError
AttemptedProgramto
LockedRegister-
Aborted
ProgramSuccessful
SR.3,SR.4=
SR.1,SR.4=
SR.1,SR.4=
FULLSTATUSCHECKPROCEDURE
BusOperation
Write
Write
Standby
ProtectionProgramoperationscanonlybeaddressedwithintheprotection
registeraddressspace.Addressesoutsidethedefinedspacewillreturnan
error.
Repeatforsubsequentprogrammingoperations.
SRFullStatusCheckcanbedoneaftereachprogramorafterasequenceof
programoperations.
WriteFFHafterthelastprogramoperationtoresetdevicetoreadarraymode.
BusOperation
Standby
Standby
SR.3MUSTbecleared,ifsetduringaprogramattempt,beforefurther
attemptsareallowedbytheWriteStateMachine.
SR.1,SR.3andSR.4areonlyclearedbytheClearStausRegisterCommand,
incasesofmultipleprotectionregisterprogramoperationsbeforefullstatusis
checked.
Ifanerrorisdetected,clearthestatusregisterbeforeattemptingretryorother
errorrecovery.
No
Yes
1,1
0,1
1,1
Command
ProtectionProgram
Setup
ProtectionProgram
Comments
Data=C0H
Data=DatatoProgram
Addr=LocationtoProgram
CheckSR.7
1=WSMReady
0=WSMBusy
Command Comments
SR.1SR.3SR.4
011V
PP
Low
001Prot.Reg.
Prog.Error
101Register
Locked:
Aborted
Read StatusRegisterDataToggle
CE#orOE#toUpdateStatus
RegisterData
Standby
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
52 Datasheet
AppendixBCFIQueryStructure
Thisappendixdefinesthedatastructureor“database”returnedbytheCommonFlashInterface
(CFI)Querycommand.Systemsoftwareshouldparsethisstructuretogaincriticalinformation
suchasblocksize,density,x8/x16,andelectricalspecifications.Oncethisinformationhasbeen
obtained,thesoftwarewillknowwhichcommandsetstousetoenableflashwrites,blockerases,
andotherwisecontroltheflashcomponent.TheQueryispartofanoverallspecificationfor
multiplecommandsetandcontrolinterfacedescriptionscalledCommonFlashInterface,orCFI.
B.1 QueryStructureOutput
TheQuery“database”allowssystemsoftwaretogaininformationforcontrollingtheflash
component.Thissectiondescribesthedevice’sCFI-compliantinterfacethatallowsthehostsystem
toaccessQuerydata.
Querydataarealwayspresentedonthelowest-orderdataoutputs(DQ0-7)only.Thenumerical
offsetvalueistheaddressrelativetothemaximumbuswidthsupportedbythedevice.Onthis
familyofdevices,theQuerytabledevicestartingaddressisa10h,whichisawordaddressforx16
devices.
Foraword-wide(x16)device,thefirsttwobytesoftheQuerystructure,“Q”and“R”inASCII,
appearonthelowbyteatwordaddresses10hand11h.ThisCFI-compliantdeviceoutputs00hdata
onupperbytes.Thus,thedeviceoutputsASCII“Q”inthelowbyte(DQ0-7)and00hinthehigh
byte(DQ8-15).
AtQueryaddressescontainingtwoormorebytesofinformation,theleastsignificantdatabyteis
presentedattheloweraddress,andthemostsignificantdatabyteispresentedatthehigheraddress.
Inallofthefollowingtables,addressesanddataarerepresentedinhexadecimalnotation,sothe
“h”suffixhasbeendropped.Inaddition,sincetheupperbyteofword-widedevicesisalways
“00h,”theleading“00”hasbeendroppedfromthetablenotationandonlythelowerbytevalueis
shown.Anyx16deviceoutputscanbeassumedtohave00hontheupperbyteinthismode.
Table20.SummaryofQueryStructureOutputasaFunctionofDeviceandMode
Device HexOffset Code ASCIIValue
DeviceAddress 10: 51 “Q”
11: 52 “R”
12: 59 “Y”
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 53
B.2 QueryStructureOverview
TheQuerycommandcausestheflashcomponenttodisplaytheCommonFlashInterface(CFI)
Querystructureor“database.”Thestructuresub-sectionsandaddresslocationsaresummarized
below.
Table21.ExampleofQueryStructureOutputofx16andx8Devices
WordAddressing ByteAddressing
Offset HexCode Value Offset HexCode Value
A15–A0D15–D0A7–A0D7–D0
0010h 0051 “Q” 10h 51 “Q”
0011h 0052 “R” 11h 52 “R”
0012h 0059 “Y” 12h 59 “Y”
0013h P_IDLO PrVendor 13h P_IDLO PrVendor
0014h P_IDHI ID# 14h P_IDLOID#
0015h PLO PrVendor 15h P_IDHI ID#
0016h PHI TblAdr 16h ... ...
0017h A_IDLO AltVendor 17h
0018h A_IDHI ID# 18h
... ... ... ...
Table22.QueryStructure
Offset Sub-SectionName Description Notes
00h ManufacturerCode 1
01h DeviceCode 1
(BA+2)h BlockStatusRegister Block-specificinformation 1,2
04-0Fh Reserved Reservedforvendor-specificinformation 1
10h CFIQueryIdentificationString CommandsetIDandvendordataoffset 1
1Bh SystemInterfaceInformation Devicetiming&voltageinformation 1
27h DeviceGeometryDefinition Flashdevicelayout 1
PPrimaryIntel-SpecificExtended
QueryTable Vendor-definedadditionalinformationspecifictothe
PrimaryVendorAlgorithm 1,3
NOTES:
1. RefertotheQueryStructureOutputsectionandoffset28hforthedetaileddefinitionofoffsetaddressasa
functionofdevicebuswidthandmode.
2. BA = ThebeginninglocationofaBlockAddress(e.g.,08000histhebeginninglocationofblock1whenthe
blocksizeis32Kword).
3. Offset15defines“P”whichpointstothePrimaryIntel-specificExtendedQueryTable.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
54 Datasheet
B.3 BlockLockStatusRegister
TheBlockStatusRegisterindicateswhetheraneraseoperationcompletedsuccessfullyorwhether
agivenblockislockedorcanbeaccessedforflashprogram/eraseoperations.
BlockEraseStatus(BSR.1)allowssystemsoftwaretodeterminethesuccessofthelastblockerase
operation.BSR.1canbeusedjustafterpower-uptoverifythattheVCCsupplywasnot
accidentallyremovedduringaneraseoperation.Thisbitisonlyresetbyissuinganothererase
operationtotheblock.TheBlockStatusRegisterisaccessedfromwordaddress02hwithineach
block.
B.4 CFIQueryIdentificationString
TheIdentificationStringprovidesverificationthatthecomponentsupportstheCommonFlash
Interfacespecification.Italsoindicatesthespecificationversionandsupportedvendor-specified
commandset(s).
Table23.BlockStatusRegister
Offset Length Description Address Value Notes
(BA+2)h 1 BlockLockStatusRegister BA+2: --00or--01 1
BSR.0BlockLockStatus
0=Unlocked
1=Locked BA+2: (bit0):0or1
BSR.1BlockLock-DownStatus
0=Notlockeddown
1=Lockeddown BA+2: (bit1):0or1
BSR2–7:Reservedforfutureuse BA+2: (bit2–7):0
NOTE: 1.BA = ThebeginninglocationofaBlockAddress(i.e.,008000histhebeginninglocationofblock1
inwordmode.)
Table24.CFIIdentification
Offset Length Description Addr. Hex
Code Value
10h 3 Query-uniqueASCIIstring“QRY“ 10 --51 “Q”
11: --52 “R”
12: --59 “Y”
13h 2 PrimaryvendorcommandsetandcontrolinterfaceIDcode. 13: --03
16-bitIDcodeforvendor-specifiedalgorithms 14: --00
15h 2 ExtendedQueryTableprimaryalgorithmaddress 15: --35
16: --00
17h 2 AlternatevendorcommandsetandcontrolinterfaceIDcode 17: --00
0000hmeansnosecondvendor-specifiedalgorithmexists 18: --00
19h 2 SecondaryalgorithmExtendedQueryTableaddress. 19: --00
0000hmeansnoneexists 1A: --00
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 55
B.5 SystemInterfaceInformation
Table25.SystemInterfaceInformation
Offset Length Description Addr. Hex
Code Value
1Bh 1 VCClogicsupplyminimumprogram/erasevoltage
bits0–3BCD100mV
bits4–7BCDvolts 1B: --27 2.7V
1Ch 1 VCClogicsupplymaximumprogram/erasevoltage
bits0–3BCD100mV
bits4–7BCDvolts 1C: --36 3.3V
1Dh 1 VPP[programming]supplyminimumprogram/erasevoltage
bits0–3BCD100mV
bits4–7HEXvolts 1D: --B4 11.4V
1Eh 1 VPP[programming]supplymaximumprogram/erasevoltage
bits0–3BCD100mV
bits4–7HEXvolts 1E: --C6 12.6V
1Fh 1 “n”suchthattypicalsinglewordprogramtime-out=2nµs 1F: --05 32µs
1Bh 1 VCClogicsupplyminimumprogram/erasevoltage
bits0–3BCD100mV
bits4–7BCDvolts 1B: --27 2.7V
1Ch 1 VCClogicsupplymaximumprogram/erasevoltage
bits0–3BCD100mV
bits4–7BCDvolts 1C: --36 3.3V
1Dh 1 VPP[programming]supplyminimumprogram/erasevoltage
bits0–3BCD100mV
bits4–7HEXvolts 1D: --B4 11.4V
1Eh 1 VPP[programming]supplymaximumprogram/erasevoltage
bits0–3BCD100mV
bits4–7HEXvolts 1E: --C6 12.6V
1Fh 1 “n”suchthattypicalsinglewordprogramtime-out=2nµs 1F: --05 32µs
1Bh 1 VCClogicsupplyminimumprogram/erasevoltage
bits0–3BCD100mV
bits4–7BCDvolts 1B: --27 2.7V
1Ch 1 VCClogicsupplymaximumprogram/erasevoltage
bits0–3BCD100mV
bits4–7BCDvolts 1C: --36 3.3V
1Dh 1 VPP[programming]supplyminimumprogram/erasevoltage
bits0–3BCD100mV
bits4–7HEXvolts 1D: --B4 11.4V
20h 1 “n”suchthattypicalmax.bufferwritetime-out=2nµs 20: --00 n/a
21h 1 “n”suchthattypicalblockerasetime-out=2nms 21: --0A 1s
22h 1 “n”suchthattypicalfullchiperasetime-out=2nms 22: --00 n/a
23h 1 “n”suchthatmaximumwordprogramtime-out=2ntimestypical 23: --04 512µs
24h 1 “n”suchthatmaximumbufferwritetime-out=2ntimestypical 24: --00 n/a
25h 1 “n”suchthatmaximumblockerasetime-out=2ntimestypical 25: --03 8s
26h 1 “n”suchthatmaximumchiperasetime-out=2ntimestypical 26: --00 NA
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
56 Datasheet
B.6 DeviceGeometryDefinition
n
Table26.DeviceGeometryDefinition
Offset Length Description Code
SeeTableBelow
27h 1 “n”suchthatdevicesize=2ninnumberofbytes 27:
28h 2 Flashdeviceinterface:x8asyncx16asyncx8/x16async 28: --01 x16
28:00,29:0028:01,29:0028:02,29:00 29: --00
2Ah 2 “n”suchthatmaximumnumberofbytesinwritebuffer=2n2A: --00 0
2B: --00
2Ch 1
Numberoferaseblockregionswithindevice:
1.x=0meansnoeraseblocking;thedeviceerasesin“bulk”
2.xspecifiesthenumberofdeviceorpartitionregionswithoneor
morecontiguoussame-sizeeraseblocks.
3.Symmetricallyblockedpartitionshaveoneblockingregion
4.Partitionsize=(totalblocks)x(individualblocksize)
2C: --02 2
2Dh 4 EraseBlockRegion1Information 2D:
bits0–15=y,y+1=numberofidentical-sizeeraseblocks 2E:
bits16–31=z,regioneraseblock(s)sizearezx256bytes 2F:
30:
31h 4 EraseBlockRegion2Information 31:
bits0–15=y,y+1=numberofidentical-sizeeraseblocks 32:
bits16–31=z,regioneraseblock(s)sizearezx256bytes 33:
34:
DeviceGeometryDefinition
Address 16-Mbit 32-Mbit
–B –T –B –T
27: --15 --15 --16 --16
28: --01 --01 --01 --01
29: --00 --00 --00 --00
2A: --00 --00 --00 --00
2B: --00 --00 --00 --00
2C: --02 --02 --02 --02
2D: --07 --1E --07 --3E
2E: --00 --00 --00 --00
2F: --20 --00 --20 --00
30: --00 --01 --00 --01
31: --1E --07 --3E --07
32: --00 --00 --00 --00
33: --00 --20 --00 --20
34: --01 --00 --01 --00
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 57
B.7 Intel-SpecificExtendedQueryTable
Certainflashfeaturesandcommandsareoptional.TheIntel-SpecificExtendedQuerytable
specifiesthisandothersimilartypesofinformation.
Table27.Primary-VendorSpecificExtendedQuery
Offset(1)
P=35h Length Description
(OptionalFlashFeaturesandCommands) Addr. Hex
Code Value
(P+0)h 3 Primaryextendedquerytable 35: --50 “P”
(P+1)h UniqueASCIIstring“PRI” 36: --52 “R”
(P+2)h 37: --49 “I”
(P+3)h 1 Majorversionnumber,ASCII 38: --31 “1”
(P+4)h 1 Minorversionnumber,ASCII 39: --30 “0”
(P+5)h 4 Optionalfeatureandcommandsupport(1=yes,0=no) 3A: --66
(P+6)h bits9–31arereserved;undefinedbitsare“0.”Ifbit31is“1”then
another31bitfieldofoptionalfeaturesfollowsattheendofthebit-30
field.
3B: --00
(P+7)h 3C: --00
(P+8)h 3D: --00
bit0Chiperasesupported bit0=0No
bit1Suspenderasesupported bit1=1Yes
bit2Suspendprogramsupported bit2=1Yes
bit3Legacylock/unlocksupported bit3=0No
bit4Queuederasesupported bit4=0No
bit5Instantindividualblocklockingsupported bit5=1Yes
bit6Protectionbitssupported bit6=1Yes
bit7Pagemodereadsupported bit7=0No
bit8Synchronousreadsupported bit8=0No
(P+9)h 1 Supportedfunctionsaftersuspend:readarray,status,query
Othersupportedoperationsare:
bits1–7reserved;undefinedbitsare“0” 3E: --01
bit0Programsupportedaftererasesuspend bit0=1Yes
(P+A)h 2 Blockstatusregistermask 3F: --03
(P+B)h bits2–15areReserved;undefinedbitsare“0” 40: --00
bit0BlockLock-BitStatusregisteractive bit0=1Yes
bit1BlockLock-DownBitStatusactive bit1=1Yes
(P+C)h 1 VCClogicsupplyhighestperformanceprogram/erasevoltage
bits0–3BCDvaluein100mV
bits4–7BCDvalueinvolts 41: --33 3.3V
(P+D)h 1 VPPoptimumprogram/erasesupplyvoltage
bits0–3BCDvaluein100mV
bits4–7HEXvalueinvolts 42: --C0 12.0V
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
58 Datasheet
Table28.ProtectionRegisterInformation
Offset(1)
P=35h Length Description
(OptionalFlashFeaturesandCommands) Addr. Hex
Code Value
(P+E)h 1 NumberofProtectionregisterfieldsinJEDECIDspace.
“00h,”indicatesthat256protectionbytesareavailable 43: --01 01
(P+F)h
4
ProtectionField1:ProtectionDescription 44: --80 80h
(P+10)h
Thisfielddescribesuser-availableOneTimeProgrammable(OTP)
Protectionregisterbytes.Somearepre-programmedwithdevice-
uniqueserialnumbers.Othersareuserprogrammable.Bits0–15point
totheProtectionregisterLockbyte,thesection’sfirstbyte.The
followingbytesarefactorypre-programmedanduser-programmable.
45: --00 00h
(P+11)h
bits0–7=Lock/bytesJEDEC-planephysicallowaddress
bits8–15=Lock/bytesJEDEC-planephysicalhighaddress
bits16–23=“n”suchthat2n=factorypre-programmedbytes
bits24–31=“n”suchthat2n=userprogrammablebytes
46: --03 8byte
(P+12)h 47: --03 8byte
(P+13)h Reservedforfutureuse 48:
NOTE: 1.ThevariablePisapointerwhichisdefinedatCFIoffset15h.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 59
AppendixCWord-WideMemoryMapDiagrams
16-Mbit,32-Mbit64-Mbit[future],Word-WideMemoryAddressing
TopBoot BottomBoot
Size
(KW) 16-Mbit 32-Mbit 64-Mbit Size
(KW) 16-Mbit 32-Mbit 64-Mbit
4 FF000-FFFFF 1FF000-1FFFFF 3FF000-3FFFFF 32 3F8000-3FFFFF
4 FE000-FEFFF 1FE000-1FEFFF 3FE000-3FEFFF 32 3F0000-3F7FFF
4 FD000-FDFFF 1FD000-1FDFFF 3FD000-3FDFFF 32 3E8000-3EFFFF
4 FC000-FCFFF 1FC000-1FCFFF 3FC000-3FCFFF 32 3E0000-3E7FFF
4 FB000-FBFFF 1FB000-1FBFFF 3FB000-3FBFFF 32 3D8000-3DFFFF
4 FA000-FAFFF 1FA000-1FAFFF 3FA000-3FAFFF 32 3D0000-3D7FFF
4 F9000-F9FFF 1F9000-1F9FFF 3F9000-3F9FFF 32 3C8000-3CFFFF
4 F8000-F8FFF 1F8000-1F8FFF 3F8000-3F8FFF 32 3C0000-3C7FFF
32 F0000-F7FFF 1F0000-1F7FFF 3F0000-3F7FFF 32 3B8000-3BFFFF
32 E8000-EFFFF 1E8000-1EFFFF 3E8000-3EFFFF 32 3B0000-3B7FFF
32 E0000-E7FFF 1E0000-1E7FFF 3E0000-3E7FFF 32 3A8000-3AFFFF
32 D8000-DFFFF 1D8000-1DFFFF 3D8000-3DFFFF 32 3A0000-3A7FFF
32 D0000-D7FFF 1D0000-1D7FFF 3D0000-3D7FFF 32 398000-39FFFF
32 C8000-CFFFF 1C8000-1CFFFF 3C8000-3CFFFF 32 390000-397FFF
32 C0000-C7FFF 1C0000-1C7FFF 3C0000-3C7FFF 32 388000-38FFFF
32 B8000-BFFFF 1B8000-1BFFFF 3B8000-3BFFFF 32 380000-387FFF
32 B0000-B7FFF 1B0000-1B7FFF 3B0000-3B7FFF 32 378000-37FFFF
32 A8000-AFFFF 1A8000-1AFFFF 3A8000-3AFFFF 32 370000-377FFF
32 A0000-A7FFF 1A0000-1A7FFF 3A0000-3A7FFF 32 368000-36FFFF
32 98000-9FFFF 198000-19FFFF 398000-39FFFF 32 360000-367FFF
32 90000-97FFF 190000-197FFF 390000-397FFF 32 358000-35FFFF
32 88000-8FFFF 188000-18FFFF 388000-38FFFF 32 350000-357FFF
32 80000-87FFF 180000-187FFF 380000-387FFF 32 348000-34FFFF
32 78000-7FFFF 178000-17FFFF 378000-37FFFF 32 340000-347FFF
32 70000-77FFF 170000-177FFF 370000-377FFF 32 338000-33FFFF
32 68000-6FFFF 168000-16FFFF 368000-36FFFF 32 330000-337FFF
32 60000-67FFF 160000-167FFF 360000-367FFF 32 328000-32FFFF
32 58000-5FFFF 158000-15FFFF 358000-35FFFF 32 320000-327FFF
32 50000-57FFF 150000-157FFF 350000-357FFF 32 318000-31FFFF
32 48000-4FFFF 148000-14FFFF 348000-34FFFF 32 310000-317FFF
32 40000-47FFF 140000-147FFF 340000-347FFF 32 308000-30FFFF
32 38000-3FFFF 138000-13FFFF 338000-33FFFF 32 300000-307FFF
32 30000-37FFF 130000-137FFF 330000-337FFF 32 2F8000-2FFFFF
32 28000-2FFFF 128000-12FFFF 328000-32FFFF 32 2F0000-2F7FFF
32 20000-27FFF 120000-127FFF 320000-327FFF 32 2E8000-2EFFFF
32 18000-1FFFF 118000-11FFFF 318000-31FFFF 32 2E0000-2E7FFF
32 10000-17FFF 110000-117FFF 310000-317FFF 32 2D8000-2DFFFF
32 08000-0FFFF 108000-10FFFF 308000-30FFFF 32 2D0000-2D7FFF
32 00000-07FFF 100000-107FFF 300000-307FFF 32 2C8000-2CFFFF
32 0F8000-0FFFFF 2F8000-2FFFFF 32 2C0000-2C7FFF
32 0F0000-0F7FFF 2F0000-2F7FFF 32 2B8000-2BFFFF
32 0E8000-0EFFFF 2E8000-2EFFFF 32 2B0000-2B7FFF
32 0E0000-0E7FFF 2E0000-2E7FFF 32 2A8000-2AFFFF
32 0D8000-0DFFFF 2D8000-2DFFFF 32 2A0000-2A7FFF
32 0D0000-0D7FFF 2D0000-2D7FFF 32 298000-29FFFF
32 0C8000-0CFFFF 2C8000-2CFFFF 32 290000-297FFF
32 0C0000-0C7FFF 2C0000-2C7FFF 32 288000-28FFFF
32 0B8000-0BFFFF 2B8000-2BFFFF 32 280000-287FFF
32 0B0000-0B7FFF 2B0000-2B7FFF 32 278000-27FFFF
32 0A8000-0AFFFF 2A8000-2AFFFF 32 270000-277FFF
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3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
60 Datasheet
16-Mbit,32-Mbit,and64-Mbit[future],Word-WideMemoryAddressing
TopBoot BottomBoot
Size
(KW) 16-Mbit 32-Mbit 64-Mbit Size
(KW) 16-Mbit 32-Mbit 64-Mbit
32 0A0000-0A7FFF 2A0000-2A7FFF 32 268000-26FFFF
32 098000-09FFFF 298000-29FFFF 32 260000-267FFF
32 090000-097FFF 290000-297FFF 32 258000-25FFFF
32 088000-08FFFF 288000-28FFFF 32 250000-257FFF
32 080000-087FFF 280000-287FFF 32 248000-24FFFF
32 078000-07FFFF 278000-27FFFF 32 240000-247FFF
32 070000-077FFF 270000-277FFF 32 238000-23FFFF
32 068000-06FFFF 268000-26FFFF 32 230000-237FFF
32 060000-067FFF 260000-267FFF 32 228000-22FFFF
32 058000-05FFFF 258000-25FFFF 32 220000-227FFF
32 050000-057FFF 250000-257FFF 32 218000-21FFFF
32 048000-04FFFF 248000-24FFFF 32 210000-217FFF
32 040000-047FFF 240000-247FFF 32 208000-20FFFF
32 038000-03FFFF 238000-23FFFF 32 200000-207FFF
32 030000-037FFF 230000-237FFF 32 1F8000-1FFFFF 1F8000-1FFFFF
32 028000-02FFFF 228000-22FFFF 32 1F0000-1F7FFF 1F0000-1F7FFF
32 020000-027FFF 220000-227FFF 32 1E8000-1EFFFF 1E8000-1EFFFF
32 018000-01FFFF 218000-21FFFF 32 1E0000-1E7FFF 1E0000-1E7FFF
32 010000-017FFF 210000-217FFF 32 1D8000-1DFFFF 1D8000-1DFFFF
32 008000-00FFFF 208000-21FFFF 32 1D0000-1D7FFF 1D0000-1D7FFF
32 000000-007FFF 200000-207FFF 32 1C8000-1CFFFF 1C8000-1CFFFF
32 1F8000-1FFFFF 32 1C0000-1C7FFF 1C0000-1C7FFF
32 1F0000-1F7FFF 32 1B8000-1BFFFF 1B8000-1BFFFF
32 1E8000-1EFFFF 32 1B0000-1B7FFF 1B0000-1B7FFF
32 1E0000-1E7FFF 32 1A8000-1AFFFF 1A8000-1AFFFF
32 1D8000-1DFFFF 32 1A0000-1A7FFF 1A0000-1A7FFF
32 1D0000-1D7FFF 32 198000-19FFFF 198000-19FFFF
32 1C8000-1CFFFF 32 190000-197FFF 190000-197FFF
32 1C0000-1C7FFF 32 188000-18FFFF 188000-18FFFF
32 1B8000-1BFFFF 32 180000-187FFF 180000-187FFF
32 1B0000-1B7FFF 32 178000-17FFFF 178000-17FFFF
32 1A8000-1AFFFF 32 170000-177FFF 170000-177FFF
32 1A0000-1A7FFF 32 168000-16FFFF 168000-16FFFF
32 198000-19FFFF 32 160000-167FFF 160000-167FFF
32 190000-197FFF 32 158000-15FFFF 158000-15FFFF
32 188000-18FFFF 32 150000-157FFF 150000-157FFF
32 180000-187FFF 32 148000-14FFFF 148000-14FFFF
32 178000-17FFFF 32 140000-147FFF 140000-147FFF
32 170000-177FFF 32 138000-13FFFF 138000-13FFFF
32 168000-16FFFF 32 130000-137FFF 130000-137FFF
32 160000-167FFF 32 128000-12FFFF 128000-12FFFF
32 158000-15FFFF 32 120000-127FFF 120000-127FFF
32 150000-157FFF 32 118000-11FFFF 118000-11FFFF
32 148000-14FFFF 32 110000-117FFF 110000-117FFF
32 140000-147FFF 32 108000-10FFFF 108000-10FFFF
32 138000-13FFFF 32 100000-107FFF 100000-107FFF
32 130000-137FFF 32 F8000-FFFFF F8000-FFFFF F8000-FFFFF
32 128000-12FFFF 32 F0000-F7FFF F0000-F7FFF F0000-F7FFF
32 120000-127FFF 32 E8000-EFFFF E8000-EFFFF E8000-EFFFF
32 118000-11FFFF 32 E0000-E7FFF E0000-E7FFF E0000-E7FFF
32 110000-117FFF 32 D8000-DFFFF D8000-DFFFF D8000-DFFFF
32 108000-10FFFF 32 D0000-D7FFF D0000-D7FFF D0000-D7FFF
32 100000-107FFF 32 C8000-CFFFF C8000-CFFFF C8000-CFFFF
32 0F8000-0FFFFF 32 C0000-C7FFF C0000-C7FFF C0000-C7FFF
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3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 61
16-Mbit,32-Mbit,and64-MbitWord-WideMemoryAddressing
TopBoot BottomBoot
Size
(KW) 16-Mbit 32-Mbit 64-Mbit Size
(KW) 16-Mbit 32-Mbit 64-Mbit
32 0F0000-0F7FFF 32 B8000-BFFFF B8000-BFFFF B8000-BFFFF
32 0E8000-0EFFFF 32 B0000-B7FFF B0000-B7FFF B0000-B7FFF
32 0E0000-0E7FFF 32 A8000-AFFFF A8000-AFFFF A8000-AFFFF
32 0D8000-0DFFFF 32 A0000-A7FFF A0000-A7FFF A0000-A7FFF
32 0D0000-0D7FFF 32 98000-9FFFF 98000-9FFFF 98000-9FFFF
32 0C8000-0CFFFF 32 90000-97FFF 90000-97FFF 90000-97FFF
32 0C0000-0C7FFF 32 88000-8FFFF 88000-8FFFF 88000-8FFFF
32 0B8000-0BFFFF 32 80000-87FFF 80000-87FFF 80000-87FFF
32 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF 78000-7FFFF
32 0A8000-0AFFFF 32 70000-77FFF 70000-77FFF 70000-77FFF
32 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF 68000-6FFFF
32 098000-09FFFF 32 60000-67FFF 60000-67FFF 60000-67FFF
32 090000-097FFF 32 58000-5FFFF 58000-5FFFF 58000-5FFFF
32 088000-08FFFF 32 50000-57FFF 50000-57FFF 50000-57FFF
32 080000-087FFF 32 48000-4FFFF 48000-4FFFF 48000-4FFFF
32 078000-07FFFF 32 40000-47FFF 40000-47FFF 40000-47FFF
32 070000-077FFF 32 38000-3FFFF 38000-3FFFF 38000-3FFFF
32 068000-06FFFF 32 30000-37FFF 30000-37FFF 30000-37FFF
32 060000-067FFF 32 28000-2FFFF 28000-2FFFF 28000-2FFFF
32 058000-05FFFF 32 20000-27FFF 20000-27FFF 20000-27FFF
32 050000-057FFF 32 18000-1FFFF 18000-1FFFF 18000-1FFFF
32 048000-04FFFF 32 10000-17FFF 10000-17FFF 10000-17FFF
32 040000-047FFF 32 08000-0FFFF 08000-0FFFF 08000-0FFFF
32 038000-03FFFF 4 07000-07FFF 07000-07FFF 07000-07FFF
32 030000-037FFF 4 06000-06FFF 06000-06FFF 06000-06FFF
32 028000-02FFFF 4 05000-05FFF 05000-05FFF 05000-05FFF
32 020000-027FFF 4 04000-04FFF 04000-04FFF 04000-04FFF
32 018000-01FFFF 4 03000-03FFF 03000-03FFF 03000-03FFF
32 010000-017FFF 4 02000-02FFF 02000-02FFF 02000-02FFF
32 008000-00FFFF 4 01000-01FFF 01000-01FFF 01000-01FFF
32 000000-007FFF 4 00000-00FFF 00000-00FFF 00000-00FFF
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
62 Datasheet
AppendixDDeviceIDTable
Table29.DeviceID
ReadConfigurationAddressandData
Item Address Data
ManufacturerCode x16 00000 0089
DeviceCode
16-Mbitx16-T x16 00001 88C2
16-Mbitx16-B x16 00001 88C3
32-Mbitx16-T x16 00001 88C4
32-Mbitx16-B x16 00001 88C5
NOTE: OtherlocationswithintheconfigurationaddressspacearereservedbyIntelforfuture
use.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 63
AppendixEProtectionRegisterAddressing
Table30.ProtectionRegisterAddressing
Word-WideProtectionRegisterAddressing
WordUseA7A6A5A4A3A2A1A0
LOCKBoth10000000
0Factory10000001
1Factory10000010
2Factory10000011
3Factory10000100
4User10000101
5User10000110
6User10000111
7User10001000
NOTE: Alladdresslinesnotspecifiedintheabovetablemustbe0whenaccessingtheProtection
Register,i.e.,A21–A8=0.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
64 Datasheet
AppendixFMechanicalandShippingMediaDetails
F.1 MechanicalSpecification
NOTE: Shadedpinsindicateupperaddressballsfor64-Mbitand128-Mbitdevices.InallFlashandSRAMcombinations,66
ballsarepopulatedonlowerdensitydevices.(Upperaddressballsarenotpopulated).
Figure21.Stacked-CSP:12x8BallMatrix
E
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
H
910 11 12
A1
Index
D
12345678 A
B
C
D
E
F
G
H
9101112
S2
S1
b
e
BottomView-BallUpTopView-BallDown
A
A2
Y
A1
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 65
Table31.PackagingSpecifications(0.18µmand0.25µm)
Millimeters Inches
Sym Min Nom Max Min Nom Max
PackageHeight A 1.400 0.0551
BallHeight A1 0.250 0.0098
PackageBodyThickness A2 0.960 0.0378
BallLeadDiameter b 0.350 0.400 0.450 0.0138 0.0157 0.0177
PackageBodyLength–16-Mbit/2-Mbit
D
9.900 10.00 10.100 0.3898 0.3937 0.3976
PackageBodyLength–
32-Mbit/4-Mbit,16-Mbit/4-Mbit 11.900 12.000 12.100 0.4685 0.4724 0.4764
PackageBodyLength–
32-Mbit/8-Mbit 13.900 14.000 14.100 0.5472 0.5512 0.5551
PackageBodyWidth–
16-Mbit/2-Mbit,16-Mbit/4-Mbit,
32-Mbit/4-Mbit,32-Mbit/8-Mbit E 7.900 8.000 8.100 0.3110 0.3150 0.3189
Pitch e 0.800 0.0315
Ball(Lead)Count N 66 66
SeatingPlaneCoplanarity Y 0.100 0.0039
CornertoBallA1DistanceAlongE
16-Mbit/2-Mbit,16-Mbit/4-Mbit,
32-Mbit/4-Mbit,32-Mbit/8-Mbit
S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
CornertoBallA1DistanceAlongD
16-Mbit/2-Mbit
S2
0.500 0.600 0.700 0.0197 0.0236 0.0276
CornertoBallA1DistanceAlongD
32-Mbit/4-Mbit,16-Mbit/4-Mbit 1.500 1.600 1.700 0.0591 0.0630 0.0669
CornertoBallA1DistanceAlongD
32-Mbit/8-Mbit 2.500 2.600 2.700 0.0984 0.1024 0.1063
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
66 Datasheet
Table32.PackagingSpecifications(0.13µm)
Millimeters Inches
Sym Min Nom Max Min Nom Max
PackageHeight
16/02-Mb,16/04-Mb,32/08-Mb A
1.200 0.0472
PackageHeight
32/04-Mb 1.400 0.0551
BallHeight
16/02-Mb,16/04-Mb,32/08-Mb A1
0.200 0.0079
BallHeight
32/04-Mb 0.250 0.0098
PackageBodyThickness
16/02-Mb,16/04-Mb,32/08-Mb A2
0.860 0.0339
PackageBodyThickness
32/04-Mb 0.960 0.0378
Ball(Lead)Width
16/02-Mb,16/04-Mb,32/08-Mb b
0.325 0.375 0.425 0.0128 0.0148 0.0167
Ball(Lead)Width
32/04-Mb 0.350 0.40 0.450 0.0138 0.0157 0.0177
PackageBodyLength
16/02-Mb,16/04-Mb D
9.900 10.000 10.100 0.3898 0.3937 0.3976
PackageBodyLength
32/04-Mb,32/08-Mb 11.900 12.000 12.100 0.4685 0.4724 0.4764
PackageBodyWidth
16/02-Mb,16/04-Mb,32/04-Mb,32/08-Mb E 7.900 8.000 8.100 0.3110 0.3150 0.3189
Pitch e 0.800 0.0315
Ball(Lead)Count N 66 66
SeatingPlaneCoplanarity Y 0.100 0.0039
CornertoBallA1DistanceAlongE
16/02-Mb,16/04-Mb,32/04-Mb,32/08-Mb S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
CornertoBallA1DistanceAlongD
16/02-Mb,16/04-Mb S2 0.500 0.600 0.700 0.0197 0.0236 0.0276
CornertoBallA1DistanceAlongD
32/04-Mb,32/08-Mb S2 1.500 1.600 1.700 0.0591 0.0630 0.0669
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 67
F.2 MediaInformation
NOTE: Drawingisnottoscaleandisonlydesignedtoshoworientationofdevices.
Figure22.Stacked-CSPDeviceinTrayOrientation(8mmx10mmand8mmx12mm
DevicePin1
TrayChamfer
Figure23.Stacked-CSPDevicein24mmTape(8mmx10mmand8mmx12mm)
DevicePin1
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
68 Datasheet
AppendixGAdditionalInformation
OrderNumber Document/Tool
292216 AP-658DesigningforUpgradetotheAdvanced+BootBlockFlashMemory
292215 AP-657DesigningwiththeAdvanced+BootBlockFlashMemoryArchitecture
ContactYourIntel
Representative FlashDataIntegrator(FDI)SoftwareDeveloper’sKit
297874 FDIInteractive:PlaywithIntel’sFlashDataIntegratoronYourPC
NOTES:
1. PleasecalltheIntelLiteratureCenterat(800)548-4725torequestInteldocumentation.International
customersshouldcontacttheirlocalIntelordistributionsalesoffice.
2. VisitIntel’sWorldWideWebhomepageathttp://www.Intel.comorhttp://developer.intel.comfor
technicaldocumentationandtools.
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
Datasheet 69
AppendixHOrderingInformation
Table33.OrderingInformationfor0.25µmand0.18µm
.
Table34.OrderingInformationforCombinationswith16M0.13µmFlash
R D 2 8 F 3 2 0 8 C 3 T 7 0
Package
RD=8x12BallMatrixCSP
ProductLineDesignator
FlashDensity
320=x16(32Mbit)
160=x16(16Mbit)
SRAMDeviceDensity
16Mbit=70,90,110
32Mbit=70,90
AccessSpeed(ns)
T=TopBlocking
B=BottomBlocking
ProductFamily
C3=3VAdvanced+BootBlock
VCC=2.7V-3.3V
VPP=1.65V-3.3Vor
11.4V-12.6V
forallIntelFlashproducts
8=x16(8Mbit)
4=x16(4Mbit)
2=x16(2Mbit)
R D 2 8 F 1 6 0 2 C 3 T D 7 0
Package
RD=Stacked-CSP
ProductLineDesignator
16Mbit=70ns
AccessSpeed(ns)
38F=IntelFlashStackedMemory
FlashDensity
320=x16(32Mbit)
160=x16(16Mbit)
SRAMDeviceDensity
4=x16(4Mbit)
2=x16(2Mbit)
ParameterLocation
T=TopBlocking
B=BottomBlocking
D=0.13µm
Technology
Differentiator
C=Advanced+BootBlock
FlashMemory
ProductFamily
3VoltIntel®Advanced+BootBlockFlashMemoryStacked-CSPFamily
70 Datasheet
Table35.OrderingInformationforCombinationswith32M0.13µmFlash
R D 3 8 F 1 0 1 0 C 0 Z T L 0
Package
RD=Stacked-CSP
ProductLineDesignator
Density
Flash#1=1=32Mbit
Flash#2=0=NoDie
Flash#3=1=4MbitSRAM
=2=8MbitSRAM
Flash#4=0=NoDie
ProductFamily
0=OriginalVersionof
thisproduct:
FlashSpeed=70ns
FlashProcess=0.13µm
Vccq=2.7Vto3.3V
DeviceDetails
L=72ball"I"-ballout
PinoutIndicator
ParameterLocation
T=TopBlocking
B=BottomBlocking
Voltage
Z=3.0VI/O
C=Advanced+BootBlockFlashMemory
38F=IntelFlashStackedMemory
Table36.OrderingInformationValidCombinations
0.25µmC3
Stacked-CSP 0.18µmC3
Stacked-CSP 0.13µmC3
Stacked-CSP
32-Mbit
Nolongeravailable. RD28F3208C3T70
RD28F3208C3B70
RD28F3208C3T90
RD28F3208C3B90
RD28F3204C3T70
RD28F3204C3B70
RD38F1010C0ZTL0
RD38F1010C0ZBL0
RD38F1020C0ZTL0
RD38F1020C0ZBL0
16-Mbit
RD28F1604C3T90
RD28F1604C3B90
RD28F1604C3T110
RD28F1604C3B110
RD28F1602C3T90
RD28F1602C3B90
RD28F1602C3T110
RD28F1602C3B110
RD28F1602C3T70
RD28F1602C3B70 RD28F1602C3TD70
RD28F1602C3BD70
RD28F1604C3TD70
RD28F1604C3BD70