DF2628FA24V - Renesas Technology / Hitachi Semiconductor

Revision Date: Oct 04, 2005

16 H8S/2628 Group

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8S Family/H8S/2600 Series

Rev. 3.00

REJ09B0155-0300

The revision list can be viewed directly by

clicking the title page.

The revision list summarizes the locations of

revisions and additions. Details should always

be checked by referring to the relevant text.

Rev. 3.00 Oct 04, 2005 page ii of xl

1. These materials are intended as a reference to assist our customers in the selection of the Renesas

Technology Corp. product best suited to the customer's application; they do not convey any license

under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or

a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-

party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or

circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and

algorithms represents information on products at the time of publication of these materials, and are

subject to change by Renesas Technology Corp. without notice due to product improvements or

other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or

an authorized Renesas Technology Corp. product distributor for the latest product information

before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising

from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means,

including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

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information contained herein.

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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the

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8. Please contact Renesas Technology Corp. for further details on these materials or the products

contained therein.

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and

more reliable, but there is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate

measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or

(iii) prevention against any malfunction or mishap.

Keep safety first in your circuit designs!

Notes regarding these materials

Rev. 3.00 Oct 04, 2005 page iii of xl

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are

used as test pins or to red uce noise. If somethi ng is connected to the NC pins, the

operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins

are in their open states, intermediate levels are induced by noise in the vicinity, a pass-

through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the

chip and a low level is input on the reset pin. During the period where the states are

undefined, the register settings and the output state of each pin are also undefined. Design

your system so that it does not malfunction because of processing while it is in this

undefined state. For those products which have a reset function, reset the LSI immediately

after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers

may have been be allocated to these addresses. Do not access these registers; the system’s

operation is not guaranteed if they are accessed.

Rev. 3.00 Oct 04, 2005 page iv of xl

Config uration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Config uration of This Manual

3. Preface

4. Main Revisions in This Edition

5. Contents

6. Overview

7. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items:

i) Feature

ii) Input/Outpu t Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section

includes notes in relation to the descriptions given, and usage notes are given, as required, as the

final part of each section.

8. List of Registers

9. Electrical Characteristics

10.Appendix

The list of revisions is a summary of points that have been revised or added to earlier versions.

This does not include all of the revised contents. For details, see the actual locations in this

manual.

11.Index

Rev. 3.00 Oct 04, 2005 page v of xl

Preface

The H8S/2628 Group are single-chip microcomputers made up of the high-speed H8S/2600 CPU

as its core, and the peripheral functions required to configure a system. The H8S/2600 CPU has an

instruction set that is compatible with the H8/300 and H8/300H CPUs.

This LSI is equipped with a data transfer controller (DTC), ROM and RAM memory, a PC break

controller (PBC), a 16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), a

watchdog timer (WDT), a serial communication interface (SCI), a controller area network

(HCAN), a synchronous serial communication unit (SSU), an A/D converter, and I/O ports as on-

chip peripheral modules required for system configuration. This LSI is suitable for use as an

embedded microcomputer for high-level control systems. A single-power flash memory (F-

ZTATTM) version is available for this LSI’s ROM. This provides flexibility as it can be

reprogrammed in no time to cope with all situations from the early stages of mass production to

full-scale mass production. This is particularly applicable to application devices with

specifications that will most probably change.

Note: * F-ZTAT is a trademark of Renesas Technology, Corp.

Target Users: This manual was written for users who will be using the H8S/2628 Group in the

design of application systems. Target users are expected to understand the

fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8S/2628 Group to the target users.

Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a

detailed des cription of the instruction se t.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts

on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU’s functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the

List of Registers.

Rev. 3.00 Oct 04, 2005 page vi of xl

Example: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse unit or serial

communication, is implemented on more than one channel:

XXX_N (XXX is the register name and N is the channel

number)

Bit order: The MSB is on the left and the LSB is on the right.

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.

http://www.renesas.com/

H8S/2628 Group manuals:

Document Title Document No.

H8S/2628 Group Hardware Manual This manual

H8S/2600 Series, H8S/2000 Series Programming Manual REJ09B0139

User’s man uals for dev el opmen t tool s:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor

User’s Manual REJ10B0058

H8S, H8/300 Series Simulator/Debugger User’s Manual ADE-702-037

H8S, H8/300 Series High-performance Embedded Workshop,

High-performance Debugging Interface Tutorial ADE-702-231

High-performance Embedded Workshop User’s Manual ADE-702-201

Rev. 3.00 Oct 04, 2005 page vii of xl

Main Revisions for This Edition

Item Page Revision (See Manual for Details)

9.6.6 Pin Functions

Table 9.27 PA2 Pin

Function

148 Table 9.27 amended

RE in SCR_2 01

PA2DDR 0 1

—

Pin function PA2 input PA2 output RxD2 input

10.4.5 PMW Modes 219 Description amended

• PMW mode 2

(Before) … clearing by a synchronization register compare

match … → (After) … clearing by a duty cycle register

compare match …

373 Description amended

(Before) Local acceptance filter mask H (LAFMH) →

(After) Local acceptance filter mask L (LAFML)

15.3 Register

Descriptions

374 (Before) Local acceptance filter mask L (LAFML) →

(After) Local acceptance filter mask H (LAFMH)

15.3.1 Master

Control Regis ter

(MCR)

375 Description deleted

Reset Request

… [Setting condi tion]

• 1-write (software reset)

15.3.2 General

Status Register (GSR) 376 Description amended

Transm it/Receive Warn ing Flag

… [Setting condition]

• Third bit of Intermission after EOF (End of Frame)

[Clearing condition]

• Wh en TEC < 96 and REC < 96 or TEC ≥ 256 (bus off state)

Description amended

Remote Frame Request Interrupt Flag

… in a mail box (buffer), when MBIMR = 0.

15.3.11 Interrupt

Receive Message Interrupt Flag

… received normally, when MBIMR = 0.

Rev. 3.00 Oct 04, 2005 page viii of xl

Item Page Revision (See Manual for Details)

15.3.16 Unread

Message Status

393 Description amended

(Before) [Setting condition] • When a new message is received

before RXPR is cleared

[Clearing condition] • Writing 1

The received message has been overwritten by a new message

before being read. →

(After) The received message has been overwritten by a new

message before being read.

[ Setting condi tion] • When a new message is received before

RXPR is cleared

[Clearing condition] • Writing 1

15.3.18 Message

Control (MC15 to

MC0)

397 Description amended

Data Length Code

(Before) 1000: 8 bytes … 1111: 8 bytes → (After) 1***: 8 bytes

15.4.2 Initialization

after Hardware Reset

Figure 15.8 Detailed

Description of One Bit

403 Figure 15.8 amended

SYNC_SEG PRSEG PHSEG1 PHSEG2

Time segment 2

(TSEG2)

Time segment 1 (TSEG1)

1-bit time (25 to 8 time quanta)

4 to 16 time quanta 2 to 8 time quanta1 time quanta

Table 15.3 Setting

Range for TSEG1 and

TSEG2 in BCR

404 Note * amended

Note: * Settable when bits BRP is not B′000000.

15.8.10 HCAN TXCR

Operation 420 Description amended

Conditions: • The HRxD pin is stacked to 1 because of …

Countermeasures: • Transmission must not be canceled …

Countermeasure: • A transmit wait message must be …

15.8.12 Canceling

HCAN Reset and

HCAN Sleep Mode

421 Description amended

... reset for HCAN or HCAN sleep mode (MCR0 = 0 or MCR5

000

0), confirm that …

Section 16

Synchronous Serial

Communication Unit

(SSU)

423 Description deleted

... different clock polarity and clock phase. Figure 16.1 is a …

16.3.6 SS transmit

Data Register 3 to 0

(SSTDR3 to SSTDR0)

433 Description amended

… SSTDR0 are valid. Do not attempt to access invalid SS

transmit data registers. When the SSU detects …

Rev. 3.00 Oct 04, 2005 page ix of xl

Item Page Revision (See Manual for Details)

16.3.7 SS Receive

Data Register 3 to 0

(SSRDR3 to SSRDR0 )

434 Description amended

… SSRDR0 are valid. Do not attempt to access invalid SS

receive data registers. When the SSU has received …

16.4.4 Data

Transmission and Data

Reception

Figure 16.4 Example

of SSU Initialization

437 Figure 16.4 amended

[4]

End

Specify TE, RE, TEIE, TIE, RIE,

and CEIE bits simultaneously

438 Description amended

Data Transmission

(Before) … data to SSTDR after the TE bit in SSER is set to 1

cl ears the TDRE b it in SSSR to 0, and the SSTDR contents is

transferred to SSTRSR. → (After) … data to SSTDR after

initialization of the SSU automatically clears the TDRE bit in

SSSR to 0, and the contents of SSTDR is transferred to

SSTRSR.

Figure 16.6 Example

of Data Transmissi on

Flowchart

440 Figure 16.6 amended

Start

[1]

[2]

Initialization

Read TDRE in SSR

441 Description amended

Data Reception

(Before) … After the SSU sets the RE bi t in SSER to 1 and

dummy-reads SSRDR, data … → (After) … After initialization,

the SSU dummy-reads SSRDR and data …

Rev. 3.00 Oct 04, 2005 page x of xl

Item Page Revision (See Manual for Details)

16.4.4 Data

Transmission and Data

Reception

Figure 16.7 Example

of Reception Operation

442 Figure 16.7 amended

SCS

SSCK

(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0

(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0

(3) When 32-bit data length is selected (SSRDR0, SSRDR1, SSRDR2, and SSRDR3 are valid) with CPOS = 0 and CPHS = 0

SSI

RDRF

SSRDR1

SCS

SSCK

RDRF

SSRDR0

SSRDR0 SSRDR1

SCS

SSCK

RDRF

SSRDR0

SSRDR3

SSRDR1

SSRDR2

SSRDR1

SSRDR3

SSRDR0

1 frame

Bit

0Bit

1Bit

Bit

2Bit

Bit

3Bit

Bit

4Bit

Bit

5Bit

Bit

6Bit

Bit

LSI operation

Dummy-read

SSRDR0

Dummy-read

SSRDR0

Dummy-read

SSRDR0

Read SSRDR0

User operation

LSI operation

User operation

LSI operation

User operation

SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission)

RXI

interrupt

generated

RXI

interrupt

generated

RXI

interrupt

generated

RXI

interrupt

generated

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6Bit

7Bit

Bit

7Bit

6Bit

5Bit

4Bit

3Bit

2Bit

Bit

SSI

(LSB first)

SSI

(MSB first)

Bit

0to to to to

to to to to

Bit

7Bit

Bit

7Bit

Bit

7Bit

Bit

0Bit

7Bit

0Bit

7Bit

SSI

(LSB first)

SSI

(MSB first)

Bit

Figure 16.8 Example

of Data Reception

Flowchart

443 Figure 16.8 amended

[1]

[2]

Start

Initialization

Dummy-read SSRDR

Rev. 3.00 Oct 04, 2005 page xi of xl

Item Page Revision (See Manual for Details)

16.4.4 Data

Transmission and Data

Reception

Figure 16.9 Example

of Simultaneous

Transmission/

Reception Flowchart

445 Figure 16.9 amended

Start

Initialization[1]

[2] Read TDRE in SSSR

Yes

Continuous data

transmission/reception

Yes

Read TEND in SSSR

TEND = 1?

1-bit internal elapsed?

Clear TEND in SSSR to 0

Clear TE and RE in SSER to 0

Error processing

End transmission/reception

Note: Hatching boxes represent SSU internal operations.

16.4.5

SCS

Control and Conflict

Error

446 Description amended

(Before) … (Hi-Z) to detect arb itrat ion. The arbitration detection

period … → (After) …(Hi-Z) to detect conflict error. The conflict

detection period …

Figure 16.10 Conflict

Error Detection Timing

(Before Transf er Star t)

Figure 16.10 am ended

(Before) Arbitration detection period → (After) Conflict error

detection period

Figure 16.11 Conflict

Error Detection Timing

(After Transfer End)

447 Figure 16.11 am ended

(Before) Arbitration detection period → (After) Conflict error

detection period

Rev. 3.00 Oct 04, 2005 page xii of xl

Item Page Revision (See Manual for Details)

Table 21.2 amended

Function High-Speed Medium-

Speed Sleep Module

Stop Software

Standby Hardware

Standby

SCI

HCAN

Peripheral

functions

A/D

Operate Operate Operate Halted*

(reset/

retained)

Halted

(reset) Halted

(reset)

Section 21 Power-

Down Modes

Table 21.2 LSI

Internal States in Each

Mode

503

Note * amended

Notes: … has been, made are halted (reset or retained).

* The SCI’s TDR, RDR, and SSR are halted (reset), and the

other registers are halted (retai ned).

22. 3 Register States

in Each Operating

Mode

571, 572 Table amended

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

SMR_0 Initialized —————

———

——

———

——

———

—————

Initialized SCI_0

BRR_0 Initialized Initialized

SCR_0 Initialized Initialized

TDR_0 Initialized Initialized Initialized Initialized

SSR_0 Initialized Initialized Initialized Initialized

RDR_0 Initialized Initialized Initialized Initialized

SCMR_0 Initialized Initialized

SMR_2 Initialized Initialized SCI_2

BRR_2 Initialized Initialized

SCR_2 Initialized Initialized

TDR_2 Initialized Initialized Initialized Initialized

SSR_2 Initialized Initialized Initialized Initialized

RDR_2 Initialized Initialized Initialized Initialized

SCMR_2 Initialized Initialized

Section 23 Electrical

Characteristics 573 to 592 “Preliminary” deleted

Appendi x C Package

Dimensions

Figure C.1 FP-100M

Package Dimensions

594 Figure C.1 replaced

Rev. 3.00 Oct 04, 2005 page xiii of xl

Contents

Se ctio n 1 Ove r v iew............................................................................................................. 1

1.1 Overview........................................................................................................................... 1

1.2 Internal Block Diagram..................................................................................................... 2

1.3 Pin Arrangement............................................................................................................... 3

1.4 Pin Functions.................................................................................................................... 4

Se ctio n 2 CPU...................................................................................................................... 11

2.1 Features............................................................................................................................. 11

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 12

2.1.2 Differences from H8/300 CPU ............................................................................ 13

2.1.3 Differences from H8/300H CPU ......................................................................... 13

2.2 CPU Operating Modes...................................................................................................... 14

2.2.1 Normal Mode....................................................................................................... 14

2.2.2 A dvanced Mode................................................................................................... 15

2.3 Address Space................................................................................................................... 18

2.4 Registers ........................................................................................................................... 19

2.4.1 General Registers................................................................................................. 20

2.4.2 Program Counter (PC)......................................................................................... 21

2.4.3 Extended Control Register (EXR)....................................................................... 21

2.4.4 Condition-Code Register (CCR).......................................................................... 22

2.4.5 Multiply-Accumulate Register (MAC)................................................................ 23

2.4.6 Initial Values of CPU Registers........................................................................... 23

2.5 Data Formats..................................................................................................................... 24

2.5.1 General Register Data Formats............................................................................ 24

2.5.2 Memory Data Formats......................................................................................... 26

2.6 Instruction Set................................................................................................................... 27

2.6.1 Table of Instructions Classified by Function....................................................... 28

2.6.2 Basic Instruction Formats.................................................................................... 38

2.7 Addressing Modes and Effective Address Calculation..................................................... 39

2.7.1 Register DirectRn ............................................................................................ 40

2.7.2 Reg ister Indire ct@ERn.................................................................................... 40

2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn).............. 40

2.7.4 Reg ister Indirect wi th Post-In crem ent or Pre-Decreme nt@ERn+ or @-ERn.. 41

2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32 ................................... 41

2.7.6 Immediate#xx:8, #xx:16, or #xx:32................................................................. 42

2.7.7 Program-Counter Relative@(d:8, PC ) or @(d:16, PC) ................................... 42

2.7.8 Memory Indirect@@aa:8................................................................................ 42

2.7.9 Effective Address Calculation ............................................................................. 43

Rev. 3.00 Oct 04, 2005 page xiv of xl

2.8 Processing States .............................................................................................................. 46

2.9 Usage Note ....................................................................................................................... 47

2.9.1 Notes on Using the Bit Operation Instruction...................................................... 47

Se ctio n 3 MCU Ope r ating Mo des.................................................................................. 49

3.1 Operating Mode Selection................................................................................................ 49

3.2 Register Descriptions........................................................................................................49

3.2.1 Mode Control Register (MDCR)......................................................................... 50

3.2.2 System Control Register (SYSCR)...................................................................... 51

3.3 Pin Functions in Each Operating Mode............................................................................ 52

3.4 A ddress Map..................................................................................................................... 53

Section 4 Exception Handling......................................................................................... 55

4.1 Exception Handling Types and Priority............................................................................ 55

4.2 Exception Sources and Exception Vector Table............................................................... 55

4.3 Reset ................................................................................................................................. 57

4.3.1 Reset Exception Handling ................................................................................... 57

4.3.2 Interrupts after Reset............................................................................................ 59

4.3.3 State of On-Chip Peripheral Modules after Reset Release .................................. 60

4.4 Traces................................................................................................................................ 60

4.5 Interrupts........................................................................................................................... 61

4.6 Trap Instruction ................................................................................................................ 62

4.7 Stack Status after Exception Handling.............................................................................. 63

4.8 Usage Note ....................................................................................................................... 64

Se ctio n 5 I nterr upt Co n tr o ller.......................................................................................... 65

5.1 Features............................................................................................................................. 65

5.2 Input/Outpu t Pins.............................................................................................................. 67

5.3 Register Descriptions........................................................................................................67

5.3.1 Interrupt Priority Registers A to M (IPRA to IPRM) .......................................... 68

5.3.2 IRQ Enable Register (IER).................................................................................. 69

5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 70

5.3.4 IRQ Status Register (ISR).................................................................................... 72

5.4 Interrupt Sources............................................................................................................... 73

5.4.1 External Interrupts............................................................................................... 73

5.4.2 Internal Interrupts................................................................................................ 74

5.5 Interrupt Exception Handling Vector Table...................................................................... 74

5.6 Interrupt Control Modes and Interrupt Operation............................................................. 78

5.6.1 Interrupt Control Mode 0..................................................................................... 78

5.6.2 Interrupt Control Mode 2..................................................................................... 80

5.6.3 Interrupt Exception Handling Sequence.............................................................. 81

Rev. 3.00 Oct 04, 2005 page xv of xl

5.6.4 Interrupt Response Times.................................................................................... 83

5.6.5 DTC Activation by Interrupt................................................................................ 84

5.7 Usage Notes...................................................................................................................... 84

5.7.1 Conflict between Interrupt Generation and Disabling......................................... 84

5.7.2 Instructions that Disable Interrupts...................................................................... 85

5.7.3 When Interrupts Are Disabled............................................................................. 85

5.7.4 Interrupts during Execution of EEPMOV Instruction ......................................... 86

5.7.5 IRQ Interrupt ....................................................................................................... 86

Section 6 PC Break Controller (PBC)........................................................................... 87

6.1 Features............................................................................................................................. 87

6.2 Register Descriptions........................................................................................................88

6.2.1 Break Address Register A (BARA)..................................................................... 88

6.2.2 Break Address Register B (BARB) ..................................................................... 89

6.2.3 Break Control Register A (BCRA)...................................................................... 89

6.2.4 Break Control Register B (BCRB) ...................................................................... 90

6.3 Operation.......................................................................................................................... 90

6.3.1 PC Break Interrupt Due to Instruction Fetch....................................................... 90

6.3.2 PC Break Interrupt Due to Data Access .............................................................. 91

6.3.3 PC Break Operation at Consecutive Data Transfer ............................................. 91

6.3.4 Operation in Transi ti ons to Power-Down Modes................................................ 91

6.3.5 When Instruction Execution Is Delayed by One State......................................... 92

6.4 Usage Notes...................................................................................................................... 93

6.4.1 Module Stop Mode Setting.................................................................................. 93

6.4.2 PC Break Interrupts ............................................................................................. 93

6.4.3 CMFA and CMFB............................................................................................... 93

6.4.4 PC Break Interrupt when DTC Is Bus Master ..................................................... 93

6.4.5 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP,

TRAPA, RTE, or RTS Instruction....................................................................... 93

6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction....................................... 93

6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction.......... 94

6.4.8 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc

Instruction............................................................................................................ 94

Se ctio n 7 Bus Co ntr o ller................................................................................................... 95

7.1 Basic Timing..................................................................................................................... 95

7.1.1 On-Chip Memory Access Timing (ROM, RAM)................................................ 95

7.1.2 On-Chip Support Module Access Timing ........................................................... 96

7.1.3 On-Chip HCAN Module Access Timing............................................................. 97

7.1.4 On-Chip SSU Module and Realtime Input Port Data Register Access Timing... 98

7.2 Bus Arbitration ................................................................................................................. 99

Rev. 3.00 Oct 04, 2005 page xvi of xl

7.2.1 Order of Priority of the Bus Masters.................................................................... 99

7.2.2 Bus Transfe r Timing............................................................................................ 99

Section 8 Data Transfer Controller (DTC)................................................................... 101

8.1 Features............................................................................................................................. 101

8.2 Register Descriptions........................................................................................................ 103

8.2.1 DTC Mode Register A (MRA)............................................................................ 104

8.2.2 DTC Mode Register B (MRB)............................................................................. 105

8.2.3 DTC Source Address Register (SAR).................................................................. 105

8.2.4 DTC Destination Address Register (DAR).......................................................... 105

8.2.5 DTC Transfer Count Register A (CRA).............................................................. 105

8.2.6 DTC Transfer Count Register B (CRB)............................................................... 106

8.2.7 DTC Enable Registers (DTCER)......................................................................... 106

8.2.8 DTC Vector Register (DTVECR)........................................................................ 107

8.3 Activation Sources............................................................................................................ 108

8.4 Location of Register Information and DTC Vector Table................................................ 109

8.5 Operation.......................................................................................................................... 112

8.5.1 Normal Mode....................................................................................................... 113

8.5.2 Repeat Mode........................................................................................................ 114

8.5.3 Block Transfer Mode........................................................................................... 115

8.5.4 Chain Transfer..................................................................................................... 117

8.5.5 Interrupts.............................................................................................................. 118

8.5.6 Operation Timing................................................................................................. 118

8.5.7 Number of DTC Execution States ....................................................................... 119

8.6 Procedures for Using DTC ............................................................................................... 121

8.6.1 Activation by Interrupt ........................................................................................ 121

8.6.2 Activation by Software........................................................................................ 121

8.7 Examples of Use of the DTC............................................................................................ 122

8.7.1 Normal Mode....................................................................................................... 122

8.7.2 Chain Transfer..................................................................................................... 123

8.7.3 Software Activation............................................................................................. 124

8.8 Usage Notes...................................................................................................................... 125

8.8.1 Module Stop Mode Setting.................................................................................. 125

8.8.2 On-Chip RAM ..................................................................................................... 125

8.8.3 DTCE Bit Setting................................................................................................. 125

Section 9 I/O Ports.............................................................................................................. 127

9.1 Port 1................................................................................................................................. 131

9.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 131

9.1.2 Port 1 Data Register (P1DR) ............................................................................... 132

9.1.3 Port 1 Register (PORT1) ..................................................................................... 132

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9.1.4 Pin Functions....................................................................................................... 133

9.2 Port 3................................................................................................................................. 136

9.2.1 Port 3 Data Direction Register (P3DDR)............................................................. 136

9.2.2 Port 3 Data Register (P3DR) ............................................................................... 137

9.2.3 Port 3 Register (PORT3) ..................................................................................... 137

9.2.4 Port 3 Open-Drain Control Register (P3ODR).................................................... 138

9.2.5 Pin Functions....................................................................................................... 138

9.3 Port 4................................................................................................................................. 140

9.3.1 Port 4 Register (PORT4) ..................................................................................... 140

9.4 Port 7................................................................................................................................. 140

9.4.1 Port 7 Data Direction Register (P7DDR)............................................................. 141

9.4.2 Port 7 Data Register (P7DR) ............................................................................... 141

9.4.3 Port 7 Register (PORT7) ..................................................................................... 142

9.4.4 Pin Functions....................................................................................................... 142

9.5 Port 9................................................................................................................................. 144

9.5.1 Port 9 Register (PORT9) ..................................................................................... 144

9.6 Port A................................................................................................................................ 145

9.6.1 Port A Data Direction Register (PADDR)........................................................... 145

9.6.2 Port A Data Register (PADR).............................................................................. 146

9.6.3 Port A Register (PORTA).................................................................................... 146

9.6.4 Port A Pull-Up MOS Control Register (PAPCR)................................................ 147

9.6.5 Port A Open-Drain Control Register (PAODR).................................................. 147

9.6.6 Pin Functions....................................................................................................... 148

9.7 Port B................................................................................................................................ 149

9.7.1 Port B Data Direction Register (PBDDR)........................................................... 149

9.7.2 Port B Data Register (PBDR).............................................................................. 150

9.7.3 Port B Register (PORTB).................................................................................... 150

9.7.4 Port B Pull-Up MOS Control Register (PBPCR) ................................................ 151

9.7.5 Port B Open-Drain Control Register (PBODR)................................................... 151

9.7.6 Pin Functions....................................................................................................... 152

9.8 Port C................................................................................................................................ 154

9.8.1 Port C Data Direction Register (PCDDR)........................................................... 154

9.8.2 Port C Data Register (PCDR).............................................................................. 155

9.8.3 Port C Register (PORTC).................................................................................... 155

9.8.4 Port C Pull-Up MOS Control Register (PCPCR) ................................................ 156

9.8.5 Port C Open-Drain Control Register (PCODR)................................................... 156

9.8.6 Pin Functions....................................................................................................... 157

9.9 Port D................................................................................................................................ 160

9.9.1 Port D Data Direction Register (PDDDR)........................................................... 160

9.9.2 Port D Data Register (PDDR).............................................................................. 161

9.9.3 Port D Register (PORTD).................................................................................... 161

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9.9.4 Port D Pull-Up MOS Control Register (PDPCR)................................................ 162

9.9.5 Port D RealTime Input Data Register (PDRTIDR)............................................. 162

9.10 Port F ................................................................................................................................ 163

9.10.1 Port F Data Direction Register (PFDDR)............................................................ 163

9.10.2 Port F Data Register (PFDR)............................................................................... 164

9.10.3 Port F Register (PORTF)..................................................................................... 164

9.10.4 Pin Functions....................................................................................................... 165

Section 10 16-Bit Timer Pulse Un it (TPU).................................................................. 167

10.1 Features............................................................................................................................. 167

10.2 Input/Outpu t Pins.............................................................................................................. 171

10.3 Register Descriptions........................................................................................................ 172

10.3.1 Timer Control Register (TCR)............................................................................. 174

10.3.2 Timer Mode Register (TMDR)............................................................................ 179

10.3.3 Timer I/O Control Register (TIOR)..................................................................... 181

10.3.4 Timer Interrupt Enable Register (TIER).............................................................. 198

10.3.5 Timer Status Register (TSR)................................................................................ 200

10.3.6 Timer Counter (TCNT)........................................................................................ 203

10.3.7 Timer General Register (TGR)............................................................................ 203

10.3.8 Timer Start Register (TSTR) ............................................................................... 203

10.3.9 Timer Synchro Register (TSYR)......................................................................... 204

10.4 Operation.......................................................................................................................... 205

10.4.1 Basic Functions.................................................................................................... 205

10.4.2 Synchronous Operation ....................................................................................... 211

10.4.3 Buffer Operation.................................................................................................. 212

10.4.4 Cascaded Operation............................................................................................. 217

10.4.5 PWM Modes........................................................................................................ 219

10.4.6 Phase Counting Mode.......................................................................................... 224

10.5 Interrupt Sources............................................................................................................... 231

10.6 DTC Activation ................................................................................................................ 233

10.7 A/D Converter Activation................................................................................................. 233

10.8 Operation Timing.............................................................................................................. 234

10.8.1 Input/Outpu t Timing............................................................................................ 234

10.8.2 Interrupt Signal Timing ....................................................................................... 237

10.9 Usage Notes...................................................................................................................... 241

10.9.1 Module Stop Mode Setting.................................................................................. 241

10.9.2 Input Clock Restrictions ...................................................................................... 241

10.9.3 Caution on Period Setting.................................................................................... 242

10.9.4 Conflict between TCNT Write and Clear Operations ......................................... 242

10.9.5 Conflict between TCNT Write and Increment Operations.................................. 243

10.9.6 Conflict between TGR Write and Compare Match ............................................. 244

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10.9.7 Conflict between Buffer Register Write and Compare Match............................. 245

10.9.8 Conflict between TGR Read and Input Capture.................................................. 246

10.9.9 Conflict between TGR Write and Input Capture................................................. 247

10.9.10 Conflict between Buffer Register Write and Input Capture................................. 248

10.9.11 Conflict between Overflow/Underflow and Counter Clearing............................ 249

10.9.12 Conflict between TCNT Write and Overflow/Underflow ................................... 250

10.9.13 Multiplexing of I/O Pins...................................................................................... 250

10.9.14 Interrupts in Module Stop Mode.......................................................................... 250

Section 11 8-Bit Timers..................................................................................................... 251

11.1 Features............................................................................................................................. 251

11.2 Input/Outpu t Pins.............................................................................................................. 253

11.3 Register Descriptions........................................................................................................ 253

11.3.1 Timer Counters (TCNT)...................................................................................... 254

11.3.2 Time Constant Registers A (TCORA)................................................................. 254

11.3.3 Time Constant Registers B (TCORB) ................................................................. 254

11.3.4 Timer Control Registers (TCR)........................................................................... 255

11.3.5 Timer Control/Status Registers (TCSR).............................................................. 257

11.4 Operation.......................................................................................................................... 262

11.4.1 Pulse Output ........................................................................................................ 262

11.5 Operation Timing.............................................................................................................. 263

11.5.1 TCNT Incremen ta tion Timing............................................................................. 263

11.5.2 Timing of CMFA and CMFB Setting When a Compare-Match Occurs ............. 264

11.5.3 Timing of Timer Output When a Compare-Match Occurs.................................. 264

11.5.4 Timing of Compare-Match Clear When a Compare-Match Occurs.................... 265

11.5.5 TCNT External Reset Timing.............................................................................. 265

11.5.6 Timing of Overflow Flag (OVF) Setting............................................................. 266

11.6 Operation with Cascaded Connection............................................................................... 267

11.6.1 16-Bit Count Mode.............................................................................................. 267

11.6.2 Compare-Match Count Mode.............................................................................. 267

11.7 Interrupt Sources............................................................................................................... 268

11.7.1 Interrupt Sources and DTC Activation................................................................ 268

11.7.2 A/D Converter Activation.................................................................................... 268

11.8 Usage Notes...................................................................................................................... 269

11.8.1 Conflict between TCNT Write and Clear............................................................ 269

11.8.2 Conflict between TCNT Write and Increment..................................................... 270

11.8.3 Conflict between TCOR Write and Compare-Match........................................... 271

11.8.4 Conflict between Compare-Matches A and B ..................................................... 271

11.8.5 Switching of Internal Clocks and TCNT Operation ............................................ 272

11.8.6 Conflict betw een Interrup ts and Module Stop Mode........................................... 273

11.8.7 Notes on Cascaded Connection........................................................................... 273

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Secti on 12 Programmable Pulse Generator (PPG).................................................... 275

12.1 Features............................................................................................................................. 275

12.2 Input/Outpu t Pins.............................................................................................................. 277

12.3 Register Descriptions........................................................................................................ 277

12.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ........................................ 278

12.3.2 Output Data Registers H, L (PODRH, PODRL) ................................................. 279

12.3.3 Next Data Registers H, L (NDRH, NDRL)......................................................... 280

12.3.4 PPG Output Control Register (PCR) ................................................................... 282

12.3.5 PPG Output Mode Register (PMR) ..................................................................... 283

12.4 Operation.......................................................................................................................... 284

12.4.1 Overview.............................................................................................................. 284

12.4.2 Output Timing ..................................................................................................... 285

12.4.3 Sample Setup Procedure for Normal Pulse Output.............................................. 286

12.4.4 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 287

12.4.5 Non-Overlapping Pulse Output ........................................................................... 288

12.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output.............................. 290

12.4.7 Example of Non-Overlapping Pulse Output (Example of Four-Phase

Complementary Non-Overlapping Output)......................................................... 291

12.4.8 Inverted Pulse Outpu t.......................................................................................... 293

12.4.9 Pulse Output Triggered by Input Capture............................................................ 294

12.5 Usage Notes...................................................................................................................... 294

12.5.1 Module Stop Mode Setting.................................................................................. 294

12.5.2 Operation of Pulse Output Pins ........................................................................... 294

Section 13 Watchdog Timer............................................................................................. 295

13.1 Features............................................................................................................................. 295

13.2 Register Descriptions........................................................................................................ 296

13.2.1 Timer Counter (TCNT)........................................................................................ 296

13.2.2 Timer Control/Status Register (TCSR)................................................................ 297

13.2.3 Reset Control/Status Register (RSTCSR)............................................................ 299

13.3 Operation.......................................................................................................................... 300

13.3.1 Watchdog Timer Mode Operation....................................................................... 300

13.3.2 Interval Timer Mode............................................................................................ 300

13.4 Interrupts........................................................................................................................... 301

13.5 Usage Notes...................................................................................................................... 301

13.5.1 Notes on Register Access .................................................................................... 301

13.5.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 302

13.5.3 Changing Value of CKS2 to CKS0 ..................................................................... 303

13.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 303

13.5.5 Internal Reset in Watchdog Timer Mode............................................................. 303

13.5.6 OVF Flag Clearing in Interval Timer Mode........................................................ 303

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Section 14 Serial Communication Interface (SC I).................................................... 305

14.1 Features............................................................................................................................. 305

14.2 Input/Outpu t Pins.............................................................................................................. 307

14.3 Register Descriptions........................................................................................................ 307

14.3.1 Receive Shift Register (RSR) .............................................................................. 308

14.3.2 Receive Data Register (RDR).............................................................................. 308

14.3.3 Transmit Data Register (TDR) ............................................................................ 308

14.3.4 Transmit Shift Register (TSR)............................................................................. 308

14.3.5 Serial Mode Register (SMR) ............................................................................... 309

14.3.6 Serial Control Register (SCR)............................................................................. 313

14.3.7 Serial Status Register (SSR) ................................................................................ 316

14.3.8 Smart Card Mode Register (SCMR).................................................................... 322

14.3.9 Bit Rate Register (BRR)...................................................................................... 323

14.4 Operation in Asynchronous Mode.................................................................................... 330

14.4.1 Data Transfer Forma t........................................................................................... 330

14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 332

14.4.3 Clock.................................................................................................................... 333

14.4.4 SCI Initialization (Asynchronous Mode)............................................................. 334

14.4.5 Data Transmi ssion (A sy nchronou s Mode ) .......................................................... 335

14.4.6 Serial Data Reception (Asynchronous Mode) ..................................................... 337

14.5 Multiprocessor Communication Function ........................................................................ 341

14.5.1 Multiprocessor Serial Data Transmission............................................................ 342

14.5.2 Multiprocessor Serial Data Reception................................................................. 343

14.6 Operation in Clocked Synchronous Mode........................................................................ 347

14.6.1 Clock.................................................................................................................... 347

14.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 348

14.6.3 Serial Data Transmission (Clocked Synchronous Mode).................................... 349

14.6.4 Serial Data Reception (Clocked Synchronous Mode) ......................................... 352

14.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous

Mode) .................................................................................................................. 354

14.7 Operation in Smart Card Interface.................................................................................... 356

14.7.1 Pin Connection Example ..................................................................................... 356

14.7.2 Data Format (Except for Block Transfer Mode).................................................. 357

14.7.3 Block Transfer Mode........................................................................................... 359

14.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface

Mode.................................................................................................................... 359

14.7.5 Initialization......................................................................................................... 360

14.7.6 Data Transmi ssion (Exc ept for Block Transfer Mod e)........................................ 361

14.7.7 Serial Data Reception (Except for Block Transfer Mode)................................... 364

14.7.8 Clock Output Control .......................................................................................... 366

14.8 Interrupt Sources............................................................................................................... 368

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14.8.1 Interrupts in Normal Serial Communication Interface Mode.............................. 368

14.8.2 Interrupts in Smart Card Interface Mode............................................................. 369

14.9 Usage Notes...................................................................................................................... 370

14.9.1 Module Stop Mode Setting.................................................................................. 370

14.9.2 Break Detection and Processing .......................................................................... 370

14.9.3 Mark State and Break Detection.......................................................................... 370

14.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode

Only).................................................................................................................... 370

Section 15 Controller Area Network (HCAN)........................................................... 371

15.1 Features............................................................................................................................. 371

15.2 Input/Outpu t Pins.............................................................................................................. 373

15.3 Register Descriptions........................................................................................................ 373

15.3.1 Master Control Register (MCR) .......................................................................... 374

15.3.2 General Status Register (GSR) ............................................................................ 375

15.3.3 Bit Configuration Register (BCR)....................................................................... 377

15.3.4 Mailbox Configuration Register (MBCR)........................................................... 379

15.3.5 Transmit Wait Register (TXPR).......................................................................... 380

15.3.6 Transmit Wait Cancel Register (TXCR).............................................................. 381

15.3.7 Transmit Acknowledge Register (TXACK)........................................................ 382

15.3.8 Abort Acknowledge Register (ABACK)............................................................. 383

15.3.9 Receive Complete Register (RXPR).................................................................... 384

15.3.10 Remote Request Register (RFPR) ....................................................................... 385

15.3.11 Interrupt Register (IRR)....................................................................................... 386

15.3.12 Mailbox Interrupt Mask Register (MBIMR) ....................................................... 390

15.3.13 Interrupt Mask Register (IMR)............................................................................ 391

15.3.14 Receive Error Counter (REC).............................................................................. 392

15.3.15 Transmit Error Counter (TEC) ............................................................................ 392

15.3.16 Unread Message Status Register (UMSR)........................................................... 393

15.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 394

15.3.18 Message Control (MC15 to MC0)....................................................................... 396

15.3.19 Message Data (MD15 to MD0)........................................................................... 398

15.3.20 HCAN Monitor Register (HCANMON) ............................................................. 399

15.4 Operation.......................................................................................................................... 400

15.4.1 Hardware and Software Resets............................................................................ 400

15.4.2 Initialization after Hardware Reset...................................................................... 400

15.4.3 Messag e Transmi ssion......................................................................................... 405

15.4.4 Message Reception.............................................................................................. 409

15.4.5 HCAN Sleep Mode .............................................................................................. 412

15.4.6 HCAN Halt Mode................................................................................................ 415

15.5 Interrupt Sources............................................................................................................... 416

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15.6 DTC Interface................................................................................................................... 417

15.7 CAN Bus Interface ........................................................................................................... 418

15.8 Usage Notes...................................................................................................................... 418

15.8.1 Module Stop Mode Setting.................................................................................. 418

15.8.2 Reset .................................................................................................................... 418

15.8.3 HCAN Sleep Mode .............................................................................................. 419

15.8.4 Interrupts.............................................................................................................. 419

15.8.5 Error Counters ..................................................................................................... 419

15.8.6 Register Access.................................................................................................... 419

15.8.7 HCAN Medium-Speed Mode.............................................................................. 419

15.8.8 Register Hold in Standby Modes......................................................................... 419

15.8.9 Use on Bit Manipulation Instructions.................................................................. 419

15.8.10 HCAN TXCR Operation ..................................................................................... 420

15.8.11 HCAN Transmit Procedure ................................................................................. 421

15.8.12 Canceling HCAN Reset and HCAN Sleep Mode................................................ 421

15.8.13 Accessing Mailbox in HCAN Sleep Mode.......................................................... 421

Sect ion 16 Synchronous Serial C om mun ication Unit (SSU)................................. 423

16.1 Features............................................................................................................................. 423

16.2 Input/Outpu t Pins.............................................................................................................. 425

16.3 Register Descriptions........................................................................................................ 425

16.3.1 SS Control Register H (SSCRH) ......................................................................... 426

16.3.2 SS Control Register L (SSCRL).......................................................................... 428

16.3.3 SS Mode Register (SSMR).................................................................................. 429

16.3.4 SS Enable Register (SSER) ................................................................................. 430

16.3.5 SS Status Register (SSSR)................................................................................... 431

16.3.6 SS Transmit Data Register 3 to 0 (SSTDR3 to SSTDR0)................................... 433

16.3.7 SS Receive Data Register 3 to 0 (SSRDR3 to SSRDR0) .................................... 434

16.3.8 SS Shift Register (SSTRSR)................................................................................ 434

16.4 Operation.......................................................................................................................... 435

16.4.1 Transfer Clock..................................................................................................... 435

16.4.2 Relationship of Clock Phase, Polari ty, and Data................................................. 435

16.4.3 Relationship between Data I/O Pins and the Shift Register................................. 436

16.4.4 Data Transmission and Data Reception............................................................... 437

16.4.5

SCS

Pin Control and Conflict Error .................................................................... 446

16.5 Interrupt Requests............................................................................................................. 447

16.6 Usage Note ....................................................................................................................... 448

16.6.1 Setting of Module Stop Mode.............................................................................. 448

Section 17 A/D Converter................................................................................................. 449

17.1 Features............................................................................................................................. 449

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17.2 Input/Outpu t Pins.............................................................................................................. 451

17.3 Register Description ......................................................................................................... 452

17.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 452

17.3.2 A/D Control/Status Register (ADCSR) ............................................................... 453

17.3.3 A/D Control Register (ADCR) ............................................................................ 455

17.4 Operation.......................................................................................................................... 456

17.4.1 Single Mode......................................................................................................... 456

17.4.2 Scan Mode........................................................................................................... 456

17.4.3 Input Sampling and A/D Conversion Time......................................................... 457

17.4.4 External Trig g er Input Timing............................................................................. 459

17.5 Interrupt Source................................................................................................................ 459

17.6 A/D Conversion Accuracy Definitions............................................................................. 460

17.7 Usage Notes...................................................................................................................... 462

17.7.1 Module Stop Mode Setting.................................................................................. 462

17.7.2 Permissible Signal Source Impedance................................................................. 462

17.7.3 Influences on Absolute Accuracy........................................................................ 462

17.7.4 Range of Analog Power Supply and Other Pin Settings...................................... 463

17.7.5 Notes on Board Design........................................................................................ 463

17.7.6 Notes on Noise Countermeasures........................................................................ 463

Se ctio n 1 8 RAM.................................................................................................................. 465

Se ctio n 1 9 ROM.................................................................................................................. 467

19.1 Features............................................................................................................................. 467

19.2 Mode Transition s.............................................................................................................. 468

19.3 Block Configuration ......................................................................................................... 472

19.4 Input/Outpu t Pins.............................................................................................................. 473

19.5 Register Descriptions........................................................................................................ 473

19.5.1 Flash Memory Control Register 1 (FLMCR1) .................................................... 473

19.5.2 Flash Memory Control Register 2 (FLMCR2) .................................................... 475

19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 475

19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 476

19.5.5 RAM Emulation Register (RAMER)................................................................... 476

19.6 On-Board Programming Modes........................................................................................ 477

19.6.1 Boot Mode........................................................................................................... 478

19.6.2 Programming/Erasing in User Program Mode..................................................... 480

19.7 Flash Memory Emulation in RAM................................................................................... 482

19.8 Flash Memory Programming/Erasing............................................................................... 484

19.8.1 Program/Program-Verify..................................................................................... 484

19.8.2 Erase/Erase-Verify............................................................................................... 486

19.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 486

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19.9 Program/Era se Protec tion................................................................................................. 488

19.9.1 Hardware Pro tection............................................................................................ 488

19.9.2 Softw are Protection ............................................................................................. 488

19.9.3 Error Protection ................................................................................................... 488

19.10 Programmer Mo de............................................................................................................ 489

19.11 Power-Down States for Flash Memory............................................................................. 489

19.12 Note on Switching from F-ZTAT Version to Masked ROM Version.............................. 490

Section 20 Clock Pulse Generator.................................................................................. 491

20.1 Register Descriptions........................................................................................................ 492

20.1.1 System Clock Control Register (SCKCR)........................................................... 492

20.1.2 Low-Power Control Register (LPWRCR)........................................................... 493

20.2 Oscillator .......................................................................................................................... 494

20.2.1 Connecting a Crystal Resonator .......................................................................... 494

20.2.2 External Clock Input............................................................................................ 495

20.3 PLL Circuit....................................................................................................................... 497

20.4 Medium-Speed Clock Divider.......................................................................................... 497

20.5 Bus Master Clock Selection Circuit.................................................................................. 497

20.6 Usage Notes...................................................................................................................... 498

20.6.1 Note on Crystal Resonator................................................................................... 498

20.6.2 Note on Board Design.......................................................................................... 498

Section 21 Power-Down Modes...................................................................................... 501

21.1 Register Descriptions........................................................................................................ 504

21.1.1 Standby Control Register (SBYCR).................................................................... 504

21.1.2 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC) .................. 506

21.2 Medium-Speed Mode ....................................................................................................... 507

21.3 Sleep Mode....................................................................................................................... 508

21.3.1 Transition to Sleep Mode..................................................................................... 508

21.3.2 Clearing Sleep Mode ........................................................................................... 508

21.4 Software Standby Mode.................................................................................................... 509

21.4.1 Transition to Software Standby Mode................................................................. 509

21.4.2 Clearing Software Standby Mode........................................................................ 509

21.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 510

21.4.4 Software Standby Mode Application Example.................................................... 511

21.5 Hardware Standby Mode.................................................................................................. 512

21.5.1 Transition to Hardware Standby Mode................................................................ 512

21.5.2 Clearing Hardware Standby Mode ...................................................................... 512

21.5.3 Hardware Standby Mode Timings....................................................................... 512

21.6 Module Stop Mode........................................................................................................... 513

21.7 φ Clock Output Disabling Function.................................................................................. 514

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21.8 Usage Notes...................................................................................................................... 515

21.8.1 I/O Port Status ..................................................................................................... 515

21.8.2 Current Consumption during Oscillation Stabilization Wait Period.................... 515

21.8.3 DTC Module Stop ............................................................................................... 515

21.8.4 On-Chip Peripheral Module Interrupt.................................................................. 515

21.8.5 Writing to MSTPCR............................................................................................ 515

Section 22 List of Regi s ters.............................................................................................. 517

22.1 Register Addresses (Address Order)................................................................................. 518

22.2 Register Bits ..................................................................................................................... 536

22.3 Register States in Each Operating Mode .......................................................................... 556

Section 23 Electrical Characteristics............................................................................. 573

23.1 Absolute Maximum Ratings............................................................................................. 573

23.2 DC Characteristics............................................................................................................ 574

23.3 AC Characteristics............................................................................................................ 576

23.3.1 Clock Timing....................................................................................................... 577

23.3.2 Control Signal Timing......................................................................................... 578

23.3.3 Timing of On-Chip Peripheral Modules.............................................................. 580

23.4 A/D Conversion Characteristics ....................................................................................... 589

23.5 Flash Memory Characteristics .......................................................................................... 590

Appendix.................................................................................................................................. 593

A. I/O Port States in Each Pin State....................................................................................... 593

B. Product Code Lineup........................................................................................................ 594

C. Package Dimensions......................................................................................................... 594

Index.......................................................................................................................................... 595

Rev. 3.00 Oct 04, 2005 page xxvii of xl

Figures

Section 1 Overview

Figure 1.1 Internal Block Diagram ....................................................................................... 2

Figure 1.2 Pin Arrangement.................................................................................................. 3

Section 2 CPU

Figure 2.1 Exception Vector Table (Normal Mode)............................................................. 15

Figure 2.2 Stack Structure in Normal Mode......................................................................... 15

Figure 2.3 Exception Vector Table (Advanced Mode)......................................................... 16

Figure 2.4 Stack Structure in Advanced Mode..................................................................... 17

Figure 2.5 Memory Map....................................................................................................... 18

Figure 2.6 CPU Registers...................................................................................................... 19

Figure 2.7 Usage of General Registers.................................................................................. 20

Figure 2.8 Stack.................................................................................................................... 21

Figure 2.9 General Register Data Formats (1)...................................................................... 24

Figure 2.9 General Register Data Formats (2)...................................................................... 25

Figure 2.10 Memory Data Formats......................................................................................... 26

Figure 2.11 Instruction Formats (Examples)........................................................................... 39

Figure 2.12 Branch Address Specification in Memory Indirect Mode ................................... 43

Figure 2.13 State Transitions.................................................................................................. 47

Section 3 MCU Opera tin g Modes

Figure 3.1 Address Map........................................................................................................ 53

Section 4 Exception Handling

Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)....................... 58

Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled:

Not Available in this LSI).................................................................................... 59

Figure 4.3 Stack Status after Exception Handling................................................................. 63

Figure 4.4 Operation when SP Value Is Odd........................................................................ 64

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller................................................................ 66

Figure 5.2 Block Diagram of Interrupts IRQ5 to IRQ0........................................................ 73

Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 79

Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2............. 81

Figure 5.5 Interrupt Exception Handling .............................................................................. 82

Figure 5.6 Conflict between Interrupt Generation and Disabling......................................... 85

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Section 6 PC Break Contro ller (P BC)

Figure 6.1 Block Diagram of PC Break Controller............................................................... 88

Figure 6.2 Operation in Power-Down Mode Transitions...................................................... 92

Section 7 Bus Controller

Figure 7.1 On-Chip Memory Access Cycle.......................................................................... 95

Figure 7.2 On-Chip Support Module Access Cycle.............................................................. 96

Figure 7.3 On-Chip HCAN Module Access Cycle (with Wait States) ................................. 97

Figure 7.4 On-Chip SSU Module Access Cycle................................................................... 98

Section 8 Data Transfer Controller (DTC)

Figure 8.1 Block Diagram of DTC ....................................................................................... 102

Figure 8.2 Block Diagram of DTC Activation Source Control............................................. 108

Figure 8.3 Location of DTC Register Information in Address Space................................... 109

Figure 8.4 Flowchart of DTC Operation............................................................................... 112

Figure 8.5 Memory Mapping in Normal Mode..................................................................... 113

Figure 8.6 Memory Mapping in Repeat Mode...................................................................... 114

Figure 8.7 Memory Mapping in Block Transfer Mode......................................................... 116

Figure 8.8 Chain Transfer Operation.................................................................................... 117

Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)................ 118

Figure 8.10 DTC Operation Timing (Example of Block Transfer Mode,

with Block Size of 2)........................................................................................... 119

Figure 8.11 DTC Operation Timing (Example of Chain Transfer)......................................... 119

Section 10 16-Bit Timer Pulse Unit (TPU)

Figure 10.1 Block Diagram of TPU........................................................................................ 170

Figure 10.2 Example of Counter Operation Setting Procedure............................................... 205

Figure 10.3 Free-Running Counter Operation ........................................................................ 206

Figure 10.4 Periodic Counter Operation................................................................................. 207

Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match.......... 207

Figure 10.6 Example of 0 Output/1 Output Operation............................................................ 208

Figure 10.7 Example of Toggle Output Operation.................................................................. 208

Figure 10.8 Example of Input Capture Operation Setting Procedure...................................... 209

Figure 10.9 Example of Input Capture Operation................................................................... 210

Figure 10.10 Example of Synchronous Operation Setting Procedure....................................... 211

Figure 10.11 Example of Synchronous Operation.................................................................... 212

Figure 10.12 Compare Match Buffer Operation....................................................................... 213

Figure 10.13 Input Capture Buffer Operation........................................................................... 213

Figure 10.14 Example of Buffer Operation Setting Procedure................................................. 214

Figure 10.15 Example of Buffer Operation (1)......................................................................... 215

Figure 10.16 Example of Buffer Operation (2)......................................................................... 216

Rev. 3.00 Oct 04, 2005 page xxix of xl

Figure 10.17 Cascaded Operation Setting Procedure................................................................ 217

Figure 10.18 Example of Cascaded Operation (1).................................................................... 218

Figure 10.19 Example of Cascaded Operation (2).................................................................... 218

Figure 10.20 Example of PWM Mode Setting Procedure......................................................... 221

Figure 10.21 Example of PWM Mode Operation (1) ............................................................... 221

Figure 10.22 Example of PWM Mode Operation (2) ............................................................... 222

Figure 10.23 Example of PWM Mode Operation (3) ............................................................... 223

Figure 10.24 Example of Phase Counting Mode Setting Procedure......................................... 224

Figure 10.25 Example of Phase Counting Mode 1 Operation................................................... 225

Figure 10.26 Example of Phase Counting Mode 2 Operation................................................... 226

Figure 10.27 Example of Phase Counting Mode 3 Operation................................................... 227

Figure 10.28 Example of Phase Counting Mode 4 Operation................................................... 228

Figure 10.29 Phase Counting Mode Application Example....................................................... 230

Figure 10.30 Count Timing in Internal Clock Operation.......................................................... 234

Figure 10.31 Count Timing in External Clock Operation......................................................... 234

Figure 10.32 Output Compare Output Timing.......................................................................... 235

Figure 10.33 Input Capture Input Signal Timing...................................................................... 235

Figure 10.34 Counter Clear Timing (Compare Match)............................................................. 236

Figure 10.35 Counter Clear Timing (Input Capture) ................................................................ 236

Figure 10.36 Buffer Operation Timing (Compare Match)........................................................ 237

Figure 10.37 Buffer Operation Timing (Input Capture)............................................................ 237

Figure 10.38 TGI Interrupt Timing (Compare Match).............................................................. 238

Figure 10.39 TGI Interrupt Timing (Input Capture) ................................................................. 238

Figure 10.40 TCIV Interrupt Setting Timing............................................................................ 239

Figure 10.41 TCIU Interrupt Setting Timing............................................................................ 239

Figure 10.42 Timing for Status Flag Clearing by CPU............................................................. 240

Figure 10.43 Timing for Status Flag Clearing by DTC Activation........................................... 240

Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode............... 241

Figure 10.45 Conflict between TCNT Write and Clear Operations.......................................... 242

Figure 10.46 Conflict between TCNT Write and Increment Operations .................................. 243

Figure 10.47 Conflict between TGR Write and Compare Match ............................................. 244

Figure 10.48 Conflict between Buffer Register Write and Compare Match............................. 245

Figure 10.49 Conflict between TGR Read and Input Capture.................................................. 246

Figure 10.50 Conflict between TGR Write and Input Capture ................................................. 247

Figure 10.51 Conflict between Buffer Register Write and Input Capture................................. 248

Figure 10.52 Conflict between Overflow and Counter Clearing............................................... 249

Figure 10.53 Conflict between TCNT Write and Overflow...................................................... 250

Section 11 8-Bit Timers

Figure 11.1 Block Diagram of 8-Bit Timer Module............................................................... 252

Figure 11.2 Example of Pulse Output..................................................................................... 262

Rev. 3.00 Oct 04, 2005 page xxx of xl

Figure 11.3 Count Timing for Internal Clock Input................................................................ 263

Figure 11.4 Count Timing for External Clock Input............................................................... 263

Figure 11.5 Timing of CMF Setting........................................................................................ 264

Figure 11.6 Timing of Timer Output ...................................................................................... 264

Figure 11.7 Timing of Compare-Match Clear ........................................................................ 265

Figure 11.8 Timing of Clearing by External Reset Input........................................................ 265

Figure 11.9 Timing of OVF Setting........................................................................................ 266

Figure 11.10 Conflict between TCNT Write and Clear............................................................ 269

Figure 11.11 Conflict between TCNT Write and Increment..................................................... 270

Figure 11.12 Conflict between TCOR Write and Compare-Match........................................... 271

Section 12 Progr a mmab le Puls e Generator (PPG)

Figure 12.1 Block Diagram of PPG........................................................................................ 276

Figure 12.2 PPG Output Operation......................................................................................... 284

Figure 12.3 Timing of Transfer and Output of NDR Contents (Example) ............................. 285

Figure 12.4 Setup Procedure for Normal Pulse Output (Example)......................................... 286

Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) ................................. 287

Figure 12.6 Non-Overlapping Pulse Output ........................................................................... 288

Figure 12.7 Non-Overlapping Operation and NDR Write Timing ......................................... 289

Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example)......................... 290

Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)............ 291

Figure 12.10 Inverted Pulse Output (Example) ........................................................................ 293

Figure 12.11 Pulse Output Triggered by Input Capture (Example).......................................... 294

Section 13 Watchdog Timer

Figure 13.1 Block Diagram of WDT ...................................................................................... 296

Figure 13.2 Example of WDT0 Watchdog Timer Operation.................................................. 300

Figure 13.3 Writing to TCNT, TCSR, and RSTCSR (Example for WDT0)........................... 302

Figure 13.4 Conflict between TCNT Write and Increment..................................................... 302

Section 14 Serial Communication Interface (SCI)

Figure 14.1 Block Diagram of SCI ......................................................................................... 306

Figure 14.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits).............................................. 330

Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode..................................... 332

Figure 14.4 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode)......................................................................................... 333

Figure 14.5 Sample SCI Initialization Flowchart.................................................................... 334

Figure 14.6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit) ................................................ 335

Figure 14.7 Sample Serial Transmission Flowchart ............................................................... 336

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Figure 14.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity,

One Stop Bit)....................................................................................................... 337

Figure 14.9 Sample Serial Reception Data Flowchart (1)....................................................... 339

Figure 14.9 Sample Serial Reception Data Flowchart (2)....................................................... 340

Figure 14.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)......................................... 342

Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart ...................................... 343

Figure 14.12 Example of SCI Operation in Reception (Example with 8-Bit Data,

Multiprocessor Bit, One Stop Bit)....................................................................... 344

Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (1)...................................... 345

Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2)...................................... 346

Figure 14.14 Data Format in Synchronous Communication (For LSB-First)........................... 347

Figure 14.15 Sample SCI Initialization Flowchart.................................................................... 348

Figure 14.16 Sample SCI Transmission Operation in Clocked Synchronous Mode ................ 350

Figure 14.17 Sample Serial Transmission Flowchart ............................................................... 351

Figure 14.18 Example of SCI Operation in Reception ............................................................. 352

Figure 14.19 Sample Serial Reception Flowchart..................................................................... 353

Figure 14.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations..... 355

Figure 14.21 Schematic Diagram of Smart Card Interface Pin Connections............................ 356

Figure 14.22 Normal Smart Card Interface Data Format.......................................................... 357

Figure 14.23 Direct Convention (SDIR = SINV = O/

= 0 )..................................................... 358

Figure 14.24 Inverse Convention (SDIR = SINV = O/

= 1)................................................... 358

Figure 14.25 Receive Data Sampling Timing in Smart Card Mode

(Using Clock of 372 Times the Transfer Rate).................................................... 360

Figure 14.26 Retransfer Operation in SCI Transmit Mode....................................................... 362

Figure 14.27 TEND Flag Generation Timing in Transmission Operation................................ 362

Figure 14.28 Example of Transmission Processing Flow......................................................... 363

Figure 14.29 Retransfer Operation in SCI Receive Mode ........................................................ 364

Figure 14.30 Example of Reception Processing Flow .............................................................. 365

Figure 14.31 Timing for Fixing Clock Output Level................................................................ 366

Figure 14.32 Clock Halt and Restart Procedure........................................................................ 367

Section 15 Controller Area Network (HCAN)

Figure 15.1 HCAN Block Diagram......................................................................................... 372

Figure 15.2 Message Control Register Configuration............................................................. 396

Figure 15.3 Standard Format .................................................................................................. 396

Figure 15.4 Extended Format.................................................................................................. 396

Figure 15.5 Message Data Configuration ............................................................................... 398

Figure 15.6 Hardware Reset Flowchart................................................................................... 401

Figure 15.7 Software Reset Flowchart.................................................................................... 402

Figure 15.8 Detailed Description of One Bit.......................................................................... 403

Rev. 3.00 Oct 04, 2005 page xxxii o f xl

Figure 15.9 Transmission Flowchart....................................................................................... 406

Figure 15.10 Transmit Message Cancellation Flowchart.......................................................... 408

Figure 15.11 Reception Flowchart............................................................................................ 409

Figure 15.12 Unread Message Overwrite Flowchart ................................................................ 412

Figure 15.13 HCAN Sleep Mode Flowchart............................................................................. 413

Figure 15.14 HCAN Halt Mode Flowchart............................................................................... 415

Figure 15.15 DTC Transfer Flowchart...................................................................................... 417

Figure 15.16 High-Speed Interface Using PCA82C250........................................................... 418

Section 16 Synchronous Serial Communication Unit (SSU)

Figure 16.1 Block Diagram of SSU........................................................................................ 424

Figure 16.2 Relationship of Clock Phase, Polarity, and Data................................................. 435

Figure 16.3 Relationship between Data I/O Pins and the Shift Register................................. 436

Figure 16.4 Example of SSU Initialization............................................................................. 437

Figure 16.5 Example of Transmission Operation ................................................................... 439

Figure 16.6 Example of Data Transmission Flowchart........................................................... 440

Figure 16.7 Example of Reception Operation......................................................................... 442

Figure 16.8 Example of Data Reception Flowchart................................................................ 443

Figure 16.9 Example of Simultaneous Transmission/Reception Flowchart ........................... 445

Figure 16.10 Conflict Error Detection Timing (Before Transfer Start).................................... 446

Figure 16.11 Conflict Error Detection Timing (After Transfer End)........................................ 447

Section 17 A/D Converter

Figure 17.1 Block Diagram of A/D Converter........................................................................ 450

Figure 17.2 A/D Conversion Timing ...................................................................................... 457

Figure 17.3 External Trigger Input Timing............................................................................. 459

Figure 17.4 A/D Conversion Accuracy Definitions................................................................ 461

Figure 17.5 A/D Conversion Accuracy Definitions................................................................ 461

Figure 17.6 Example of Analog Input Circuit......................................................................... 462

Figure 17.7 Example of Analog Input Protection Circuit ....................................................... 464

Figure 17.8 Analog Input Pin Equivalent Circuit.................................................................... 464

Section 19 ROM

Figure 19.1 Block Diagram of Flash Memory....................................................................... 468

Figure 19.2 Flash Memory State Transitions.......................................................................... 469

Figure 19.3 Boot Mode........................................................................................................... 470

Fig ure 19.4 User Program Mode............................................................................................. 471

Figure 19.5 Flash Memory Block Configuration.................................................................... 472

Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode .................... 481

Figure 19.7 Flowchart for Flash Memory Emulation in RAM ............................................... 482

Figure 19.8 Example of RAM Overlap Operation.................................................................. 483

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Figure 19.9 Program/Program-Verify Flowchart.................................................................... 485

Figure 19.10 Erase/Erase-Verify Flowchart.............................................................................. 487

Section 20 Clock Pulse Generator

Figure 20.1 Block Diagram of Clock Pulse Generator ........................................................... 491

Figure 20.2 Connection of Crystal Resonator (Example)....................................................... 494

Figure 20.3 Crystal Resonator Equivalent Circuit .................................................................. 494

Figure 20.4 External Clock Input (Examples) ........................................................................ 495

Figure 20.5 External Clock Input Timing............................................................................... 496

Figure 20.6 Note on Board Design of Oscillator Circuit ........................................................ 498

Figure 20.7 External Circuitry Recommended for PLL Circuit.............................................. 499

Section 21 Power-Down Modes

Figure 21.1 Mode Transition Diagram.................................................................................... 502

Figure 21.2 Medium-Speed Mode Transition and Clearance Timing..................................... 508

Figure 21.3 Software Standby Mode Application Example.................................................... 511

Figure 21.4 Timing of Transition to Hardware Standby Mode............................................... 512

Figure 21.5 Timing of Recovery from Hardware Standby Mode ........................................... 513

Section 23 Electrical Characteristics

Figure 23.1 Output Load Circuit............................................................................................. 576

Figure 23.2 System Clock Timing .......................................................................................... 577

Figure 23.3 Oscillation Settling Timing.................................................................................. 578

Figure 23.4 Reset Input Timing .............................................................................................. 579

Figure 23.5 Interrupt Input Timing......................................................................................... 579

Figure 23.6 I/O Port Input/Output Timing.............................................................................. 583

Figure 23.7 Realtime Input Port Data Input Timing ............................................................... 583

Fig ure 23.8 TPU Input/Output Timing ................................................................................... 583

Figure 23.9 TPU Clock Input Timing..................................................................................... 584

Figure 23.10 SCK Clock Input Timing..................................................................................... 584

Figure 23.11 SCI Input/Output Timing (Clocked Synchronous Mode ).................................... 584

Figure 23.12 A/D Converter External Trigger Input Timing.................................................... 584

Figure 23.13 HCAN Input/Output Timing................................................................................ 585

Figure 23.14 PPG Output Timing............................................................................................. 585

Figure 23.15 8-Bit Timer Output Timing.................................................................................. 585

Figure 23.16 8-Bit Timer Clock Input Timing.......................................................................... 585

Figure 23.17 8-Bit Timer Reset Input Timing .......................................................................... 586

Figure 23.18 SSU Timing (Master, CPHS = 1) ........................................................................ 586

Figure 23.19 SSU Timing (Master, CPHS = 0) ........................................................................ 587

Figure 23.20 SSU Timing (Slave, CPHS = 1)........................................................................... 587

Figure 23.21 SSU Timing (Slave, CPHS = 0)........................................................................... 588

Rev. 3.00 Oct 04, 2005 page xxxiv of xl

Appendix

Figure C.1 FP-100M Package Dimensions............................................................................ 594

Rev. 3.00 Oct 04, 2005 page xxxv of xl

Tables

Section 2 CPU

Table 2.1 Instruction Classification ....................................................................................... 27

Table 2.2 Operation Notation................................................................................................. 28

Table 2.3 Data Transf er Instruc tions...................................................................................... 29

Table 2.4 Arithmetic Operations Instructions (1) .................................................................. 30

Table 2.4 Arithmetic Operations Instructions (2) .................................................................. 31

Table 2.5 Logic Operations Instructions................................................................................ 32

Table 2.6 Shift Instructions.................................................................................................... 33

Table 2.7 Bit Manipulation Instructions (1)........................................................................... 34

Table 2.7 Bit Manipulation Instructions (2)........................................................................... 35

Table 2.8 Branch Instructions................................................................................................ 36

Table 2.9 System Control Instructions................................................................................... 37

Table 2.10 Block Data Transfer Instructions ........................................................................... 38

Table 2.11 Addressing Modes.................................................................................................. 40

Table 2.12 Absolute Address Access Ranges.......................................................................... 41

Section 3 MCU Opera tin g Modes

Table 3.1 MCU Operating Mode Selection ........................................................................... 49

Section 4 Exception Handling

Table 4.1 Exception Types and Priority................................................................................. 55

Table 4.2 Exception Handling Vector Table.......................................................................... 56

Table 4.3 Statuses of CCR and EXR after Trace Exception Handling .................................. 60

Table 4.4 Statuses of CCR and EXR after Trap Instruction Exception Handling.................. 62

Section 5 Interrupt Controller

Table 5.1 Pin Configuration................................................................................................... 67

Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................ 75

Table 5.3 Interrupt Control Modes......................................................................................... 78

Table 5.4 Interrupt Response Times ...................................................................................... 83

Table 5.5 Number of States in Interrupt Handling Routine Execution Status........................ 84

Section 8 Data Transfer Controller (DTC)

Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................ 110

Table 8.2 Register Information in Normal Mode................................................................... 113

Table 8.3 Register Information in Repeat Mode.................................................................... 114

Table 8.4 Register Information in Block Transfer Mode....................................................... 115

Table 8.5 DTC Execution Status............................................................................................ 120

Rev. 3.00 Oct 04, 2005 page xxxvi of xl

Table 8.6 Number of States Required for Each Execution Status.......................................... 120

Section 9 I/O Ports

Table 9.1 Port Functions........................................................................................................ 128

Table 9.2 P17 Pin Function.................................................................................................... 133

Table 9.3 P16 Pin Function.................................................................................................... 133

Table 9.4 P15 Pin Function.................................................................................................... 134

Table 9.5 P14 Pin Function.................................................................................................... 134

Table 9.6 P13 Pin Function.................................................................................................... 134

Table 9.7 P12 Pin Function.................................................................................................... 135

Table 9.8 P11 Pin Function.................................................................................................... 135

Table 9.9 P10 Pin Function.................................................................................................... 135

Table 9.10 P37 Pin Function.................................................................................................... 138

Table 9.11 P36 Pin Function.................................................................................................... 138

Table 9.12 P35 Pin Function.................................................................................................... 138

Table 9.13 P34 Pin Function.................................................................................................... 139

Table 9.14 P33 Pin Function.................................................................................................... 139

Table 9.15 P32 Pin Function.................................................................................................... 139

Table 9.16 P31 Pin Function.................................................................................................... 139

Table 9.17 P30 Pin Function.................................................................................................... 139

Table 9.18 P77 Pin Function.................................................................................................... 142

Table 9.19 P76 Pin Function.................................................................................................... 142

Table 9.20 P75 Pin Function.................................................................................................... 142

Table 9.21 P74 Pin Function.................................................................................................... 143

Table 9.22 P73 Pin Function.................................................................................................... 143

Table 9.23 P72 Pin Function.................................................................................................... 143

Table 9.24 P71 Pin Function.................................................................................................... 143

Table 9.25 P70 Pin Function.................................................................................................... 143

Table 9.26 PA3 Pin Function................................................................................................... 148

Table 9.27 PA2 Pin Function................................................................................................... 148

Table 9.28 PA1 Pin Function................................................................................................... 148

Table 9.29 PA0 Pin Function................................................................................................... 148

Table 9.30 PB7 Pin Function................................................................................................... 152

Table 9.31 PB6 Pin Function................................................................................................... 152

Table 9.32 PB5 Pin Function................................................................................................... 152

Table 9.33 PB4 Pin Function................................................................................................... 153

Table 9.34 PB3 Pin Function................................................................................................... 153

Table 9.35 PB2 Pin Function................................................................................................... 153

Table 9.36 PB1 Pin Function................................................................................................... 153

Table 9.37 PB0 Pin Function................................................................................................... 154

Table 9.38 PC7 Pin Function................................................................................................... 157

Rev. 3.00 Oct 04, 2005 page xxxvii of xl

Table 9.39 PC6 Pin Function................................................................................................... 157

Table 9.40 PC5 Pin Function................................................................................................... 157

Table 9.41 PC4 Pin Function................................................................................................... 158

Table 9.42 PC3 Pin Function................................................................................................... 158

Table 9.43 PC2 Pin Function................................................................................................... 158

Table 9.44 PC1 Pin Function................................................................................................... 159

Table 9.45 PC0 Pin Function................................................................................................... 159

Table 9.46 PF7 Pin Function.................................................................................................... 165

Table 9.47 PF6 Pin Function.................................................................................................... 165

Table 9.48 PF5 Pin Function.................................................................................................... 165

Table 9.49 PF4 Pin Function.................................................................................................... 165

Table 9.50 PF3 Pin Function.................................................................................................... 165

Table 9.51 PF2 Pin Function.................................................................................................... 166

Table 9.52 PF1 Pin Function.................................................................................................... 166

Table 9.53 PF0 Pin Function.................................................................................................... 166

Section 10 16-Bit Timer Pulse Unit (TPU)

Table 10.1 TPU Functions ....................................................................................................... 168

Table 10.2 TPU Pins................................................................................................................ 171

Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3)................................................................... 175

Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5).......................................................... 175

Table 10.5 TPSC2 to TPSC0 (Channel 0)................................................................................ 176

Table 10.6 TPSC2 to TPSC0 (Channel 1)................................................................................ 176

Table 10.7 TPSC2 to TPSC0 (Channel 2)................................................................................ 177

Table 10.8 TPSC2 to TPSC0 (Channel 3)................................................................................ 177

Table 10.9 TPSC2 to TPSC0 (Channel 4)................................................................................ 178

Table 10.10 TPSC2 to TPSC0 (Channel 5)................................................................................ 178

Table 10.11 MD3 to MD0.......................................................................................................... 180

Table 10.12 TIORH_0 (Channel 0) ........................................................................................... 182

Table 10.13 TIORL_0 (Channel 0)............................................................................................ 183

Table 10.14 TIOR_1 (Channel 1) .............................................................................................. 184

Table 10.15 TIOR_2 (Channel 2) .............................................................................................. 185

Table 10.16 TIORH_3 (Channel 3) ........................................................................................... 186

Table 10.17 TIORL_3 (Channel 3)............................................................................................ 187

Table 10.18 TIOR_4 (Channel 4) .............................................................................................. 188

Table 10.19 TIOR_5 (Channel 5) .............................................................................................. 189

Table 10.20 TIORH_0 (Channel 0) ........................................................................................... 190

Table 10.21 TIORL_0 (Channel 0)............................................................................................ 191

Table 10.22 TIOR_1 (Channel 1) .............................................................................................. 192

Table 10.23 TIOR_2 (Channel 2) .............................................................................................. 193

Table 10.24 TIORH_3 (Channel 3) ........................................................................................... 194

Rev. 3.00 Oct 04, 2005 page xxxviii of xl

Table 10.25 TIORL_3 (Channel 3)............................................................................................ 195

Table 10.26 TIOR_4 (Channel 4) .............................................................................................. 196

Table 10.27 TIOR_5 (Channel 5) .............................................................................................. 197

Table 10.28 Register Combinations in Buffer Operation........................................................... 213

Table 10.29 Cascaded Combinations......................................................................................... 217

Table 10.30 PWM Output Registers and Output Pins................................................................ 220

Table 10.31 Phase Counting Mode Clock Input Pins ................................................................ 224

Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1....................................... 225

Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2....................................... 226

Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3....................................... 227

Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4....................................... 228

Table 10.36 TPU Interrupts ....................................................................................................... 232

Section 11 8-Bit Timers

Table 11.1 Pin Configuration................................................................................................... 253

Table 11.2 8-Bit Timer Interrupt Sources................................................................................ 268

Table 11.3 Timer Output Priorities.......................................................................................... 271

Table 11.4 Switching of Internal Clock and TCNT Operation................................................ 272

Section 12 Progr a mmab le Puls e Generator (PPG)

Table 12.1 Pin Configuration................................................................................................... 277

Section 13 Watchdog Timer

Table 13.1 WDT Interrupt Source ........................................................................................... 301

Section 14 Serial Communication Interface (SCI)

Table 14.1 Pin Configuration................................................................................................... 307

Table 14.2 The Relationships between The N Setting in BRR and Bit Rate B........................ 323

Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ............................ 324

Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ............................ 325

Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ............................ 326

Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ 326

Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 327

Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)...................... 328

Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 328

Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)

(When n = 0 and S = 372)...................................................................................... 329

Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)

(When S = 372)...................................................................................................... 329

Table 14.10 Serial Transfer Formats (Asynchronous Mode)..................................................... 331

Table 14.11 SSR Status Flags and Receive Data Handling....................................................... 338

Rev. 3.00 Oct 04, 2005 page xxxix of xl

Table 14.12 SCI Interrupt Sources............................................................................................. 368

Table 14.13 SCI Interrupt Sources............................................................................................. 369

Section 15 Controller Area Network (HCAN)

Table 15.1 HCAN Pins ............................................................................................................ 373

Table 15.2 Limits for the Settable Value ................................................................................. 403

Table 15.3 Setting Range for TSEG1 and TSEG2 in BCR...................................................... 404

Table 15.4 HCAN Interrupt Sources........................................................................................ 416

Table 15.5 Interval Li mitation between TX PR and TXPR or betw een TXPR and TXCR...... 421

Section 16 Synchronous Serial Communication Unit (SSU)

Table 16.1 Pin Configuration................................................................................................... 425

Table 16.2 Interrupt Souses ..................................................................................................... 448

Section 17 A/D Converter

Table 17.1 Pin Configuration................................................................................................... 451

Table 17.2 Analog Input Channels and Corresponding ADDR Registers ............................... 452

Table 17.3 A/D Conversion Time (Single Mode).................................................................... 458

Table 17.4 A/D Conversion Time (Scan Mode) ...................................................................... 458

Table 17.5 A/D Converter Interrupt Source............................................................................. 459

Table 17.6 Analog Pin Specifications...................................................................................... 464

Section 19 ROM

Table 19.1 Differences between Boot Mode and User Program Mode.................................... 469

Table 19.2 Pin Configuration................................................................................................... 473

Table 19.3 Setting On-Board Programming Modes................................................................. 477

Table 19.4 Boot Mode Operation............................................................................................. 479

Table 19.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is

Possible.................................................................................................................. 479

Table 19.6 Flash Memory Operating States............................................................................. 489

Table 19.7 Registers Present in F-ZTAT Version but Absent in Masked ROM Version........ 490

Section 20 Clock Pulse Generator

Table 20.1 Damping Resistance Value.................................................................................... 494

Table 20.2 Crystal Resonator Characteristics .......................................................................... 495

Table 20.3 External Clock Input Conditions............................................................................ 496

Section 21 Power-Down Modes

Table 21.1 Low Power Consumption Mode Transition Conditions......................................... 502

Table 21.2 LSI Internal States in Each Mode .......................................................................... 503

Table 21.3 Oscillation Stabilization Time Settings.................................................................. 510

Rev. 3.00 Oct 04, 2005 page xl of xl

Table 21.4 φ Pin State in Each Processing State...................................................................... 514

Section 23 Electrical Characteristics

Table 23.1 Absolute Maximum Ratings .................................................................................. 573

Table 23.2 DC Characteristics ................................................................................................. 574

Table 23.3 Permissible Output Currents.................................................................................. 576

Table 23.4 Clock Timing ......................................................................................................... 577

Table 23.5 Control Signal Timing............................................................................................ 578

Table 23.6 Timing of On-Chip Peripheral Modules ................................................................ 580

Table 23.7 Timing of SSU ....................................................................................................... 582

Table 23.8 A/D Conversion Characteristics............................................................................. 589

Table 23.9 Flash Memory Characteristics................................................................................ 590

Section 1 Overview

Rev. 3.00 Oct 04, 2005 page 1 of 598

REJ09B0155-0300

Section 1 O verview

1.1 Overview

• High-speed H8S/2600 central processing unit with an internal 16-bit architecture

 Upward-compatible with H8/300 and H8/300H CPUs on an object level

 Sixteen 16-bit general registers

 69 basic instructions

• Various peripheral functions

 PC break controller

 Data trans fer con t rol l er

 16-bit timer-pulse unit (TPU)

 8-bit timer (TMR)

 Programmable pulse generator (PPG)

 Watchdog timer

 Asynchronous or clocked synchronous serial communication interface (SCI)

 Controller area network (HCAN)

 Synchronous serial communication unit (SSU)

 10-bit A/D converter

 Clock pulse generator

• On-chip memory

ROM Model ROM RAM Remarks

F-ZTAT Version HD64F2628 128 kbytes 8 kbytes

Masked ROM Version HD6432628 128 kbytes 8 kbytes

HD6432627 128 kbytes 6 kbytes

• General I/O ports

 I/O pins: 59

 Input-only pins: 17

• Supports various power-down states

• Compact package

Package Package Code Body Size Pin Pitch

QFP-100 FP-100M 14.0 × 14.0 mm 0.5 mm

Section 1 Overview

Rev. 3.00 Oct 04, 2005 page 2 of 598

REJ09B0155-0300

1.2 Int ern a l Bl ock Diag ram

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

VCL

VCC

VSS

PA3/SCK2

PA2/RxD2

PA1/TxD2

PA0

PB7/TIOCB5

PB6/TIOCA5

PB5/TIOCB4

PB4/TIOCA4

PB3/TIOCD3

PB2/TIOCC3

PB1/TIOCB3

PB0/TIOCA3

PC7/SCS1

PC6/SSCK1

PC5/SSI1

PC4/SSO1

PC3/SCS0

PC2/SSCK0

PC1/SSI0

PC0/SSO0

P97/AN15

P96/AN14

P95/AN13

P94/AN12

P93/AN11

P92/AN10

P91/AN9

P90/AN8

P47/AN7

P46/AN6

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

HRxD

HTxD

Vref

AVCC

AVSS

P17/PO15/TIOCB2/TCLKD

P16/PO14/TIOCA2/IRQ1

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1/IRQ0

P13/PO11/TIOCD0/TCLKB

P12/PO10/TIOCC0/TCLKA

P11/PO9/TIOCB0

P10/PO8/TIOCA0

PF7/φ

PF6

PF5

PF4

PF3/ADTRG/IRQ3

PF2

PF1/BUzz

PF0/IRQ2

RAM

Interrupt controller

PC break controller

(2 channels)

ROM

(Masked ROM,

flash memory)

TPU

PPG

Port 1 Port 4

Note: * The FWE pin is provided only in the flash memory version. The NC pin is provided only in the masked ROM version.

MD2

MD1

MD0

EXTAL

XTAL

PLLVCL

PLLCAP

PLLVSS

STBY

RES

FWE/NC*

NMI

H8S/2600 CPU

DTC

WDT × 1 channel

TMR × 4 channels

SCI × 2 channels

SSU × 2 channels

HCAN × 1 channel

A/D converter

Port D

P37

P36

P35/IRQ5

P34

P33

P32/SCK0/IRQ

P31/RxD0

P30/TxD0

P77

P76

P75/TMO3

P74/TMO2

P73/TMO1

P72/TMO0

P71/TMCI23/TMRI23

P70/TMCIO1/TMRIO1

Port 9 Port 3 Port C Port B

Bus controller

Internal data bus

Internal address bus

Peripheral data bus

Peripheral address bus

Port FPort 7

Port A

Clock pulse

generator

Figure 1.1 Internal Block Diagram

Section 1 Overview

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REJ09B0155-0300

1.3 Pin Arrangement

P97/AN15

P96/AN14

P95/AN13

P94/AN12

P93/AN11

P92/AN10

P91/AN9

P90/AN8

AVSS

Vref

AVCC

P47/AN7

P46/AN6

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

P10/PO8/TIOCA0

P11/PO9/TIOCB0

P12/PO10/TIOCC0/TCLKA

P13/PO11/TIOCD0/TCLKB

P14/PO12/TIOCA1/IRQ0

P15/PO13/TIOCB1/TCLKC

100

PF0/IRQ2

PF1

PF2

PF3/ADTRG/IRQ

PF4

PF5

PF6

PF7/φ

PLLCAP

FWE/NC*

PLLVSS

VSS

EXTAL

XTAL

VCC

NMI

STBY

VCL

RES

VSS

MD2

MD1

MD0

P30/TxD0

P31/RxD0

75747372717069686766656463626160595857565554535251

P32/SCK0/IRQ4

P33

P34

P35/IRQ5

P36

P37

PA3/SCK2

PA2/RxD2

PA0

PB7/TIOCB5

PB5/TIOCB4

PB4/TIOCA4

PB3/TIOCD3

PB2/TIOCC3

VSS

PB1/TIOCB3

VCC

PB0/TIOCA3

PC7/SCS1

PC6/SSCK1

PC5/SSI1

PC4/SSO1

PC3/SCS0

PA1/TxD2

PB6/TIOCA5

12345678910111213141516171819202122232425

P16/PO14/TIOCA2/IRQ1

VCC

P17/PO15/TIOCB2/TCLKD

VSS

HRxD

HTxD

P70/TMCI01/TMRI01

P71/TMCI23/TMRI23

P72/TMO0

P73/TMO1

P74/TMO2

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PC1/SSI0

PC2/SSCK0

P75/TMO3

P76

P77

PC0/SSO0

FP-100M

(Top view)

Note: * The FWE pin is provided only in the flash memory version. The NC pin is provided only in the masked ROM

version.

Figure 1.2 Pin Arrangement

Section 1 Overview

Rev. 3.00 Oct 04, 2005 page 4 of 598

REJ09B0155-0300

1.4 Pin Functions

Type Symbol Pin NO. I/O Function

Power

Supply VCC 2

Input Power supply pins. Connect all these pins to the

system power supply.

VSS 4

Input Ground pins. Connect all these pins to the system

power supply (0 V).

VCL 58 Output Ex ternal capacitance pin for interna l power-down

power supply. Connect this pin to VSS via a 0.1-

µF capacitor (placed close to the pins).

Clock PLLVSS 65 Input On-chip PLL oscillator ground pin.

PLLCAP 67 Output External capacitance pin for an on-chip PLL

oscillator.

XTAL 62 Input For connection to a crystal resonator. For

examples of crystal resonator connection and

external cl ock input, see section 20, Clock Pulse

Generator.

EXTAL 63 Input For connection to a crystal resonator (An external

clock can be supplied from the EXTAL pin). For

examples of crystal resonator connection and

external cl ock input, see section 20, Clock Pulse

Generator.

φ68 Output Supplies the system clock to external devices.

Operating

mode

control

MD2

MD1

MD0

Input Set the operating mode. Inputs at these pins

should not be changed during operation.

System

control

RES

57 Input Reset input pin. When this pin is low, the chip is

reset.

STBY

59 Input When this pin is low, a transition is made to

hardware standby mode.

FWE 66 Input Pin for use by flash memory. This pin is only used

in the flash memory version.

Section 1 Overview

Rev. 3.00 Oct 04, 2005 page 5 of 598

REJ09B0155-0300

Type Symbol Pin NO. I/O Function

Interrupts NMI 60 Input Nonmaskable interrupt pin. If this pin is not used,

it should be fi xed high.

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ0

Input These pins request a maskable interrupt.

16-bit timer-

pulse unit TCLKA

TCLKB

TCLKC

TCLKD

100

Input These pins input an external clock.

TIOCA0

TIOCB0

TIOCC0

TIOCD0

Input/

Output TGRA_0 to TGRD_0 input capture input/outpu t

compare output/PWM output pins.

TIOCA1

TIOCB1 99

100 Input/

Output TGRA_1 to TGRB_1 input capture input/output

compare output/PWM output pins.

TIOCA2

TIOCB2 1

3Input/

Output TGRA_2 to TGRB_2 input capture input/output

compare output/PWM output pins.

TIOCA3

TIOCB3

TIOCC3

TIOCD3

Input/

Output TGRA_3 to TGRD_3 input capture input/outpu t

compare output/PWM output pins.

TIOCA4

TIOCB4 37

38 Input/

Output TGRA_4 to TGRB_4 input capture input/output

compare output/PWM output pins.

TIOCA5

TIOCB5 39

40 Input/

Output TGRA_5 to TGRB_5 input capture input/output

compare output/PWM output pins.

Program-

mable pulse

generator

(PPG)

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

100

Output Pulse output pins.

Section 1 Overview

Rev. 3.00 Oct 04, 2005 page 6 of 598

REJ09B0155-0300

Type Symbol Pin NO. I/O Function

8-bit timer

(TMR) TMO3

TMO2

TMO1

TMO0

Output Compare-match output pins.

TMCI23

TMCI01 8

7Input Input pins of external clocks input to the counter.

8-bit timer

(TMR) TMRI23

TMRI01 8

7Input Counter reset input pins.

TxD2

TxD0 42

52 Output Data output pins.

RxD2

RxD0 43

51 Input Data input pins.

Serial

communi-

cation

Interface

(SCI)/

smart card

interface SCK2

SCK0 44

50 Input/

Output Clock input/out put pins.

HCAN HTxD 6 Output CAN bus transmission pin.

HRxD 5 Input CAN bus reception pi n.

SSO1

SSO0 27

23 Input/

Output Data input/output pins.

SSI1

SSI0 28

24 Input/

Output Data input/output pins.

SSCK1

SSCK0 29

25 Input/

Output Clock input/out put pins.

Synchro-

nous serial

communi-

cation unit

(SSU)

SCS1

SCS0

26 Input/

Output Chip select input/output pins.

Section 1 Overview

Rev. 3.00 Oct 04, 2005 page 7 of 598

REJ09B0155-0300

Type Symbol Pin NO. I/O Function

A/D

converter AN15

AN14

AN13

AN12

AN11

AN10

AN9

AN8

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

Input Analog input pins.

ADTRG

72 Input Pin for input of an external trigger to start A/D

conversion.

AVCC 86 Input Power supply pin for the A/D converter. When the

A/D converter is not used, connect this pin to the

system power supply (+5 V).

AVSS 84 Input The ground pin for the A/D converter. Connect

this pin to the system power supply (0 V).

Vref 85 Input The reference voltage input pin for the A/D

converter. When the A/D converter is not used,

connect this pin to the system power supply

(+5 V).

I/O ports P17

P16

P15

P14

P13

P12

P11

P10

100

Input/

Output Eight input/output pins.

Section 1 Overview

Rev. 3.00 Oct 04, 2005 page 8 of 598

REJ09B0155-0300

Type Symbol Pin NO. I/O Function

I/O ports P37

P36

P35

P34

P33

P32

P31

P30

Input/

Output Eight input/output pins.

P47

P46

P45

P44

P43

P42

P41

P40

Input Eight input pins.

P77

P76

P75

P74

P73

P72

P71

P70

Input/

Output Eight input/output pins.

P97

P96

P95

P94

P93

P92

P91

P90

Input Eight input pins.

PA3

PA2

PA1

PA0

Input/

Output Four input/out put pins.

Section 1 Overview

Rev. 3.00 Oct 04, 2005 page 9 of 598

REJ09B0155-0300

Type Symbol Pin NO. I/O Function

I/O ports PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

Input/

Output Eight input/output pins.

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

Input/

Output Eight input/output pins.

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Input/

Output Eight input/output pins.

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

Input/

Output Eight input/output pins.

Section 1 Overview

Rev. 3.00 Oct 04, 2005 page 10 of 598

REJ09B0155-0300

Section 2 CPU

Rev. 3.00 Oct 04, 2005 page 11 of 598

REJ09B0155-0300

Section 2 C PU

The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that

is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit

general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending

on the product. For details on each product, refer to section 3, MCU Operating Modes.

2.1 Features

• Upward-compatible with H8/300 and H8/300H CPUs

 Can execute H8/300 and H8/300H CPUs object programs

• G ener al- reg i ster arc hi te ctu re

 Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

• Sixty-nine basic instructions

 8/16/32-bi t arithm etic and log ic instruc ti ons

 Multiply and divide instructions

 Powerful bit-manipulation instructions

 Multiply-and-accumulate instruction

• Eight addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]

 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

 A bsolute addre ss [@aa: 8, @aa: 16, @aa:24 , or @aa:32 ]

 Immediate [#xx:8, #xx:16, or #xx:32]

 Program-counter relative [@(d:8,PC) or @(d:16,PC)]

 Memory indirect [@@aa:8]

• 16-Mbyte address space

 Program: 16 Mbytes

 Data: 16 Mbytes

• High-speed operation

 All frequently-used instructions execute in one or two states

 8/16/32-bit register-register add/subtract: 1 state

 8 × 8-bit register-register multiply: 3 states

 16 ÷ 8-bit register-register divide: 12 states

CPUS260A_000020020300

Section 2 CPU

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REJ09B0155-0300

 16 × 16-bit register-register multiply: 4 states

 32 ÷ 16-bit register-register divide: 20 states

• Two CPU operating modes

 Normal mode*

 Advanced mode

• Power-down state

 Transition to power-down state by the SLEEP instruction

 CPU clock speed selection

Note: * Normal mode is not available in this LSI.

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.

• Register configuration

The MAC register is supported by the H8S/2600 CPU only.

• Basic instructions

The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600

CPU only.

• The number of execution states of the MULXU and MULXS instructions;

Execution States

Instruction Mnemonic H8S/2600 H8S/2000

MULXU MULXU.B Rs, Rd 3 12

MULXU.W Rs, ERd 4 20

MULXS MULXS.B Rs, Rd 4 13

MULXS.W Rs, ERd 5 21

In addition, there are differences in address space, CCR and EXR register functions, and power-

down modes, etc., depending on the model.

Section 2 CPU

Rev. 3.00 Oct 04, 2005 page 13 of 598

REJ09B0155-0300

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements:

• More general registers and control registers

 Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been

added.

• Expanded address space

 Normal mode suppo rts the same 6 4-k byte address space as the H8/30 0 C PU.

 Advanced mode supports a maximum 16-Mbyte address space.

• Enhanced addressing

 The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions

 Addressing modes of bit-manipulation instructions have been enhanced.

 Signed multiply and divide instructions have been added.

 A multiply-and-accumulate instruction has been added.

 Two-bit shift instructions have been added.

 Instructions for saving and restoring multiple registers have been added.

 A test and set instruction has been added.

• Higher speed

 Basic instructions execute twice as fast.

2.1.3 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements:

• More control registers

 One 8-bit and two 32-bit control registers have been added.

• Enhanced instructions

 Addressing modes of bit-manipulation instructions have been enhanced.

 A multiply-and-accumulate instruction has been added.

 Two-bit shift instructions have been added.

 Instructions for saving and restoring multiple registers have been added.

 A test and set instruction has been added.

• Higher speed

 Basic instructions execute twice as fast.

Section 2 CPU

Rev. 3.00 Oct 04, 2005 page 14 of 598

REJ09B0155-0300

2.2 CPU Operating Modes

The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a

maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address

space. The mode is selected by the mode pins.

2.2.1 Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU.

• Address Space

Linear access to a 64-kbyte maximum address space is provided.

• Extended Registers (En)

The extended reg iste rs (E7 to E0) can be used as 16-bi t registe rs, or as the upper 16-bit

segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even

when the corresponding general register (Rn) is used as an address register. If the general

post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding

extended register (En) will be affected.

• Instruction Set

All instructions and addressing modes can be used. Only the lower 16 bits of effective

addresses (EA) are valid.

• Exception Vector Table and Memory Indirect Branch Addresses

In normal mode the top area starting at H'0000 is allocated to the exception vector table. One

branch address is stored per 16 bits. The exception vector table structure in normal mode is

shown in figure 2.1. For details of the exception vector table, see section 4, Exception

Handling.

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions

uses an 8-bit absolute address included in the instruction code to specify a memory operand

that contains a branch address. In normal mode the operand is a 16-bit word operand,

providing a 16-bit branch address. Branch addresses can be stored in the area from H'0000 to

H'00FF. Note that the first part of this range is also used for the exception vector table.

• Stack Structure

When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,

condition-code register (CCR), and extended control register (EXR) are pushed onto the stack

in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack

in interrupt control mode 0. For details, see section 4, Exception Handling.

Note: Normal mode is not available in this LSI.

Section 2 CPU

Rev. 3.00 Oct 04, 2005 page 15 of 598

REJ09B0155-0300

H'0000

H'0001

H'0002

H'0003

H'0004

H'0005

H'0006

H'0007

H'0008

H'0009

H'000A

H'000B

Exception vector 1

Exception vector 2

Exception vector 3

Exception vector 5

Exception vector 6

Exception

vector table

Exception vector 4

Figure 2.1 Exception Vector Table (Normal Mode)

(16 bits) EXR*1

Reserved*1*3

CCR

CCR*3

(16 bits)

SP SP

(SP*2

1. When EXR is not used it is not stored on the stack.

2. SP when EXR is not used.

3. lgnored when returning.

Notes:

(b) Exception Handling(a) Subroutine Branch

)

Figure 2.2 Stack Structure in Normal Mode

2.2.2 Advanced Mode

• Address Space

Linear access to a 16-Mbyte maximum address space is provided.

• Extended Registers (En)

The extended reg iste rs (E7 to E0) can be used as 16-bi t registe rs, or as the upper 16-bit

segments of 32-bit registers or address registers.

Section 2 CPU

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REJ09B0155-0300

• Instruction Set

All instructions and addressing modes can be used.

• Exception Vector Table and Memory Indirect Branch Addresses

In advanced mod e, the top area starting at H'00000000 is all ocated to the exc eption vec tor

table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is

stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4,

Exception Handling.

H'00000000

H'00000003

H'00000004

H'0000000B

H'0000000C

H'00000010

H'00000008

H'00000007

Reserved

Exception vector 1

Exception vector 2

Exception vector 3

Exception vector 4

Exception vector table

Exception vector 5

Figure 2.3 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions

uses an 8-bit absolute address included in the instruction code to specify a memory operand

that contains a branch address. In advanced mode the operand is a 32-bit longword operand,

providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is

regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.

Note that the first part of this range is also used for the excep ti on vector table.

Section 2 CPU

Rev. 3.00 Oct 04, 2005 page 17 of 598

REJ09B0155-0300

• Stack Structure

In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine

call, and the PC, condition-code register (CCR), and extended control register (EXR) are

pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When

EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4,

Exception Handling.

(24 bits)

EXR*

Reserved*

CCR

(24 bits)

SP SP

(SP *

Reserved

(a) Subroutine Branch (b) Exception Handling

Notes:1. When EXR is not used it is not stored on the stack.

2. SP when EXR is not used.

3. Ignored when returning.

)

Figure 2.4 Stack Structure in Advanced Mode

Section 2 CPU

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REJ09B0155-0300

2.3 Address Space

Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear

access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte

(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces

differ depending on the product. For details on each product, refer to section 3, MCU Operating

Modes.

H'0000

H'FFFF

H'00000000

H'FFFFFFFF

H'00FFFFFF

64 kbytes

16 Mbytes

Cannot be

used for

this LSI

Program area

Data area

(b) Advanced Mode(a) Normal Mode

Figure 2.5 Memory Map

Section 2 CPU

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REJ09B0155-0300

2.4 Registers

The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers;

general registers and control registers. The control registers are a 24-bit program counter (PC), an

8-bit extended control register (EXR), an 8-bit condition cod e regi ster (CCR), and a 64-bit

mul tip ly - accumu late registe r (MAC).

TI2I1I0

EXR

76543210

MACH

MACL

MAC

63 3241

31 0

15 0 7 0 7 0

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

SP:

PC:

EXR:

I2 to I0:

CCR:

UI:

Stack pointer

Program counter

Extended control register

Trace bit

Interrupt mask bits

Condition-code register

Interrupt mask bit

User bit or interrupt mask bit

Half-carry flag

User bit

Negative flag

Zero flag

Overflow flag

Carry flag

Multiply-accumulate register

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

IUIHUNZVC

CCR

76543210

MAC:

General Registers (Rn) and Extended Registers (En)

Control Registers (CR)

Legend:

(Sign extension)

----

Figure 2.6 CPU Registers

Section 2 CPU

Rev. 3.00 Oct 04, 2005 page 20 of 598

REJ09B0155-0300

2.4.1 General Registers

The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally

identical and can be used as both address registers and data registers. When a general register is

used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates

the usage of the general registers. When the general registers are used as 32-bit registers or address

registers, they are designated by the letters ER (ER7 to ER0).

The ER registers divide into 16-bit general registers designated by the letters E (E7 to E0) and R

(R7 to R0). These registers are functionally equivalent, providing a maximum of sixteen 16-bit

registers. The E registers (E7 to E0) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R7H to R0H) and

RL (R7L to R0L). These registers are functionally equivalent, providing a maximum of sixteen 8-

bit registers.

The usage of each register can be selected independently.

General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the

stack.

• Address registers

• 32-bit registers • 16-bit registers • 8-bit registers

ER registers

(ER7 to ER0)

E registers (extended registers)

(E7 to E0)

R registers

(R7 to R0)

RH registers

(R7H to R0H)

RL registers

(R7L to R0L)

Figure 2.7 Usage of General Registers

Section 2 CPU

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REJ09B0155-0300

SP (ER7)

Free area

Stack area

Figure 2.8 Stack

2.4.2 Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length

of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored (When an

instruction is fetched, the least significant PC bit is regarded as 0).

2.4.3 Extended Control Register (EXR)

EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.

When these instructions, except for the STC instruction, are executed, all interrupts including NMI

will be masked for three states after execution is completed.

Bit Bit Name Initial Value R/W Description

7 T 0 R/W Trace Bit

When this bit is set to 1, a trace exception is

generated each time an instruction is executed.

When this bit is cleared to 0, instructi ons are

executed in sequence.

6 to 3 All 1 Reserved

These bits are always read as 1.

R/W

These bits designate the interrupt mask level (7

to 0). For details, refer to section 5, Interrupt

Controller.

Section 2 CPU

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2.4.4 Condition-Code Register (CCR)

This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and

half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC

instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch

(Bcc) instructions.

Bit Bit Name Initial Value R/W Description

7 I 1 R/W Interrupt Mask Bit

Masks interrupts other than NMI when set to 1.

NMI is accepted regardless of the I bit setting.

The I bit is set to 1 at the start of an exception-

handling sequence. For details, refer to section 5,

Interrupt Controller.

6 UI undefined R/W User Bit or Interrupt Mask Bit

Can be read or written by software using the

LDC, STC, ANDC, ORC, and XORC instructions.

This bit cannot be used as an interrupt mask bit

in this LSI.

5 H undefined R/W Half-Carry Flag

When the ADD. B, ADDX.B, SUB.B, SUBX.B,

CMP.B, or NEG.B instructi on is executed, this

flag is set to 1 if there is a carry or borrow at bit 3,

and cleared to 0 otherwise. When the ADD.W,

SUB.W, CMP.W, or NEG. W instruction is

executed, the H flag is set to 1 if there is a carry

or borrow at bit 11, and cleared to 0 otherwise.

When the ADD.L, SUB.L, CMP.L, or NEG.L

instruction is executed, the H flag is set to 1 if

there is a carry or borrow at bit 27, and cleared to

0 otherwise.

4 U undefined R/W User Bit

Can be read or written by software using the

LDC, STC, ANDC, ORC, and XORC instructions.

3 N undefined R/W Negative Flag

Stores the value of the most significant bit of data

as a sign bit.

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Bit Bit Name Initial Value R/W Description

2 Z undefined R/ W Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to

indicate non-zero data.

1 V undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow occurs, and

cleared to 0 at other times.

0 C undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0

otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract in structions, to indicate a borrow

• Shift and rotate instruct ions, to indicate a

carry

The carry flag is also used as a bit accumulator

by bit manipulation instructions.

2.4.5 Multiply-Accumulate Register (MAC)

This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32-

bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are

a sign extension.

2.4.6 Initial Values of CPU Registers

Reset exception handling loads the CPU’s program count er ( PC) from the vector tabl e, clear s the

trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits

and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.

The stack pointer should therefore be initialized by an MOV.L instruction executed immediately

after a rese t.

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2.5 Data Fo rmat s

The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit

(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,

…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two

digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figure 2.9 shows the data formats in general registers.

MSB LSB

7043

Don't care

7043

Don't care

65432710

Don't care 65432710

Don't care

RnH

RnL

RnH

RnL

RnH

RnL

Data Type Register Number Data Format

Byte data

4-bit BCD data

1-bit data

Upper Lower

Figure 2.9 General Register Data Formats (1)

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15 0

MSB LSB

15 0

MSB LSB

31 16

MSB

15 0

LSB

En Rn

ERn:

En:

Rn:

RnH:

RnL:

MSB:

LSB:

General register ER

General register E

General register R

General register RH

General register RL

Most significant bit

Least significant bit

Data Type Data FormatRegister Number

Word data

Longword data

Legend:

ERn

Figure 2.9 General Register Data Formats (2)

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2.5.2 Memory Data Formats

Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and

longword data in memory, however word or longword data must begin at an even address. If an

attempt is made to access word or longword data at an odd address, an address error does not

occur, however the least significant bit of the address is regarded as 0, so access begins the

preceding address. This also applies to instruction fetches.

When ER7 is used as an address register to access the stack, the operand size should be word or

longword.

76 543210

MSB LSB

MSB

LSB

Data Type Address

1-bit data

Byte data

Word data

Address L

Address 2M

Address 2M+1

Longword data Address 2N

Address 2N+1

Address 2N+2

Address 2N+3

Data Format

Figure 2.10 Memory Data Formats

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2.6 Instruc tio n Set

The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1.

Table 2.1 Instruc tion Class ifica ti on

Function Instructions Size Types

Data transfer MOV B/W/L 5

POP*1, PUSH*1W/L

LDM, STM L

MOVFPE*3, MOVTPE*3B

Arithmetic ADD, SUB, CMP, NEG B/W /L 23

operations ADDX, SUBX, DAA, DAS B

INC, DEC B/W/L

ADDS, SUBS L

MULXU, DIVXU, MULXS, DIVXS B/W

EXTU, EXTS W/L

TAS*4B

MAC, LDMAC, STMAC, CLRMAC 

Logic operations AND, OR, XOR, NOT B/W/L 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,

ROTXR B/W/L 8

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD , BST, BIST,

BAND, BIAND, BOR, BIOR, BXOR, BIXOR B14

Branch Bcc*2, JMP, BSR, JSR, RTS 5

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, O RC, XORC,

NOP 9

Block data transfer EEPMOV 1

Total: 69

Notes: B: Byte

W: Word

L: Longword

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+,Rn and MOV.W Rn,@-SP.

POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+,ERn and

MOV.L ERn,@-SP.

2. Bcc is the general name for conditional branch instructions.

3. Cannot be used in thi s LSI.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

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2.6.1 Table of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in

tables 2.3 to 2.10 is defined below.

Table 2.2 Operation Notatio n

Symbol Description

Rd General registe r (destinat ion)*

Rs Genera l register (source)*

Rn General registe r*

ERn General register (32-bit register)

MAC Multiply-accumulate register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

EXR Extended control register

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflo w) flag in CCR

C C (carry) flag in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

–Subtraction

×Multiplication

÷Division

∧Logical AND

∨Logical OR

⊕Logical XOR

→Move

∼NOT (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: *General registers include 8-bit registers (R7H to R0H, R7L to R0L), 16-bit registers (R7

to R0, E7 to E0), and 32-bit regi sters (ER7 to ER0).

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Table 2.3 Data Transf er Ins truct ions

Instruction Size*Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register

and memory, or moves immediate data to a general register.

MOVFPE B Cannot be used in this LSI.

MOVTPE B Cannot be used in this LSI.

POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to MOV.W

@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a general register onto the stack. PUSH.W Rn is identical to

MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.

LDM L @SP+ → Rn (register list)

Pops two or more general registers from the stack.

STM L Rn (register list) → @–SP

Pushes two or more general registers onto the stack.

Note: * Refers to the operand size.

B: Byte

W: Word

L: Longword

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Tab le 2. 4 A rithme t ic Op e rat io n s In str u ct ions (1)

Instruction Size*Function

ADD

SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on

immediate data and data in a general register (immediate byte data

cannot be subtracted from byte data in a general register. Use the SUBX

or ADD instruction).

ADDX

SUBX BRd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry on byte data in two general

registers, or on immediate data and data in a general register.

INC

DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2 (Byte operands

can be incremented or decremented by 1 only).

ADDS

SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

DAA

DAS BRd decimal adjust → Rd

Decimal-adjusts an addition or subtraction result in a general register by

referring to the CCR to produce 4-bit BCD data.

MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general registers: either

8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

MULXS B/W Rd × Rs → Rd

Performs signed mul tiplication on data in two general registers: either 8

bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data i n two general registers: either 16

bits ÷ 8 bits → 8-bit quoti ent and 8-bit remainder or 32 bits ÷ 16 bits →

16-bit quotient and 16-bit remainder.

Note: * Refers to the operand size.

B: Byte

W: Word

L: Longword

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Tab le 2. 4 A rithme t ic Op e rat io n s In str u ct ions (2)

Instruction Size*1Function

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16 bits ÷

8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit

quotient and 16-bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general regi ster with data in another general register

or with immediat e data, and sets CCR bits according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two’s complement (arithmetic complement) of data in a

general registe r.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16

bits of a 32-bit register to longword size, by padding with zeros on the

left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16

bits of a 32-bit register to longword size, by extending the sign bit.

TAS*2B@ERd – 0, 1 → (<bit 7> of @ERd)

Tests memory contents, and sets the most significant bit (bit 7) to 1.

MAC (EAs) × (EAd) + MAC → MAC

Performs signed multiplication on memory contents and adds the result

to the multiply-accumul ate register. The following operations can be

performed:

16 bits × 16 bits + 32 bits → 32 bits, saturating

16 bits × 16 bits + 42 bits → 42 bits, non-saturating

CLRMAC 0 → MAC

Clears the multiply-accumulate register to zero.

LDMAC

STMAC LRs → MAC, MAC → Rd

Transfers data between a general register and a multiply-accumulate

Note: 1.Refers to the operand size.

B: Byte

W: Word

L: Longword

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

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Table 2.5 Logic Opera ti ons Ins tructi ons

Instruction Size*Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another

general registe r or imm ediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another

general registe r or imm ediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and

another general register or immediate data.

NOT B/W/L ∼(Rd) → (Rd)

Takes the one’s complement (logical comple ment) of general register

contents.

Note: * Refers to the operand size.

B: Byte

W: Word

L: Longword

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Table 2.6 Shift Instruc tions

Instruction Size*Function

SHAL

SHAR B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents.

1-bit or 2-bit shifts are possible.

SHLL

SHLR B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.

1-bit or 2-bit shifts are possible.

ROTL

ROTR B/W/L Rd (rotate) → Rd

Rotates general register contents.

1-bit or 2-bit rotations are possible.

ROTXL

ROTXR B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry flag.

1-bit or 2-bit rotations are possible.

Note: * Refers to the operand size.

B: Byte

W: Word

L: Longword

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Table 2.7 Bit Manipulat ion Instructions (1)

Instruction Size*Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit

number is specified by 3-bit immediate data or the lower three bits of a

general registe r.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0. The

bit number is specified by 3-bit immediate data or the lower three bits of a

general registe r.

BNOT B ∼(<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit

number is specified by 3-bit immediate data or the lower three bits of a

general registe r.

BTST B ∼(<bi t-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets or

clears the Z flag accordingly. The bit number is specified by 3-bit

immediate data or the lower three bits of a general register.

BAND

BIAND

C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specifi ed bit in a general register or memory

operand and stores the result i n the carry flag.

C ∧ [∼(<bit-No.> of <EAd> )] → C

ANDs the carry flag with the inverse of a specified bit in a general

The bit number is specified by 3-bit immediate data.

BOR

BIOR

C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general register or memory

operand and stores the result i n the carry flag.

C ∨ [∼(<bit-No.> of <EAd>)] → C

ORs the carry flag with the inverse of a specified bit in a general register

or memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

Note: * Refers to the operand size.

B: Byte

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Table 2.7 Bit Manipulat ion Instructions (2)

Instruction Size*Function

BXOR

BIXOR

C ⊕ (<bit-No.> of <EAd>) → C

XORs the carry flag with a specified bit in a general register or memory

operand and stores the result i n the carry flag.

C ⊕ [∼(<bit-No.> of <EAd>)] → C

XORs the carry flag with the inverse of a specified bit in a general

The bit number is specified by 3-bit immediate data.

BLD

BILD

(<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory operand to the

carry flag.

∼(<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or memory

operand to the carry flag.

The bit number is specified by 3-bit immediate data.

BST

BIST

C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a general register or

memory operand.

∼C → (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a specifi ed bit in a general

The bit number is specified by 3-bit immediate data.

Note: * Refers to the operand size.

B: Byte

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Table 2.8 Branch Instructi ons

Instruction Size Function

Bcc Branches to a specified address if a specified condition is true. The

branching conditions are listed below.

Mnemonic Description Condition

BRA (BT ) Always (true) Always

BRN (BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

BCC (BHS) Carry clear

(high or same) C = 0

BCS (BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0

BLT Less than N ⊕ V = 1

BGT Greater than Z ∨ (N ⊕ V) = 0

BLE Less or equal Z ∨ (N ⊕ V) = 1

JMP Branches unconditionally to a specified address.

BSR Branches to a subroutine at a specified address.

JSR Branches to a subroutine at a specified address.

RTS Returns from a subroutine

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Table 2.9 System C ontrol Instru ctions

Instruction Size*Function

TRAPA Starts trap-instruction exception handling.

RTE Returns from an exception-handling routine.

SLEEP Causes a transition to a power-down state.

LDC B/W (EAs) → CCR, (EAs) → EXR

Moves general register or memory contents or immediate data to CCR or

EXR. Although CCR and EXR are 8-bit registers, word-size transfers are

performed between them and me mory. The upper 8 bits are valid.

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or memory.

Although CCR and EXR are 8-bit registers, word-size transfers are

performed between them and me mory. The upper 8 bits are valid.

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with immediate data.

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate data.

XORC B CCR ⊕ # IMM → CCR, EXR ⊕ #IMM → EXR

Logically XORs the CCR or EXR contents with immediate data.

NOP PC + 2 → PC

Only increments the program counter.

Note: *Refers to the operand size.

B: Byte

W: Word

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Table 2.10 Block Data Transfer Instructions

Instruction Size Function

EEPMOV.B

EEPMOV.W



if R4L ≠ 0 then

Repeat @ER5+ → @ER6+

R4L–1 → R4L

Until R4L = 0

else next;

if R4 ≠ 0 then

Repeat @ER5+ → @ER6+

R4–1 → R4

Until R4 = 0

else next;

Transfers a data block. Starting from the address set in ER5, transfers

data for the number of bytes set in R4L or R4 to the address location set

in ER6.

Execution of the next instruction begins as soon as the transfer is

completed.

2.6.2 Basic Instruction Formats

The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an

operation field (op field), a register field (r field), an effective address extension (EA field), and a

condition fiel d (cc).

Figure 2.11 shows examples of instruction formats.

• Operation Field

Indicates the function of the instruction, the addressing mode, and the operation to be carried

out on the operand. The operation field always includes the first four bits of the instruction.

Some instructions have two operation fields.

• Register Field

Specifies a general register. Address registers are specified by 3 bits, and data registers by 3

bits or 4 bits. Some instructions have two register fields. Some have no register field.

• Effective Address Extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

• Condition Field

Specifies the branching condition of Bcc instructions.

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op rn rm

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

rn rm

EA(disp)

op cc EA(disp) BRA d:16, etc.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

(4) Operation field, effective address extension, and condition field

Figure 2.11 Instruction Formats (Examples)

2.7 Addressi ng Modes and Effective Address Calculation

The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses

a subset of these addressing modes. Arithmetic and logic instructions can use the register direct

and immediate modes. Data transfer instructions can use all addressing modes except program-

counter relative and memory indirect. Bit manipulation instructions use register direct, register

indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR,

BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in

the operand.

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Table 2.11 Addressing Modes

No. Addressing Mode Symbol

1 Regi ster direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)

4Register indirect with post-increment

@–ERn

5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

2.7.1 Register Direct



Rn

The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the

operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7

can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

2.7.2 Register Indirect



@ERn

The register field of the instruction code specifies an address register (ERn) which contains the

address of the operand on memory. If the address is a program instruction address, the lower 24

bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

2.7.3 Register Indirect with Displacement



@(d:16, ERn) or @(d:32, ERn)

A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)

specified by the register field of the instruction, and the sum gives the address of a memory

operand. A 16-bit displacement is sign-extended when added.

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2.7.4 Register Indirect with Post-Increment or Pre-Decrement



@ERn+ or @-ERn



@ERn+: The registe r field of the instruc ti on code

specifies an address register (ERn) which contains the address of a memory operand. After the

operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the

address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for

longword transfer instruction. For the word or longword transfer instructions, the register value

should be even.



@-ERn: The value 1, 2, or 4 is subtracted from an

address register (ERn) specified by the register field in the instruction code, and the result is the

address of a memory operand. The result is also stored in the address register. The value

subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer

instruction. For the word or longword transfer instructions, the register value should be even.

2.7.5 Absolute Address



@aa:8, @aa:16, @aa:24, or @aa:32

The instruction code contains the absolute address of a memory operand. The absolute address

may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long

(@aa:32 ). Table 2.12 indic at es the acc essibl e absol u te add ress rang es.

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits

(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).

For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can

access the enti re addres s space.

A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8

bits are all assumed to be 0 (H'00).

Table 2.12 Absolute Address Access Ranges

Absolute Address Normal Mode*Advanced Mode

Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF

16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF

32 bits (@aa:32) H'000000 to H'FFFFFF

Program instruction

address 24 bits (@aa:24)

Note: Normal mode is not available in this LSI.

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2.7.6 Immediate



#xx:8, #xx:16, or #xx:32

The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an

operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit

number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a

vector add res s.

2.7.7 Program-Counter Relative



@(d:8, PC) or @(d:16, PC)

This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in

the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address.

Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0

(H'00). The PC value to which the displacement is added is the address of the first byte of the next

instruction, so the possible branching range is –126 to +128 byte s (–63 to +64 words) or –32766 to

+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should

be an even number.

2.7.8 Memory Indirect



@@aa:8

This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit

absolute address specifying a memory operand. This memory operand contains a branch address.

The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255

(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode,

the memory operand is a word operand and the branch address is 16 bits long. In advanced mode,

the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00).

Note that the first part of the address range is also the exception vector area. For further details,

refer to section 4, Exception Handl ing .

If an odd address is specified in word or longword memory access, or as a branch address, the

least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched

at the address preceding the specified address (For further information, see section 2.5.2, Memory

Data Formats).

Note: Normal mode is not available in this LSI.

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Specified

by @aa:8 Specified

by @aa:8

Branch address

Reserved

(a) Normal Mode

(a) Advanced Mode

Note: * Normal mode is not available in this LSI.

Figure 2.12 Branch Address Specification in Memory Indirect Mode

2.7.9 Effective Address Calculation

Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal

mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.

Note: Normal mode is not available in this LSI.

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Table 2.13 Effective Address Calculation (1)

Offset

31 0

31 23

3Register indirect with displacement

@(d:16,ERn) or @(d:32,ERn)

op disp

op rn

31 0

Don't care

31 23

31 0

Don't care

31 0

disp

31 0

31 23

31 0

Don't care

31 23

31 0

Don't care

Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

General register contents

Sign extension

pre-decrement

•Register indirect with post-increment @ERn+

•Register indirect with pre-decrement @-ERn

1, 2, or 4

Operand Size

Byte

Word

Longword

Operand is general register contents.

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Table 2.13 Effective Address Calculation (2)

op 31 23

31 0

Don't care

abs

@aa:8 7

H'FFFF

op 31 23

31 0

Don't care

@aa:16

@aa:24

@aa:32

abs 15

31 23

31 0

Don't care

31 23

31 0

Don't care

abs

op IMM

#xx:8/#xx:16/#xx:32

Addressing Mode and Instruction Format

Absolute address

Immediate

Effective Address Calculation Effective Address (EA)

Sign extension

Operand is immediate data.

31 23

Program-counter relative

@(d:8,PC)/@(d:16,PC)

Memory indirect @@aa:8

• Normal mode*

• Advanced mode

31 0

Don't care

23 0

disp

31 23

31 0

Don't care

disp

abs 31 0

abs

H'000000 7

15 31 23

31 0

Don't care 15

H'0016

op abs 31 0

abs

H'000000 78

Note: * Normal mode is not available in this LSI.

PC contents

Sign

extension

Memory contents

Section 2 CPU

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2.8 Processing States

The H8S/2600 CPU has five main processing states: the reset state, exception handling state,

program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state

transitions.

• Reset State

In this state, the CPU and all on-chip peripheral modules are initialized and not operating.

When the

RES

input goes low, all current processing stops and the CPU enters the reset state.

All interrupts are masked in the reset state. Reset exception handling starts when the

RES

signal changes from low to high. For details, refer to section 4, Exception Handling.

The reset state can also be entered by a watchdog timer overflow.

• Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction.

The CPU fetches a start address (vector) from the exception vector table and branches to that

address. For further details, refer to section 4, Exception Handling.

• Program Execution State

In this state, the CPU executes program instructions in sequence.

• Bus-Released State

The bus has been released in response to a bus request from a bus master other than the CPU.

While the bus is released, the CPU halts operations.

• Program stop state

This is a power-down state in which the CPU stops operating. The program stop state occurs

when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further

details, refer to section 21, Pow er-D ow n Modes.

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Program execution state

Exception handling state

Program halt state

Bus-released state

Reset state

End of bus

request

Bus

request

Interrupt

request

SLEEP instruction

RES = High

STBY = High,

RES = Low

Notes: From any state, a transition to hardware standby mode occurs when STBY goes low.

* From any state except hardware standby mode, a transition to the reset state

occurs whenever RES goes low. A transition can also be made to the reset state

when the watchdog timer overflows.

Bus

request End of

bus request

Request for

exception

handling

End of

exception

handling

Figure 2.13 State Transitions

2.9 Usage Note

2.9.1 Notes on Us ing the Bit Opera ti on Instr uction

Instructions BSET, BCLR, BNOT, BST, and BIST read data in byte units, and write data in byte

units after bit operation. Therefore, attention must be paid when these instructions are used for

ports or registers including write-only bits.

Instruction BCLR can be used to clear the flag in the internal I/O register to 0. If it is obvious that

the flag has been set to 1 by the interrupt processing routine, it is unnecessary to read the flag

beforehand.

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Section 3 MCU Operating Modes

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Sectio n 3 MCU Operating Modes

3.1 Opera ting Mode Selection

This LSI supports only operating mode 7, that is, the advanced single-chip mode. The operating

mode is determined by the setting of the mode pins (MD2 to MD0). Only mode 7 can be used in

this LSI. Therefore, all mode pins must be fixed high, as shown in table 3.1. Do not change the

mode pin settings during operation.

Table 3.1 MCU Opera tin g Mode Sel ect ion

External Data Bus

MCU

Operating

Mode MD2 MD1 MD0

CPU

Operating

Mode Description On-Chip

ROM Initial

Width Max.

Width

7111

Advanced

mode Single-chip mode Enabled 

3.2 Register Descriptions

The follow i ng registers are related to the ope rating mode.

• Mode control register (MDCR)

• System control register (SYSCR)

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3.2.1 Mode Control Register (MDCR)

Bit Bit Name Initial Value R/W Descriptions

71R/WReserved

Only 1 should be written to this bit.

6 to

3All 0 Reserved

These bits are always read as 0 and cannot be

modified.

MDS2

MDS1

MDS0



Mode select 2 to 0

These bits indicate the input levels at pins MD2 to MD0

(the current operating mode). Bits MDS2 to MDS0

correspond to MD2 to MD0. MDS2 to MDS0 are read-

only bits and they cannot be written to. The mode pin

(MD2 to MD0) input levels are latched into these bits

when MDCR is read. These latches are canceled by a

reset.

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3.2.2 System Control Register (SYSCR)

SYSCR is an 8-bit readable/writable register that selects saturating or non-saturating calculation

for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and

enables or disables on-chip RAM.

Bit Bit Name Initial Value R/W Descriptions

7 MACS 0 R/W MAC Saturation

Selects either saturating or non-saturating calculation

for the MAC instruction.

0: Non-saturating calculation for the MAC instruction

1: Saturating calculation for the MAC instruction

60Reserved

This bi t is always read as 0 and cannot be modified.

4INTM1

INTM0 0

0R/W

R/W These bits select the control mode of the interrupt

controller. For details of the interrupt control modes,

see section 5.6, Interrupt Control Modes and Interrupt

Operation.

00: Interrupt control mode 0

01: Setting prohibited

10: Interrupt control mode 2

11: Setting prohibited

3 NMIEG 0 R/W NMI Edge Sele ct

Selects the valid edge of the NMI interrupt input.

0: An i nterrupt is requested at the falling edge of NMI

input

1: An in terrupt is requested at the rising edge of NMI

input

2, 1 All 0 Reserved

These bits are always read as 0 and cannot be

modified.

0 RAME 1 R/W RAM Enable

Enables or disables on-chip RAM. The RAME bit is

initialized when the reset status is released.

0: On-chip RAM is disabled

1: On-chip RAM is enabled

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3.3 Pin Functions in Each Operating Mode

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,

however external addresses cannot be accessed.

All I/O ports are available for use as input-output ports.

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3.4 Address Map

Figure 3.1 shows the address map in each operating mode.

H'000000

H'01FFFF

H'FFD000

H'FFEFBF

H'FFF800

H'FFFFC0

H'FFFFFF

H'FFFF3F

H'FFFF60

H'FFFFBF

H8S/2628

On-chip ROM

(F-ZTAT/masked ROM)

On-chip RAM

Internal I/O registers

ROM: 128 kbytes, RAM: 8 kbytes

Mode 7

Advanced single-chip mode

H'000000

H'01FFFF

H'FFD800

H'FFEFBF

H'FFF800

H'FFFFC0

H'FFFFFF

H'FFFF3F

H'FFFF60

H'FFFFBF

H8S/2627

On-chip ROM

(Masked ROM)

On-chip RAM

Internal I/O registers

ROM: 128 kbytes, RAM: 6 kbytes

Mode 7

Advanced single-chip mode

Figure 3.1 Address Map

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Section 4 Exception Handling

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Section 4 E xcepti on Ha ndling

4.1 Exception Handling Types and Priority

As shown in table 4.1, exception handling may be caused by a reset, trace, interrupt, or trap

instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions

occur simultaneously, they are accepted and processed in order of priority. Exception sources, the

stack structure, and operation of the CPU vary depending on the interrupt control mode. For

details on the interrupt control mode, refer to section 5, Interrupt Controller.

Table 4.1 Exception Types and Priority

Priority Exception Type Start of Exception Handling

High Reset Starts immediately after a low-to-high transition at the

RES

pin, or when the watchdog timer overflows. The CPU enters

the reset state when the

RES

pin is low.

Trace*1Starts when execution of the current instruction or exception

handling ends, if the trace (T) bit in EXR is set to 1.

Dire ct transition Starts when a direction transition occurs as the result of

SLEEP instruction execution.

Interrupt Starts when execution of the current instruction or exception

handling ends, if an interrupt request has been issued.*2

Low Trap instruct ion *3Started by execution of a trap instruc tion (TRAPA).

Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not

executed after execution of an RTE instruction.

2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC

instruction execution, or on completion of reset exception handling.

3. Trap instruction exception handling requests are accepted at all times in program

execution state.

4.2 Except i on S ources and Ex cept ion Vector T ab le

Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception

sources and their vector addresses. Since the usable modes differ depending on the product, for

details on each product, refer to section 3, MCU Operating Modes.

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Table 4.2 Exception Handl ing Vect or Table

Vector Address*1

Exception Source Vector Number Normal Mode Advanced Mode

Power-on reset 0 H'0000 to H'0001 H'0000 to H'0003

Manual reset *21 H'0002 to H'0003 H'0004 to H'0007

Reserved for system use 2 H'0004 to H'0005 H'0008 to H'000B

3 H'0006 to H'0007 H'000C to H'000F

4 H'0008 to H'0019 H'0010 to H'0013

Trace 5 H'000A to H'000B H'0014 to H'0017

Interrupt (direct transitions)*26 H'000C to H'000D H'0018 to H'001B

Interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F

Trap instruction (#0) 8 H'0010 to H'0011 H'0020 to H'0023

(#1) 9 H'0012 to H'0013 H'0024 to H'0027

(#2) 10 H'0014 to H'0015 H'0028 to H'002B

(#3) 11 H'0016 to H'0017 H'002C to H'002F

Reserved for system use 12 H'0018 to H'0019 H''0030 to H'0033

13 H'001A to H'001B H'0034 to H'0037

14 H'001C to H'001D H'0038 to H'003B

15 H'001E to H'001F H'003C to H'003F

External interrupt IRQ0 16 H'0020 to H'0021 H'0040 to H'0043

IRQ1 17 H'0022 to H'0023 H'0044 to H'0047

IRQ2 18 H'0024 to H'0025 H'0048 to H'004B

IRQ3 19 H'0026 to H'0027 H'004C to H'004F

IRQ4 20 H'0028 to H'0029 H'0050 to H'0053

IRQ5 21 H'002A to H'002B H'0054 to H'0057

Reserved for system use 22 H'002C to H'002D H'0058 to H'005B

23 H'002E to H'002F H'005C to H'005F

Internal interr upt*324



127

H'0030 to H'0031



H'00FE to H'00FF

H'0060 to H'0063



H'01FC to H'01FF

Notes: 1. Lower 16 bits of the address.

2. Not available in this LSI.

3. For details of internal interrupt vectors, see section 5.5, Interrupt Excepti on Handling

Vector Table.

Section 4 Exception Handling

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4.3 Reset

A reset has the highest exception priority.

When the

RES

pin goes low, all processing halts and this LSI enters the reset state. To ensure that

this LSI is reset, hold the

RES

pin low for at least 20 ms at power-up. To reset the chip during

operation, hold the

RES

pin low for at least 20 states. A reset initializes the internal state of the

CPU and the registers of on-chip peripheral modules.

The chip can also be reset by overflow of the watchdog timer. For details, see section 13,

Watchdog Timer.

The interrupt control mode is 0 immediately after reset.

4.3.1 Reset Exception Handling

When the

RES

pin goes high after being held low for the necessary period, this LSI starts reset

exception handling as follows:

1. The internal state of the CPU and the registers of the on-chip peripheral modules are

initialized, the T bit in EXR is cleared to 0, and the I bit in EXR and CCR is set to 1.

2. The reset exception handling vector address is read and transferred to the PC, and program

executi on star ts from the add res s indica ted by the PC.

Figures 4.1 and 4.2 show examples of the reset sequence.

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RES

High

Vector fetch Internal

processing Fetch of first

program instruction

(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)

(2)(4) Start address (contents of reset exception handling vector address)

(5) Start address ((5)=(2)(4))

(6) First program instruction

Internal

address bus

Internal read

signal

Internal write

signal

Internal data

bus

(1)

(2) (4) (6)

(3) (5)

Figure 4.1 Reset Sequence

(Advanced Mode with On-Chip ROM Enabled)

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RES

HWR, LWR

D15 to D0

High

* * *

Address bus

Vector fetch Internal

processing Fetch of first

program instruction

(1)

(2) (4) (6)

(3) (5)

(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)

(2)(4) Start address (contents of reset exception handling vector address)

(5) Start address ((5)=(2)(4))

(6) First program instruction

Note: * Three program wait states are inserted.

Figure 4.2 Reset Sequence

(Advanced Mode with On-chip ROM Disabled: Not Available in this LSI)

4.3.2 Interrupts after Reset

If an interrupt is accepted immediately after a reset and before the stack pointer (SP) is initialized,

the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all

interrupt requests, including NMI, are disabled immediately after a reset exception handling is

executed. Since the first instruction of a program is always executed immediately after the reset,

make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP).

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4.3.3 State of On-Chip Peripheral Modules after Reset Release

After reset release, MSTPCRA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, respectively,

and all modules except the DTC enter module stop mode. Consequently, on-chip peripheral

module registers cannot be read or written to. Register reading and writing is enabled when the

module stop mode is cancelled.

4.4 Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control

mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,

Interrupt Controller.

If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on

completion of each instruction. Trace mode is not affected by interrupt mask bit in CCR. Table 4.3

shows the states of CCR and EXR after execution of trace exception handling. Trace mode is

cancelled by clearing the T bit in EXR to 0 with the trace exception handling. The T bit saved on

the stack retains its value of 1, and when control is returned from the trace exception handling

routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out

after execution of the RTE instruction.

Interrup ts are ac cep ted ev en wi thin the trace excepti on handli ng routi ne.

Table 4.3 Statuses of CCR and EXR after Trace Exception Handling

CCR EXR

Interrupt Control Mode IUII2 to I0T

0 Trace exception handling cannot be used.

21——0

Legend:

1: Set to 1

0: Cleared to 0

—: Retains val ue prior to execution

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4.5 Interrupts

Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt

control modes and can assign interrupts other than NMI to eight priority/mask levels to enable

multiplexed interrupt control. The source to start interrupt exception handling and the vector

address differ depending on the product. For details, refer to section 5, Interrupt Controller.

Interrupt exception handling is conducted as follows:

1. The values in the program counter (PC), condition code register (CCR), and extended control

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. A vector address corresponding to the interrupt source is generated, the start address is loaded

from the vector table to the PC, and program execution begins from that address.

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4.6 Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction

exception handling can be executed at all times in the program execution state.

Trap instruction exception handling is conducted as follows:

1. The values in the program counter (PC), condition code register (CCR), and extended control

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. A vector address corresponding to the interrupt source is generated, the start address is loaded

from the vecto r table to the PC, and program exec ution st ar ts from that addres s.

The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector

number from 0 to 3, as specified in the instruction code.

Table 4.4 shows the statuses of CCR and EXR after execution of trap instruction exception

handling.

Table 4.4 Statuses of CCR and EXR after Trap Instruction Exception Handling

CCR EXR

Interrupt Control Mode IUII2 to I0T

01———

21——0

Legend:

1: Set to 1

0: Cleared to 0

—: Retains val ue prior to execution

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4.7 Stack Status after Exception Handling

Figures 4.3 shows the stack after completion of trap instruction exception handling and interrupt

exception handling.

CCR

CCR*

PC (16 bits)

EXR

Reserved*

CCR

CCR*

PC (16 bits)

CCR

PC (24 bits)

EXR

Reserved*

CCR

PC (24 bits)

(a) Normal Modes*

(b) Advanced Modes

Interrupt control mode 0 Interrupt control mode 2

Notes: 1.

2. Ignored on return.

Normal modes are not available in this LSI.

Figure 4.3 Stack Status after Exception Handling

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4.8 Usage Note

When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The

stack should always be accessed by word transfer instruction or longword transfer instruction, and

the value of the stack pointer (SP: ER7) should always be kept even. Use the following

instructions to save registers:

PUSH.W Rn (or MOV.W Rn, @-SP)

PUSH.L ERn (or MOV.L ERn, @-SP)

Use the following instructions to restore registers:

POP.W Rn (or MOV.W @SP+, Rn)

POP.L ERn (or MOV.L @SP+, ERn)

Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of what

happens when the SP value is odd.

CCR:

PC:

R1L:

SP:

Condition code register

Program counter

General register R1L

Stack pointer

CCR

SP SP R1L H'FFFEFA

H'FFFEFB

H'FFFEFC

H'FFFEFD

H'FFFEFE

H'FFFEFF

PC PC

TRAP instruction executedSP set to H'FFFEFF

Data saved above SP

MOV.B R1L, @-ER7 instruction executed

Contents of CCR lost

Address

Legend:

Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.

Figure 4.4 Operation when SP Value Is Odd

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Section 5 Interrupt Controller

5.1 Features

• Two interrupt control modes

 Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in

the system control register (SYSCR).

• Priorities settable with IPR

 An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority

levels can be set for each module for all interrupts except NMI. NMI is assigned the

highest priority level of 8, and can be accepted at all times.

• Independent vector addresses

 All interrupt sources are assigned independent vector addresses, making it unnecessary for

the source to be identified in the interrupt handling routine.

• Seven external interrupts

 NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling

edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level

sensing, can be selected for IRQ5 to IRQ0.

• DTC control

 The DTC can be activated by an interrupt request.

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A block diagram of the interrupt controller is shown in figure 5.1.

SYSCR

NMI input

IRQ input

Internal interrupt request

SWDTEND to SSERT_i1

NMIEG

INTM1, INTM0

NMI input unit

IRQ input unit

ISR

ISCR IER

IPR

Interrupt controller

Priority

determination

Interrupt

request

Vector number

I2 to I0 CCR

EXR

CPU

ISCR:

IER:

ISR:

IPR:

SYSCR:

IRQ sense control register

IRQ enable register

IRQ status register

Interrupt priority register

System control register

Legend:

Figure 5.1 Block Diagram of Interrup t Contro ller

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5.2 Input/Output Pi ns

Table 5.1 summarizes the pins of the interrupt controller.

Table 5.1 Pin Configura tion

Name I/O Function

NMI Input Nonmaskable external interrupt

Rising or falling edge can be selected.

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ0

Input

Maskable external interrupts

Rising, falli ng, or both edges, or level sensing, can be

selected.

5.3 Register Descriptions

The interrupt controller has the following registers. For the system control register (SYSCR), refer

to section 3.2.2, System Control Register (SYSCR).

• System control register (SYSCR)

• IRQ sense control register H (ISCRH)

• IRQ sense control register L (ISCRL)

• IRQ enable register (IER)

• IRQ status register (ISR)

• Interrupt priority register A (IPRA)

• Interrupt priority register B (IPRB)

• Interrupt priority register C (IPRC)

• Interrupt priority register D (IPRD)

• Interrupt priority register E (IPRE)

• Interrupt priority register F (IPRF)

• Interrupt priority register G (IPRG)

• Interrupt priority register H (IPRH)

• Interrupt priority register I (IPRI)

• Interrupt priority register J (IPRJ)

• Interrupt priority register K (IPRK)

• Interrupt priority register L (IPRL)

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• Interrupt priority register M (IPRM)

5.3.1 Interrupt Priority Registers A to M (IPRA to IPRM)

The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for

interrupts other than NMI.

The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a

value in the range from H'7 to H'0 in the 3-bit groups of bits 2 to 0 and 6 to 4 sets the priority of

the corresponding inte rrupt.

Bit Bit Name Initial Value R/W Description

70Reserved

These bits are always read as 0.

IPR6

IPR5

IPR4

R/W

Sets the priority of the corresponding interrupt

source.

000: Priority level 0 (Lowest)

001: Priority l e vel 1

010: Priority l e vel 2

011: Priority l e vel 3

100: Priority l e vel 4

101: Priority l e vel 5

110: Priority l e vel 6

111: Priority level 7 (Highest)

30Reserved

These bits are always read as 0.

IPR2

IPR1

IPR0

R/W

Sets the priority of the corresponding interrupt

source.

000: Priority level 0 (Lowest)

001: Priority l e vel 1

010: Priority l e vel 2

011: Priority l e vel 3

100: Priority l e vel 4

101: Priority l e vel 5

110: Priority l e vel 6

111: Priority level 7 (Highest)

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5.3.2 IRQ Enable Register (IER)

IER is an 8-bit readable/writable register that controls the enabling and disabling of interrupt

requests IRQ5 to IRQ0.

Bit Bit Name Initial Value R/W Description

7, 6 All 0 R/W Reserve d

Only 0 should be written to these bits.

5 IRQ5E 0 R/W IRQ5 Enable

The IRQ5 interrupt request is enabled when this

bit is 1.

4 IRQ4E 0 R/W IRQ4 Enable

The IRQ4 interrupt request is enabled when this

bit is 1.

3 IRQ3E 0 R/W IRQ3 Enable

The IRQ3 interrupt request is enabled when this

bit is 1.

2 IRQ2E 0 R/W IRQ2 Enable

The IRQ2 interrupt request is enabled when this

bit is 1.

1 IRQ1E 0 R/W IRQ1 Enable

The IRQ1 interrupt request is enabled when this

bit is 1.

0 IRQ0E 0 R/W IRQ0 Enable

The IRQ0 interrupt request is enabled when this

bit is 1.

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5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)

The ISCR registers are 16-bit readable/writable registers that select the source that generates an

interrupt request at pins

IRQ5

IRQ0

• ISCRH

Bit Bit Name Initial Value R/W Description

15 to

12 All 0 R/W Reserved

Only 0 should be written to these bits.

10 IRQ5SCB

IRQ5SCA 0

0R/W

R/W IRQ5 Sense Control B

IRQ5 Sense Control A

00: Interrupt request generated at

IRQ5

input

lev el low

01: Interrupt request generated at falling edge

IRQ5

input

10: Interrupt request generated at rising edge of

IRQ5

input

11: Interrupt request generated at both falling

and rising edges of

IRQ5

input

8IRQ4SCB

IRQ4SCA 0

0R/W

R/W IRQ4 Sense Control B

IRQ4 Sense Control A

00: Interrupt request generated at

IRQ4

input

lev el low

01: Interrupt request generated at falling edge

IRQ4

input

10: Interrupt request generated at rising edge of

IRQ4

input

11: Interrupt request generated at both falling

and rising edges of

IRQ4

input

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• ISCRL

Bit Bit Name Initial Value R/W Description

6IRQ3SCB

IRQ3SCA 0

0R/W

R/W IRQ3 Sense Control B

IRQ3 Sense Control A

00: Interrupt request generated at

IRQ3

input

lev el low

01: Interrupt request generated at falling edge

IRQ3

input

10: Interrupt request generated at rising edge of

IRQ3

input

11: Interrupt request generated at both falling

and rising edges of

IRQ3

input

4IRQ2SCB

IRQ2SCA 0

0R/W

R/W IRQ2 Sense Control B

IRQ2 Sense Control A

00: Interrupt request generated at

IRQ2

input

lev el low

01: Interrupt request generated at falling edge

IRQ2

input

10: Interrupt request generated at rising edge of

IRQ2

input

11: Interrupt request generated at both falling

and rising edges of

IRQ2

input

2IRQ1SCB

IRQ1SCA 0

0R/W

R/W IRQ1 Sense Control B

IRQ1 Sense Control A

00: Interrupt request generated at

IRQ1

input

lev el low

01: Interrupt request generated at falling edge

IRQ1

input

10: Interrupt request generated at rising edge of

IRQ1

input

11: Interrupt request generated at both falling

and rising edges of

IRQ1

input

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Bit Bit Name Initial Value R/W Description

0IRQ0SCB

IRQ0SCA 0

0R/W

R/W IRQ0 Sense Control B

IRQ0 Sense Control A

00: Interrupt request generated at

IRQ0

input

lev el low

01: Interrupt request generated at falling edge

IRQ0

input

10: Interrupt request generated at rising edge of

IRQ0

input

11: Interrupt request generated at both falling

and rising edges of

IRQ0

input

5.3.4 IRQ Status Register (ISR)

ISR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt

requests.

Bit Bit Name Initial Value R/W Description

7, 6 All 0 R/W Reserve d

Only 0 should be written to these bits.

IRQ5F

IRQ4F

IRQ3F

IRQ2F

IRQ1F

IRQ0F

R/W

[Setting condition]

• When the interrupt source selected by the

ISCR registers occurs

[Clearing conditions]

• Cleared by reading IRQnF flag when IRQnF

= 1, then writing 0 to IRQnF flag

• When interrupt exception handling is

executed when low-level detection is set

and

IRQn

input is h ig h

• When IRQn interrupt exception handling is

executed when falling, rising, or both-edge

detection is set

• When the DTC is activated by an IRQn

interrupt, and the DISEL bit in MRB of the

DTC is cleared to 0

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5.4 Inter rupt Sources

5.4.1 External Interr upts

There are seven external interrupts: NMI and IRQ5 to IRQ0. These interrupts can be used to

restore this LSI from software standby mode.

NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU

regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG

bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling

edge on the NMI pin.

IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are reques ted by an input signal at pins

IRQ5

IRQ0

. Interrupts IRQ5 to IRQ0 have the following features:

• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling

edge, rising edge, or both edges, at pins

IRQ5

IRQ0

• Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IER.

• The interrupt priority level can be set with IPR.

• The status of interrupt requests IRQ5 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0

by software.

The detection of IRQ5 to IRQ0 interrupts does not depend on whether the relevant pin has been

set for input or output. However, when a pin is used as an external interrupt input pin, do not clear

the corresponding DDR to 0; and use the pin as an I/O pin for another function.

A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5.2.

IRQn interrupt

request

IRQnE

IRQnF

Clear signal

Edge/level

detection circuit

IRQnSCA, IRQnSCB

IRQn input

Note: n = 5 to 0

Figure 5.2 Block Diagram of Interrup ts IR Q5 to IRQ0

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5.4.2 Internal Interrupts

The sources for internal interrupts from on-chip peripheral modules have the following features:

• For each on-chip peripheral module there are flags that indicate the interrupt request status,

and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1

for a particular interrupt source, an interrupt request is issued to the interrupt controller.

• The interrupt priority level can be set by means of IPR.

• The DTC can be activated by a TPU, SCI, or other interrupt request.

• When the DTC is activated by an interrupt request, it is not affected by the interrupt control

mode or CPU interrupt mask bit.

5.5 Interrupt Excep tion Handling Vector Table

Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.

For default priorities, the lower the vector number, the higher the priority. Priorities among

modules can be set by means of IPR. Modules set at the same priority will conform to their default

priorities. Priorities within a module are fixed.

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Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities

Vector

Address*

Interrupt

Source Origin of

Interrupt Source Vector

Number Advanced

Mode IPR Priority

NMI 7 H'001C HighExternal

pin IRQ0 16 H'0040 IPRA6 to IPRA4

IRQ1 17 H'0044 IPRA2 to IPRA0

IRQ2 18 H'0048 IPRB6 to IPRB4

IRQ3 19 H'004C

IRQ4 20 H'0050 IPRB2 to IPRB0

IRQ5 21 H'0054

— 22 H'0058

Reserved for

system use 23 H'005C

DTC SWDTEND 24 H'0060 IPRC2 to IPRC0

Watchdog

timer 0 WOVI0 25 H'0064 IPRD6 to IPRD4

PC break

control PC break 27 H'006C IPRE6 to IPRE4

A/D ADI 28 H'0070 IPRE2 to IPRE0

TGIA_0 32 H'0080 IPRF6 to IPRF4

TPU

channel 0 TGIB_0 33 H'0084

TGIC_0 34 H'0088

TGID_0 35 H'008C

TCIV_0 36 H'0090

TGIA_1 40 H'00A0 IPRF2 to IPRF0TPU

channel 1 TGIB_1 41 H'00A4

TCIV_1 42 H'00A8

TCIU_1 43 H'00AC

TGIA_2 44 H'00B0 IPRG6 to IPRG4

TPU

channel 2 TGIB_2 45 H'00B4

TCIV_2 46 H'00B8

TCIU_2 47 H'00BC Low

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Vector

Address*

Interrupt

Source Origin of

Interrupt Source Vector

Number Advanced

Mode IPR Priority

TGIA_3 48 H'00C0 IPRG2 to IPRG0 High

TPU

channel 3 TGIB_3 49 H'00C4

TGIC_3 50 H'00C8

TGID_3 51 H'00CC

TCIV_3 52 H'00D0

TGIA_4 56 H'00E0 IPRH6 to IPRH4TPU

channel 4 TGIB_4 57 H'00E4

TCIV_4 58 H'00E8

TCIU_4 59 H'00EC

TGIA_5 60 H'00F0 IPRH2 to IPRH0TPU

channel 5 TGIB_5 61 H'00F4

TCIV_5 62 H'00F8

TCIU_5 63 H'00FC

CMIA_0 64 H'0100 IPRI6 to IPRI4

8-bit timer

channel 0 CMIB_0 65 H'0104

OVI_0 66 H'0108

CMIA_1 68 H'0110 IPRI2 to IPRI08-bit timer

channel 1 CMIB_1 69 H'0114

OVI_1 70 H'0118

ERI_0 80 H'0140 IPRJ2 to IPRJ0SCI

channel 0 RXI_0 81 H'0144

TXI_0 82 H'0148

TEI_0 83 H'014C

ERI_2 88 H'0160 IPRK2 to IPRK0SCI

channel 2 RXI_2 89 H'0164

TXI_2 90 H'0168

TEI_2 91 H'016C Low

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Vector

Address*

Interrupt

Source Origin of

Interrupt Source Vector

Number Advanced

Mode IPR Priority

CMIA_2 92 H'0170 IPRL6 to IPRL4 High

8-bit timer

channel 2 CMIB_2 93 H'0174

OVI_2 94 H'0178

CMIA_3 96 H'0180

8-bit timer

channel 3 CMIB_3 97 H'0184

OVI_3 98 H'0188

HCAN ERS0, OVR0 104 H'01A0 IPRM6 to IPRM4

RM0 105 H'01A4

RM1 106 H'01A8

SLE0 107 H'01AC

SSEr_i0 108 H'01B0 I PRM2 to IPRM0SSU

channel 0 SSRx_i0 109 H'01B4

SSTx_i0 110 H'01B8

SSU

channel 1 SSERT_i1 111 H'01BC Low

Note: *Lower 16 bits of the start address.

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5.6 Inter rupt Control Modes and Interrupt Operation

The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.

Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is

selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and

interrupt control mode 2.

Table 5.3 Interrup t Con tro l Modes

Interrupt

Control Mode Priority Setting

Registers Interrupt

Mask Bits Description

0 Default I The priorities of interrupt sources are fi xed at

the default settings.

Interrupt sources, except for NMI, are masked

by the I bit.

2 IPR I2 to I0 8 priority levels other than NMI can be set with

IPR.

8-level in terrupt mask control is performed by

bits I2 to I0.

5.6.1 Interrupt Control Mode 0

In interrupt control mode 0, interrupt requests other than for NMI are masked by the I bit in CCR

in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.

1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an

interrupt request is sent to the interrupt controller.

2. If the I bit in CCR is set to 1, only an NMI interrupt is accepted, and other interrupt requests

are held pending. If the I bit is cleared, an interrupt request is accepted.

3. When interrupt requests are sent to the interrupt controller, the interrupt with the highest

priority according to the interrupt priority levels is selected and other interrupt requests are

held pending.

4. When the CPU accepts an interrupt request, it starts interrupt exception handling after

execution of the current instruction has been completed.

5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on

the stack shows the address of the first instruction to be executed after returning from the

interrupt handling routine.

6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.

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7. The CPU generates a vector address for the accepted interrupt and starts execution of the

interrupt handling routine at the address indicated by the contents of the vector address in the

vector table.

Program execution status

Interrupt generated?

NMI

IRQ0

IRQ1

TEI_2

I = 0

Save PC and CCR

I ← 1

Read vector address

Branch to interrupt handling routine

Yes

Yes No

Yes

Hold

pending

Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance

in Interrupt Control Mode 0

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5.6.2 Interrupt Control Mode 2

In interrupt control mode 2, mask control is applied to eight levels for interrupt requests other than

NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting.

Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.

1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt

request is sent to the interrupt controller.

2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest

priority according to the interrupt priority levels set in IPR is selected, and lower-priority

interrupt requests are held pending. If a number of interrupt requests with the same priority are

generated at the same time, the interrupt request with the highest priority according to the

priority system shown in table 5.2 is selected.

3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set

in EXR. An interrupt request with a priority no higher than the mask level set at that time is

held pending, and only an interrupt request with a priority higher than the interrupt mask level

is accepted.

4. When the CPU accepts an interrupt request, it starts interrupt exception handling after

execution of the current instruction has been completed.

5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC

saved on the stack shows the address of the first instruction to be executed after returning from

the interrupt handling routine.

6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of

the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7.

7. The CPU generates a vector address for the accepted interrupt and starts execution of the

interrupt handling routine at the address indicated by the contents of the vector address in the

vector table.

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Yes

Program execution status

Interrupt generated?

NMI

Level 6 interrupt?

Mask level 5

or below?

Level 7 interrupt?

Mask level 6

or below?

Save PC, CCR, and EXR

Clear T bit to 0

Update mask level

Read vector address

Branch to interrupt handling routine

Hold

pending

Level 1 interrupt?

Mask level 0?

Yes

No Yes

Yes

Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2

5.6.3 Interrupt Exception Handling Sequence

Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case

where interrupt control mode 0 is set in advanced mode, and the program area and stack area are

in on-chip memory.

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(14)(12)(10)(6)(4)(2)

(1) (5) (7) (9) (11) (13)

Interrupt service

routine instruction

prefetch

Internal

operation

Vector fetch

stack

Instruction

prefetch Internal

operation

Interrupt

acceptance

Interrupt level determination

Wait for end of instruction

Interrupt

request signal

Internal

address bus

Internal

read signal

Internal

write signal

Internal

data bus

(3)

(1)

(2) (4)

(3)

(5)

(7)

Instruction prefetch address (Not executed.

This is the contents of the saved PC, the return address)

Instruction code (Not executed)

Instruction prefetch address (Not executed)

SP-2

SP-4

Saved PC and saved CCR

Vector address

Interrupt handling routine start address (Vector address contents)

Interrupt handling routine start address ((13) = (10)(12))

First instruction of interrupt handling routine

(6) (8)

(9) (11)

(10) (12)

(13)

(14)

(8)

Figure 5.5 Interrupt Exception Handling

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5.6.4 Interrupt Response Times

Table 5.4 shows interrupt response times—the interval between generation of an interrupt request

and execution of the first instruction in the interrupt handling routine. The execution status

symbols used in table 5.4 are explained in table 5.5.

This LSI is capable of fast word transfer to on-chip memory, has the program area in on-chip

ROM and the stack area in on-chip RAM, enabling high-speed processing.

Table 5.4 Interrupt Response Times

Normal Mode*5Advanced Mode

No. Execution Status

Interrupt

control

mode 0

Interrupt

control

mode 2

Interrupt

control

mode 0

Interrupt

control

mode 2

1 Interrupt priority determination*133 33

2Number of wait states until executing

instruction ends*219 to 1+2·SI19 to 1+2·SI19 to 1+2·SI19 to 1+2·SI

3 PC, CCR, EXR stack save 2·SK3·SK2·SK3·SK

4 Vector fetch SISI2·SI2·SI

5 Instruction fetch*32·SI2·SI2·SI2·SI

6 Internal processing*422 22

Total (using on-chip memory) 31 to 11 32 to 12 32 to 12 33 to 13

Notes: 1. Two states in case of internal interrupt.

2. Refers to MULXS and DIVXS instructions.

3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.

4. Internal processing after interrupt acceptance and internal processing after vector fetch.

5. Not available in this LSI.

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Table 5.5 Number of State s in Interrupt Handling Routine Execut ion Status

Object of Access

External Device*

8-Bit Bus 16-Bit Bus

Symbol Internal

Memory 2-State

Access 3-State

Access 2-State

Access 3-State

Access

Instruction fetch SI1 4 6+2m 2 3+m

Branch address read SJ

Stack manipulation SK

Legend:

m: Number of wait states in an external device access.

Note: *Not available in thi s LSI.

5.6.5 DTC Activation by Interrupt

The DTC can be activated by an interrupt. For details, see section 8, Data Transfer Controller

(DTC).

5.7 Usage Notes

5.7.1 Conflict between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective

after execution of the instruction.

When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an

interrupt is generated during execution of the instruction, the interrupt concerned will still be

enabled on completion of the instruction, and so interrupt exception handling for that interrupt will

be executed on completion of the instruction. However, if there is an interrupt request of higher

priority than that interrupt, interrupt exception handling will be executed for the higher-priority

interrupt, and the lower-priority interrupt will be ignored.

The same also applies when an interrupt source flag is cleared to 0.

Figure 5.6 shows an example in which the TCIEV bit in TIER_0 of the TPU is cleared to 0.

The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the

interrupt is masked.

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Internal

address bus

Internal

write signal

TCIEV

TCFV

TCIV

interrupt signal

TIER_0 write cycle by CPU TCIV exception handling

TIER_0 address

Figure 5.6 Conflict between Interrupt Generation and Disabling

5.7.2 Instructions that Disable Interrupts

The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these

instructions are executed, all interrupts including NMI are disabled and the next instruction is

always executed. When the I bit is set by one of these instructions, the new value becomes valid

two states after execution of the instruction ends.

5.7.3 When Interrupts Are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.

The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has

updated the mask level with an LDC, ANDC, ORC, or XORC instruction.

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5.7.4 Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.

With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer

is not accepted until the transfer is completed.

With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt

exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this

case is the address of the next instruction.

Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the

following coding should be used.

L1: EEPMOV.W

MOV.W R4,R4

BNE L1

5.7.5 IRQ Interrupt

When operating by clock input, acceptance of input to an IRQ is synchronized with the clock. In

software standby mode, the input is accepted asynchronously. For details on the input conditions,

see section 23.3.2, Control Signal Timing.

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Section 6 PC Break Controller (PBC)

The PC break controller (PBC) provides functions that simplify program debugging. Using these

functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with

the chip alone, without using an in-circuit emulator. A block diagram of the PC break controller is

shown in figure 6.1.

6.1 Features

• Two break channels (A and B)

• 24-bit break address

 Bit masking possible

• Four types of break compare conditions

 Ins tru cti on fe tch

 Data read

 Data write

 Data re a d/wri te

• Bus master

 Either CPU or CPU/DTC can be selected

• The timing of PC break exception handling after the occurrence of a break condition is as

follows

 Immediately before execution of the instruction fetched at the set address (instruction

fetch)

 Immediately after execution of the instruction that accesses data at the set address (data

access)

• Module stop mode can be set

PBC0000A_000020020300

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Output controlOutput control

Mask control

PC break

interrupt

Match signal

Mask control

BARA BCRA

BARB BCRB

Comparator Control

logic

Comparator Control

logic

Internal address

Access

status

Figure 6.1 Block Diagram of PC Break Controller

6.2 Register Descriptions

The PC break controller has the following registers.

• Break address register A (BARA)

• Break address register B (BARB)

• Break control register A (BCRA)

• Break control register B (BCRB)

6.2.1 Break Address Register A (BARA)

BARA is a 32-bit readable/writable register that specifies the channel A break address.

Bit Bit Name Initial Value R/W Description

31 to 24 −Undefined −Reserved

These bits are read as an undefined value

and cannot be modified.

23 to 0 BAA23 to BAA0 H'000000 R/W These bits set the channel A PC break

address.

Section 6 PC Break Controller (PBC)

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6.2.2 Break Address Register B (BARB)

BARB is the channel B break address register. The bit configuration is the same as for BARA.

6.2.3 Break Control Register A (BCRA)

BCRA controls channel A PC breaks. BCRA also contains a condition match flag.

Bit Bit Name Initial Value R/W Description

7 CMFA 0 R/W Condi tion Match Flag A

[Setting condition]

• When a condition set for channel A is satisfied

[Clearing condition]

• When 0 is written to CMFA after reading CMFA =

6 CDA 0 R/W CPU Cycle/DTC Cycle Select A

Selects the channel A break condition bus master.

0: CPU

1: CPU or DTC

BAMRA2

BAMRA1

BAMRA0

R/W

Break Address Mask Register A2 to A0

These bits specify which bits of the break address

set in BARA are to be masked.

000: BAA23 t o BAA0 (All bits are unmasked)

001: BAA23 to BAA1 (Lowest bit is masked)

010: BAA23 to BAA2 (Lower 2 bits are masked)

011: BAA23 to BAA3 (Lower 3 bits are masked)

100: BAA23 to BAA4 (Lower 4 bits are masked)

101: BAA23 to BAA8 (Lower 8 bits are masked)

110: BAA23 to BAA12 (Lower 12 bits are masked)

111: BAA23 to BAA16 (Lower 16 bits are masked)

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Bit Bit Name Initial Value R/W Description

1CSELA1

CSELA0 0

0R/W

R/W Break Condition Select A

Selects break condition of channel A.

00: Instruction fetch is used as break condition

01: Data read cycle is used as break condition

10: Data write cycle is used as break condition

11: Data read/write cycle is used as break condition

0 BIEA 0 R/W Break Interrupt Enable A

When this bit is 1, the PC break interrupt request of

channel A is enabled.

6.2.4 Break Control Register B (BCRB)

BCRB is the channel B break control register. The bit configuration is the same as for BCRA.

6.3 Operation

The operation flow from break condition setting to PC break interrupt exception handling is

shown in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and section 6.3.2, PC Break

Interrupt Due to Data Access, taking the example of channel A.

6.3.1 PC Break Interrupt Due to Instruction Fetch

1. Set the break address in BARA.

For a PC break caused by an instruction fetch, set the address of the first instruction byte as the

break address.

2. Set the break conditions in BCR.

Set bit 6 (CDA) to 0 to select the CPU because the bus master must be the CPU for a PC break

caused by an instruction fetch. Set the address bits to be masked to bits 5 to 3 (BAMA2 to

BAMA0). Set bits 2 and 1 (CSELA1 and CSELA0) to 00 to specify an instruction fetch as the

break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.

3. When the instruction at the set address is fetched, a PC break request is generated immediately

before execution of the fetched instruction, and the condition match flag (CMFA) is set.

4. After priority determination by the interrupt controller, PC break interrupt exception handling

is started.

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6.3.2 PC Break Inte rrup t Due to Data Acce ss

1. Set the break address in BARA.

For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address

space address as the break address. Stack operations and branch address reads are included in

data accesses.

2. Set the break conditions in BCRA.

Select the bus master with bit 6 (CDA). Set the address bits to be masked to bits 5 to 3

(BAMA2 to BAMA0). Set bits 2 and 1 (CSELA1 and CSELA0) to 01, 10, or 11 to specify

data access as the break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.

3. After execution of the instruction that performs a data access on the set address, a PC break

request is generated and the condition match flag (CMFA) is set.

4. After priority determination by the interrupt controller, PC break interrupt exception handling

is started.

6.3.3 PC Break Operat ion at Consecut ive Data Transfe r

• When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction

PC break exception handling is executed after all data transfers have been completed and the

EEPMOV.B ins truction has ended.

• When a PC break interrupt is generated at a DTC transfer address

PC break exception handling is executed after the DTC has completed the specified number of

data transfers, or after data for which the DISEL bit is set to 1 has been transferred.

6.3.4 Operation in Transitions to Power-Down Modes

The operation when a PC break interrupt is set for an instruction fetch at the address after a

SLEEP instruction is shown below.

• When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to

sleep mode:

After execution of the SLEEP instruction, a transition is not made to sleep mode, and PC break

exception handling is executed. After execution of PC break exception handling, the

instruction at the address after the SLEEP instruction is executed (figure 6.2 (A)).

• When the SLEEP instruction causes a transition to software standby mode:

After execution of the SLEEP instruction, a transition is made to software standby mode, and

PC break exception handling is not executed. However, the CMFA or CMFB flag is set (figure

6.2 (B)).

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SLEEP

instruction execution SLEEP

instruction execution

Transition to

respective mode

PC break exception

handling

Execution of instruction

after sleep instruction

(A)

(B)

Figure 6.2 Operation in Power-D ow n Mode Transi tions

6.3.5 When Instruction Execution Is Delayed by One State

While the break interrupt enable bit is set to 1, instruction execution is one state later than usual.

• For 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, and RTS) in on-chip

ROM or RAM.

• When break interrupt by instruction fetch is set, the set address indicates on-chip ROM or

RA M space, and that addres s is used for da ta access, th e instruc ti on will be one state later than

in normal operation.

• When break interrupt by instruction fetch is set and a break interrupt is generated, if the

executing instruction immediately preceding the set instruction has one of the addressing

modes shown below, and that address indicates on-chip ROM or RAM, the instruction will be

one state later than in normal operation.

A ddressing modes: @ERn, @(d: 16,ERn ), @(d:32, ERn), @-ER n/ER n +, @aa:8, @aa: 24,

@aa:32, @(d:8, PC ), @(d:16, PC), @@aa:8

• When break interrupt by instruction fetch is set and a break interrupt is generated, if the

executing instruction immediately preceding the set instruction is NOP or SLEEP, or has

#xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the

instruction will be one state later than in normal operation.

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6.4 Usage Notes

6.4.1 Module Stop Mode Setting

PBC operation can be disabled or enabled using the module stop control register. The initial

setting is for PBC operation to be halted. Register access is enabled by clearing module stop

mode. For details, refer to sec tion 21, Pow er-Do w n Modes.

6.4.2 PC Break Interrupts

The PC break interrupt is shared by channels A and B. The channel from which the request was

issued must be determined by the interrupt handler.

6.4.3 CMFA and CMFB

The CMFA and CMFB flags are not automatically cleared to 0, so 0 must be written to CMFA or

CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt

will be requested after interrupt handling ends.

6.4.4 PC Break Inte rrup t wh en DTC Is Bus Master

A PC break interrupt generated when the DTC is the bus master is accepted after the bus

mastership has been transferred to the CPU by the bus controller.

6.4.5 PC Break Set for Instru ct ion Fetch at Address Fol low ing BSR, JSR, JMP, TRA PA,

RTE, or RTS Instruction

Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS

instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the

instruction fetch at the next address.

6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction

When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt

becomes valid two states after the end of the instruction execution. If a PC break interrupt is set

for the instruction following one of these instructions, since interrupts, including NMI, are

disabled for a 3-state period in the case of LDC, ANDC, ORC, and XOR, the next instruction is

always executed. For details, see section 5, Interrupt Controller.

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6.4.7 PC Break Set for Ins truct ion Fetch at Ad dre ss Fol low ing Bcc Instru ction

A PC break interrupt is generated if the instruction at the next address is executed in accordance

with the branch condition, and is not generated if the instruction at the next address is not

executed.

6.4.8 PC Break Set for Instru ct ion Fetch at Branch Destin ation Add ress of Bcc

Instruction

A PC break interrupt is generated if the instruction at the branch destination is executed in

accordance with the branch condition, and is not generated if the instruction at the branch

destination is not executed.

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Section 7 B us Contro ller

The H8S/2600 CPU is driven by a system clock, denoted by the symbol φ.

The bus controller controls a memory cycle and a bus cycle. Different methods are used to access

on-chip memory and on-chip support modules. The bus controller also has a bus arbitration

function, and controls the operation of the internal bus masters: the CPU and data transfer

cont rol l er (DTC).

7.1 Basic Timing

The period from one rising edge of φ to the next is referred to as a “state”. The memory cycle or

bus cycle consists of one, two, three, or four states. Different methods are used to access on-chip

memory and on-chip support modules.

7.1.1 On-Chip Memory Access Timing (ROM, RAM)

On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and

word transfer instruction. Figure 7.1 shows the on-chip memory access cycle.

Internal address bus

Bus cycle

Address

Read data

Write data

Internal read signal

Internal data bus

Internal write signal

Internal data bus

Read

Write

Figure 7.1 On-Chip Memory Access Cycle

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7.1.2 On-Chip Support Module Access Timing

The on-chip support modules, except for the HCAN, SSU, and realtime input port data register,

are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular

internal I/O register being accessed. For details, refer to section 22, List of Registers. Figure 7.2

shows access timing for the on-chip peripheral modules.

Internal address bus

Bus cycle

Address

Read data

Write data

Internal read signal

Internal data bus

Internal write signal

Internal data bus

Read

Write

Figure 7.2 On-Chip Support Module Access Cycle

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7.1.3 On-Chip HCAN Module Access Timing

On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait

states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access

timing is shown in figure 7.3.

T1T3

T2T4

TwTw

Internal address bus

Bus cycle

Address

Read data

Write data

HCAN read signal

Internal data bus

HCAN write signal

Internal data bus

Read

Write

Figure 7.3 On-Chip HCAN Module Access Cycle (with Wait States)

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7.1.4 On-Chip SSU Module and Realtime Input Port Data Register Access Timing

The on-chip SSU module or realtime input port data register is accessed in three states. At this

time, a data bus width is 16 bits. Figure 7.4 shows the SSU module access timing.

Internal address bus

Bus cycle

Address

Read data

Write data

SSU read signal

Internal data bus

SSU write signal

Internal data bus

Read

Write

Figure 7.4 On-Chip SSU Module Access Cycle

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7.2 Bus Arbitration

The Bus Controller has a bus arbiter that arbitrates bus master operations.

There are two bus masters, the CPU and DTC, which perform read/write operations when they

control the bus.

7.2.1 Order of Priority of the Bus Masters

Each bus master requests the bus mastership by means of a bus request signal. The bus arbiter

detects the bus masters’ bus request signals, and if the bus mastership is requested, sends a bus

request acknowledge signal to the bus master making the request. If there are bus requests from

more than one bus master, the bus request acknowledge signal is sent to the one with the highest

priority. When a bus master receives the bus request acknowledge signal, it takes possession of the

bus until that signal is cancelled.

The order of priority of the bus mastership is as follows:

(High) DTC > CPU (Low)

7.2.2 Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority than that of the bus

master that has acquired the bus mastership and is currently operating, the bus mastership is not

necessarily transferred immediately. The CPU is the lowest-priority bus master, and if a bus

request is received from the DTC, the bus arbiter transfers the bus mastership to the bus master

that issued the request. The timing for transfer of the bus mastership is as follows:

• The bus mastership is transferred at a break between bus cycles.

However, if a bus cycle is executed in discrete operations, as in the case of a longword-size

access, the bus mastership is not transferred between such operations. For details, refer to

section 2.7, Bus Status in Instruction Execution in the H8S/2600 Series, H8S/2000 Series

Programming Manual.

• If the CPU is in sleep mode, it transfers the bus mastership immediately.

The DTC can release the bus mastership after a vector read, a register information read (3 states),

a single data transfer, or a register information write (3 states). It does not release the bus

mastership during a register information read (3 states), a single data transfer, or a register

information write (3 states).

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Section 8 Data Transfer Controller (DTC)

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Section 8 Data Transfer C ontroller (DTC)

This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or

softw are, to transf er data.

Figure 8.1 shows a block diagram of the DTC.

The DTC’s register information is stored in the on-chip RAM. When the DTC is used, the RAME

bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte),

enabling 32-bit/1-state reading and writing of the DTC register information.

8.1 Features

• Transfer is possible over any number of channels

• Three transfer modes

 Normal, repeat, and block transfer modes are available

• One activation source can trigger a number of data transfers (chain transfer)

• The direct specification of 16-Mbyte address space is possible

• Activation by software is possible

• Transfer can be set in byte or word units

• A CPU interrupt can be requested for the interrupt that activated the DTC

• Module stop mode can be set

DTCH80BA_010020020900

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Internal address bus

DTCER

DTVECR

Interrupt controller

Interrupt

request

DTC On-chip

RAM

Internal data busCPU interrupt

request

MRA MRB

CRA

CRB

DAR

SAR

MRA, MRB:

CRA, CRB:

SAR:

DAR:

DTCERA to DTCERG:

DTVECR:

DTC mode registers A and B

DTC transfer count registers A and B

DTC source address register

DTC destination address register

DTC enable registers A to G

DTC vector register

Legend:

DTC service

request

Control logic

Figure 8.1 Block Diagram of DTC

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8.2 Register Descriptions

The DTC has the following registers.

• DTC mode register A (MRA)

• DTC mode register B (MRB)

• DTC source address register (SAR)

• DTC destination address register (DAR)

• DTC transfer count register A (CRA)

• DTC transfer count register B (CRB)

These six registers cannot be directly accessed from the CPU.

When activated, the DTC reads a set of register information that is stored in on-chip RAM to the

corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated

• DTC enable registers (DTCER)

• DTC vector register (DTVECR)

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8.2.1 DTC Mode Register A (MRA)

MRA is an 8-bit register that selects the DTC operating mode.

Bit Bit Name Initial Value R/W Description

6SM1

SM0 Undefined

Undefined 

Source Address Mode 1 and 0

These bits specify an SAR operation after a data

transfer.

0×: SAR is fixed

10: SAR is incremented after a transfer

(by +1 when Sz = 0; by +2 when Sz = 1)

11: SAR is decremented after a transfer

(by –1 when Sz = 0; by –2 when Sz = 1)

4DM1

DM0 Undefined

Undefined 

Destination Address Mode 1 and 0

These bits specify a DAR operation after a data

transfer.

0×:DAR is fixed

10: DAR is incremented after a transfer

(by +1 when Sz = 0; by +2 when Sz = 1)

11: DAR is decremented after a transfer

(by –1 when Sz = 0; by –2 when Sz = 1)

2MD1

MD0 Undefined

Undefined 

DTC Mode

These bits specify the DTC transfer mode.

00: Normal mode

01: Repeat mode

10: Block transfer mode

11: Setting prohibited

1 DTS Undefined DTC Transfer Mode Select

Specifies whether the source side or the destination

side is set to be a repeat area or block area, in

repeat mode or block transfer mode.

0: Destination side is repeat area or block area

1: Source side is repeat area or block area

0 Sz Undefined DTC Data Transfer Size

Specifies the size of data to be transferred.

0: Byte-size transfer

1: Word-size transfer

Legend:

×: Don’t care

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8.2.2 DTC Mode Register B (MRB)

MRB is an 8-bit register that selects the DTC operating mode.

Bit Bit Name Initial Value R/W Description

7 CHNE Undefined DTC Chain Transfer Enable

When this bit is set to 1, a chain transfer will be

performed. For details, refer to 8.5.4, Chain Transfer.

In data transfer with CHNE set to 1, determination of

the end of the specified number of transfers, clearing

of the interrupt source flag, and clearing of DTCER,

are not performed.

6 DISEL Undefined DTC Interrupt Select

When this bit is set to 1, a CPU interrupt request is

generated every time after the end of a data transfer.

When this bit is set to 0, a CPU interrupt request is

generated at the time when the specified number of

data transfer ends.

5 to 0 Undefined Reserved

These bits have no effect on DTC operation. Only 0

should be written to these bits.

8.2.3 DTC Source Address Register (SAR)

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.

For word-size transfer, specify an even source address.

8.2.4 DTC Destination Address Register (DAR)

DAR is a 24-bit register that designates the destination address of data to be transferred by the

DTC. For word-size transfer, specify an even destination address.

8.2.5 DTC Transfer Count Register A (CRA)

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is

decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.

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In repeat mode or block transfer mode, the CRA is divided into two parts; the upper 8 bits

(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL

functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is

transferred, and the contents of CRAH are sent when the count reaches H'00.

8.2.6 DTC Transfer Count Register B (CRB)

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in

block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1

every time data is transferred, and transfer ends when the count reaches H'0000.

8.2.7 DTC Enable Registers (DTCER)

DTCER is comprised of seven registers; DTCERA to DTCERG, and is a register that specifies

DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is

shown in table 8.1. For DTCE bit setting, use bit manipulation instructions such as BSET and

BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set

at one time (only at the initial setting) by writing data after executing a dummy read on the

relevant register.

Bit Bit Name Initial Value R/W Description

DTCE7

DTCE6

DTCE5

DTCE4

DTCE3

DTCE2

DTCE1

DTCE0

R/W

DTC Acti vation Enable

Setting these bits to 1 specifies a relevant interrupt

source as a DTC activation source.

[Clearing conditions]

• When the DISEL bit in MRB i s 1 and the data

transfer has ended

• When the specified number of transfers have

ended

These bits are not cleared when the DISEL bit is 0

and the specified number of transfers have not been

completed.

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8.2.8 DTC Vector Register (DTVECR)

DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by

software, and sets a vector number for the software activation interrupt.

Bit Bit Name Initial Value R/W Description

7 SWDTE 0 R/W DTC Software Activation Enable

Setting thi s bit to 1 activates DTC. Onl y 1 can be

written to this bit.

[Clearing conditions]

• When the DISEL bit is 0 and the specified

number of transfers have not ended

• When 0 is wri tten to the DISEL bit after a

software-activated data transfer end interrupt

(SWDTEND) request has been sent to the CPU.

When the DISEL bit is 1 and data transfer has ended

or when the specified number of transfers have

ended, this bit will not be cleared.

DTVEC6

DTVEC5

DTVEC4

DTVEC3

DTVEC2

DTVEC1

DTVEC0

R/W

DTC Software Activation Vectors 6 to 0

These bits specify a vector number for DTC software

activation.

The vector address is expressed as H'0400 + (vector

number × 2). For example, when DTVEC6 to

DTVEC0 = H'10, the vector address is H'0420. When

the bit SWDTE is 0, these bits can be written.

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8.3 Activation Sources

The DTC operates when activated by an interrupt or by a write to DTVECR by software. An

interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER

bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the

activation source or corresponding DTCER bit is cleared. The activation source flag, in the case

of RXI_0, for example, is the RDRF flag of SCI_0.

When an interrupt has been designated a DTC activation source, the existing CPU mask level and

interrupt controller priorities have no effect. If there is more than one activation source at the same

time, the DTC operates in accordance with the default priorities.

Figure 8.2 shows a block diagram of DTC activation source control. For details, see section 5,

Interrupt Controller.

CPU

DTC

DTCER

Source flag cleared

On-chip

supporting

module

IRQ interrupt Interrupt

request

Clear

controller

Clear request

Interrupt controller

Selection circuit

Interrupt mask

Select

DTVECR

Figure 8.2 Block Diagram of DTC Activation Source Control

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8.4 Location of Register Information and DTC Vector Table

Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF).

Locating the register information in address space is shown in figure 8.3. Locate the MRA, SAR,

MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register

information.

In the case of chain transfer, register information should be located in consecutive areas and the

interrupt source as shown in figure 8.3. The DTC reads the start address of the register information

from the vector address set for each activation source, and then reads the register information from

that start address.

When the DTC is activated by software, the vector address is obtained from: H'0400 +

(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420. The

configuration of the vector address is the same in both normal and advanced modes, a 2-byte unit

being used in both cases. These two bytes specify the lower bits of the register information start

address.

MRA

0123

SAR

MRB DAR

CRA CRB

MRA SAR

MRB DAR

CRA CRB

Lower address

4 bytes

for 2nd transfer in

chain transfer

information

start address

Chain

transfer

Figure 8.3 Location of DTC Register Information in Address Space

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Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs

Interrupt

Source Origin of

Interrupt Source Vector Number DTC

Vector Address DTCE*Priority

Softw are Write to DTVECR DTVE CR H'0400 + (vector

number × 2) High

External pin IRQ0 16 H'0420 DTCEA7

IRQ1 17 H'0422 DTCEA6

IRQ2 18 H'0424 DTCEA5

IRQ3 19 H'0426 DTCEA4

IRQ4 20 H'0428 DTCEA3

IRQ5 21 H'042A DTCEA2

22 H'042C DTCEA1Reserved for

system use 23 H'042E DTCEA0

A/D counter ADI (A/D conversion

end) 28 H'0438 DTCEB6

TGIA_0 32 H'0440 DTCEB5

TPU

channel 0 TGIB_0 33 H'0442 DTCEB4

TGIC_0 34 H'0444 DTCEB3

TGID_0 35 H'0446 DTCEB2

TGIA_1 40 H'0450 DTCEB1TPU

channel 1 TGIB_1 41 H'0452 DTCEB0

TGIA_2 44 H'0458 DTCEC7TPU

channel 2 TGIB_2 45 H'045A DTCEC6

TGIA_3 48 H'0460 DTCEC5

TPU

channel 3 TGIB_3 49 H'0462 DTCEC4

TGIC_3 50 H'0464 DTCEC3

TGID_3 51 H'0466 DTCEC2

TGIA_4 56 H'0470 DTCEC1TPU

channel 4 TGIB_4 57 H'0472 DTCEC0

TGIA_5 60 H'0478 DTCED5TPU

channel 5 TGIB_5 61 H'047A DTCED4 Low

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Interrupt

Source Origin of

Interrupt Source Vector Number DTC

Vector Address DTCE*Priority

CMIA_1 64 H'0480 DTCED3 High8-bit timer

channel 0 65 H'0482 DTCED2

CMIB_1 68 H'0488 DTCED18-bit timer

channel 1 69 H'048A DTCED0

Reserved 72 H'0490 DTCEE7

73 H'0492 DTCEE6

74 H'0494 DTCEE5

75 H'0496 DTCEE4

RXI_081H'04A2DTCEE3

SCI

channel 0 TXI_0 82 H'04A4 DTCEE2

RXI_289H'04B2DTCEF7

SCI

channel 2 TXI_2 90 H'04B4 DTCEF6

CMIA_2 92 H'04B8 DTCEF58-bit timer

channel 2 CMIB_2 93 H'04BA DTCEF4

CMIA_3 96 H'04C0 DTCEF38-bit timer

channel 3 CMIB3 97 H'04C2 DTCEF2

HCAN Reserved for system

use 104 H'04D0 DTCEG7

RM0 105 H'04D2 DTCEG6

Reserved for system

use 106 H'04D4 DTCEG5

Reserved for system

use 107 H'04D6 DTCEG4

SSRx_i0 109 H'04DA DTCEG2SSU

channel 0 SSTx_i0 110 H'04DC DTCEG1 Low

Note: *DTCE bits with no corresponding interrupt are reserved, and the write value should

aslways be 0.

Section 8 Data Transfer Controller (DTC)

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8.5 Operation

information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated

The pre-storage of register information in the on-chip RAM makes it possible to transfer data over

any required number of channels. The transfer mode can be specified as normal, repeat, and block

transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of

transfers with a single activation source (chain transfer).

The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the

transfer destination address. After each transfer, SAR and DAR are independently incremented,

decremen ted, or left fixed dep endi ng on its regi ste r informa tion.

Start

End

Read DTC vector

Read register information

Data transfer

Write register information

Clear an activation flag

Interrupt exception

handling

Clear DTCER

CHNE=1

Next transfer

Yes

Transfer Counter=0

or DISEL=1

Figure 8.4 Flowchart of DTC Operation

Section 8 Data Transfer Controller (DTC)

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8.5.1 Normal Mode

In normal mode, one operation transfers one byte or one word of data.

Table 8.2 lists the register information in normal mode.

From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been

completed, a CPU interrupt can be requested.

Table 8.2 Register Information in Normal Mode

Name Abbreviation Function

DTC source address register SAR Designates source address

DTC destination address register DAR Designates destinati on address

DTC transfer count register A CRA Designates transfer count

DTC transfer count register B CRB Not used

SAR DAR

Transfer

Figure 8.5 Memory Mapping in Normal Mode

Section 8 Data Transfer Controller (DTC)

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8.5.2 Repeat Mode

In repeat mode, one operation transfers one byte or one word of data. Table 8.3 lists the register

information in repeat mode.

From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the

initial state of the transfer counter and the address register specified as the repeat area is restored,

and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and

therefore CPU interrupts cannot be requested when DISEL = 0.

Table 8.3 Register Information in Repeat Mode

Name Abbreviation Function

DTC source address register SAR Designates source address

DTC destination address register DAR Designates destinati on address

DTC transfer count register AH CRAH Holds number of transfers

DTC transfer count register AL CRAL Designates transfer count

DTC transfer count register B CRB Not used

SAR

DAR

SAR

Repeat area

Transfer

Figure 8.6 Memory Mapping in Repeat Mode

Section 8 Data Transfer Controller (DTC)

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8.5.3 Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the

transfer destination is designated as a block area. Table 8.4 lists the register information in block

transfer mode.

The block size can be between 1 and 256. When the transfer of one block ends, the initial state of

the block size counter and the address register specified as the block area is restored. The other

address register is then incremented, decremented, or left fixed.

From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been

completed, a CPU interrupt is requested.

Table 8.4 Register Information in Block Transfer Mode

Name Abbreviation Function

DTC source address register SAR Designates source address

DTC destination address register DAR Designates destinati on address

DTC transfer count register AH CRAH Holds block size

DTC transfer count register AL CRAL Designates block size count

DTC transfer count register B CRB Transfer count

Section 8 Data Transfer Controller (DTC)

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First block

.Transfer Block area

Nth block

DAR

SAR

DAR

Figure 8.7 Memory Mapping in Block T ransfe r Mode

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8.5.4 Chain Transfer

Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed

consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB,

which define data transfers, can be set independently.

Figure 8.8 shows the outline of the chain transfer operation.

When activated, the DTC reads the register information start address stored at the vector address

corresponding to the activation source, and then reads the first register information at that start

address. After data transfer ends, the CHNE bit will be tested. When it has been set to 1, DTC

reads the next register information located in a consecutive area and performs the data transfer.

These sequences are repeated until the CHNE bit is cleared to 0.

In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the

end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt

source flag for the activation source is not affected.

DTC vector

address

CHNE=1

CHNE=0

start address

Source

Destination

Source

Destination

Figure 8.8 Chain Transfer Operation

Section 8 Data Transfer Controller (DTC)

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8.5.5 Interrupts

A n interrupt requ es t is issued to the CPU when the D TC has compl e ted the speci fied nu mber of

data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt

activation, the interrupt set as the activation source is generated. These interrupts to the CPU are

subject to CPU mask level and interrupt controller priority level control.

In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is

generated.

When the DISEL bit is 1 and one data transfer has been completed, or the specified number of

transfers have been completed, after data transfer ends the SWDTE bit is held at 1 and an

SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit

to 0.

When the DTC is activated by software, an SWDTEND interrupt is not generated during a data

transfer wait or during data transfer even if the SWDTE bit is set to 1.

8.5.6 Operation Timing

DTC activation

request

DTC

request

Address

Vector read

Read Write

Data transfer

Transfer

information write

Transfer

information read

Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)

Section 8 Data Transfer Controller (DTC)

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DTC activation

request

DTC

request

Address

Vector read

Read Write Read Write

Data transfer

Transfer

information write

Transfer

information read

Figure 8.10 DTC Operation Timing (Example of Block Transfer Mode,

with Block Size of 2)

DTC activation

request

DTC

request

Address

Vector read

Read Write Read Write

Data transfer Data transfer

Transfer

information

write

Transfer

information write

Transfer

information read Transfer

information

read

Figure 8.11 DTC Operation Timing (Example of Chain Transfer)

8.5.7 Number of DTC Execution States

Table 8.5 lists execution status for a single DTC data transfer, and table 8.6 shows the number of

states required for each execution status.

Section 8 Data Transfer Controller (DTC)

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Table 8.5 DTC Execution Status

Mode Vector Read

Read/Write

JData Read

KData Write

Internal

Operations

Normal 1 6 1 1 3

Repeat 1 6 1 1 3

Block transfer 1 6 N N 3

Legend:

N: Block size (initial setting of CRAH and CRAL)

Table 8.6 Number of States Required for Each Execution Status

Object to be Accessed On-

Chip

RAM

On-

Chip

ROM

On-Chip I/O

Registers External Devices*

Bus width 32 1 6 8 16 8 16

Access states 1 1 2 2 2 3 2 3

Vector read SI146+2m2 3+m

read/write SJ

1

Byte data read SK1 1 2 2 2 3+m 2 3+m

Word data read SK114246+2m23+m

Byte data write SL1 1 2 2 2 3+m 2 3+m

Word data write SL114246+2m23+m

Execution

status

Internal operat ion SM1

Note: *Not available in thi s LSI.

The number of execution states is calculated from using the formula below. Note that Σ is the sum

of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,

plus 1).

Number of execution states = I · (1 + SI) + Σ (J · SJ + K · SK + L · SL) + M · SM

For example, when the DTC vector address table is located in the on-chip ROM, normal mode is

set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for

the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.

Section 8 Data Transfer Controller (DTC)

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8.6 Procedures for Using DTC

8.6.1 Activation by Interrupt

The procedure for using the DTC with interrupt activation is as follows:

1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM.

2. Set the start address of the register information in the DTC vector address.

3. Set the corresponding bit in DTCER to 1.

4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC

is activated when an interrupt used as an activation source is generated.

5. After one data transfer has been completed, or after the specified number of data transfers have

been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to

continue transferring data, set the DTCE bit to 1.

8.6.2 Activation by Software

The procedure for using the DTC with software activation is as follows:

1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM.

2. Set the start address of the register information in the DTC vector address.

3. Check that the SWDTE bit is 0.

4. Write 1 to SWDTE bit and the vector number to DTVECR.

5. Check the vector number written to DTVECR.

6. After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not

requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the

SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have

been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested.

Section 8 Data Transfer Controller (DTC)

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8.7 E xamples of Use of the DTC

8.7.1 Normal Mode

An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.

1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1

= 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have

any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the

SCI RDR address in SAR, the start address of the RAM area where data will be received in

DAR, and 128 (H'0080) in CRA. CRB can be set to any value.

2. Set the start address of the register information at the DTC vector address.

3. Set the corresponding bit in DTCER to 1.

4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception

complete (RXI) interrupt. Since the generation of a receive error during the SCI reception

operation will disable subsequent reception, the CPU should be enabled to accept receive error

interrupts.

5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in

SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is

transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented.

The RDRF flag is automatically cleared to 0.

6. When CRA becomes 0 after the 128 data transfers have been completed, the RDRF flag is held

at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The

interrupt handling routine will perform wrap-up processing.

Section 8 Data Transfer Controller (DTC)

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8.7.2 Chain Transfer

An example of DTC chain transfer is shown in which pulse output is performed using the PPG.

Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle

updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain

transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because clearing

of the activation source and interrupt generation at the end of the specified number of transfers are

restricted to the second half of the chain transfer (transfer when CHNE = 0).

1. Perform settings for transfer to the PPG’s NDR. Set MRA to incrementing source address

(SM1 = 1, SM0 = 0), a fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,

MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to

chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH

address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.

2. Perform settings for transfer to the TPU’s TGR. Set MRA to incrementing source address

(SM1 = 1, SM0 = 0), a fixed destination address (DM1 = DM0 = 0), normal mode (MD1 =

MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address

in DAR, and the data table size in CRA. CRB can be set to any value.

3. Locate the TPU transfer register information consecutively after the NDR transfer register

information.

4. Set the start address of the NDR transfer register information to the DTC vector address.

5. Set the bit corresponding to TGIA in DTCER to 1.

6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA

interrupt with TIER.

7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and

NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to

be used as the output trigger.

8. Set the CST bit in TSTR to 1, and start the TCNT count operation.

9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the

set value of the next output trigger period is transferred to TGRA. The activation source TGFA

flag is cleared.

10.When the specified number of transfers are completed (the TPU transfer CRA value is 0), the

TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the

CPU. Termination processing should be performed in the interrupt handling routine.

Section 8 Data Transfer Controller (DTC)

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8.7.3 Software Activation

An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means

of software activation. The transfer source address is H'1000 and the destination address is

H'2000. The vector number is H'60, so the vector address is H'04C0.

1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination

address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =

0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =

0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,

and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.

2. Set the start address of the register information at the DTC vector address (H'04C0).

3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated

by software.

4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.

5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this

indicates that the write failed. This is presumably because an interrupt occurred between steps

3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.

6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.

7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear

the SWDTE bit to 0 and perform other wrap-up processing.

Section 8 Data Transfer Controller (DTC)

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8.8 Usage Notes

8.8.1 Module Stop Mode Setting

DTC operation can be disabled or enabled using the module stop control register. The initial

setting is for DTC operation to be enabled. Register access is disabled by setting module stop

mode. Note that module stop mode cannot be set during DTC being activated. For details, refer to

section 21, Power-Down Modes.

8.8.2 On-Chip RAM

The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the

DTC is used, the RAME bit in SYSCR must not be cleared to 0.

8.8.3 DTCE Bit Setting

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts

are masked, multiple activation sources can be set at one time (only at the initial setting) by

writing data after executing a dummy read on the relevant register.

Section 8 Data Transfer Controller (DTC)

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Section 9 I/O Ports

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Section 9 I/O Ports

Table 9.1 summarizes the port functions. The pins of each port also have other functions such as

input/output or interrupt input pins of on-chip peripheral modules.

Each I/O port includes a data direction register (DDR) that controls input/output, a data register

(DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only

ports do not have a DR or DDR register.

Ports A to D have built-in input pull-up MOS functions and input pull-up MOS control registers

(PCR) to control the on/off state of input pull-up MOS.

Ports A to C include an open-drain control register (ODR) that controls the on/off state of the

output buffer PMOS.

All the I/O ports can drive a single TTL load and a 30 pF capacitive load.

Section 9 I/O Ports

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Table 9.1 Port Function s

Port Description Port a nd

Ot her Functions Name Input/Output and

Output Type

Port 1 General I/O port also

functioning as TPU_2,

TPU_1, and TPU_0

I/O pins, PPG output

pins, and interrupt

input pins

P17/PO15/TIOCB2/TCLKD

P16/PO14/TIOCA2/

IRQ1

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1/

IRQ0

P13/PO11/TIOCD0/TCLKB

P12/PO10/TIOCC0/TCLKA

P11/PO9/TIOCB0

P10/PO8/TIOCA0

Port 3 General I/O port also

functioning as SCI_0

I/O pins and interrupt

input pins

P37

P36

P35/

IRQ5

P34

P33

P32/SCK0/

IRQ4

P31/RxD0

P30/TxD0

Port 4 General input port also

functioning as A/D

converter analog

inputs

P47/AN7

P46/AN6

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

Section 9 I/O Ports

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Port Description Port a nd

Ot her Functions Name Input/Output and

Output Type

Port 7 General I/O port al so

functioning as TMR_0,

TMR_1, TMR_2, and

TMR_3 I/O pi ns

P77

P76

P75/TMO3

P74/TMO2

P73/TMO1

P72/TMO0

P71/TMCI23/TMRI23

P70/TMCI01/TMRI01

Port 9 General input port also

functioning as A/D

converter analog

inputs

P97/AN15

P96/AN14

P95/AN13

P94/AN12

P93/AN11

P92/AN10

P91/AN9

P90/AN8

Port A General I/O port also

functioning as SCI_2

I/O pins

PA3/SCK2

PA2/RxD2

PA1/TxD2

PA0

Built-in input pull-up MOS

Push-pu ll or open-drain output

selectable

Port B General I/O port also

functioning as TPU_5,

TPU_4, and TPU_3

I/O pins

PB7/TIOCB5

PB6/TIOCA5

PB5/TIOCB4

PB4/TIOCA4

PB3/TIOCD3

PB2/TIOCC3

PB1/TIOCB3

PB0/TIOCA3

Built-in input pull-up MOS

Push-pu ll or open-drain output

selectable

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Port Description Port a nd

Ot her Functions Name Input/Output and

Output Type

Port C General I/O port also

functioning as SSU_0

and SSU_1 I/O pins

PC7/

SCS1

PC6/SSCK1

PC5/SSI1

PC4/SSO1

PC3/

SCS0

PC2/SSCK0

PC1/SSI0

PC0/SSO0

Built-in input pull-up MOS

Push-pu ll or open-drain output

selectable

Port D General I/O port PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Built-in input pull-up MOS

Port F General I/O port also

functioning as interrupt

input pins, an A/D

converter start trigger

input pin, and a

system clock output

pin (φ)

PF7/φ

PF6

PF5

PF4

PF3/

ADTRG

IRQ3

PF2

PF1

PF0/

IRQ2

Section 9 I/O Ports

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9.1 Port 1

Port 1 is an 8-bit I/O port and has the following registers.

• Port 1 data direction register (P1DDR)

• Port 1 data register (P1DR)

• Port 1 register (PORT1)

9.1.1 Port 1 Data Direction Register (P1DDR)

P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port 1.

P1DDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7 P17DDR 0 W

6 P16DDR 0 W

5 P15DDR 0 W

4 P14DDR 0 W

3 P13DDR 0 W

2 P12DDR 0 W

1 P11DDR 0 W

0 P10DDR 0 W

When a pin is specified as a general purpose I/O

port, setting these bits to 1 makes the corresponding

port 1 pin an output pin. Clearing these bits to 0

makes the pin an input pin.

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9.1.2 Port 1 Data Register (P1DR)

P1DR is an 8-bit readable/writable register that stores output data for port 1 pins.

Bit Bit Name Initial Value R/W Description

7 P17DR 0 R/W

6 P16DR 0 R/W

5 P15DR 0 R/W

4 P14DR 0 R/W

3 P13DR 0 R/W

2 P12DR 0 R/W

1 P11DR 0 R/W

0 P10DR 0 R/W

Output data for a pin is stored when the pin is

specified as a general purpose I/O port.

9.1.3 Port 1 Register (PORT1)

PORT1 is an 8-bit read-only register that shows the pin states.

PORT1 cannot be modifi ed .

Bit Bit Name Initial Value R/W Description

7 P17 Undefined*R

6 P16 Undefined*R

5 P15 Undefined*R

4 P14 Undefined*R

3 P13 Undefined*R

2 P12 Undefined*R

1 P11 Undefined*R

0 P10 Undefined*R

If a port 1 read is performed while P1DDR bits are

set to 1, the P1DR values are read. If a port 1 read is

perfor med while P1DDR bits are cleared to 0, the pin

states are read.

Note: *Determined by the states of pins P17 to P10.

Section 9 I/O Ports

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9.1.4 Pin Functions

Port 1 pins also function as TPU I/O pins, PPG output pins, and interrupt input pins. The

correspondence between the register specification and the pin functions is shown below.

Table 9.2 P17 Pin Function

TPU Channel 2

Setting*Output Input or Initial Value

P17DDR 011

NDER15  01

Pin function TIOCB2 output P17 input P17 output PO15 output

TIOCB2 input

TCLKD input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

Table 9.3 P16 Pin Function

TPU Channel 2

Setting*Output Input or Initial Value

P16DDR 011

NDER14  01

Pin function TIOCA2 output P16 input P16 output PO14 output

TIOCA2 input

IRQ1

input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

Section 9 I/O Ports

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Table 9.4 P15 Pin Function

TPU Channel 1

Setting*Output Input or Initial Value

P15DDR 011

NDER13  01

Pin function TIOCB1 output P15 input P15 output PO13 output

TIOCB1 input

TCLKC input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

Table 9.5 P14 Pin Function

TPU Channel 1

Setting*Output Input or Initial Value

P14DDR 011

NDER12  01

Pin function TIOCA1 output P14 input P14 output PO12 output

TIOCA1 input

IRQ0

input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

Table 9.6 P13 Pin Function

TPU Channel 0

Setting*Output Input or Initial Value

P13DDR 011

NDER11  01

Pin function TIOCD0 output P13 input P13 output PO11 output

TIOCD0 input

TCLKB input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

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Table 9.7 P12 Pin Function

TPU Channel 0

Setting*Output Input or Initial Value

P12DDR 011

NDER10  01

Pin function TIOCC0 output P12 input P12 output PO10 output

TIOCC0 input

TCLKA input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

Table 9.8 P11 Pin Function

TPU Channel 0

Setting*Output Input or Initial Value

P11DDR 011

NDER9  01

Pin function TIOCB0 output P11 input P11 output PO9 output

TIOCB0 input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

Table 9.9 P10 Pin Function

TPU Channel 0

Setting*Output Input or Initial Value

P10DDR 011

NDER8  01

Pin function TIOCA0 output P10 input P10 output PO8 output

TIOCA0 input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

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9.2 Port 3

Port 3 is an 8-bit I/O port and has the following registers.

• Port 3 data direction register (P3DDR)

• Port 3 data register (P3DR)

• Port 3 register (PORT3)

• Port 3 open-drain control register (P3ODR)

9.2.1 Port 3 Data Direction Register (P3DDR)

P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port 3.

Bit Bit Name Initial Value R/W Description

7 P37DDR 0 W

6 P36DDR 0 W

5 P35DDR 0 W

4 P34DDR 0 W

3 P33DDR 0 W

2 P32DDR 0 W

1 P31DDR 0 W

0 P30DDR 0 W

When a pin is specified as a general purpose I/O

port, setting these bits to 1 makes the corresponding

port 3 pin an output pin. Clearing these bits to 0

makes the pin an input pin.

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9.2.2 Port 3 Data Register (P3DR)

P3DR is an 8-bit readable/writable register that stores output data for port 3 pins.

Bit Bit Name Initial Value R/W Description

7 P37DR 0 R/W

6 P36DR 0 R/W

5 P35DR 0 R/W

4 P34DR 0 R/W

3 P33DR 0 R/W

2 P32DR 0 R/W

1 P31DR 0 R/W

0 P30DR 0 R/W

Output data for a pin is stored when the pin is

specified as a general I/O port.

9.2.3 Port 3 Register (PORT3)

PORT3 is an 8-bit read-only register that shows the pin states.

Bit Bit Name Initial Value R/W Description

7 P37 Undefined*R

6 P36 Undefined*R

5 P35 Undefined*R

4 P34 Undefined*R

3 P33 Undefined*R

2 P32 Undefined*R

1 P31 Undefined*R

0 P30 Undefined*R

If a port 3 read is performed while P3DDR bits are

set to 1, the P3DR values are read. If a port 3 read is

perfor med while P3DDR bits are cleared to 0, the pin

states are read.

Note: *Determined by the states of pins P37 to P30.

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9.2.4 Port 3 Open-Drain Control Register (P3ODR)

P3ODR is an 8-bit readable/writable register that specifies the output type of port 3.

Bit Bit Name Initial Value R/W Description

7 P37ODR 0 R/W

6 P36ODR 0 R/W

5 P35ODR 0 R/W

4 P34ODR 0 R/W

3 P33ODR 0 R/W

2 P32ODR 0 R/W

1 P31ODR 0 R/W

0 P30ODR 0 R/W

When a pin is specified as an output port, setting the

corresponding bits to 1 specifies pin output to open-

drain and the input pull-up MOS to the off state.

Clearing these bits to 0 specifies that to push-pull

output.

9.2.5 Pin Functions

Port 3 pins also function as SCI_0 I/O pins and interrupt input pins. The correspondence between

the register specification and the pin functions is shown below.

Table 9.10 P37 Pin Function

P37DDR 0 1

Pin function P37 input P37 output

Table 9.11 P36 Pin Function

P36DDR 0 1

Pin function P36 input P36 output

Table 9.12 P35 Pin Function

P35DDR 0 1

Pin function P35 input P35 output

IRQ5

input*

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Table 9.13 P34 Pin Function

P34DDR 0 1

Pin function P34 input P34 output

Table 9.14 P33 Pin Function

P33DDR 0 1

Pin function P33 input P33 output

Table 9.15 P32 Pin Function

CKE1 in SCR_0 0 1

in SMR_0 0 1 

CKE0 in SCR_0 0 1 

P32DDR 0 1 

Pin function P32 input P32 output SCK0 output SCK0 output SCK0 input

IRQ4

input*

Table 9.16 P31 Pin Function

RE in SCR_0 0 1

P31DDR 0 1 

Pin function P31 input P31 output RxD0 output

Table 9.17 P30 Pin Function

TE in SCR_0 0 1

P30DDR 0 1 

Pin function P30 input P30 output TxD0 output

Note: *When used as an external interrupt input pin, do not use as an I/O pin for another

function.

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9.3 Port 4

Port 4 is an input-only port. Port 4 pins also function as A/D converter analog input pins. Port 4

has the fol l owi ng regi ster.

• Port 4 register (PORT4)

9.3.1 Port 4 Register (PORT4)

PORT4 is an 8-bit read-only register that shows port 4 pin states.

Bit Bit Name Initial Value R/W Description

7 P47 Undefined*R

6 P46 Undefined*R

5 P45 Undefined*R

4 P44 Undefined*R

3 P43 Undefined*R

2 P42 Undefined*R

1 P41 Undefined*R

0 P40 Undefined*R

The pin states are always read when a port 4 read is

performed.

Note: *Determined by the states of pins P47 to P40.

9.4 Port 7

Port 7 is an 8-bit I/O port and has the following registers.

• Port 7 data direction register (P7DDR)

• Port 7 data register (P7DR)

• Port 7 register (PORT7)

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9.4.1 Port 7 Data Direction Register (P7DDR)

P7DDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port 7.

P7DDR cannot be read, if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7 P77DDR 0 W

6 P76DDR 0 W

5 P75DDR 0 W

4 P74DDR 0 W

3 P73DDR 0 W

2 P72DDR 0 W

1 P71DDR 0 W

0 P70DDR 0 W

When a pin is specified as a general purpose I/O

port, setting these bits to 1 makes the corresponding

port 7 pin an output pin. Clearing these bits to 0

makes the pin an input pin.

9.4.2 Port 7 Data Register (P7DR)

P7DR is an 8-bit readable/writable register that stores output data for port 7 pins.

Bit Bit Name Initial Value R/W Description

7 P77DR 0 R/W

6 P76DR 0 R/W

5 P75DR 0 R/W

4 P74DR 0 R/W

3 P73DR 0 R/W

2 P72DR 0 R/W

1 P71DR 0 R/W

0 P70DR 0 R/W

Output data for a pin is stored when the pin is

specified as a general purpose I/O port.

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9.4.3 Port 7 Register (PORT7)

PORT7 is an 8-bit read-only register that shows the pin states.

PORT7 cannot be modifi ed .

Bit Bit Name Initial Value R/W Description

7 P77 Undefined*R

6 P76 Undefined*R

5 P75 Undefined*R

4 P74 Undefined*R

3 P73 Undefined*R

2 P72 Undefined*R

1 P71 Undefined*R

0 P70 Undefined*R

If a port 7 read is performed while P7DDR bits are

set to 1, the P7DR values are read. If a port 7 read is

perfor med while P7DDR bits are cleared to 0, the pin

states are read.

Note: *Determined by the states of pins P77 to P70.

9.4.4 Pin Functions

Port 7 pins al so function as TMR_3, TMR _2, TMR_ 1, and TMR _0 I/O pins. The corre spond ence

between the reg iste r specifi ca tion and the pin functi on s is shown below.

Table 9.18 P77 Pin Function

P77DDR 0 1

Pin function P77 input P77 output

Table 9.19 P76 Pin Function

P76DDR 0 1

Pin function P76 input P76 output

Table 9.20 P75 Pin Function

OS3 to OS0 in TCSR_3 All 0 Any of 1

P75DDR 0 1 

Pin function P75 input P75 output TMO3 output

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Table 9.21 P74 Pin Function

OS3 to OS0 in TCSR_2 All 0 Any of 1

P74DDR 0 1 

Pin function P74 input P74 output TMO2 output

Table 9.22 P73 Pin Function

OS3 to OS0 in TCSR_1 All 0 Any of 1

P73DDR 0 1 

Pin function P73 input P73 output TMO1 output

Table 9.23 P72 Pin Function

OS3 to OS0 in TCSR_0 All 0 Any of 1

P72DDR 0 1 

Pin function P72 input P72 output TMO0 output

Table 9.24 P71 Pin Function

P71DDR 0 1

Pin function P71 input P71 output

TMCI23 input/TMRI23 input

Table 9.25 P70 Pin Function

P70DDR 0 1

Pin function P70 input P70 output

TMCI01 input/TMRI01 input

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9.5 Port 9

Port 9 is an input-only port. Port 9 pins also function as A/D converter analog input pins. Port 9

has the fol l owi ng regi ster.

• Port 9 register (PORT9)

9.5.1 Port 9 Register (PORT9)

PORT9 is an 8-bit read-only register that shows port 9 pin states.

PORT9 cannot be modifi ed .

Bit Bit Name Initial Value R/W Description

7 P97 Undefined*R

6 P96 Undefined*R

5 P95 Undefined*R

4 P94 Undefined*R

3 P93 Undefined*R

2 P92 Undefined*R

1 P91 Undefined*R

0 P90 Undefined*R

The pin states are always read when a port 9 read is

performed.

Note: *Determined by the states of pins P97 to P90.

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9.6 Port A

Port A is a 4-bit I/O port that also has other functions. Port A has the following registers.

• Port A data direction register (PADDR)

• Port A data register (PADR)

• Port A register (PORTA)

• Port A pull-up MOS control register (PAPCR)

• Port A open-drain control register (PAODR)

9.6.1 Port A Data Direction Register (PADDR)

PADDR is an 8-bit write-only register, the individual bits of which specify whether the pins of

port A are used for input or output.

Bit Bit Name Initial Value R/W Description

7 to

4Undefined Reserved

These bits are read as undefined value and cannot

be modified.

3 PA3DDR 0 W

2 PA2DDR 0 W

1 PA1DDR 0 W

0 PA0DDR 0 W

When a pin is specified as a general purpose I/O

port, setting these bits to 1 makes the corresponding

port A pin an output pi n. Clearing these bits to 0

makes the pin an input pin.

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9.6.2 Port A Data Register (PADR)

PADR is an 8-bit readable/writable register that stores output data for port A pins.

Bit Bit Name Initial Value R/W Description

7 to

4Undefined Reserved

These bits are read as an undefined value and

cannot be modified.

3 PA3DR 0 R/W

2 PA2DR 0 R/W

1 PA1DR 0 R/W

0 PA0DR 0 R/W

Output data for a pin is stored when the pin is

specified as a general purpose I/O port.

9.6.3 Port A Register (PORTA)

PORTA is an 8-bit read-only register that shows port A pin states.

Bit Bit Name Initial Value R/W Description

7 to

4Undefined Reserved

These bits are read as an undefined value.

3 PA3 0 R

2 PA2 0 R

1 PA1 0 R

0 PA0 0 R

If a port A read is performed while PADDR bits are

set to 1, the PADR values are read. If a port A read is

performed while PADDR bits are cle ared to 0, the pin

states are read.

Note: *Determined by the states of pins PA3 to PA0.

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9.6.4 Port A Pull-Up MOS Control Register (PAPCR)

PAPCR is an 8-bit register that controls the input pull-up MOS function.

Bit Bit Name Initial Value R/W Description

7 to

4Undefined Reserved

These bits are read as an undefined value and

cannot be modified.

3 PA3PCR 0 R/W

2 PA2PCR 0 R/W

1 PA1PCR 0 R/W

0 PA0PCR 0 R/W

When a pin is specified as an input port, setting the

corresponding bit to 1 turns on the input pull-up MOS

for that pin.

9.6.5 Port A Open-Drain Control Register (PAODR)

PAODR is an 8-bit readable/writable register that specifies the output type of port A.

Bit Bit Name Initial Value R/W Description

7 to

4Undefined Reserved

These bits are read as an undefined value and

cannot be modified.

3 PA3ODR 0 R/W

2 PA2ODR 0 R/W

1 PA1ODR 0 R/W

0 PA0ODR 0 R/W

When a pin is specified as an output port, setting the

corresponding bits to 1 specifies pin output to open-

drain and the input pull-up MOS to the off state.

Clearing these bits to 0 specifies that to push-pull

output.

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9.6.6 Pin Functions

Port A pins also function as SCI_2 I/O pins. The correspondence between the register

specification and the pin functions is shown below.

Table 9.26 PA3 Pin Function

CKE1 in SCR_2 0 1

in SMR_2 0 1 

CKE0 in SCR_2 0 1 

PA3DDR 0 1 

Pin function PA3 input PA3 output SCK2 output SCK2 output SCK2 input

Table 9.27 PA2 Pin Function

RE in SCR_2 0 1

PA2DDR 0 1 

Pin function PA2 input PA2 output RxD2 input

Table 9.28 PA1 Pin Function

TE in SCR_2 0 1

PA1DDR 0 1 

Pin function PA1 input PA1 output TxD2 output

Table 9.29 PA0 Pin Function

PA0DDR 0 1

Pin function PA0 input PA0 output

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9.7 Port B

Port B is an 8-bit I/O port that also has other functions. Port B has the following registers.

• Port B data direction register (PBDDR)

• Port B data register (PBDR)

• Port B register (PORTB)

• Port B pull-up MOS control register (PBPCR)

• Port B open-drain control register (PBODR)

9.7.1 Port B Data Direction Register (PBDDR)

PBDDR is an 8-bit write-only register, the individual bits of which specify whether the pins of

port B are used for input or output.

Bit Bit Name Initial Value R/W Description

7 PB7DDR 0 W

6 PB6DDR 0 W

5 PB5DDR 0 W

4 PB4DDR 0 W

3 PB3DDR 0 W

2 PB2DDR 0 W

1 PB1DDR 0 W

0 PB0DDR 0 W

When a pin is specified as a general purpose I/O

port, setting these bits to 1 makes the corresponding

port 1 pin an output pin. Clearing these bits to 0

makes the pin an input pin.

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9.7.2 Port B Data Register (PBDR)

PBDR is an 8-bit readable/writable register that stores output data for the port B pins.

Bit Bit Name Initial Value R/W Description

7 PB7DR 0 R/W

6 PB6DR 0 R/W

5 PB5DR 0 R/W

4 PB4DR 0 R/W

3 PB3DR 0 R/W

2 PB2DR 0 R/W

1 PB1DR 0 R/W

0 PB0DR 0 R/W

Output data for a pin is stored when the pin is

specified as a general purpose I/O port.

9.7.3 Po rt B R egi ster ( PORT B)

PORTB is an 8-bit read-only register that shows port B pin states.

Bit Bit Name Initial Value R/W Description

7 PB7 0 R

6 PB6 0 R

5 PB5 0 R

4 PB4 0 R

3 PB3 0 R

2 PB2 0 R

1 PB1 0 R

0 PB0 0 R

If a port B read is performed while PBDDR bits are

set to 1, the PBDR values are read. If a port B read is

performed while PBDDR bits are cle ared to 0, the pin

states are read.

Note: *Determined by the states of pins PB7 to PB0.

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9.7.4 Port B Pull-Up MO S Contro l Register (PBPCR )

PBPCR is an 8-bit readable/writable register that controls the on/off state of input pull-up MOS of

port B.

Bit Bit Name Initial Value R/W Description

7 PB7PCR 0 R/W

6 PB6PCR 0 R/W

5 PB5PCR 0 R/W

4 PB4PCR 0 R/W

3 PB3PCR 0 R/W

2 PB2PCR 0 R/W

1 PB1PCR 0 R/W

0 PB0PCR 0 R/W

When a pin is specified as an input port, setting the

corresponding bits to 1 turns on the input pull-up

MOS for that pin.

9.7.5 Port B Open-Dr ain C ontrol Regi st er (P BODR)

PBODR is an 8-bit readable/writable register that specifies the output type of port B.

Bit Bit Name Initial Value R/W Description

7 PB7ODR 0 R/W

6 PB6ODR 0 R/W

5 PB5ODR 0 R/W

4 PB4ODR 0 R/W

3 PB3ODR 0 R/W

2 PB2ODR 0 R/W

1 PB1ODR 0 R/W

0 PB0ODR 0 R/W

When a pin function is specified as an output port,

setting the corresponding bits to 1 specifies pin

output as open-drain and the input pull-up MOS to

the off state. Clearing these bits to 0 specifies push-

pull output.

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9.7.6 Pin Functions

Port B pins also function as TPU I/O pins. The correspondence between the register specification

and the pin functions is shown below.

Table 9.30 PB7 Pin Function

TPU channel 5 setting*Output Input or Initial Value

PB7DDR 01

Pin function TIOCB5 output PB7 input PB7 output

TIOCB5 input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

Table 9.31 PB6 Pin Function

TPU channel 5 setting*Output Input or Initial Value

PB6DDR 01

Pin function TIOCA5 output PB6 input PB6 output

TIOCA5 input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

Table 9.32 PB5 Pin Function

TPU channel 4 setting*Output Input or Initial Value

PB5DDR 01

Pin function TIOCB4 output PB5 input PB5 output

TIOCB4 input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

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Table 9.33 PB4 Pin Function

TPU channel 4 setting*Output Input or Initial Value

PB4DDR 01

Pin function TIOCA4 output PB4 input PB4 output

TIOCA4 input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

Table 9.34 PB3 Pin Function

TPU channel 3 setting*Output Input or Initial Value

PB3DDR 01

Pin function TIOCD3 output PB3 input PB3 output

TIOCD3 input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

Table 9.35 PB2 Pin Function

TPU channel 3 setting*Output Input or Initial Value

PB2DDR 01

Pin function TIOCC3 output PB2 input PB2 output

TIOCC3 input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

Table 9.36 PB1 Pin Function

TPU channel 3 setting*Output Input or Initial Value

PB1DDR 01

Pin function TIOCB3 output PB1 input PB1 output

TIOCB3 input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

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Table 9.37 PB0 Pin Function

TPU channel 3 setting*Output Input or Initial Value

PB0DDR 01

Pin function TIOCA3 output PB0 input PB0 output

TIOCA3 input

Note: *For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse

Unit (TPU ).

9.8 Port C

Port C is an 8-bit I/O port that also has other functions. Port C has the following registers.

• Port C data direction register (PCDDR)

• Port C data register (PCDR)

• Port C register (PORTC)

• Port C pull-up MOS control register (PCPCR)

• Port C open-drain control register (PCODR)

9.8.1 Port C Data Direction Register (PCDDR)

PCDDR is an 8-bit write-only register, the individual bits of which specify whether the pins of

port C are used for input or output.

Bit Bit Name Initial Value R/W Description

7 PC7DDR 0 W

6 PC6DDR 0 W

5 PC5DDR 0 W

4 PC4DDR 0 W

3 PC3DDR 0 W

2 PC2DDR 0 W

1 PC1DDR 0 W

0 PC0DDR 0 W

When a pin is specified as a general purpose I/O

port, setting these bits to 1 makes the corresponding

port 1 pin an output pin. Clearing these bits to 0

makes the pin an input pin.

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9.8.2 Port C Data Register (PCDR)

PCDR is an 8-bit readable/writable register that stores output data for the port C pins.

Bit Bit Name Initial Value R/W Description

7 PC7DR 0 R/W

6 PC6DR 0 R/W

5 PC5DR 0 R/W

4 PC4DR 0 R/W

3 PC3DR 0 R/W

2 PC2DR 0 R/W

1 PC1DR 0 R/W

0 PC0DR 0 R/W

Output data for a pin is stored when the pin is

specified as a general purpose I/O port.

9.8.3 Port C Register (PORTC)

PORTC is an 8-bit read-only register that shows port C pin states.

Bit Bit Name Initial Value R/W Description

7PC7 0 R

6PC6 0 R

5PC5 0 R

4PC4 0 R

3PC3 0 R

2PC2 0 R

1PC1 0 R

0PC0 0 R

If a port C read is performed while PCDDR bits are

set to 1, the PCDR values are read. If a port C read

is performed while PCDDR bits are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins PC7 to PC0.

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9.8.4 Port C Pull-Up MOS Control Register (PCPCR)

PCPCR is an 8-bit readable/writable register that controls the on/off state of input pull-up MOS of

port C.

Bit Bit Name Initial Value R/W Description

7 PC7PCR 0 R/W

6 PC6PCR 0 R/W

5 PC5PCR 0 R/W

4 PC4PCR 0 R/W

3 PC3PCR 0 R/W

2 PC2PCR 0 R/W

1 PC1PCR 0 R/W

0 PC0PCR 0 R/W

When a pin is specified as an input port, setting the

corresponding bit to 1 turns on the input pull-up MOS

for that pin.

9.8.5 Port C Open-Drain Control Register (PCODR)

PCODR is an 8-bit readable/writable register that specifies an output type of port C.

Bit Bit Name Initial Value R/W Description

7 PC7ODR 0 R/W

6 PC6ODR 0 R/W

5 PC5ODR 0 R/W

4 PC4ODR 0 R/W

3 PC3ODR 0 R/W

2 PC2ODR 0 R/W

1 PC1ODR 0 R/W

0 PC0ODR 0 R/W

When a pin is specified as an output port, setting the

corresponding bits to 1 specifies pin output as open-

drain and the input pull-up MOS to the off state.

Clearing these bits to 0 specifies push-pull output.

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9.8.6 Pin Functions

Port C pins also function as SSU_1 and SSU_0 I/O pins. The correspondence between the register

specification and the pin functions is shown below.

Table 9.38 PC7 Pin Function

CSS1 0 1

CSS0 0 1 0 1

PC7DDR 0 1 

Pin function PC7 input PC7 output

SCS1

input

SCS1

input/output

auto switch

SCS1

output

Table 9.39 PC6 Pin Function

MSS 0 1

SCKS 0 1 1 0

PC6DDR 0 1 

Pin function PC6 input PC6 output SSCK1 input SSCK1 output Setting

prohibited

Table 9.40 PC5 Pin Function

MSS 0 1

BIDE 0 1 0 1

RE 01

TE 0 1 

PC5DDR 0 1 010101

SCS1

input 01 

Pin functi on PC5

input PC5

output SSI1

Hi-Z PC5

input PC5

output PC5

input PC5

output SSI1

input PC5

output

Section 9 I/O Ports

Rev. 3.00 Oct 04, 2005 page 158 of 598

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Table 9.41 PC4 Pin Function

MSS 0 1 01

BIDE 0 1

RE 0 1 01 0

TE 01001 1

PC4DDR 0 1 0101 

SCS1

input 01

function PC4

input PC4

output SSO1

input PC4

output SSO1

output PC4

input PC4

output SSO1

input Setting

pro-

hibited

SSO1

output SSO1

Hi-Z SSO1

output

Table 9.42 PC3 Pin Function

CSS1 0 1

CSS0 0 1 0 1

PC3DDR 0 1 

Pin function PC3 input PC3 output

SCS0

input

SCS0

input/output

auto switch

SCS0

output

Table 9.43 PC2 Pin Function

MSS 0 1

SCKS 0 1 1 0

PC2DDR 0 1 

Pin function PC2 input PC2 output SSCK0 input SSCK0 output Setting

prohibited

Section 9 I/O Ports

Rev. 3.00 Oct 04, 2005 page 159 of 598

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Table 9.44 PC1 Pin Function

MSS 0 1

BIDE 0 1 0 1

RE 01

TE 0 1 

PC1DDR 0 1 010101

SCS0

input 01 

Pin functi on PC1

input PC1

output SSI0

Hi-Z PC1

input PC1

output PC1

input PC1

output SSI0

input PC1

output

Table 9.45 PC0 Pin Function

MSS 0 1 01

BIDE 0 1

RE 0 1 01 0

TE 01001 1

PC0DDR 0 1 0101 

SCS0

input 01

Pin functi on PC0

input PC0

output SSO0

input PC0

output SSO0

output PC0

input PC0

output SSO0

input Setting

pro-

hibited

SSO0

output SSO0

Hi-Z SSO0

output

Section 9 I/O Ports

Rev. 3.00 Oct 04, 2005 page 160 of 598

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9.9 Port D

Port D is an 8-bit I/O port that also functions as the realtime input port pins.

The realtime input port stores the pin states of port D in PDRTIDR using the

IRQ3

pin as the

trigger input. The falling, rising, or both edges of the

IRQ3

pin can be used as a trigger timing.

Port D has the following registers.

• Port D data direction register (PDDDR)

• Port D data register (PDDR)

• Port D register (PORTD)

• Port D pull-up MOS control register (PDPCR)

• Port D realtime input data register (PDRTIDR)

9.9.1 Port D Data Direction Register (PDDDR)

PDDDR is an 8-bit write-only register, the individual bits of which specify whether the pins of

port D are used for input or output.

Bit Bit Name Initial Value R/W Description

7 PD7DDR 0 W

6 PD6DDR 0 W

5 PD5DDR 0 W

4 PD4DDR 0 W

3 PD3DDR 0 W

2 PD2DDR 0 W

1 PD1DDR 0 W

0 PD0DDR 0 W

When a pin is specified as a general purpose I/O

port, setting these bits to 1 makes the corresponding

port 1 pin an output pin. Clearing these bits to 0

makes the pin an input pin.

Section 9 I/O Ports

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9.9.2 Port D Data Register (PDDR)

PDDR is an 8-bit readable/writable register that stores output data for the port D pins.

Bit Bit Name Initial Value R/W Description

7 PD7DR 0 R/W

6 PD6DR 0 R/W

5 PD5DR 0 R/W

4 PD4DR 0 R/W

3 PD3DR 0 R/W

2 PD2DR 0 R/W

1 PD1DR 0 R/W

0 PD0DR 0 R/W

Output data for a pin is stored when the pin is

specified as a general purpose I/O port.

9.9.3 Port D Register (PORTD)

PORTD is an 8-bit read-only register that shows port D pin states.

Bit Bit Name Initial Value R/W Description

7 PD7 Undefined*R

6 PD6 Undefined*R

5 PD5 Undefined*R

4 PD4 Undefined*R

3 PD3 Undefined*R

2 PD2 Undefined*R

1 PD1 Undefined*R

0 PD0 Undefined*R

If a port D read is performed while PDDDR bits are

set to 1, the PDDR values are read. If a port D read

is performed while PDDDR bits are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins PD7 to PD0.

Section 9 I/O Ports

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9.9.4 Port D Pull-Up MOS Control Register (PDPCR)

PDPCR is an 8-bit readable/writable register that controls on/off states of the input pull-up MOS

of port D.

Bit Bit Name Initial Value R/W Description

7 PD7PCR 0 R/W

6 PD6PCR 0 R/W

5 PD5PCR 0 R/W

4 PD4PCR 0 R/W

3 PD3PCR 0 R/W

2 PD2PCR 0 R/W

1 PD1PCR 0 R/W

0 PD0PCR 0 R/W

When the pin is in its input state, the input pull-up

MOS of the i nput pin is on when the corresponding

bits are set to 1.

9.9.5 Port D RealTime Input Data Register (PDRTIDR)

The realtime input port stores the pin states of port D in PDRTIDR using the

IRQ3

pin as the

trigger input. The falling, rising, or both edges of the

IRQ3

pin can be specified as a trigger timing

by bits 7 and 6 in the IRQ sense control register L (ISCRL). For details of this setting, see section

5.3.3, IRQ Sense Control Registers H and L (ISCRH, ISCRL).

Bit Bit Name Initial Value R/W Description

7 PDRTIDR7 0 R/W

6 PDRTIDR6 0 R/W

5 PDRTIDR5 0 R/W

4 PDRTIDR4 0 R/W

3 PDRTIDR3 0 R/W

2 PDRTIDR2 0 R/W

1 PDRTIDR1 0 R/W

0 PDRTIDR0 0 R/W

Stores pin states using the

IRQ3

pin as a trigger

input.

Section 9 I/O Ports

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9.10 Port F

Port F is an 8-bit I/O port that also has other functions. Port F has the following registers.

• Port F data direction register (PFDDR)

• Port F data register (PFDR)

• Port F register (PORTF)

9.10.1 Port F Data Direction Register (PFDDR)

PFDDR is an 8-bit write-only register, the individual bits of which specify whether the pins of port

F are used for input or output.

Bit Bit Name Initial Value R/W Description

7 PF7DDR 0 W When a pin is specified as a general purpose I/O

port, setting this bit to 1 makes the PF7 pin a φ

output pin. Clearing thi s bit to 0 makes the pin an

input pin.

6 PF6DDR 0 W

5 PF5DDR 0 W

4 PF4DDR 0 W

3 PF3DDR 0 W

2 PF2DDR 0 W

1 PF1DDR 0 W

0 PF0DDR 0 W

When a pin is specified as a general purpose I/O

port, setting these bits to 1 makes the corresponding

port F pin an output pin. Clearing these bits to 0

makes the pin an input pin.

Section 9 I/O Ports

Rev. 3.00 Oct 04, 2005 page 164 of 598

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9.10.2 Port F Data Register (PFDR)

PFDR is an 8-bit readable/writable register that stores output data for the port F pins.

Bit Bit Name Initial Value R/W Description

70R/WReserved

The write value should al ways be 0.

6PF6DR 0 R/W

5PF5DR 0 R/W

4PF4DR 0 R/W

3PF3DR 0 R/W

2PF2DR 0 R/W

1PF1DR 0 R/W

0PF0DR 0 R/W

Output data for a pin is stored when the pin is

specified as a general purpose I/O port.

9.10.3 Port F Regist er ( PORTF )

PORTF is an 8-bit read-only register that shows port F pin states.

PORTF cannot be modified.

Bit Bit Name Initial Value R/W Description

7 PF7 Undefined*R

6 PF6 Undefined*R

5 PF5 Undefined*R

4 PF4 Undefined*R

3 PF3 Undefined*R

2 PF2 Undefined*R

1 PF1 Undefined*R

0 PF0 Undefined*R

If a port F read is performed while PFDDR bits are

set to 1, the PFDR values are read. If a port F read is

performed while PFDDR bits are cleared to 0, the pin

states are read.

Note: *Determined by the states of pins PF7 to PF0.

Section 9 I/O Ports

Rev. 3.00 Oct 04, 2005 page 165 of 598

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9.10.4 Pin Functions

Port F is an 8-bit I/O port. Port F pins also function as external interrupt input,

IRQ3

and

IRQ2

A/D trigger input (

ADTRG

), and system clo ck output (φ).

Table 9.46 PF7 Pin Function

PF7DDR 0 1

Pin function PF7 input φ output

Table 9.47 PF6 Pin Function

PF6DDR 0 1

Pin function PF6 input PF6 output

Table 9.48 PF5 Pin Function

PF5DDR 0 1

Pin function PF5 input PF5 output

Table 9.49 PF4 Pin Function

PF4DDR 0 1

Pin function PF4 input PF4 output

Table 9.50 PF3 Pin Function

PF3DDR 0 1

Pin function PF3 input PF3 output

ADTRG

input*1

IRQ3

input*2

Notes: 1.

ADTRG

input when TRGS0 = TRGS1 = 1.

2. When used as an external interrupt input pin, do not use as an I/O pin for another

function. This pin also functions as the trigger input for the realtime input port.

Section 9 I/O Ports

Rev. 3.00 Oct 04, 2005 page 166 of 598

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Table 9.51 PF2 Pin Function

PF2DDR 0 1

Pin function PF2 input PF2 output

Table 9.52 PF1 Pin Function

PF1DDR 0 1

Pin function PF1 input PF1 output

Table 9.53 PF0 Pin Function

PF0DDR 0 1

Pin function PF0 input PF0 output

IRQ2

input*

Note: *When used as an external interrupt input pin, do not use as an I/O pin for another

function.

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 167 of 598

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Section 10 1 6-Bit T i mer Pul se Unit (TPU)

This LSI has an on-chip 16-bit timer pulse unit (TPU) comprised of six 16-bit timer channels.

The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure

10.1, respec tiv el y .

10.1 Features

• Maximum 16-pulse input/output

• Selection of 8 counter input clocks for each channel

• The following operations can be set for each channel:

 Waveform output at compare match

 Input capture function

 Counter clear ope ra tion

 Synchronous operation:

Multiple timer counters (TCNT) can be written to simultaneously

Simultaneous clearing by compare match and input capture is possible

 A maximum 15-phase PWM output is possible in combination with synchronous operation

• Buff er operati on se ttabl e for channel s 0 and 3

• Phase counting mode settable independently for each of channels 1, 2, 4, and 5

• Casca ded ope ratio n

• Fast access via internal 16-bit bus

• 26 interrupt sources

• Automatic transfer of register data

• Programmable pulse generator (PPG) output trigger can be generated

• A/D converter conversion start trigger can be generated

• Module stop mode can be set

TIMTPU0A_000020020300

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 168 of 598

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Table 10.1 TPU Functions

Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

Count cl ock φ/1

φ/4

φ/16

φ/64

TCLKA

TCLKB

TCLKC

TCLKD

φ/1

φ/4

φ/16

φ/64

φ/256

TCLKA

TCLKB

φ/1

φ/4

φ/16

φ/64

φ/1024

TCLKA

TCLKB

TCLKC

φ/1

φ/4

φ/16

φ/64

φ/256

φ/1024

φ/4096

TCLKA

φ/1

φ/4

φ/16

φ/64

φ/1024

TCLKA

TCLKC

φ/1

φ/4

φ/16

φ/64

φ/256

TCLKA

TCLKC

TCLKD

General registe rs

(TGR) TGRA_0

TGRB_0 TGRA_1

TGRB_1 TGRA_2

TGRB_2 TGRA_3

TGRB_3 TGRA_4

TGRB_4 TGRA_5

TGRB_5

General registers/

buffer registe rs TGRC_0

TGRD_0 TGRC_3

TGRD_3 

I/O pins TIOCA0

TIOCB0

TIOCC0

TIOCD0

TIOCA1

TIOCB1 TIOCA2

TIOCB2 TIOCA3

TIOCB3

TIOCC3

TIOCD3

TIOCA4

TIOCB4 TIOCA5

TIOCB5

Counter clear

function TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

Compare 0 output

match 1 output

output Toggle

output

Input capture

function

Synchronous

operation

PWM mode

Phase counting

mode  

Buffer operation  

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 169 of 598

REJ09B0155-0300

Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

DTC

activation TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

A/D

converter

trigger

TGRA_0

compare

match or

input capture

TGRA_1

compare

match or

input capture

TGRA_2

compare

match or

input capture

TGRA_3

compare

match or

input capture

TGRA_4

compare

match or

input capture

TGRA_5

compare

match or

input capture

PPG

trigger TGRA_0/

TGRB_0

compare

match or

input capture

TGRA_1/

TGRB_1

compare

match or

input capture

TGRA_2/

TGRB_2

compare

match or

input capture

TGRA_3/

TGRB_3

compare

match or

input capture



Interrupt

sources 5 sources

• Compare

match or

input

capture 0A

• Compare

match or

input

capture 0B

• Compare

match or

input

capture 0C

• Compare

match or

input

capture 0D

• Overflow

4 sources

• Compare

match or

input

capture 1A

• Compare

match or

input

capture 1B

• Overflow

• Underflow

4 sources

• Compare

match or

input

capture 2A

• Compare

match or

input

capture 2B

• Overflow

• Underflow

5 sources

• Compare

match or

input

capture 3A

• Compare

match or

input

capture 3B

• Compare

match or

input

capture 3C

• Compare

match or

input

capture 3D

• Overflow

4 sources

• Compare

match or

input

capture 4A

• Compare

match or

input

capture 4B

• Overflow

• Underflow

4 sources

• Compare

match or

input

capture 5A

• Compare

match or

input

capture 5B

• Overflow

• Underflow

Legend:

: Possible

: Not possible

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 170 of 598

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Channel 3

TMDR

TIORL

TSR

TCR

TIORH

TIER

TGRA

TCNT

TGRB

TGRC

TGRD

Channel 4

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Channel 5

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Control logic for channels 3 to 5

Channel 2

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

TGRC

Channel 1

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Channel 0

Control logic for channels 0 to 2

TGRA

TCNT

TGRB

TGRD

Bus

interface

Common

TSYR

Control logic

TSTR

TIOCA3

TIOCB3

TIOCC3

TIOCD3

TIOCA4

TIOCB4

TIOCA5

TIOCB5

φ/1

φ/4

φ/16

φ/64

φ/256

φ/1024

φ/4096

TCLKA

TCLKB

TCLKC

TCLKD

Legend:

TSTR:

TSYR:

TCR:

TMDR:

Timer start register

Timer synchro register

Timer control register

Timer mode register

Timer I/O control registers (H, L)

Timer interrupt enable register

Timer status register

Timer general registers (A, B, C, D)

TIOCA0

TIOCB0

TIOCC0

TIOCD0

TIOCA1

TIOCB1

TIOCA2

TIOCB2

Interrupt request signals

Channel 3:

Channel 4:

Channel 5:

Interrupt request signals

Channel 3:

Channel 4:

Channel 5:

Internal data bus

PPG output trigger signal

A/D converter conversion start signal

Module data bus

TGIA_3

TGIB_3

TGIC_3

TGID_3

TCIV_3

TGIA_4

TGIB_4

TCIV_4

TCIU_4

TGIA_5

TGIB_5

TCIV_5

TCIU_5

TGIA_0

TGIB_0

TGIC_0

TGID_0

TCIV_0

TGIA_1

TGIB_1

TCIV_1

TCIU_1

TGIA_2

TGIB_2

TCIV_2

TCIU_2

TMDR

TSR

TCR

TIORH

TIER TIORL

Input/output pins

Channel 3:

Channel 4:

Channel 5:

Input/output pins

Channel 0:

Channel 1:

Channel 2:

Clock input

Internal clock:

External clock:

TIOR (H, L):

TIER:

TSR:

TGR (A, B, C, D):

Figure 10.1 Block Diagram of TPU

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 171 of 598

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10.2 Input/O utput Pins

Table 10.2 TPU Pins

Channel Symbol I/O Function

All TCLKA Input External clock A input pin

(Channel 1 and 5 phase counting mode A phase input)

TCLKB Input External clock B input pin

(Channel 1 and 5 phase counting mode B phase input)

TCLKC Input External clock C input pin

(Channel 2 and 4 phase counting mode A phase input)

TCLKD Input External clock D input pin

(Channel 2 and 4 phase counting mode B phase input)

0 TIOCA0 I/O TGRA_0 input capture input/output compare output/PWM output pin

TIOCB0 I/O TGRB_0 input capture input/output compare output/PWM output pin

TIOCC0 I/O TGRC_0 input capture input/output compare output/PWM output pin

TIOCD0 I/O TGRD_0 input capture input/output compare output/PWM output pin

1 TIOCA1 I/O TGRA_1 input capture input/output compare output/PWM output pin

TIOCB1 I/O TGRB_1 input capture input/output compare output/PWM output pin

2 TIOCA2 I/O TGRA_2 input capture input/output compare output/PWM output pin

TIOCB2 I/O TGRB_2 input capture input/output compare output/PWM output pin

3 TIOCA3 I/O TGRA_3 input capture input/output compare output/PWM output pin

TIOCB3 I/O TGRB_3 input capture input/output compare output/PWM output pin

TIOCC3 I/O TGRC_3 input capture input/output compare output/PWM output pin

TIOCD3 I/O TGRD_3 input capture input/output compare output/PWM output pin

4 TIOCA4 I/O TGRA_4 input capture input/output compare output/PWM output pin

TIOCB4 I/O TGRB_4 input capture input/output compare output/PWM output pin

5 TIOCA5 I/O TGRA_5 input capture input/output compare output/PWM output pin

TIOCB5 I/O TGRB_5 input capture input/output compare output/PWM output pin

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 172 of 598

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10.3 Register Descriptions

The TPU has the following registers. To distinguish registers in each channel, an underscore and

the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as

TCR_0.

• Tim er control reg i ste r_0 ( TCR _0)

• Timer mo de reg iste r_0 (TMDR _ 0)

• Tim er I/O contro l regi ste r H_0 ( TIOR H _0 )

• Timer I/O control register L_0 (TIORL_0)

• Timer in terru pt enable regi ste r_0 (TIER _0)

• Timer status register_0 (TSR_0)

• Timer coun ter_0 ( TCN T_0)

• Timer general register A_0 (TGRA_0)

• Timer general register B_0 (TGRB_0)

• Timer general register C_0 (TGRC_0)

• Timer general register D_0 (TGRD_0)

• Tim er control reg i ste r_1 ( TCR _1)

• Timer mo de reg iste r_1 (TMDR _ 1)

• Tim er I/O contro l regi ste r _1 (TIO R_1)

• Timer in terru pt enable regi ste r_1 (TIER _1)

• Timer status register_1 (TSR_1)

• Timer coun ter_1 ( TCN T_1)

• Timer general register A_1 (TGRA_1)

• Timer general register B_1 (TGRB_1)

• Tim er control reg i ste r_2 ( TCR _2)

• Timer mo de reg iste r_2 (TMDR _ 2)

• Tim er I/O contro l regi ste r_2 ( TIO R_2)

• Timer in terru pt enable regi ste r_2 (TIER _2)

• Timer status register_2 (TSR_2)

• Timer coun ter_2 ( TCN T_2)

• Timer general register A_2 (TGRA_2)

• Timer general register B_2 (TGRB_2)

• Tim er control reg i ste r_3 ( TCR _3)

• Timer mo de reg iste r_3 (TMDR _ 3)

• Tim er I/O contro l regi ste r H_3 ( TIOR H _3 )

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 173 of 598

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• Timer I/O control register L_3 (TIORL_3)

• Timer in terru pt enable regi ste r_3 (TIER _3)

• Timer status register_3 (TSR_3)

• Timer coun ter_3 ( TCN T_3)

• Timer general register A_3 (TGRA_3)

• Timer general register B_3 (TGRB_3)

• Timer general register C_3 (TGRC_3)

• Timer general register D_3 (TGRD_3)

• Tim er control reg i ste r_4 ( TCR _4)

• Timer mo de reg iste r_4 (TMDR _ 4)

• Tim er I/O contro l regi ste r _4 (TIO R_4)

• Timer in terru pt enable regi ste r_4 (TIER _4)

• Timer status register_4 (TSR_4)

• Timer coun ter_4 ( TCN T_4)

• Timer general register A_4 (TGRA_4)

• Timer general register B_4 (TGRB_4)

• Tim er control reg i ste r_5 ( TCR _5)

• Timer mo de reg iste r_5 (TMDR _ 5)

• Tim er I/O contro l regi ste r_5 ( TIO R_5)

• Timer in terru pt enable regi ste r_5 (TIER _5)

• Timer status register_5 (TSR_5)

• Timer coun ter_5 ( TCN T_5)

• Timer general register A_5 (TGRA_5)

• Timer general register B_5 (TGRB_5)

Common Registers

• Tim er st ar t reg i ster ( TS TR )

• Tim er synchr o regi ster ( TSY R)

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 174 of 598

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10.3.1 Timer Control Register (TCR)

The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each

channel. The TPU has a total of six TCR registers, one for each channel (channels 5 to 0). TCR

Bit Bit Name Initial value R/W Description

CCLR2

CCLR1

CCLR0

R/W

Counter Clear 2 to 0

These bits select the TCNT counter clearing source.

See tables 10.3 and 10.4 for details.

3CKEG1

CKEG0 0

0R/W

R/W Clock Edge 1 and 0

These bits select the i nput clock edge. W hen the

input clock is counted using both edges, the input

clock per iod is halved (e.g. φ/4 both edges = φ/2

rising edge). If phase counting mode is used on

channels 1, 2, 4, and 5, this setting is ignored and

the phase counting mode setting has priority. Internal

clock edge selection is valid when the input clock is

φ/4 or slower. This setting is ignored if the input clock

is φ/1, or when overflow/underflow of another

channel is select ed.

00: Count at rising edge

01: Count at falling edge

1×: Count at both edges

Legend:

×: Don’t care

TPSC2

TPSC1

TPSC0

R/W

Time Prescaler 2 to 0

These bits select the TCNT counter clock. The clock

source can be selected independently for each

channel. See tables 10.5 to 10.10 for details.

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 175 of 598

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Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3)

Channel Bit 7

CCLR2 Bit 6

CCLR1 Bit 5

CCLR0 Description

0, 3 0 0 0 TCNT clearing disabled

1 TCNT cleared by TGRA compare match/input

capture

10TCNT cleared by TGRB compare match/input

capture

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*1

1 0 0 TCNT clearing disabled

1 TCNT cleared by TGRC compare match/input

capture*2

10TCNT cleared by TGRD compare match/input

capture*2

1TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*1

Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.

2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the

buffer register setting has priority, and compare match/input capture does not occur.

Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)

Channel Bit 7

Reserved*

Bit 6

CCLR1 Bit 5

CCLR0 Description

1, 2, 4, 5 0 0 0 TCNT clearing disabled

1 TCNT cleared by TGRA compare match/input

capture

1 0 TCNT cleared by TGRB compare match/in put

capture

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*1

Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.

2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be

modified.

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 176 of 598

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Table 10.5 TPSC2 to TPSC0 (Channel 0)

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

0 0 0 0 Internal clock: counts on φ/1

1 Internal clock: counts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: counts on φ/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 External clock: counts on TCLKC pin input

1 External clock: counts on TCLKD pin input

Table 10.6 TPSC2 to TPSC0 (Channel 1)

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

1 0 0 0 Internal clock: counts on φ/1

1 Internal clock: counts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: counts on φ/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 Internal clock: counts on φ/256

1 Counts on TCNT2 overflow/underflow

Note: This setting is ignored when channel 1 is in phase counting mode.

Section 10 16-Bit Timer Pulse Unit (TPU)

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Table 10.7 TPSC2 to TPSC0 (Channel 2)

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

2 0 0 0 Internal clock: counts on φ/1

1 Internal clock: counts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: counts on φ/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 External clock: counts on TCLKC pin input

1 Internal clock: counts on φ/1024

Note: This setting is ignored when channel 2 is in phase counting mode.

Table 10.8 TPSC2 to TPSC0 (Channel 3)

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

3 0 0 0 Internal clock: counts on φ/1

1 Internal clock: counts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: counts on φ/64

1 0 0 External clock: counts on TCLKA pin input

1 Internal clock: counts on φ/1024

1 0 Internal clock: counts on φ/256

1 Internal clock: counts on φ/4096

Section 10 16-Bit Timer Pulse Unit (TPU)

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Table 10.9 TPSC2 to TPSC0 (Channel 4)

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

4 0 0 0 Internal clock: counts on φ/1

1 Internal clock: counts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: counts on φ/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKC pin input

1 0 Internal clock: counts on φ/1024

1 Counts on TCNT5 overflow/underflow

Note: This setting is ignored when channel 4 is in phase counting mode.

Table 10.10 TPSC2 to TPSC0 (Channel 5)

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

5 0 0 0 Internal clock: counts on φ/1

1 Internal clock: counts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: counts on φ/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKC pin input

1 0 Internal clock: counts on φ/256

1 External clock: counts on TCLKD pin input

Note: This setting is ignored when channel 5 is in phase counting mode.

Section 10 16-Bit Timer Pulse Unit (TPU)

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10.3.2 Timer Mode R egist er (T MDR)

The TMDR reg iste rs are 8-bi t readabl e/w ri table reg iste rs that are use d to set the opera ting mode of

each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings

should be changed only when TCNT operation is stopped.

Bit Bit Name Initial value R/W Description

7, 6 All 1 Reserved

These bits are always read as 1 and cannot be

modified.

5 BFB 0 R/W Buffer Operation B

Specifies whether TGRB is to operate in the normal

way, or TGRB and TGRD are to be used together for

buffer operation. When TGRD is used as a buffer

generated.

In channels 1, 2, 4, and 5, which have no TGRD, bit

5 is reserved. It is always read as 0 and cannot be

modified.

0: TGRB operates normally

1: TGRB and TGRD used together for buffer

operation

4 BFA 0 R/W Buffer Operation A

Specifies whether TGRA is to operate in the normal

way, or TGRA and TGRC are to be used together for

buffer operation. When TGRC is used as a buffer

generated.

In channels 1, 2, 4, and 5, which have no TGRC, bit

4 is reserved. It is always read as 0 and cannot be

modified.

0: TGRA operates normally

1: TGRA and TGRC used together for buffer

operation

MD3

MD2

MD1

MD0

R/W

Modes 3 to 0

These bits are used to set the timer operating mode.

MD3 is a reserved bit. In a write, it should always be

written with 0. See table 10.11 for details.

Section 10 16-Bit Timer Pulse Unit (TPU)

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Table 10.11 MD3 to MD0

Bit 3

MD3*1Bit 2

MD2*2Bit 1

MD1 Bit 0

MD0 Description

0 0 0 0 Normal operation

1 Reserved

1 0 PWM mode 1

1 PWM mode 2

1 0 0 Phase counting mode 1

1 Phase counting mode 2

1 0 Phase counting mode 3

1 Phase counting mode 4

1×××

Legend:

×: Don’t care

Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.

2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always

be written to MD2.

Section 10 16-Bit Timer Pulse Unit (TPU)

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10.3.3 Timer I/O Control Register (TIOR)

The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The TPU

has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5.

Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is

valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM

mode 2, the output at the point at which the counter is cleared to 0 is specified.

When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register

operates as a buffer register.

• TIORH_5, TIOR _4, TIOR_3, TIORH_2, TIOR _1, TIOR_0

Bit Bit Name Initial

value R/W Description

IOB3

IOB2

IOB1

IOB0

R/W

I/O Control B3 to B0

Specify the function of TGRB.

IOA3

IOA2

IOA1

IOA0

R/W

I/O Control A3 to A0

Specify the function of TGRA.

• TIORL_3, TIORL_0

Bit Bit Name Initial

value R/W Description

IOD3

IOD2

IOD1

IOD0

R/W

I/O Control D3 to D0

Specify the function of TGRD.

IOC3

IOC2

IOC1

IOC0

R/W

I/O Control C3 to C0

Specify the function of TGRC.

Section 10 16-Bit Timer Pulse Unit (TPU)

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Table 10.12 TIORH_0 (Chann el 0)

Description

Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 TGRB_0

Function TIOCB0 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1 0 0 0 Capture input source is the TIOCB0 pin

Input capture at rising edge

1 Capture input source is the TIOCB0 pin

Input capture at falling edge

1×Capture input source is the TIOCB0 pin

Input capture at both edges

1××

Input

capture

Capture input source is channel 1/count clock

Input capture at TCNT_1 count-up/count-down*

Legend:

×: Don’t care

Note: *When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/ 1 is used as the TCNT_1

count clock, this setting is invalid and input capture is not generated.

Section 10 16-Bit Timer Pulse Unit (TPU)

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Table 10.13 TIORL_0 (Chann el 0)

Description

Bit 7

IOD3 Bit 6

IOD2 Bit 5

IOD1 Bit 4

IOD0 TGRD_0

Function TIOCD0 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1 0 0 0 Capture input source is the TIOCD0 pin

Input capture at rising edge

1 Capture input source is the TIOCD0 pin

Input capture at falling edge

1×Capture input source is the TIOCD0 pin

Input capture at both edges

1××

Input

capture

Capture input source is channel 1/count clock

Input capture at TCNT_1 count-up/count-down*1

Legend:

×: Don’t care

Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1

count clock, this setting is invalid and input capture is not generated.

2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this

setting is invalid and inpu t capture/output com pare is not generated.

Section 10 16-Bit Timer Pulse Unit (TPU)

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Table 10.14 TIOR_1 (Channel 1)

Description

Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 TGRB_1

Function TIOCB1 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1 0 0 0 Capture input source is the TIOCB1 pin

Input capture at rising edge

1 Capture input source is the TIOCB1 pin

Input capture at falling edge

1×Capture input source is the TIOCB1 pin

Input capture at both edges

1××

Input

capture

TGRC_0 compare match/ input capture

Input capture at generation of TGRC_0 compare

match/input capture

Legend:

×: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU)

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Table 10.15 TIOR_2 (Channel 2)

Description

Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 TGRB_2

Function TIOCB2 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1×0 0 Capture input source is the TIOCB2 pin

Input capture at rising edge

1 Capture input source is the TIOCB2 pin

Input capture at falling edge

1×

Input

capture

Capture input source is the TIOCB2 pin

Input capture at both edges

Legend:

×: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 186 of 598

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Table 10.16 TIORH_3 (Chann el 3)

Description

Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 TGRB_3

Function TIOCB3 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1 0 0 0 Capture input source is the TIOCB3 pin

Input capture at rising edge

1 Capture input source is the TIOCB3 pin

Input capture at falling edge

1×Capture input source is the TIOCB3 pin

Input capture at both edges

1××

Input

capture

Capture input source is channel 4/count clock

Input capture at TCNT_4 count-up/count-down*

Legend:

×: Don’t care

Note: *When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/ 1 is used as the TCNT_4

count clock, this setting is invalid and input capture is not generated.

Section 10 16-Bit Timer Pulse Unit (TPU)

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Table 10.17 TIORL_3 (Chann el 3)

Description

Bit 7

IOD3 Bit 6

IOD2 Bit 5

IOD1 Bit 4

IOD0 TGRD_3

Function TIOCD3 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1 0 0 0 Capture input source is the TIOCD3 pin

Input capture at rising edge

1 Capture input source is the TIOCD3 pin

Input capture at falling edge

1×Capture input source is the TIOCD3 pin

Input capture at both edges

1××

Input

capture

Capture input source is channel 4/count clock

Input capture at TCNT_4 count-up/count-down*1

Legend:

×: Don’t care

Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4

count clock, this setting is invalid and input capture is not generated.

2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this

setting is invalid and inpu t capture/output com pare is not generated.

Section 10 16-Bit Timer Pulse Unit (TPU)

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Table 10.18 TIOR_4 (Channel 4)

Description

Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 TGRB_4

Function TIOCB4 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1 0 0 0 Capture input source is the TIOCB4 pin

Input capture at rising edge

1 Capture input source is the TIOCB4 pin

Input capture at falling edge

1×Capture input source is the TIOCB4 pin

Input capture at both edges

1××

Input

capture

Capture input source is TGRC_3 compare

match/input capture

Input capture at generation of TGRC_3 compare

match/input capture

Legend:

×: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 189 of 598

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Table 10.19 TIOR_5 (Channel 5)

Description

Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 TGRB_5

Function TIOCB5 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1×0 0 Capture input source is the TIOCB5 pin

Input capture at rising edge

1 Capture input source is the TIOCB5 pin

Input capture at falling edge

1×

Input

capture

Capture input source is the TIOCB5 pin

Input capture at both edges

Legend:

×: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 190 of 598

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Table 10.20 TIORH_0 (Chann el 0)

Description

Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 TGRA_0

Function TIOCA0 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1 0 0 0 Capture input source is the TIOCA0 pin

Input capture at rising edge

1 Capture input source is the TIOCA0 pin

Input capture at falling edge

1×Capture input source is the TIOCA0 pin

Input capture at both edges

1××

Input

capture

Capture input source is channel 1/count clock

Input capture at TCNT_1 count-up/count-down

Legend:

×: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 191 of 598

REJ09B0155-0300

Table 10.21 TIORL_0 (Chann el 0)

Description

Bit 3

IOC3 Bit 2

IOC2 Bit 1

IOC1 Bit 0

IOC0 TGRC_0

Function TIOCC0 Pin Functio n

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1 0 0 0 Capture input source is the TIOCC0 pin

Input capture at rising edge

1 Capture input source is the TIOCC0 pin

Input capture at falling edge

1×Capture input source is the TIOCC0 pin

Input capture at both edges

1××

Input

capture

Capture input source is channel 1/count clock

Input capture at TCNT_1 count-up/count-down

Legend:

×: Don’t care

Note: *When the BFA bi t in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this

setting is invalid and inpu t capture/output com pare is not generated.

Section 10 16-Bit Timer Pulse Unit (TPU)

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REJ09B0155-0300

Table 10.22 TIOR_1 (Channel 1)

Description

Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 TGRA_1

Function TIOCA1 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1 0 0 0 Capture input source is the TIOCA1 pin

Input capture at rising edge

1 Capture input source is the TIOCA1 pin

Input capture at falling edge

1×Capture input source is the TIOCA1 pin

Input capture at both edges

1××

Input

capture

Capture input source is TGRA_0 compare

match/input capture

Input capture at generation of channel 0/TGRA_0

compare match/input capture

Legend:

×: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 193 of 598

REJ09B0155-0300

Table 10.23 TIOR_2 (Channel 2)

Description

Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 TGRA_2

Function TIOCA2 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1×0 0 Capture input source is the TIOCA2 pin

Input capture at rising edge

1 Capture input source is the TIOCA2 pin

Input capture at falling edge

1×

Input

capture

Capture input source is the TIOCA2 pin

Input capture at both edges

Legend:

×: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 194 of 598

REJ09B0155-0300

Table 10.24 TIORH_3 (Chann el 3)

Description

Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 TGRA_3

Function TIOCA3 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1 0 0 0 Capture input source is the TIOCA3 pin

Input capture at rising edge

1 Capture input source is the TIOCA3 pin

Input capture at falling edge

1×Capture input source is the TIOCA3 pin

Input capture at both edges

1××

Input

capture

Capture input source is channel 4/count clock

Input capture at TCNT_4 count-up/count-down

Legend:

×: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Oct 04, 2005 page 195 of 598

REJ09B0155-0300

Table 10.25 TIORL_3 (Chann el 3)

Description

Bit 3

IOC3 Bit 2

IOC2 Bit 1

IOC1 Bit 0

IOC0 TGRC_3

Function TIOCC3 Pin Functio n

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1 0 0 0 Capture input source is the TIOCC3 pin

Input capture at rising edge

1 Capture input source is the TIOCC3 pin

Input capture at falling edge

1×Capture input source is the TIOCC3 pin

Input capture at both edges

1××

Input

capture

Capture input source is channel 4/count clock

Input capture at TCNT_4 count-up/count-down

Legend:

×: Don’t care

Note: *When the BFA bi t in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this

setting is invalid and inpu t capture/output com pare is not generated.

Section 10 16-Bit Timer Pulse Unit (TPU)

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REJ09B0155-0300

Table 10.26 TIOR_4 (Channel 4)

Description

Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 TGRA_4

Function TIOCA4 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1 0 0 0 Capture input source is the TIOCA4 pin

Input capture at rising edge

1 Capture input source is the TIOCA4 pin

Input capture at falling edge

1×Capture input source is the TIOCA4 pin

Input capture at both edges

1××

Input

capture

Capture input source is TGRA_3 compare

match/input capture

Input capture at generation of TGRA_3 compare

match/input capture

Legend:

×: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU)

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Table 10.27 TIOR_5 (Channel 5)

Description

Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 TGRA_5

Function TIOCA5 Pin Function

0 0 0 0 Output disabled

1 Initial output is 0

0 output at compare match

1 0 Initial output is 0

1 output at compare match

1 Initial output is 0

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1

0 output at compare match

1 0 Initial output is 1

1 output at compare match

Output

compare

Initial output is 1

Toggle output at compare match

1×0 0 Capture input source is the TIOCA5 pin

Input capture at rising edge

1 Capture input source is the TIOCA5 pin

Input capture at falling edge

1×

Input

capture

Capture input source is the TIOCA5 pin

Input capture at both edges

Legend:

×: Don’t care

Section 10 16-Bit Timer Pulse Unit (TPU)

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10.3.4 Timer Interrupt Enable Register (TIER)

The TIER registers are 8-bit readable/writable registers that control enabling or disabling of

interrup t reque st s for each ch annel. Th e TPU has si x TIER reg i sters, one for ea ch ch ann el.

Bit Bit Name Initial value R/W Description

7 TTGE 0 R/W A/D Conversion Start Request Enable

Enables or disables generation of A/D conversion

start requests by TGRA input capture/compare

match.

0: A/D conversion start request generation disabled

1: A/D conversion start request generation enabled

61Reserved

This bi t is always read as 1 and cannot be modified.

5 TCIEU 0 R/W Underflow Interrupt Enable

Enables or disables interrupt requests (TCIU) by the

TCFU flag when the TCFU flag in TSR is set to 1 in

channels 1, 2, 4, and 5.

In channels 0 and 3, bit 5 i s reserved. It is always

read as 0 and cannot be modified.

0: Interrupt requests (TCIU) by TCFU disabled

1: Interrupt requests (TCIU) by TCFU enabled

4 TCIEV 0 R/W Overflow Interrupt Enable

Enables or disables interrupt requests (TCIV) by the

TCFV flag when the TCFV flag in TSR is set to 1.

0: Interrupt requests (TCIV) by TCFV disabled

1: Interrupt requests (TCIV) by TCFV enabled

3 TGIED 0 R/W T GR Interrupt Enable D

Enables or disables interrupt requests (TGID) by the

TGFD bit when the TGFD bit in TSR is set to 1 in

channels 0 and 3.

In channels 1, 2, 4, and 5, bit 3 is reserved. It is

always read as 0 and cannot be modifi ed.

0: Interrupt requests (TGID) by TGFD bit disabled

1: Interrupt requests (TGID) by TGFD bit enabled

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Bit Bit Name Initial value R/W Description

2 TGIEC 0 R/W T GR Interrupt Enable C

Enables or disables interrupt requests (TGIC) by the

TGFC bit when the TGFC bit in TSR is set to 1 in

channels 0 and 3.

In channels 1, 2, 4, and 5, bit 2 is reserved. It is

always read as 0 and cannot be modifi ed.

0: Interrupt requests (TGIC) by TGFC bit disabled

1: Interrupt requests (TGIC) by TGFC bit enabled

1 TGIEB 0 R/W TGR Interrupt Enable B

Enables or disables interrupt requests (TGIB) by the

TGFB bit when the TGFB bit in TSR is set to 1.

0: Interrupt requests (TGIB) by TGFB bit disabled

1: Interrupt requests (TGIB) by TGFB bit enabled

0 TGIEA 0 R/W TGR Interrupt Enable A

Enables or disables interrupt requests (TGIA) by the

TGFA bit when the TGFA bit in TSR is set to 1.

0: Interrupt requests (TGIA) by TGFA bit disabled

1: Interrupt requests (TGIA) by TGFA bit enabled

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10.3.5 Timer Status Register (TSR)

The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The

TPU has six TSR registers, one for each channel.

Bit Bit Name Initial value R/W Description

7 TCFD 1 R Count Direction Flag

Status flag that shows the direction in which TCNT

counts in channels 1, 2, 4, and 5.

In channels 0 and 3, bit 7 i s reserved. It is always

read as 1 and cannot be modified.

0: TCNT counts down

1: TCNT counts up

61Reserved

This bi t is always read as 1 and cannot be modified.

5 TCFU 0 R/(W) Underflow Flag

Status flag that indicates that TCNT underflow has

occurred when channels 1, 2, 4, and 5 are set to

phase counting mode. Only 0 can be written, for flag

clearing.

In channels 0 and 3, bit 5 i s reserved. It is always

read as 0 and cannot be modified.

[Setting condition]

• When the TCNT value underflows (changes from

H'0000 to H'FFFF)

[Clearing condition]

• When 0 is written to TCFU after reading TCFU =

4 TCFV 0 R/(W) Overflow Flag

Status flag that indicates that TCNT overflow has

occurred. Only 0 can be written, for flag clearing.

[Setting condition]

• When the TCNT value overflows (changes from

H'FFFF to H'0000 )

[Clearing condition]

• When 0 is written to TCFV after reading TCFV =

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Bit Bit Name Initial value R/W Description

3 TGFD 0 R/(W) Input Capture/Output Compare Flag D

Status flag that indicates the occurrence of TGRD

input capture or compare match in channel s 0 and 3.

Only 0 can be written, for flag clearing. In channels 1,

2, 4, and 5, bit 3 is reserved. It is always read as 0

and cannot be modified.

[Setting conditions]

• When TCNT = TGRD and TGRD is functioning

as output compare register

• When TCNT value is transferred to TGRD by

input capture signal and TGRD is functioning as

input capture register

[Clearing conditions]

• When DTC is activated by TGID interrupt and the

DISEL bit of MRB in DTC is 0

• When 0 is written to TGFD after reading TGFD =

2 TGFC 0 R/(W) Input Capture/Output Compare Flag C

Status flag that indicates the occurrence of TGRC

input capture or compare match in channel s 0 and 3.

Only 0 can be written, for flag clearing. In channels 1,

2, 4, and 5, bit 2 is reserved. It is always read as 0

and cannot be modified.

[Setting conditions]

• When TCNT = TGRC and TGRC is functioning

as output compare register

• When TCNT value is transferred to TGRC by

input capture signal and TGRC is functioning as

input capture register

[Clearing conditions]

• When DTC is activated by TGIC interrupt and the

DISEL bit of MRB in DTC is 0

• When 0 is written to TGFC after reading TGFC =

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Bit Bit Name Initial value R/W Description

1 TGFB 0 R/(W) Input Capture/Output Compare Flag B

Status flag that indicates the occurrence of TGRB

input capture or compare match. Only 0 can be

written, for flag clearing.

[Setting conditions]

• When TCNT = TGRB and TGRB is functioning as

output compare register

• When TCNT value is transferred to TGRB by

input capture signal and TGRB is functioning as

input capture register

[Clearing conditions]

• When DTC is activated by TGIB interrupt and the

DISEL bit of MRB in DTC is 0

• When 0 is written to TGFB after reading TGFB =

0 TGFA 0 R/(W) Input Capture/Output Compare Flag A

Status flag that indicates the occurrence of TGRA

input capture or compare match. Only 0 can be

written, for flag clearing.

[Setting conditions]

• When TCNT = TGRA and TGRA is functioning as

output compare register

• When TCNT value is transferred to TGRA by

input capture signal and TGRA is functioning as

input capture register

[Clearing conditions]

• When DTC is activated by TGIA interrupt and the

DISEL bit of MRB in DTC is 0

• When 0 is written to TGFA after reading TGFA =

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10.3.6 Timer Counter (TCNT)

The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one

for each channel .

The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode.

The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit

unit.

10.3.7 Timer General Register (TGR)

The TGR registers are dual function 16-bit readable/writable registers, functioning as either output

compar e or input captu re regi ste rs. The TPU has 16 TGR reg i sters, four each for chan nel s 0 and 3

and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be

designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units;

they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA–

TGRC and TGRB–TGRD.

10.3.8 Timer Start Register (TSTR)

TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5.

When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT

counter.

Bit Bit Name Initial value R/W Description

7, 6 All 0 Reserved

The write value should al ways be 0.

CST5

CST4

CST3

CST2

CST1

CST0

R/W

Counter Start 5 to 0 (CST5 to CST0)

These bits select operation or stoppage for TCNT.

If 0 is wri tten to the CST bit during operation with the

TIOC pin designated for output, the counter stops but

the TIOC pin output compare output level is retained.

If TIOR is written to when the CST bit is cleared to 0,

the pin output level will be changed to the set initial

output value.

0: TCNT_5 to TCNT_0 count operation is stopped

1: TCNT_5 to TCNT_0 performs count operation

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10.3.9 Timer Synchro Register (TSYR)

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous

operation for the channel 0 to 5 TCNT counters. A channel performs synchronous operation when

the corresponding bit in TSYR is set to 1.

Bit Bit Name Initial value R/W Description

7, 6 All 0 R/W Reserved

The write value should al ways be 0.

SYNC5

SYNC4

SYNC3

SYNC2

SYNC1

SYNC0

R/W

Timer Synchro 0 to 5

These bits are used to select whether operation is

independent of or synchronized with other channels.

When synchronous operation is selected, the TCNT

synchronous presetting of multiple channels, and

synchronous clearing by counter cleari ng on another

channel, are possible.

To set synchronous operation, the SYNC bits for at

least two channels must be set to 1. To set

synchronous clearing, in addition to the SYNC bit ,

the TCNT clearing source must al so be set by means

of bits CCLR0 to CCL R2 in TCR.

0: TCNT_0 to TCNT_5 operates independently

(TCNT presetting/clearing is unrelated to

other channels)

1: TCNT_0 to TCNT_5 performs synchronous

operation

TCNT synchronous presetting/synchronous

clearing is possible

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10.4 Operation

10.4.1 Basic Functions

Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of

free-running operation, periodic counting, and external event counting.

Each TGR can be used as an input capture register or output compare register.

Counter Operation: When one of bits CST5 to CST0 is set to 1 in TSTR, the TCNT counter for

the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic

counter, for example.

1. Example of count operation setting procedure

Figure 10.2 shows an example of the count operation setting procedure.

Operation selection

Select counter clock

Periodic counter

Select counter clearing source

Select output compare register

Set period

Free-running counter

Start count operation

<Free-running counter><Periodic counter>

Start count operation

Select the counter

clock with bits

TPSC2 to TPSC0 in

TCR. At the same

time, select the

input clock edge

with bits CKEG1

and CKEG0 in TCR.

For periodic counter

operation, select the

TGR to be used as

the TCNT clearing

source with bits

CCLR2 to CCLR0 in

TCR.

Designate the TGR

selected in [2] as an

output compare

TIOR.

Set the periodic

counter cycle in the

TGR selected in [2].

Set the CST bit in

TSTR to 1 to start

the counter

operation.

[1]

[2]

[3][3]

[4]

[5]

Figure 10.2 Example of Counter Operation Setting Procedure

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2. Free-running count operation and periodic count operation

Immediately after a reset, the TPU’s TCNT counters are all designated as free-running

counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-

count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000),

the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at

this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from

H'0000.

Figure 10.3 illustrates free-running counter operation.

TCNT value

H'FFFF

H'0000

CST bit

TCFV

Time

Figure 10.3 Free-Running Counter Operation

When compare match is selected as the TCNT clearing source, the TCNT counter for the

relevant chan nel perform s periodi c coun t operati on. The TGR regi ster for setting the period is

designated as an output compare register, and counter clearing by compare match is selected

by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts

up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When

the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared

to H'0000.

If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an

interrupt. After a compare match, TCNT starts counting up again from H'0000.

Figure 10.4 illustrates periodic counter operation.

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TCNT value

TGR

H'0000

CST bit

TGF

Time

Counter cleared by TGR

compare match

Flag cleared by software or

DTC activation

Figure 10.4 Periodic Counter Operation

Waveform Ou tput by Compare Match: The TPU can perform 0, 1, or tog g le output from the

corresponding output pin using compare match.

1. Example of setting procedure for waveform output by compare match

Figure 10.5 shows an example of the setting procedure for waveform output by compare

match.

Output selection

Select waveform output mode

Set output timing

Start count operation

Select initial value 0 output or 1 output, and

compare match output value 0 output, 1 output,

or toggle output, by means of TIOR. The set

initial value is output at the TIOC pin unit the

first compare match occurs.

Set the timing for compare match generation in

TGR.

Set the CST bit in TSTR to 1 to start the count

operation.

[1]

[1] [2]

[2]

[3]

Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match

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2. Examples of waveform output operation

Figure 10.6 shows an example of 0 output/1 output.

In this example TCNT has been designated as a free-running counter, and settings have been

made such that 1 is output by compare match A, and 0 is output by compare match B. When

the set level and the pin level coincide, the pin level does not change.

TCNT value

H'FFFF

H'0000

TIOCA

TIOCB

Time

TGRA

TGRB

No change No change

1 output

0 output

Figure 10.6 Example of 0 Output/1 Output Operation

Figure 10.7 shows an example of toggle output.

In this example, TCNT has been designated as a periodic counter (with counter clearing on

compare match B), and settings have been made such that the output is toggled by both

compare match A and compare match B.

TCNT value

H'FFFF

H'0000

TIOCB

TIOCA

Time

TGRB

TGRA

Toggle output

Counter cleared by TGRB compare match

Figure 10.7 Example of Toggle Output Operation

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Input Capture Function: The TCN T value can be trans fer red to TGR on detection of the TIOC

pin input edge.

Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3,

and 4, it is also possible to specify another channel’s counter input clock or compare match signal

as the input capture source.

Note: When another channel’s counter input clock is used as the input capture input for channels

0 and 3, φ/1 should not be selected as the counter input clock used for input capture input.

Input capture will not be generated if φ/1 is selected.

1. Example of input capture operation setting procedure

Figure 10.8 shows an example of the input capture operation setting procedure.

Input selection

Select input capture input

Start count

Designate TGR as an input capture register by

means of TIOR, and select rising edge, falling

edge, or both edges as the input capture source

and input signal edge.

Set the CST bit in TSTR to 1 to start the count

operation.

[1]

[2]

[1]

[2]

Figure 10.8 Example of Input Capture Operation Setting Procedure

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2. Example of input capture operation

Figure 10.9 shows an example of input capture operation.

In this example both rising and falling edges have been selected as the TIOCA pin input

capture input edge, the falling edge has been selected as the TIOCB pin input capture input

edge, and counter clearing by TGRB input capture has been designated for TCNT.

TCNT value

H'0180

H'0000

TIOCA

TGRA

H'0010

H'0005

Counter cleared by TIOCB

input (falling edge)

H'0160

H'0005 H'0160 H'0010

TGRB H'0180

TIOCB

Time

Figure 10.9 Example of Input Capture Operation

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10.4.2 Synchronous Op era tion

In synchronous operation, the values in a number of TCNT counters can be rewritten

simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared

simultaneously by making the appropriate setting in TCR (synchronous clearing).

Synchronous operation enables TGR to be incremented with respect to a single time base.

Channels 0 to 5 can all be designated for synchronous operation.

Example of Synchronous Operation Setting Procedure: Figure 10.10 shows an example of the

synchronous operation setting procedure.

Yes

Synchronous operation

selection

Set synchronous

operation

Synchronous presetting

Set TCNT

Synchronous clearing

Clearing

source generation

channel?

Select counter

clearing source

Start count

Set synchronous

counter clearing

Start count

Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous

operation.

When the TCNT counter of any of the channels designated for synchronous operation is

written to, the same value is simultaneously written to the other TCNT counters.

Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare,

etc.

Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing

source.

Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.

[1]

[2]

[3]

[4]

[5]

[1]

[3]

[4]

[5]

[2]

Figure 10.10 Example of Synchronous Operation Setting Procedure

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Example of Synchronous Operation: Figure 10.11 shows an example of synchronous operation.

In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to

2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and

synchronous clearing has been set for the channel 1 and 2 counter clearing sources.

Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this

time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are

performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM

cycle.

For details of PWM modes, see section 10.4.5, PWM Modes.

TCNT0 to TCNT2 values

H'0000

TIOCA_0

TIOCA_1

TGRB_0

Synchronous clearing by TGRB_0 compare match

TGRA_2

TGRA_1

TGRB_2

TGRA_0

TGRB_1

TIOCA_2

Time

Figure 10.11 Example of Synchronous Operation

10.4.3 Buffer Oper at ion

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer

registers.

Buffer operation differs depending on whether TGR has been designated as an input capture

Table 10.28 shows the register combinations used in buffer operation.

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Table 10.28 Register Co mbinat ions in Buffer Ope ration

Channel Timer General Register Buffer Register

0 TGRA_0 TGRC_0

TGRB_0 TGRD_0

3 TGRA_3 TGRC_3

TGRB_3 TGRD_3

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the corresponding channel is

transferred to the timer general register.

This operation is illustrated in figure 10.12.

Buffer register Timer general

Compare match signal

Figure 10.12 Compare Match Buffer Operation

• When TGR is an input capture register

When input capture occurs, the value in TCNT is transferred to TGR and the value previously

held in the timer general register is transferred to the buffer register.

This operation is illustrated in figure 10.13.

Buffer register Timer general

Input capture

signal

Figure 10.13 Input Capture Buffer Operation

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Exa mple of Buffer Ope rat ion Set ting Procedure: Figure 10.14 shows an example of the buffer

operation se tting procedu re.

Buffer operation

Select TGR function

Set buffer operation

Start count

[1]

[2]

[3]

[1]

[2]

[3]

Designate TGR as an input capture register or

output compare register by means of TIOR.

Designate TGR for buffer operation with bits

BFA and BFB in TMDR.

Set the CST bit in TSTR to 1 start the count

operation.

Figure 10.14 Exa mple of Buffer Operation Set ting Procedu re

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Exa mple s of Buffer Op era tio n :

1. When TGR is an output compare register

Figure 10.15 shows an operation example in which PWM mode 1 has been designated for

channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used

in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0

output at compare match B.

As buffer operation has been set, when compare match A occurs the output changes and the

value in buffer register TGRC is simultaneously transferred to timer general register TGRA.

This operation is repeated each time that compare match A occurs.

For details of PWM modes, see section 10.4.5, PWM Modes.

TCNT value

TGRB_0

H'0000

TGRC_0

TGRA_0

H'0200 H'0520

TIOCA

H'0200

H'0450 H'0520

H'0450

TGRA_0 H'0450H'0200

Transfer

Time

Figure 10.15 Example of Buffer Operation (1)

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2. When TGR is an input capture register

Figure 10.16 shows an operation example in which TGRA has been designated as an input

capture register, and buffer operation has been designated for TGRA and TGRC.

Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling

edges have been selected as the TIOCA pin input capture input edge.

As buffer operation has been set, when the TCNT value is stored in TGRA upon the

occurrence of input capture A, the value previously stored in TGRA is simultaneously

transferred to TGRC.

TCNT value

H'09FB

H'0000

TGRC

Time

H'0532

TIOCA

TGRA H'0F07H'0532

H'0F07

H'0532

H'0F07

H'09FB

Figure 10.16 Example of Buffer Operation (2)

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10.4.4 Cascad ed Oper ation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit

counter.

This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow

of TCNT_2 (TCNT_5) as set in bits TPSC0 to TPSC2 in TCR.

Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.

Table 10.29 shows the register combinations used in cascaded operation.

Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid

and the counters operates independently in phase counting mode.

Table 10.29 Cascad ed Combin ations

Combination Upper 16 Bits Lower 16 Bits

Channels 1 and 2 TCNT_1 TCNT_2

Channels 4 and 5 TCNT_4 TCNT_5

Example of Cascaded Operation Setting Procedure: Figure 10.17 shows an example of the

setting procedure for cascad ed oper ati on.

Cascaded operation

Set cascading

Start count

Set bits TPSC2 to TPSC0 in the channel 1

(channel 4) TCR to B'111 to select TCNT_2

(TCNT_5) overflow/underflow counting.

Set the CST bit in TSTR for the upper and lower

channel to 1 to start the count operation.

[1]

[2]

[1]

[2]

Figure 10.17 Cascaded Operation Setting Procedure

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Examples of Cascaded Operation: Figure 10.18 illustrates the operation when TCNT_2

overflow/underflow counting has been set for TCNT_1, when TGRA_1 and TGRA_2 have been

designated as input capture registers, and when TIOC pin rising edge has been selected.

When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of

the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.

TCNT_2

clock

TCNT_2 H'FFFF H'0000 H'0001

TIOCA2,

TIOCA1

TGRA_1 H'03A2

TGRA_2 H'0000

TCNT_1

clock

TCNT_1 H'03A1 H'03A2

Figure 10.18 Example of Cascaded Operation (1)

Figure 10.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for

TCNT_1 and phase counting mode has been designated for channel 2.

TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.

TCLKA

TCNT_2 FFFD

TCNT_1 0001

TCLKB

FFFE FFFF 0000 0001 0002 0001 0000 FFFF

0000 0000

Figure 10.19 Example of Cascaded Operation (2)

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10.4.5 PWM Modes

In PWM mode, PWM waveforms are output from the output pins. The output level can be selected

as 0, 1, or toggle output in response to a compare match of each TGR.

TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty

cycle.

Designating TGR compare match as the counter clearing source enables the period to be set in that

also possible.

There are two PWM modes, as described below.

• PWM mode 1

PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and

TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is

output from the TIOCA and TIOCC pins at compare matches A and C, and the output

specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B

and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired

TGRs are identical, the output value does not change when a compare match occurs.

In PWM mode 1, a maximum 8-phase PWM output is possible.

• PWM mode 2

PWM output is generated using one TGR as the cycle register and the others as duty cycle

registers. The output specified in TIOR is performed by means of compare matches. Upon

counter clearing by a duty cycle register compare match, the output value of each pin is the

initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the

output value does not change when a compare match occurs.

In PWM mode 2, a maximum 15-phase PWM output is possible in combination use with

synchron ous ope rati on.

The correspondence between PWM output pins and registers is shown in table 10.30.

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Table 10.30 PWM Output R egist ers and Output Pins

Output Pins

Channel Registers PWM Mode 1 PWM Mode 2

0 TGRA_0 TIOCA0 TIOCA0

TGRB_0 TIOCB0

TGRC_0 TIOCC0 TIOCC0

TGRD_0 TIOCD0

1 TGRA_1 TIOCA1 TIOCA1

TGRB_1 TIOCB1

2 TGRA_2 TIOCA2 TIOCA2

TGRB_2 TIOCB2

3 TGRA_3 TIOCA3 TIOCA3

TGRB_3 TIOCB3

TGRC_3 TIOCC3 TIOCC3

TGRD_3 TIOCD3

4 TGR4A_4 TIOCA4 TIOCA4

TGR4B_4 TIOCB4

5 TGRA_5 TIOCA5 TIOCA5

TGRB_5 TIOCB5

Note: *In PWM mode 2, PWM output is not possible for the TGR register in which the period is

set.

Exa mple of PWM Mode Sett ing Proce dure: Figure 10.20 shows an example of the PWM mode

setting procedure.

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PWM mode

Select counter clock

Select counter clearing source

Select waveform output level

Set TGR

Set PWM mode

Start count

Select the counter clock with bits TPSC2 to

TPSC0 in TCR. At the same time, select the

input clock edge with bits CKEG1 and CKEG0

in TCR.

Use bits CCLR2 to CCLR0 in TCR to select the

TGR to be used as the TCNT clearing source.

Use TIOR to designate the TGR as an output

compare register, and select the initial value and

output value.

Set the cycle in the TGR selected in [2], and set

the duty in the other the TGR.

Select the PWM mode with bits MD3 to MD0 in

TMDR.

Set the CST bit in TSTR to 1 start the count

operation.

[1]

[2]

[3]

[4]

[5]

[6]

[1]

[2]

[3]

[4]

[5]

[6]

Figure 10.20 Example of PWM Mode Setting Procedure

Example s of PWM Mode Operation: Figure 10.21 shows an example of PWM mode 1

operation.

In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA

initial output value and output value, and 1 is set as the TGRB output value.

In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers

are used as the duty cycle levels.

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

Counter cleared by

TGRA compare match

Figure 10.21 Example of PWM Mode Oper ation (1)

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Figure 10.22 shows an example of PWM mode 2 operation.

In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare

match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the

output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase

PWM waveform.

In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are

used as the duty cycle lev el s.

TCNT value

TGRB_1

H'0000

TIOCA0

Counter cleared by

TGRB_1 compare match

Time

TGRA_1

TGRD_0

TGRC_0

TGRB_0

TGRA_0

TIOCB0

TIOCC0

TIOCD0

TIOCA1

Figure 10.22 Example of PWM Mode Oper ation (2)

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Figure 10.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle

in PWM mode.

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

0% duty

TGRB rewritten

TGRB

rewritten

TGRB rewritten

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

100% duty

TGRB rewritten

Output does not change when cycle register and duty register

compare matches occur simultaneously

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

100% duty

TGRB rewritten

Output does not change when cycle register and duty

0% duty

Figure 10.23 Example of PWM Mode Oper ation (3)

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10.4.6 Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and

TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.

When phase counting mode is set, an external clock is selected as the counter input clock and

TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits

CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of

TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be

used.

This can be used for two-phase encoder pulse input.

If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs

when TCNT is counting down, the TCFU flag is set.

The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is

counting up or down.

Table 10.31 shows the correspondence between external clock pins and channels.

Table 10.31 Phase Counting Mode Clock Input Pins

External Clock Pins

Channels A-Phase B-Phase

When channel 1 or 5 is set to phase counting mode TCLKA TCLKB

When channel 2 or 4 is set to phase counting mode TCLKC TCLKD

Example of Phase Counting Mode Setting Procedure: Figure 10.24 shows an example of the

phase counting mode setting procedure.

Phase counting mode

Select phase counting mode

Start count

Select phase counting mode with bits MD3 to

MD0 in TMDR.

Set the CST bit in TSTR to 1 to start the count

operation.

[1]

[2]

[1]

[2]

Figure 10.24 Example of Phase Counting Mode Setting Procedure

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Examples of Phase Counting Mode Operation : In phase counting mode, TCNT counts up or

down according to the phase difference between two external clocks. There are four modes,

accordi ng to the count condition s.

1. Phase counting mode 1

Figure 10.25 shows an example of phase counting mode 1 operation, and table 10.32

summarizes the TCNT up/down-count conditions.

TCNT value

Time

Down-count

Up-count

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Figure 10.25 Example of Phase Counting Mode 1 Operation

Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Up-count

Low level

High level

High level Down-count

Low level

High level

Low level

Legend:

: Rising edge

: Falling edge

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2. Phase counting mode 2

Figure 10.26 shows an example of phase counting mode 2 operation, and table 10.33

summarizes the TCNT up/down-count conditions.

Time

Down-countUp-count

TCNT value

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Figure 10.26 Example of Phase Counting Mode 2 Operation

Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Don’t care

Low level Don’t care

High level U p-count

High level Don’t care

Low level Don’t care

High level D on’t care

Low level Down-count

Legend:

: Rising edge

: Falling edge

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3. Phase counting mode 3

Figure 10.27 shows an example of phase counting mode 3 operation, and table 10.34

summarizes the TCNT up/down-count conditions.

Time

Up-count Down-count

TCNT value

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Figure 10.27 Example of Phase Counting Mode 3 Operation

Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Don’t care

Low level Don’t care

High level U p-count

High level Down-count

Low level Don’t care

High level D on’t care

Low level Don’t care

Legend:

: Rising edge

: Falling edge

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4. Phase counting mode 4

Figure 10.28 shows an example of phase counting mode 4 operation, and table 10.35

summarizes the TCNT up/down-count conditions.

Time

Up-count Down-count

TCNT value

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Figure 10.28 Example of Phase Counting Mode 4 Operation

Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Up-count

Low level

Low level Don’t care

High level

High level Down-count

Low level

High level D on’t care

Low level

Legend:

: Rising edge

: Falling edge

Section 10 16-Bit Timer Pulse Unit (TPU)

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Phase Counting Mode Application Example: Figure 10.29 shows an example in which channel

1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase

encoder pulses in order to detect position or speed.

Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input

to TCLKA and TCLKB.

Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and

TGRC_0 are used for the compare match function and are set with the speed control period and

position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating

in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture

source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected.

TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and

TGRC_0 compare matches are selected as the input capture source and store the up/down-counter

values for the control periods.

This procedu re ena bl es the accu ra te detec tion of posi tion and speed.

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TCNT_1

TCNT_0

Channel 1

TGRA_1

(speed period capture)

TGRA_0

(speed control period)

TGRB_1

(speed period capture)

TGRC_0

(position control period)

TGRB_0 (pulse width capture)

TGRD_0 (buffer operation)

Channel 0

TCLKA

TCLKB

Edge

detection

circuit

Figure 10.29 Phase Counting Mode Application Example

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10.5 Interrupt Sources

There are three kinds of TPU interrupt source; TGR input capture/compare match, TCNT

overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled

bit, allowing the generation of interrupt request signals to be enabled or disabled individually.

When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the

corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The

interrupt request is cleared by clearing the status flag to 0.

Relative channel priorities can be changed by the interrupt controller, however the priority order

within a channel is fixed. For details, see section 5, Interrupt Controller.

Table 10.36 lists the TPU interrupt sources.

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Table 10.36 TPU Interrup ts

Channel Name Interrupt Source Interrupt Flag DTC

Activation

0 TGIA_0 TGRA_0 input capture/compare match TGFA_0 Possible

TGIB_0 TGRB_0 input capture/compare match TGFB_0 Possible

TGIC_0 TGRC_0 input capture/compare match TGFC_0 Possible

TGID_0 TGRD_0 input capture/compare match TGFD_0 Possible

TCIV_0 TCNT_0 overflow TCFV_0 Not possible

1 TGIA_1 TGRA_1 input capture/compare match TGFA_1 Possible

TGIB_1 TGRB_1 input capture/compare match TGFB_1 Possible

TCIV_1 TCNT_1 overflow TCFV_1 Not possible

TCIU_1 TCNT_1 underflow TCFU_1 Not possible

2 TGIA_2 TGRA_2 input capture/compare match TGFA_2 Possible

TGIB_2 TGRB_2 input capture/compare match TGFB_2 Possible

TCIV_2 TCNT_2 overflow TCFV_2 Not possible

TCIU_2 TCNT_2 underflow TCFU_2 Not possible

3 TGIA_3 TGRA_3 input capture/compare match TGFA_3 Possible

TGIB_3 TGRB_3 input capture/compare match TGFB_3 Possible

TGIC_3 TGRC_3 input capture/compare match TGFC_3 Possible

TGID_3 TGRD_3 input capture/compare match TGFD_3 Possible

TCIV_3 TCNT_3 overflow TCFV_3 Not possible

4 TGIA_4 TGRA_4 input capture/compare match TGFA_4 Possible

TGIB_4 TGRB_4 input capture/compare match TGFB_4 Possible

TCIV_4 TCNT_4 overflow TCFV_4 Not possible

TCIU_4 TCNT_4 underflow TCFU_4 Not possible

5 TGIA_5 TGRA_5 input capture/compare match TGFA_5 Possible

TGIB_5 TGRB_5 input capture/compare match TGFB_5 Possible

TCIV_5 TCNT_5 overflow TCFV_5 Not possible

TCIU_5 TCNT_5 underflow TCFU_5 Not possible

Note: *This table shows the initial state immediately after a reset. The relative channel

priorities can be changed by the interrupt controller.

Section 10 16-Bit Timer Pulse Unit (TPU)

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Input Capture/C o mpare Ma tch Interru pt : An interrupt is requested if the TGIE bit in TIER is

set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare

match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The

TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each

for channels 1, 2, 4, and 5.

Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the

TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt

request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for

each channel .

Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the

TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt

request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one

each for channels 1, 2, 4, and 5.

10.6 DTC Acti vation

The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For

details, see section 8, Data Transfer Controller (DTC).

A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources,

four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.

10. 7 A/D Converter Activation

The A/D converter can be activated by the TGRA input capture/compare match for a channel.

If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a

TGRA input capture/compare match on a particular channel, a request to begin A/D conversion is

sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D

converter side at this time, A/D conversion is begun.

In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D

converter conversion start sources, one for each channel.

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10.8 Operation Timing

10.8.1 Input/Output Timing

TCNT Count Timing: Figure 10.30 shows TCNT count timing in internal clock operation, and

figure 10.31 shows TCNT count timing in external clock operation.

TCNT

input clock

Internal clock

N-1 N N+1 N+2

Falling edge Rising edge

Figure 10.30 Count Timing in Internal Clock Operation

TCNT

input clock

External clock

N-1 N N+1 N+2

Falling edge Rising edge Falling edge

Figure 10.31 Count Timing in External Clock Operation

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Output Compare Output Timing: A compare match signal is generated in the final state in

which TCNT and TGR match (the point at which the count value matched by TCNT is updated).

When a compare match signal is generated, the output value set in TIOR is output at the output

compare output pin. After a match between TCNT and TGR, the compare match signal is not

generated until the TCNT input clock is generated.

Figure 10.32 shows output compare output timing.

TGR

TCNT

input clock

N N+1

Compare

match signal

TIOC pin

Figure 10.32 Output Compare Output Timing

Input Capture Signal Timing: Figure 10.33 shows input capture signal timing.

TCNT

Input capture

input

N N+1 N+2

NN+2

TGR

Input capture

signal

Figure 10.33 Input Capture Input Signal Timing

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Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.34 shows the

timin g when counter clearing on compare match is specified, and figure 10.35 shows the timing

when counter clearing on input capture is specified.

TCNT

Counter

clear signal

Compare

match signal

TGR N

N H'0000

Figure 10.34 Counter Clear Timing (Compare Match)

TCNT

Counter clear

signal

Input capture

signal

TGR

N H'0000

Figure 10.35 Counter Clear Timing (Input Capture)

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Buffe r Op er at io n T i ming : Figures 10.36 and 10.37 show the timing in buffer operation.

TGRA,

TGRB

Compare

match signal

TCNT

TGRC,

TGRD

n n+1

Figure 10.36 Buffer Operation Timing (Compare Match)

TGRA,

TGRB

TCNT

Input capture

signal

TGRC,

TGRD

n N+1

N N+1

Figure 10.37 Buffer Operation Timing (Input Capture)

10.8.2 Interrupt Signal Timing

TGF Flag Setting Timing in Case of Compare Match: Figure 10.38 shows the timing for

setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing.

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TGR

TCNT

TCNT input

clock

N N+1

Compare

match signal

TGF flag

TGI interrupt

Figure 10.38 TGI Interrupt Timing (Compare Match)

TGF Flag Setting Timing in Case of Input Capture: Figure 10.39 shows the timing for setting

of the TGF flag in TSR on input capture, and TGI interrupt request signal timing.

TGR

TCNT

Input capture

signal

TGF flag

TGI interrupt

Figure 10.39 TGI Interrupt Timing (Input Capture)

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TCFV Flag/TCFU Flag Setting T iming: Figure 10.40 shows the timing for setting of the TCFV

flag in TSR on overflow, and TCIV interrupt request signal timing.

Figure 10.41 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU

interrupt request signal timing.

Overflow

signal

TCNT

(overflow)

TCNT input

clock

H'FFFF H'0000

TCFV flag

TCIV interrupt

Figure 10.40 TCIV Interrupt Setting Timing

Underflow

signal

TCNT

(underflow)

TCNT

input clock

H'0000 H'FFFF

TCFU flag

TCIU interrupt

Figure 10.41 TCIU Interrupt Setting Timing

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Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing

0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.42 shows the

timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status flag

clearing by the DTC.

Status flag

Write signal

Address TSR address

Interrupt

request

signal

TSR write cycle

T1T2

Figure 10.42 Timing for Status Flag Clearing by CPU

Interrupt

request

signal

Status flag

Address Source address

DTC

read cycle

T1T2

Destination

address

T1T2

DTC

write cycle

Figure 10.43 Timing for Status Flag Clearing by DTC Activation

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10.9 Usage Notes

10.9.1 Module Stop Mode Setti ng

TPU operation can be disabled or enabled using the module stop control register. The initial

setting is for TPU operation to be halted. Register access is enabled by clearing module stop

mode. For details, refer to sec tion 21, Pow er-Do w n Modes.

10.9.2 Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at

least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower

pulse widths.

In phase counting mode, the phase difference and overlap between the two input clocks must be at

least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.44 shows the input clock

conditions in phase counting mode.

Overlap

Phase

differ-

ence

Phase

differ-

ence

Overlap

TCLKA

(TCLKC)

TCLKB

(TCLKD)

Pulse width Pulse width

Notes: Phase difference and overlap

Pulse width : 1.5 states or more

: 2.5 states or more

Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

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10.9.3 Caution on Period Setting

When counter clearing on compare match is set, TCNT is cleared in the final state in which it

matches the TGR value (the point at which the count value matched by TCNT is updated).

Consequently, the actual counter frequency is given by the following formula:

= φ

(N + 1)

Where f : Counter frequency

φ: Operating frequency

N: TGR set value

10.9.4 Conflict between TCNT Write and Clear Operations

If the counter clear signal is generated in the T2 state of a TCN T write cycl e, TCN T cleari ng takes

precedence and the TCNT write is not performed.

Figure 10.45 shows the timing in this case.

Counter clear

signal

Write signal

Address

TCNT address

TCNT

TCNT write cycle

NH'0000

Figure 10.45 Conflict between TCNT Write and Clear Operations

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10.9.5 Conflict between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence

and TCNT is not incremented.

Figure 10.46 shows the timing in this case.

TCNT input

clock

Write signal

Address

TCNT address

TCNT

TCNT write cycle

T1T2

N M

TCNT write data

Figure 10.46 Conflict between TCNT Write and Increment Operations

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10.9.6 Conflict between TGR Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence

and the compare match signal is inhibited. A compare match does not occur even if the previous

value is written.

Figure 10.47 shows the timing in this case.

Compare

match signal

Write signal

Address

TGR address

TCNT

TGR write cycle

N M

TGR write data

TGR

N N+1

Prohibited

Figure 10.47 Conflict between TGR Write and Compare Match

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10.9.7 Conflic t between Buf fer Regist er Wr ite and Compa re Match

If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR

by the buffer operation will be that in the buffer prior to the write.

Figure 10.48 shows the timing in this case.

Compare

match signal

Write signal

Address

Buffer register

address

Buffer

TGR write cycle

T1T2

TGR

N M

Buffer register write data

Figure 10.48 Conflict between Buffer Register Write and Compare Match

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10.9.8 Conflict between TGR Read and Input Capture

If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will

be that in the buffer after input capture transfer.

Figure 10.49 shows the timing in this case.

Input capture

signal

Read signal

Address

TGR address

TGR

TGR read cycle

T1T2

Internal

data bus

X M

Figure 10.49 Conflict between TGR Read and Input Capture

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10.9.9 Conflict between TGR Write and Input Capture

If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture

operation takes precedence and the write to TGR is not performed.

Figure 10.50 shows the timing in this case.

Input capture

signal

Write signal

Address

TCNT

TGR write cycle

TGR

TGR address

Figure 10.50 Conflict between TGR Write and Input Capture

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10.9.10 Conflict between Buffer Register Write and Input Capture

If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer

operation takes precedence and the write to the buffer register is not performed.

Figure 10.51 shows the timing in this case.

Input capture

signal

Write signal

Address

TCNT

Buffer register write cycle

T1T2

TGR

Buffer

Buffer register

address

Figure 10.51 Conflict between Buffer Register Write and Input Capture

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10.9.11 Conflict between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is

not set and TCNT clearing takes precedence.

Figure 10.52 shows the operation timing when a TGR compare match is specified as the clearing

source, and when H'FFFF is set in TGR.

Counter

clear signal

TCNT input

clock

TCNT

TGF

Prohibited

TCFV

H'FFFF H'0000

Figure 10.52 Conflict between Overflow and Counter Clearing

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10.9.12 Conflict between TCNT Write and Overflow/Underflow

If there is an up-co un t or down-count in the T2 state of a TCNT write cycle, and

overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is

not set.

Figure 10.53 shows the operation timing when there is conflict between TCNT write and

overflow.

Write signal

Address

TCNT address

TCNT

TCNT write cycle

H'FFFF M

TCNT write data

TCFV flag Prohibited

Figure 10.53 Conflict between TCNT Write and Overflow

10.9.13 Multiplexing of I/O Pins

In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin

with the TIOCD0 I/O pin, the TCLK C input pin with the TIOCB1 I/O pin, and the TCLKD input

pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not

be performed from a multiplexed pin.

10.9.14 Interrupts in Modu le Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to

clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be

disabled before entering module stop mode.

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Section 11 8-Bit Timers

This LSI has an on-chip 8-bit timer module with four channels operating on the basis of an 8-bit

counter.

The 8-bit timer module can be used to coun t extern al events and be used as a multifuncti on tim er

in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output

with an arbitrary duty cycle using a compare-match signal with two registers.

11.1 Features

• Selection of clock sources

Selected from three internal clocks (φ/8, φ/64, and φ/8192) and an external clock.

• Selection of three ways to clear the counters

The counters can be cleared on compare-match A or B, or by an external reset signal.

• Timer output controlled by two compare-match signals

The timer output signal in each channel is controlled by two independent compare-match

signals, enabling the timer to be used for various applications, such as the generation of pulse

output or PWM output with an arbitrary duty cycle.

• Cascading of the two channels

 Cascading of TMR_1 and TMR_0

The module can operate as a 16-bit timer using TMR_0 as the upper half and TMR_1 as

the lower half (16-bit count mode).

TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count

mode).

 Cascading of TMR_3 and TMR_2

The module can operate as a 16-bit timer using TMR_2 as the upper half and TMR_3 as

the lower half (16-bit count mode).

TMR_3 can be used to count TMR_2 compare-match occurrences (compare-match count

mode).

• Multiple interrupt sources for each channel

Two compare-match interrupts and one overflow interrupt can be requested independently.

• Generation of A/D conversion start trigger

Channel 0 compare-match A signal can be used as the A/D conversion start trigger.

• Module stop mode can be set

At initialization, the 8-bit timer operation is halted. Register access is enabled by canceling the

module stop mode.

TIMH263A_000020020300

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Figure 11.1 shows a block diagram of the 8-bit timer module (TMR_1 and TMR_0).

External clock

sources Internal clock

sources

φ/8

φ/64

φ/8192

Clock 1

Clock 0

Compare-match A1

Compare-match A0

Clear 1

CMIA0

CMIB0

OVI0

CMIA1

CMIB1

OVI1

Interrupt signals

TMO0

TMRI01

Internal bus

TCORA_0

Comparator A_0

Comparator B_0

TCORB_0

TCSR_0

TCR_0

TCORA_1

Comparator A_1

TCNT_1

Comparator B_1

TCORB_1

TCSR_1

TCR_1

TMCI01

TCNT_0

Overflow 1

Overflow 0

Compare-match B1

Compare-match B0

TMO1

A/D conversion start

request signal

Clock select

Control logic

Clear 0

TCORA_1:

TCORB_1:

TCNT_1:

TCSR_1:

TCR_1:

Time constant register A_1

Time constant register B_1

Timer counter_1

Timer control/status register_1

Timer control register_1

Legend:

TCORA_0:

TCORB_0:

TCNT_0:

TCSR_0:

TCR_0:

Time constant register A_0

Time constant register B_0

Timer counter_0

Timer control/status register_0

Timer control register_0

Figure 11.1 Block Diagram of 8-Bit Timer Module

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11.2 Input/O utput Pins

Table 11.1 summarizes the input and output pins of the 8-bit timer module.

Table 11.1 Pin Configura tion

Channel Name Symbol I/O Function

0 Timer output TMO0 Output Output controlled by compare-match

1 Timer output TMO1 Output Output controlled by compare-match

Timer clock input TMCI01 Input External clock input for the counter Common to

0 and 1 Timer reset input TMRI01 Input External reset input for the counter

2 Timer output TMO2 Output Output controlled by compare-match

3 Timer output TMO3 Output Output controlled by compare-match

Timer clock input TMCI23 Input External clock input for the counter

Common to

2 and 3 Timer reset input TMRI23 Input External reset input for the counter

11.3 Register Descriptions

The 8-bit timer has the following registers. For details on the module stop register, refer to 21.1.2,

Module Stop Registers A to C (MSTPCRA to MSTPCRC).

• Timer coun ter_0 ( TCN T_0)

• Time constant register A_0 (TCORA_0)

• Time constant register B_0 (TCORB_0)

• Tim er control reg i ste r_0 ( TCR _0)

• Timer con trol /s tatus reg iste r_0 ( TCSR _0)

• Timer coun ter_1 ( TCN T_1)

• Time constant register A_1 (TCORA_1)

• Time constant register B_1 (TCORB_1)

• Tim er control reg i ste r_1 ( TCR _1)

• Timer con trol /s tatus reg iste r_1 ( TCSR _1)

• Timer coun ter_2 ( TCN T_2)

• Time constant register A_2 (TCORA_2)

• Time constant register B_2 (TCORB_2)

• Tim er control reg i ste r_2 ( TCR _2)

• Timer con trol /s tatus reg iste r_2 ( TCSR _2)

• Timer coun ter_3 ( TCN T_3)

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• Time constant register A_3 (TCORA_3)

• Time constant register B_3 (TCORB_3)

• Tim er control reg i ste r_3 ( TCR _3)

• Timer con trol /s tatus reg iste r_3 ( TCSR _3)

11.3.1 Timer Counters (TCNT)

Each TCNT is an 8-bit u p-coun te r. TCNT_1 and TCN T_0, or TCN T_3 and TCNT_2 compri se a

single 16-bit register, so they can be accessed together by word access.

This clock source is selected by clock select bits CKS2 to CKS0 in TCR. TCNT can be cleared by

an external reset input signal or compare-match signals A and B. Counter clear bits CCLR1 and

CCLR0 in TCR select the method of clearing.

When TCNT overflows from H'FF to H'00, the overflow flag (OVF) in TCSR is set to 1.

The initial value of TCNT is H'00.

11.3.2 Time Constant Registers A (TCORA)

TCORA is an 8-bit readable/writable register. TCORA_3, TCORA_2, TCORA_1 and TCORA_0

comprise a single 16-bit register, so they can be accessed together by word access.

TCORA is continually compared with the value in TCNT. When a match is detected, the

corresponding compare-match flag A (CMFA) in TCSR is set. Note, however, that comparison is

disabled during the T2 state of a TCORA write cycle.

The timer output from the TMO pin can be freely controlled by the compare-match signal A and

the settings of output select bits OS1 and OS0 in TCSR.

The initial value of TCORA is H'FF.

11.3.3 Time Constant Registers B (TCORB)

TCORB is an 8-bit readabl e/w ritable reg iste r. TCORB _3 , TCORB _2, TCORB _1 and TCORB_ 0

comprise a single 16-bit register, so they can be accessed together by word access.

TCORB is continually compared with the value in TCNT. When a match is detected, the

corresponding compare-match flag B (CMFB) in TCSR is set. Note, however, that comparison is

disabled during the T2 state of a TCORB write cycle.

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The timer output from the TMO pin can be freely controlled by the compare-match signal B and

the settings of output select bits OS1 and OS0 in TCSR.

The initial value of TCORB is H'FF.

11.3.4 Timer Control Registers (TCR)

TCR selects the TCNT clock source and the time at which TCNT is cleared, and controls interrupt

requests.

Bit Bit Name Initial

Value R/W Description

7 CMIEB 0 R/W Compare-Match Interrupt Enable B

Selects whether the CMFB interrupt request (CMIB) is

enabled or disabled when the CMFB flag in TCSR is set

to 1.

0: CMFB interrupt reque st (CMIB) is disabled

1: CMFB interrupt request (CMIB) is enabled

6 CMIEA 0 R/W Compare-Match Interrupt Enable A

Selects whether the CMFA interrupt request (CMIA) is

enabled or disabled when the CMFA flag in TCSR is set

to 1.

0: CMFA interrupt reque st (CMIA) is disabled

1: CMFA interrupt request (CMIA) is enabled

5 OVIE 0 R/W Timer Overflow Interrupt Enable

Selects whether the OVF interrupt request (OVI) is

enabled or disabled when the OVF flag in TCSR is set to

0: OVF interrupt request (OVI) is disabled

1: OVF interrupt request (OVI) is enabled

3CCLR1

CCLR0 0

0R/W

R/W Counter Clear 1 and 0

These bits select the method by which TCNT is cleared

00: Clearing is disabled

01: Cleared on compare-match A

10: Cleared on compare-match B

11: Cleared on rising edge of external reset input

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Bit Bit Name Initial

Value R/W Description

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

The input clock can be selected from three clocks divided

from the system clock (φ). When use of an external clock

is selected, three types of count can be selected: at the

rising edge, the falling edge, and both rising and falling

edges.

000: Clock input disabled

001: φ/8 internal clock source, counted on the falling

edge

010: φ/64 internal clock source, counted on the falling

edge

011: φ/8192 internal clock source, counted on the falling

edge

100: For channel 0: Counted on TCNT1 overflow signal*

For channel 1: Counted on TCNT0 overflow signal*

For channel 2: Counted on TCNT3 overflow signal*

For channel 3: Counted on TCNT2 overflow signal*

101: External clock source, counted at rising edge

110: External clock source, counted at falling edge

111: External clock source, counted at both ri sing and

falling edges

Note: *If the count input of channel 0 (channel 2) is the TCNT1 (TCNT3) overflow signal and

that of channel 1 (channel 3) is the TCNT1 (TCNT3) compare-match signal, no

incrementing clock will be generated. Do not use this setting.

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11.3.5 Timer Control/Status Registers (TCSR)

TCSR indicates status flags and controls compare-match output.

• TCSR_0

Bit Bit Name Initial

Value R/W Description

7 CMFB 0 R/(W)*Compare-Match Flag B

[Setting condition]

• When TCNT = TCORB

[Clearing conditions]

• Read CMFB when CMFB = 1, then write 0 in CMFB.

• DTC is activated by the CMIB interrupt and the DISEL

bit = 0 in MRB of TDC.

6 CMFA 0 R/(W)*Compare-match Flag A

[Setting condition]

• When TCNT = TCORA

[Clearing conditions]

• Read CMFA when CMFA = 1, then write 0 in CMFA.

• DTC is activated by the CMIA interrupt and DISEL bit

= 0 in MRB of DTC.

5OVF 0 R/(W)

*Timer Overflow Flag

[Setting condition]

• When TCNT overflows from H'FF to H'00

[Clearing condition]

• Read OVF when OVF = 1, then write 0 in OVF

4 ADTE 0 R/W A/D Trigger Enable

Enables or disables A/D converter start requests by

compare- match A.

0: A/D converter start requests by compare-match A are

disabled

1: A/D converter start requests by compare-match A are

enabled

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Bit Bit Name Initial

Value R/W Description

2OS3

OS2 0

0R/W

R/W Output Select 3 and 2

These bits specify how the timer output level is to be

changed by a compare-match B of TCORB and TCNT.

00: No change when compare-match B occurs

01: 0 is output when compare-match B occurs

10: 1 is output when compare-match B occurs

11: Output is inverted when compare-match B occurs

(toggle output)

0OS1

OS0 0

0R/W

R/W Output Select 1 and 0

These bits specify how the timer output level is to be

changed by a compare-match A of TCORA and TCNT.

00: No change when compare-match A occurs

01: 0 is output when compare-match A occurs

10: 1 is output when compare-match A occurs

11: Output is inverted when compare-match A occurs

(toggle output)

Note: *Only a 0 can be written to this bit, to clear the fl ag

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• TCSR_3 and TCSR_1

Bit Bit Name Initial

Value R/W Description

7 CMFB 0 R/(W)*Compare-Match Flag B

[Setting condition]

• When TCNT = TCORB

[Clearing conditions]

• Read CMFB when CMFB = 1, then write 0 in CMFB

• DTC is activated by the CMIB interrupt and the DISEL

bit = 0 in MRB of DTC.

6 CMFA 0 R/(W)*Compare-match Flag A

[Setting condition]

• When TCNT = TCORA

[Clearing conditions]

• Read CMFA when CMFA = 1, then write 0 in CMFA

• DTC is activated by the CMIA interrupt and the DISEL

bit = 0 in MRB of DTC.

5OVF 0 R/(W)

*Timer Overflow Flag

[Setting condition]

• When TCNT overflows from H'FF to H'00

[Clearing condition]

• Read OVF when OVF = 1, then write 0 in OVF

41Reserved

This bi t is always read as 1 and cannot be modified.

2OS3

OS2 0

0R/W

R/W Output Select 3 and 2

These bits specify how the timer output level is to be

changed by a compare-match B of TCORB and TCNT.

00: No change when compare-match B occurs

01: 0 is output when compare-match B occurs

10: 1 is output when compare-match B occurs

11: Output is inverted when compare-match B occurs

(toggle output)

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Bit Bit Name Initial

Value R/W Description

0OS1

OS0 0

0R/W

R/W Output Select 1 and 0

These bits specify how the timer output level is to be

changed by a compare-match A of TCORA and TCNT.

00: No change when compare-match A occurs

01: 0 is output when compare-match A occurs

10: 1 is output when compare-match A occurs

11: Output is inverted when compare-match A occurs

(toggle output)

Note: *Only a 0 can be written to this bit, to clear the fl ag.

• TCSR_2

Bit Bit Name Initial

Value R/W Description

7 CMFB 0 R/(W)*Compare-Match Flag B

[Setting condition]

• When TCNT = TCORB

[Clearing conditions]

• Read CMFB when CMFB = 1, then write 0 in CMFB

• DTC is activated by the CMIB interrupt and the DISEL

bit = 0 in MRB of DTC.

6 CMFA 0 R/(W)*Compare-match Flag A

[Setting condition]

When TCNT = TCORA

[Clearing conditions]

• Read CMFA when CMFA = 1, then write 0 in CMFA

• DTC is activated by the CMIA interrupt and the DISEL

bit = 0 in MRB of DTC.

5OVF 0 R/(W)

*Timer Overflow Flag

[Setting condition]

• When TCNT overflows from H'FF to H'00

[Clearing condition]

• Read OVF when OVF = 1, then write 0 in OVF

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Bit Bit Name Initial

Value R/W Description

40R/WReserved

This bit is a readable/writable bit, but the write value

should always be 0.

2OS3

OS2 0

0R/W

R/W Output Select 3 and 2

These bits specify how the timer output level is to be

changed by a compare-match B of TCORB and TCNT.

00: No change when compare-match B occurs

01: 0 is output when compare-match B occurs

10: 1 is output when compare-match B occurs

11: Output is inverted when compare-match B occurs

(toggle output)

0OS1

OS0 0

0R/W

R/W Output Select 1 and 0

These bits specify how the timer output level is to be

changed by a compare-match A of TCORA and TCNT.

00: No change when compare-match A occurs

01: 0 is output when compare-match A occurs

10: 1 is output when compare-match A occurs

11: Output is inverted when compare-match A occurs

(toggle output)

Note: *Only a 0 can be written to this bit, to clear the fl ag.

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11.4 Operation

11.4.1 Pulse Output

Figure 11.2 shows an example of arbitrary duty cycle pulse output.

1. Set TCR in CCR1 to 0 and CCLR0 to 1 to clear TCNT by a TCORA compare-match.

2. Set OS3 to OS0 bits in TCSR to B'0110 to output 1 by a compare-match A and 0 by compare-

match B.

By the above settings, waveforms with the cycle of TCORA and the pulse width of TCRB can be

output without software intervention.

TCNT

H'FF Counter clear

TCORA

TCORB

H'00

TMO

Figure 11.2 Example of Pulse Output

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11.5 Operation Timing

11.5.1 TCNT Incrementation Timing

Figure 11.3 shows the TCNT count timing with internal clock source. Figure 11.4 show s the

TCNT incrementation timing with external clock source. The pulse width of the external clock for

incrementation at signal edge must be at least 1.5 system clock (φ) periods, and at least 2.5 states

for incrementation at both edges. The counter will not increment correctly if the pulse width is less

than these val ue s.

Internal clock

TCNT input

clock

TCNT N – 1 N N + 1

Figure 11.3 Count Timing for Internal Clock Input

External clock

input pin

TCNT input

clock

TCNT N – 1 N N + 1

Figure 11.4 Count Timing for External Clock Input

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11.5.2 Timing of CMFA and CMFB Setting When a Compare-Match Occurs

The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the

TCOR and TCNT values match. The compare-match signal is generated at the last state in which

the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT

match, the compare-match signal is not generated until the next incrementation clock input. Figure

11.5 shows the timing of CMF flag setting.

TCNT NN + 1

TCOR N

Compare-match

signal

CMF

Figure 11.5 Timing of CMF Setting

11.5.3 Timing of Timer Output When a Compare-Match Occurs

When a compare-match occurs, the timer output changes as specified by the output select bits

(OS3 to OS0) in TCSR. Figure 11.6 shows the timing when the output is set to toggle at compare-

match A.

Compare-match A

signal

Timer output

Figure 11.6 Timing of Timer Output

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11.5.4 Timing of Compare-Match Clear When a Compare-Match Occurs

TCNT is cleared when compare-match A or B occurs, depending on the setting of the CCLR1 and

CCLR0 bits in TCR. Figure 11.7 shows the timing of this operation.

N H'00

Compare-match

signal

TCNT

Figure 11.7 Timing of Compare-Match Clear

11.5.5 TCNT External Reset Timing

TCNT is cleared at the rising edge of an external reset input, depending on the settings of the

CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure

11.8 shows the timing of this operation.

Clear signal

External reset

input pin

TCNT N H'00N – 1

Figure 11.8 Timing of Clearing by External Reset Input

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11.5.6 Timing of Overflow Flag (OVF) Setting

OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure

11.9 shows the timing of this operation.

OVF

Overflow signal

TCNT H'FF H'00

Figure 11.9 Timing of OVF Setting

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11.6 Operation with Cascaded Connection

If bits CKS2 to CKS0 in one of TCR_1 and TCR_0, or TCR_3 and TCR_2 are set to B'100, the 8-

bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be

used (16-bit tim er mode) or compa re-m atches of 8- bit channel 0 (Channel 2) can be counted by

the timer of channel 1 (Channel 3) (compare-match count mode). In the case that channel 0 is

connected to channel 1 in cascade, the timer operates as described below.

11.6.1 16-Bit Count Mode

When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer

with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.

• Setting of compare-match flags

 The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs.

 The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs.

• Count er clear spe ci fica tion

 If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match,

the 16-bit counter (TCNT_1 and TCNT_0 together) is cleared when a 16-bit compare-

match occurs . The 16-bit count er (TCN T_1 and TCN T_0 tog ether) is cleared ev en if

counter clear by the TMRI01 pin has also been set.

 The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot

be cleared independently.

• Pin output

 Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with

the 16-bit compare-match conditions.

 Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with

the lower 8-bit compare-match conditions.

11.6.2 Compare-Match Count Mode

When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare-match A for channel 0.

Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,

generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the

settings for each channel.

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11.7 Interrupt Sources

11.7.1 Interrupt Sources and DTC Activation

The 8-bit timer can generate three types of interrupt: CMIA, CMIB, and OVI. Table 11.2 shows

the interrupt sources and priority. Each interrupt source can be enabled or disabled independently

by interrupt enable bits in TCR. Independent signals are sent to the interrupt controller for each

interrupt. It is also possible to activate the DTC by means of CMIA and CMIB interrupts.

Table 11.2 8-Bit Timer Interrupt Sources

Interrupt

source Description Flag DT C Activation Interrupt

Priority

CMIA0 TCORA_0 compare-match CMFA Possible High

CMIB0 TCORB_0 compare-match CMFB Possible

OVI0 TCNT_0 overflow OVF Not possible

CMIA1 TCORA_1 compare-match CMFA Possible

CMIB1 TCORB_1 compare-match CMFB Possible

OVI1 TCNT_1 overflow OVF Not possible

CMIA2 TCORA_2 compare-match CMFA Possible

CMIB2 TCORB_2 compare-match CMFB Possible

OVI2 TCNT_2 overflow OVF Not possible

CMIA3 TCORA_3 compare-match CMFA Possible

CMIB3 TCORB_3 compare-match CMFB Possible

OVI3 TCNT_3 overflow OVF Not possible Low

11.7.2 A/D Converter Activation

The A/D converter can be activated only by channel 0 compare match A.

If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of channel

0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit

timer conversion start trigger has been selected on the A/D converter side at this time, A/D

conversion is started.

Section 11 8-Bit Timers

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11.8 Usage Notes

11.8.1 Conflict between TCNT Write and Clear

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear

takes priority, so that the counter is cleared and the write is not performed. Figure 11.10 shows

this operation.

Address TCNT address

Internal write signal

Counter clear signal

TCNT N H'00

TCNT write cycle by CPU

Figure 11.10 Conflict between TCNT Write and Clear

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11.8.2 Conflict between TCNT Write and Increment

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write

takes priority and the counter is not incremented. Figure 11.11 shows this operation.

Address TCNT address

Internal write signal

TCNT input clock

TCNT NM

T1T2

TCNT write cycle by CPU

Counter write data

Figure 11.11 Conflict between TCNT Write and Increment

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11.8.3 Conflict between TCOR Write and Compare-Match

During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match

occurs and the compare-match signal is disabled. Figure 11.12 shows this operation.

Address TCOR address

Internal write signal

TCNT

TCOR NM

TCOR write cycle by CPU

TCOR write data

N N + 1

Compare-match signal

Prohibited

Figure 11.12 Conflict between TCOR Write and Compare-Match

11.8.4 Conflict between Compare-Matches A and B

If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with

the priorities for the output states set for compare-match A and compare-match B, as shown in

table 11.3.

Table 11.3 Timer Output Priori ties

Output Setting Priority

Toggle output High

1 output

0 output

No change Low

Section 11 8-Bit Timers

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11.8.5 Switching of Internal Clocks and TCNT Operation

TCNT may increment erroneously when the internal clock is switched over. Table 11.4 shows the

relationship between the timing at which the internal clock is switched (by writing to the CKS1

and CKS0 bits) and the TCNT operation.

When the TCNT clock is generated from an internal clock, the falling edge of the internal clock

pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in

table 11.4, a TCNT clock pulse is generated on the assumption that the switchover is a falling

edge. This increments TCNT.

Erroneous incrementation can also happen when switching between internal and external clocks.

Table 11.4 Switching of Internal Clock and TCNT Operation

No.

Timing of Switchover

by Means of CKS1

and CKS0 Bits TCNT Clock Operation

1 Switching from low

to low*1

Clock before

switchover

Clock after

switchover

TCNT clock

TCNT

CKS bit rewrite

NN + 1

2 Switching from low

to high*2

Clock before

switchover

Clock after

switchover

TCNT clock

TCNT

CKS bit rewrite

NN + 1N + 2

Section 11 8-Bit Timers

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No.

Timing of Switchover

by Means of CKS1

and CKS0 Bits TCNT Clock Operation

3 Switching from high

to low*3

Clock before

switchover

Clock after

switchover

TCNT clock

TCNT

CKS bit rewrite

NN + 1 N + 2

4 Switching from high

to high

Clock before

switchover

Clock after

switchover

TCNT clock

TCNT

CKS bit rewrite

NN + 1N + 2

Notes: 1. Includes switching from low to stop, and from stop to low.

2. Includes switching from stop to high.

3. Includes switching from high to stop.

4. Generated on the assumption that the switchover is a falling edge; TCNT is

incremented.

11.8.6 Conflict between Interrupts and Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to

clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be

disabled before entering module stop mode.

11.8.7 Notes on Cascaded Connection

If 16-bit count mode and compare-match count mode are set simultaneously, the counter stops and

does not operate since input clocks of TCNT_1 and TCNT_0 (TCNT_3 and TCNT_2) are not

generated. This setting is prohibited.

Section 11 8-Bit Timers

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Section 12 Programmable Pulse Generator (PPG)

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Section 12 Programmable Pulse Generator (PPG)

The programmable pulse generator provides pulse outputs using the 16-bit timer pulse unit (TPU)

as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 and group 2) that can

operate both simultaneously and independently. The block diagram of the PPG is shown in figure

12.1.

12.1 Features

• 8-bit output data

• Two output groups

• Selectable output trigger signals

• Non-overlap mode

• Can operate in tandem with the data transfer controller (DTC)

• Settable inverted output

• Module stop mode can be set

PPG0000A_000020020300

Section 12 Programmable Pulse Generator (PPG)

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Compare match signals

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

Legend: PPG output mode register

PPG output control register

Next data enable register H

Next data enable register L

Next data register H

Next data register L

Output data register H

Output data register L

PMR:

PCR:

NDERH:

NDERL:

NDRH:

NDRL:

PODRH:

PODRL:

Pulse output

pins, group 3

Pulse output

pins, group 2

Pulse output

pins, group 1

Pulse output

pins, group 0

PODRH

PODRL

NDRH

NDRL

Control logic

NDERH

PMR

NDERL

PCR

Internal

data bus

Figure 12.1 Block Diagram of PPG

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12.2 Input/Output Pins

Table 12.1 summarizes the pin configuration of the PPG.

Table 12.1 Pin Configura tion

Pin Name I/O Function

PO15 Output

PO14 Output

PO13 Output

PO12 Output

Group 3 pulse output

PO11 Output

PO10 Output

PO9 Output

PO8 Output

Group 2 pulse output

12.3 Register Descriptions

The PPG has the foll owing regi sters.

• PPG output control register (PCR)

• PPG output mode register (PMR)

• Next data enable register H (NDERH)

• Next data enable register L (NDERL)

• Output data register H (PODRH)

• Output data register L (PODRL)

• Next data register H (NDRH)

• Next data register L (NDRL)

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12.3.1 Next Data Enable Registers H, L (NDERH, NDERL)

NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a

bit-by-bit basis. The corresponding DDR also needs to be set to 1 in order to enable pulse output

by the PPG.

• NDERH

Bit Bit Name Initial Value R/W Description

NDER15

NDER14

NDER13

NDER12

NDER11

NDER10

NDER9

NDER8

R/W

Next Data Enable 15 to 8

When a bit is set to 1 for pulse output by NDRH,

the value in the corresponding NDRH bit is

transferred to the PODRH bit by the selected

output trigger. Values are not transferred from

NDRH to PODRH for cleared bits.

• NDERL

Bit Bit Name Initial Value R/W Description

NDER7

NDER6

NDER5

NDER4

NDER3

NDER2

NDER1

NDER0

R/W

Next Data Enable 7 to 0

When a bit is set to 1 for pulse output by NDRL, the

value in the corresponding NDRL bit is transferred

to the PODRL bit by the selected output trigger.

Values are not transferred from NDRL to PODRL

for cleared bits.

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12.3.2 Output Data Registers H, L (PODRH, PODRL)

PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse

output. A bit that has been set for pulse output by NDER is read-only and cannot be modified.

• PODRH

Bit Bit Name Initial Value R/W Description

POD15

POD14

POD13

POD12

POD11

POD10

POD9

POD8

R/W

Output Data Register 15 to 8

For bits that have been set to pulse output by

NDERH, the output trigger transfers NDRH values

to this regi ster during PPG operation. While

NDERH is set to 1, the CPU cannot write to this

value of the pulse can be set.

• PODRL

Bit Bit Name Initial Value R/W Description

POD7

POD6

POD5

POD4

POD3

POD2

POD1

POD0

R/W

Output Data Register 7 to 0

For bits which have been set to pulse output by

NDERL, the output trigger transfers NDRL values

to this regi ster during PPG operation. While

NDERL is set to 1, the CPU cannot write to this

value of the pulse can be set.

Section 12 Programmable Pulse Generator (PPG)

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12.3.3 Next Data Registers H, L (NDRH, NDRL)

NDRH and NDRL are 8-bit readable/writable registers that store the data for the next pulse output.

The NDR addresses differ depending on whether pulse output groups have the same output trigger

or different output triggers.

• NDRH

If pulse output groups 3 and 2 have the same output trigger, all eight bits are mapped to the

same address and can be accessed at one time, as shown below.

Bit Bit Name Initial Value R/W Description

NDR15

NDR14

NDR13

NDR12

NDR11

NDR10

NDR9

NDR8

R/W

Next Data Register 15 to 8

The register contents are transferred to the

corresponding PODRH bi ts by the output trigger

specified with PCR.

If pulse output groups 3 and output pulse groups 2 have different output triggers, the upper 4

bits and the lower 4 bits are mapped to different addresses, as shown below.

Bit Bit Name Initial Value R/W Description

NDR15

NDR14

NDR13

NDR12

R/W

Next Data Register 15 to 12

The register contents are transferred to the

corresponding PODRH bi ts by the output trigger

specified with PCR.

3 to

0All 1 Reserved

These bits are always read as 1 and cannot be

modified.

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Bit Bit Name Initial Value R/W Description

7 to

4All 1 Reserved

These bits are always read as 1 and cannot be

modified.

NDR11

NDR10

NDR9

NDR8

R/W

Next Data Register 11 to 8

The register contents are transferred to the

corresponding PODRH bi ts by the output trigger

specified with PCR.

• NDRL

If pulse output groups 1 and 0 have the same output trigger, all eight bits are mapped to the

same address and can be accessed at one time, as shown below.

Bit Bit Name Initial Value R/W Description

NDR7

NDR6

NDR5

NDR4

NDR3

NDR2

NDR1

NDR0

R/W

Next Data Register 7 to 0

The register contents are transferred to the

corresponding PODRL bits by the output trigger

specified with PCR.

If pulse output groups 1 and output pulse groups 0 have different output triggers, upper 4 bits

and lower 4 bits are mapped to the different addresses as shown below.

Bit Bit Name Initial Value R/W Description

NDR7

NDR6

NDR5

NDR4

R/W

Next Data Register 7 to 4

The register contents are transferred to the

corresponding PODRL bits by the output trigger

specified with PCR.

3 to 0 All 1 Reserved

These bits are always read as 1 and cannot be

modified.

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Bit Bit Name Initial Value R/W Description

7 to

4All 1 Reserved

These bits are always read as 1 and cannot be

modified.

NDR3

NDR2

NDR1

NDR0

R/W

Next Data Register 3 to 0

The register contents are transferred to the

corresponding PODRL bits by the output trigger

specified with PCR.

12.3.4 PPG Output Control Register (PCR)

PCR is an 8-bit readable/writable register that selects output trigger signals on a group-by-group

basis. For details on output trigger selection, refer to section 12.3.5, PPG Output Mode Register

(PMR).

Bit Bit Name Initial Value R/W Description

6G3CMS1

G3CMS0 1

1R/W

R/W Group 3 Compare Match Select 1 and 0

Select output trigger of pulse output group 3.

00: Compare match in TPU channel 0

01: Compare match in TPU channel 1

10: Compare match in TPU channel 2

11: Compare match in TPU channel 3

4G2CMS1

G2CMS0 1

1R/W

R/W Group 2 Compare Match Select 1 and 0

Select output trigger of pulse output group 2.

00: Compare match in TPC channel 0

01: Compare match in TPC channel 1

10: Compare match in TPC channel 2

11: Compare match in TPC channel 3

2G1CMS1

G1CMS0 1

1R/W

R/W Reserved

0G0CMS1

G0CMS0 1

1R/W

R/W Reserved

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12.3.5 PPG Output Mode Regis ter (PMR)

The PMR is an 8-bit readable/writable register that selects the pulse output mode of the PPG for

each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a

high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG

updates its output values on compare match A or B of the TPU that becomes the output trigger.

For details, refer to section 12.4.5, Non-Overlapping Pulse Output.

Bit Bit Name Initial Value R/W Description

7 G3INV 1 R/W Group 3 Inversion

Selects direct output or in verted output for pulse

output group 3.

0: Inverted output

1: Direct output

6 G2INV 1 R/W Group 2 Inversion

Selects direct output or in verted output for pulse

output group 2.

0: Inverted output

1: Direct output

5, 4 All 1 R/W Reserved

3 G3NOV 0 R/W Group 3 Non-Overlap

Selects normal or non-overlapping operation for

pulse output group 3.

0: Normal operation (output values updated at

compare match A in the selected TPU channel)

1: Non-overlapping operation (output values at

compare match A or B in the selected TPU

channel)

2 G2NOV 0 R/W Group 2 Non-Overlap

Selects normal or non-overlapping operation for

pulse output group 2.

0: Normal operation (output values updated at

compare match A in the selected TPU channel)

1: Non-overlapping operation (output values at

compare match A or B in the selected TPU

channel)

1, 0 All 0 R/W Reserved

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12.4 Operation

12.4.1 Overview

Figure 12.2 shows a block diagram of the PPG. PPG pulse output is enabled when the

corresponding bits in P1DDR and NDER are set to 1. An initial output value is determined by its

corresponding PODR initial setting. When the compare match event specified by PCR occurs, the

corresponding NDR bit contents are transferred to PODR to update the output values.

The sequential output of up to 8 bits of data is possible by writing new output data to NDR before

the next compare match.

Output trigger signal

Pulse output pin Internal data bus

Normal output/inverted output

PODRQD

NDER

NDRQD

DDR

Figure 12.2 PPG Output Operation

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12.4.2 Output Timing

If pulse output is enabled, the contents of NDR contents are transferred to PODR and output when

the specified compare match event occurs. Figure 12.3 shows the timing of these operations for

the case of normal output in groups 3 and 2, triggered by compare match A.

TCNT NN + 1

TGRA N

Compare match

A signal

NDRH

PODRH

PO15 to PO8

Figure 12.3 Timing of Transfer and Output of NDR Contents (Example)

Section 12 Programmable Pulse Generator (PPG)

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12.4.3 Sample Setup Procedure for Normal Pulse Output

Figure 12.4 shows a sample procedure for setting up normal pulse output.

Select TGR functions [1]

Set TGRA value

Set counting operation

Select interrupt request

Set initial output data

Enable pulse output

Select output trigger

Set next pulse

output data

Start counter

Set next pulse

output data

Normal PPG output

Yes

TPU setup

Port and

PPG setup

TPU setup

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

Compare match?

[1] Set TIOR to make TGRA an output

compare register (with output

disabled).

[2] Set the PPG output trigger period.

[3] Select the counter clock source with

bits TPSC2 to TPSC0 in TCR.

Select the counter clear source with

bits CCLR1 and CCLR0.

[4] Enable the TGIA interrupt in TIER.

The DTC can also be set up to

transfer data to NDR.

[5] Set the initial output values in

PODR.

[6] Set the DDR and NDER bits for the

pins to be used for pulse output to 1.

[7] Select the TPU compare match

event to be used as the output

trigger in PCR.

[8] Set the next pulse output values in

NDR.

[9] Set the CST bit in TSTR to 1 to start

the TCNT counter.

[10] At each TGIA interrupt, set the next

output values in NDR.

Figure 12.4 Setup Procedure for Normal Pulse Output (Example)

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12.4.4 Exa mple of Nor mal Pulse Outpu t (Example of Five-Phase Pulse Ou tput)

Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output.

TCNT value TCNT

TGRA

H'0000

NDRH

00 80 C0 40 60 20 30 10 18 08 88

PODRH

PO15

PO14

PO13

PO12

PO11

Time

Compare match

C080 40 60 20 30 10 18 08 88 80 C0 40

Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output)

1. Set up TGRA of the TPU that is used as the output trigger to be an output compare register. Set

a frequency in TGRA so the counter will be cleared on compare match A. Set the TGIEA bit

of TIER to 1 to enable the compare match/input capture A (TGIA) interrupt.

2. Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0

bits in PCR to select compare match in the TPU channel set up in the previous step to be the

output trigger. Write output data H'80 in NDRH.

3. When compare match A occurs, the NDRH contents are transferred to PODRH and output.

The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH.

4. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained

subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA

interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained

without imposing a load on the CPU.

Section 12 Programmable Pulse Generator (PPG)

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12.4.5 Non- Overlapping Pul se Output

During non-overlapping operation, transfer from NDR to PODR is performed as follows:

• NDR bits are always transferred on PODR bits on compare match A.

• On compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred

if their value is 1.

Figure 12.6 illustrates the non-overlapping pulse output operation.

Compare match A

Compare match B

Pulse

output

Internal data bus

Normal output/inverted output

PODRQD

NDER

NDRQD

DDR

Figure 12.6 Non-Overlapping Pulse Output

Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before

compare match A. The NDR contents should not be altered during the interval between compare

match B and compare match A (the non-overlap margin).

This can be accomplished by having the TGIA interrupt handling routine write the next data in

NDR, or by having the TGIA interrupt activate the DTC. Note, however, that the next data must

be written before the next compare match B occurs.

Figure 12.7 shows the timing of this operation.

Section 12 Programmable Pulse Generator (PPG)

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0/1 output0 output 0/1 output0 output

Do not write

to NDR here

Write to NDR

here

Compare match A

Compare match B

NDR

PODR

Do not write

to NDR here

Write to NDR

here

Write to NDR Write to NDR

Figure 12.7 Non-Overlapping Operation and NDR Write Timing

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12.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output

Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output.

Select TGR functions [1]

Set TGR values

Set counting operation

Select interrupt request

Set initial output data

Enable pulse output

Select output trigger

Set next pulse

output data

Start counter

Set next pulse

output data

Compare match A? No

Yes

TPU setup

PPG setup

TPU setup

Non-overlapping

PPG output

Set non-overlapping groups

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[1] Set TIOR to make TGRA and

TGRB an output compare registers

(with output disabled).

[2] Set the pulse output trigger period

in TGRB and the non-overlap

margin in TGRA.

[3] Select the counter clock source

with bits TPSC2 to TPSC0 in TCR.

Select the counter clear source

with bits CCLR1 and CCLR0.

[4] Enable the TGIA interrupt in TIER.

The DTC can also be set up to

transfer data to NDR.

[5] Set the initial output values in

PODR.

[6] Set the DDR and NDER bits for the

pins to be used for pulse output to

[7] Select the TPU compare match

event to be used as the pulse

output trigger in PCR.

[8] In PMR, select the groups that will

operate in non-overlap mode.

[9] Set the next pulse output values in

NDR.

[10] Set the CST bit in TSTR to 1 to

start the TCNT counter.

[11] At each TGIA interrupt, set the next

output values in NDR.

Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example)

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12.4.7 Exa mple of Non-Ove rlap ping Pulse Output (Exa mple of Four-Ph ase

Complementary Non-Overlapping Output)

Figure 12.9 shows an example in which pulse output is used for four-phase complementary non-

overlapping pulse output.

TCNT value

TCNT

TGRB

TGRA

H'0000

NDRH 95 65 59 56 95 65

00 95 05 65 41 59 50 56 14 95 05 65

PODRH

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

Time

Non-overlap margin

Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)

Section 12 Programmable Pulse Generator (PPG)

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1. Set up the TPU channel to be used as the output trigger channel such that TGRA and TGRB

are output compare registers. Set the trigger period in TGRB and the non-overlap margin in

TGRA, and set the counter to be cleared on compare match B. Set the TGIEA bit in TIER to 1

to enab l e the TG IA inte rr up t.

2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0

bits in PCR to select compare match in the TPU channel set up in the previous step to be the

output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output.

Write output data H'95 in NDRH.

3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs,

outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0

to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt

handling routine writes the next output data (H'65) in NDRH.

4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by

writing H'59, H'56, H'95, ... at successive TGIA interrupts. If the DTC is set for activation by

this interrupt, pulse output can be obtained without imposing a load on the CPU.

Section 12 Programmable Pulse Generator (PPG)

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12.4.8 Inverted Pul se Output

If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the

inverse of the PODR contents can be output.

Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the

settings of figure 12.9.

TCNT value

TCNT

TGRB

TGRA

H'0000

NDRH 95 65 59 56 95 65

00 95 05 65 41 59 50 56 14 95 05 65

PODRL

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

Time

Figure 12.10 Inverted Pulse Output (Exampl e )

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12.4.9 Pulse Output Triggered by Input Capture

Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA

functions as an input capture register in the TPU channel selected by PCR, pulse output will be

triggered by the input capture signal.

Figure 12.11 shows the timing of this output.

TIOC pin

Input capture

signal

NDR

PODR

MNPO

Figure 12.11 Pulse Output Triggered by Input Capture (Example)

12.5 Usage Notes

12.5.1 Module Stop Mode Setti ng

PPG operation can be disabled or enabled using the module stop control register. The initial

setting is for PPG operation to be halted. Register access is enabled by clearing module stop mode.

For details, refer to secti on 21, Power- Down Modes.

12.5.2 Operation of Pulse Output Pins

Pins PO15 to PO8 are also used for other periphe ral functi ons such as the TPU. When output by

another peripheral function is enabled, the corresponding pins cannot be used for pulse output.

Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage

of the pins.

Pin functions should be changed only under conditions in which the output trigger event will not

occur.

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Section 13 Watchdog T imer

The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI,

if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.

When this watchdog function is not needed, the WDT can be used as an interval timer. In interval

timer operation, an interval timer interrupt is generated each time the counter overflows.

The block diagram of the WDT is shown in figure 13.1.

13.1 Features

• Selectable from eight counter input clocks.

• Switchable between watchdog timer mode and interval timer mode

In watchdog timer mode

• If the counter overflows, it is possible to select whether this LSI is internally reset or not.

In interval timer mode

• If the counter overflows, the WDT generates an interval timer interrupt (WOVI).

WDT0100A_000020020300

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Overflow

Interrupt

control

WOVI

(interrupt request

signal)

Internal reset signal*Reset

control

RSTCSR TCNT TSCR

φ/2

φ/64

φ/128

φ/512

φ/2048

φ/8192

φ/32768

φ/131072

Clock Clock

select

Internal clock

sources

Bus

interface

Module bus

TCSR:

TCNT:

RSTCSR:

Note: * The type of internal reset signal depends on a register setting.

Timer control/status register

Timer counter

Reset control/status register

WDT

Legend:

Internal bus

Figure 13.1 Block Diagram of WDT

13.2 Register Descriptions

The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and

RSTCSR have to be written to by a different method to normal registers. For details, refer to

section 13.5.1, Notes on Register Access.

• Tim er control /s tat us registe r (TCSR)

• Tim er co un ter (TCNT)

• Reset control/status register (RSTCSR)

13.2.1 Timer Counter (TCNT)

TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 by a reset, when the

TME bit in TCSR is cleared to 0.

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13.2.2 Timer Control/Status Register (TCSR)

TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be

input to TCNT, and selecting the timer mode.

Bit Bit Name Initial Value R/W Description

7OVF 0 R/(W)

*Overflow Flag

Indicates that TCNT has overflowed. Onl y a write

of 0 is permitted, to clear the flag.

[Setting condition]

• When TCNT overflows (changes from H'FF to

H'00)

When internal reset request generation is

selected in watchdog timer mode, OVF is

cleared automatically by the internal reset.

[Clearing condition]

• Cleared by reading TCSR when OVF = 1, then

writing 0 to OVF

6WT/

0 R/W Timer Mode Select

Selects whether the WDT is used as a watchdog

timer or an interval timer.

0: Interval timer mode

1: Watchdog timer mode

5 TME 0 R/W Timer Enable

When this bit is set to 1, TCNT starts counting.

When this bit is cleared, TCNT stops counting and

is initia l iz e d t o H' 00.

4, 3 All 1 Reserved

These bits are always read as 1 and cannot be

modified.

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Bit Bit Name Initial Value R/W Description

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

Selects the cl ock source to be input to TCNT. The

overflow frequency for φ = 20 MHz is enclosed in

parentheses.

000: Clock φ/2 (frequency: 25.6 µs)

001: Clock φ/64 (frequency: 819.2 µs)

010: Clock φ/128 (frequency: 1.6 ms)

011: Clock φ/512 (frequency: 6.6 ms)

100: Clock φ/2048 (frequency: 26.2 ms)

101: Clock φ/8192 (frequency: 104.9 ms)

110: Clock φ/32768 (frequency: 419.4 ms)

111: Clock φ/131072 (frequency: 1.68 s)

Note: *Only 0 can be written, for flag clearing.

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13.2.3 Reset Control/Status Register (RSTCSR)

RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset

signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized

to H'1F by a reset signal from the

RES

pin, and not by the WDT internal reset signal caused by

overflows.

Bit Bit Name Initial Value R/W Description

7WOVF 0 R/(W)

*Watchdog Overflow Flag

This bit is set when TCNT overflows in watchdog

timer mode. This bit cannot be set in interval timer

mode, and only 0 can be written.

[Setting condition]

• Set when TCNT overflows (changed from

H'FF to H'00) in watchdog timer mode

[Clearing condition]

• Cleared by reading RSTCSR when WOVF =

1, and then writing 0 to WOVF

6 RSTE 0 R/W Reset Enable

Specifies whether or not a reset signal is generated

in the chip if TCNT overflows during watchdog timer

operation.

0: Reset signal is not generated even if TCNT

overflows

(Though this LSI is not reset, TCNT and TCSR in

WDT are reset)

1: Reset signal is generated if TCNT overflow s

5 RSTS 0 R/W Reset Sele ct

Selects the type of internal reset generated if TCNT

overflows during watchdog timer operation.

0: Power-on reset

1: Setting prohibited

4 to

0All 1 Reserved

These bits are always read as 1 and cannot be

modified.

Note: *Only 0 can be written, for flag clearing.

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13.3 Operation

13.3.1 Watchdog Ti mer Mod e Operat ion

To use the WDT as a watchdog time r, set the WT/

bit in TCSR and the TME bit to 1. Software

must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before

overflow occurs. This ensures that TCNT does not overflow while the system is operating

normally. If TCNT overflows without being rewritten because of a system malfunction or other

error, the WOVF bit in RSTCSR is set to 1. If the RSTE bit in RSTCSR is set to 1, an internal

reset is issued. This is shown in figure 13.2. At this time, select the power-on reset by clearing the

RSTS bit in RSTCSR to 0. The internal reset signal is output for 518 states.

If a reset caused by a signal input to the

RES

pin occurs at the same time as a reset caused by a

WDT overflow, the reset by the

RES

pin has priority and the WOVF bit in RSTCSR is cleared to

TCNT value

H'00 Time

H'FF

WT/IT=1

TME=1 Write H'00

to TCNT WT/IT=1

TME=1 Write H'00

to TCNT

518 states

Internal reset signal*

WT/IT:

TME:

Note: * The internal reset signal is generated only if the RSTE bit is set to 1.

Overflow

internal reset is

generated

WOVF=1

Timer mode select bit

Timer enable bit

Legend:

Figure 13.2 Example of WDT0 Watchdog Timer Operation

13.3.2 Interval Timer Mode

When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each

time the TCNT overflows. Therefore, an interrupt can be generated at intervals.

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When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested

at the time the OVF bit of the TCSR is set to 1.

13.4 Interrupts

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).

The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be

cleared to 0 in the interrupt handling routine.

Table 13.1 WDT Interrupt Source

Name Interrupt Source Interrupt Flag DT C Activation

WOVI TCNT overflow WOVF Impossible

13.5 Usage Notes

13.5.1 Notes on Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being

more difficult to write to. The procedures for writing to and reading these registers are given

below.

Writing to TCNT, TCSR, and RSTCSR: To write to TCNT and TCSR, execute a word transfer

instruction. They cannot be written to by a byte transfer instruction.

TCNT and TCSR both have the same write address. Therefore, the relative condition shown in

fig ure 13.3 needs to be satisfie d in order to w rite to TCN T or TCSR. The trans fe r instructi on

writes the lower byte data to TCNT or TCSR according to the satisfied condition.

To write to RSTCSR, execute a word transfer instruction for address H'FF76. A byte transfer

instruction cannot write to RSTCSR.

The method of writing 0 to the WOVF bit differs from that of writing to the RSTE and RSTS bits.

To write 0 to the WOVF bit, satisfy the condition shown in figure 13.3. If satisfied, the transfer

instruction clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to

the RSTE and RSTS bits, satisfy the condition shown in figure 13.3. If satisfied, the transfer

instruction writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits,

respectively, but has no effect on the WOVF bit.

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TCNT write

Writing to RSTE and RSTS bits

TCSR write

Writing 0 to WOVF bit

Address:

15 8 7 0

H'A5

H'FF74

H'FF76 Write data

15 8 7 0

H'A5

H'FF74

H'FF76 Write data or H'00

Figure 13.3 Writing to TCNT, TCSR, and RSTCSR (Example for WDT0)

Reading TCNT, TCSR, and RSTCSR (WDT0): These registers are read in the same way as

other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for

RSTCSR.

13.5.2 Conflict between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write

takes priority and the timer counter is not incremented. Figure 13.4 shows this operation.

Address

Internal write signal

TCNT input clock

TCNT NM

T1T2

TCNT write cycle

Counter write data

Figure 13.4 Conflict between TCNT Write and Increment

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13.5.3 Changing Value of CKS2 to CKS0

If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in

the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to

0) before changing the value of bits CKS2 to CKS0.

13.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer while the WDT is operating, errors

could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing

the TME bit to 0) before switching the mode.

13.5.5 Interna l Reset in Watchdog Ti mer Mod e

This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during

watchdog timer operation, however TCNT and TCSR of the WDT are reset.

TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this

period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states

after overflow to write 0 to the WOVF flag for clearing.

13.5.6 OVF Flag Clearing in Interva l Ti mer Mode

When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0

to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there

is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is

polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before

writing 0 to the OVF bit to clear the flag.

Section 13 Watchdog Timer

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Section 14 Serial Communication Interface (SCI)

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SCI0027A_0100020020900

Section 14 S erial Communication Interface (SCI)

This LSI has two independent serial communication interface (SCI) channels. The SCI can handle

both asynchronous and clocked synchronous serial communication. Serial data communication

can be carried out using standard asynchronous communication chips such as a Universal

Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface

Adapter (ACIA). A function is also provided for serial communication between processors

(multiprocessor communication function). The SCI also supports an IC card (Smart Card)

interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface

extension fun ction.

Figure 14.1 shows a block diagram of the SCI.

14.1 Features

• Choice of asynchronous or clocked synchronous serial communication mode

• Full-duplex communication capability

The transmitter and receiver are mutually independent, enabling transmission and reception to

be executed simultaneously.

Double-buffering is used in both the transmitter and the receiver, enabl ing conti nuous

transmission and continuous reception of serial data.

• On-chip baud rate generator allows any bit rate to be selected

External clock can be selected as a transfer clock source (except for in Smart Card interface

mode).

• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)

• Four interrupt sources

Transmit-end, transmit-data-empty, receive-data-full, and receive error  that can issue

requests.

The transmit-data-empty interrupt and receive-data-full interrupt can be used to activate the

data transfer controller (DTC).

• Module stop mode can be set

Asynchronous mode

• Data length: 8 or 7 bits

• Stop bit length: 2 or 1 bits

• Parity: Even, odd, or none

• Receive error detection: Parity, overrun, and framing errors

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• Break detection: Break can be detected by reading the RxD pin level directly in the case of a

framing error

Clocked synchronous mode

• Data length: 8 bits

• Receive error detection: Overrun errors detected

Smart Card interface

• Automatic transmission of error signal (parity error) in receive mode

• Error signal detection and automatic data retransmission in transmit mode

• Direct convention and inverse convention both supported

RxD

TxD

SCK

Clock

External clock

φ/4

φ/16

φ/64

TEI

TXI

RXI

ERI

RSR:

RDR:

TSR:

TDR:

SMR:

SCR:

SSR:

SCMR:

BRR:

Receive shift register

Receive data register

Transmit shift register

Transmit data register

Serial mode register

Serial control register

Serial status register

Smart Card mode register

Bit rate register

SCMR

SSR

SCR

SMR

Transmission/

reception control

Baud rate

generator

BRR

Module data bus

Bus interface

RDR

TSRRSR

Parity generation

Parity check

Legend:

TDR

Internal

data bus

Figure 14.1 Block Diagram of SCI

Section 14 Serial Communication Interface (SCI)

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14.2 Input/Output Pins

Table 14.1 shows the serial pins for each SCI channel.

Table 14.1 Pin Configura tion

Channel Pin Name*I/O Function

SCK0 I/O SCI0 clock input/output

RxD0 Input SCI0 receive data input

TxD0 Output SCI0 transmit data output

SCK2 I/O SCI2 clock input/output

RxD2 Input SCI2 receive data input

TxD2 Output SCI2 transmit data output

Note: *Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the

channel designation.

14.3 Register Descriptions

The SCI has the following registers for each channel. The serial mode register (SMR), serial status

communication interface mode and Smart Card interface mode because their bit functions differ in

part.

• Receive Shift Register (RSR)

• Receive Data Register (RDR)

• Transmit Data Register (TDR)

• Transmit Shift Register (TSR)

• Serial Mode Register (SMR)

• Serial Control Register (SCR)

• Serial Status Register (SSR)

• Smart Card Mode Register (SCMR)

• Bit Rate Register (BRR)

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14.3.1 Receive Shift Register (RSR)

RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into

parallel data. When one byte of data has been received, it is transferred to RDR automatically.

RSR cannot be directly accessed by the CPU.

14.3.2 Receive Data Register (RDR)

RDR is an 8-bit register that stores received data. When the SCI has received one byte of serial

data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is

receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive

operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only

once. RDR cannot be written to by the CPU.

14.3.3 Transmit Data Register (TDR)

TDR is an 8-bit register that stores data for transmission. When the SCI detects that TSR is empty,

it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered

structure of TDR and TSR enables continuous serial transmission. If the next transmit data has

already been written to TDR during serial transmission, the SCI transfers the written data to TSR

to continue transmission. Although TDR can be read or written to by the CPU at all times, to

achieve reliable serial transmission, write transmit data to TDR only once after confirming that the

TDRE bit in SSR is set to 1.

14.3.4 Transmit Shift Register (TSR)

TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first

transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be

directly accessed by the CPU.

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14.3.5 Serial Mod e Regis ter (SMR )

SMR is used to set the SCI’s serial transfer format and select the baud rate generator clock source.

Some bit functions of SMR differ between normal serial communication interface mode and Smart

Card interface mode.

• Normal Serial Communication Interface Mode (When SMIF in SCMR Is 0)

Bit Bit Name Initial Value R/W Description

7C/

0 R/W Communication Mode

0: Asynchronous mode

1: Clocked synchronous mode

6 CHR 0 R/W Character Length (enabled only in asynchronous

mode)

0: Selects 8 bits as the data length

1: Selects 7 bits as the data length. LSB-first is

fixed and the MSB of TDR is not transmitted in

transmission

In clocked synchronous mode, a fixed data length

of 8 bits is used.

5PE 0 R/WParity Enable (enabled only in asynchronous

mode)

When this bit is set to 1, the parity bit is added to

transmit data before transmission, and the parity

bit is checked in reception. For a multiprocessor

format, parity bit addition and checking are not

performed regardless of the PE bit setting.

4O/

0R/W

Parity Mode (enabled only when the PE bit is 1 in

asynchronous mode)

0: Selects even parity

1: Selects odd parity

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Bit Bit Name Initial Value R/W Description

3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous

mode)

Selects the stop bit length in transm ission.

0: 1 stop bit

1: 2 stop bits

In reception, only the first stop bit is checked. If

the second stop bit is 0, it is treated as the start bit

of the next transmit character.

2 MP 0 R/W Multiprocessor Mode (enabled only in

asynchronous mode)

When this bit is set to 1, the multiprocessor

communication function is enabled. The PE bit

and O/

bit settings are invali d in multiprocessor

mode.

0CKS1

CKS0 0

0R/W

R/W Clock Select 1 and 0

These bits select the clock source for the baud

rate generator.

00: φ clock (n = 0)

01: φ/4 clock (n = 1)

10: φ/16 clock (n = 2)

11: φ/64 clock (n = 3)

For the relationship between the bit rate register

setting and the baud rate, see 14.3.9, Bit Rate

the value of n in BRR (see 14.3.9, Bit Rate

Regi ster (BRR)).

Section 14 Serial Communication Interface (SCI)

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• Smart Card Interface Mode (When SMIF in SCMR Is 1)

Bit Bit Name Initial Value R/W Description

7 GM 0 R/W GSM Mode

When this bit i s set to 1, the SCI operates i n GSM

mode. In GSM mode, the timing of the TEND

setting is advanced by 11.0 etu (Elementary Time

Unit: the time for transfer of one bit), and clock

output control mode addition is performed. For

details, refer to section 14.7.8, Clock Output

Control.

6 BLK 0 R/W When this bit is set to 1, the SCI operates in block

transfer mode. For details on block transfer mode,

refer to section 14.7.3, Block Transfer Mode.

5PE 0 R/WParity Enable (enabled only in asynchronous

mode)

When this bit is set to 1, the parity bit is added to

transmit data in transmission, and the parity bit is

checked in reception. In Smart Card interface

mode, this bit must be set to 1.

4O/

0R/W

Parity Mode (enabled only when the PE bit is 1 in

asynchronous mode)

0: Selects even parity

1: Selects odd parity

For detail s on setting this bit in Smart Card

interface mode, refer to section 14.7.2, Data

Format (Except for Block Transfer Mode).

2BCP1

BCP0 0

0R/W

R/W Basic Clock Pulse 2 and 1

These bits specify the number of basic clock

periods in a 1-bit transfer interval on the Smart

Card interface.

00: 32 clock (S = 32)

01: 64 clock (S = 64)

10: 372 clock (S = 372)

11: 256 clock (S = 256)

For details, refer to secti on 14.7.4, Recei ve Data

Sampling Timing and Reception Margin in Smart

Card Interface Mode. S stands for the value of S

in BRR (see section 14.3.9, Bit Rate Register

(BRR)).

Section 14 Serial Communication Interface (SCI)

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Bit Bit Name Initial Value R/W Description

0CKS1

CKS0 0

0R/W

R/W Clock Select 1 and 0

These bits select the clock source for the baud

rate generator.

00: φ clock (n = 0)

01: φ/4 clock (n = 1)

10: φ/16 clock (n = 2)

11: φ/64 clock (n = 3)

For the relationship between the bit rate register

setting and the baud rate, see section 14.3.9, Bit

Rate Register (BRR). n is the decimal

representation of the value of n in BRR (see

section 14.3.9, Bit Rate Register (BRR)).

Section 14 Serial Communication Interface (SCI)

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14.3.6 Serial Control Register (SCR)

SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also

used to selection of the transfer clock source. For details on interrupt requests, refer to section

14.8, Interrupt Sources. Some bit functions of SCR differ between normal serial communication

interface mode and Smart Card interface mode.

• Normal Serial Communication Interface Mode (When SMIF in SCMR Is 0)

Bit Bit Name Initial Value R/W Description

7 TIE 0 R/W Transmit Interrupt Enable

When this bit is set to 1, the TXI interrupt request

is enabled.

6 RIE 0 R/ W Receive Interrupt Enab le

When this bit is set to 1, RXI and ERI interrupt

requests are enabled.

5 TE 0 R/W Transmit Enable

When this bit s set to 1, transmission is enabled.

4 RE 0 R/W Receive Enable

When this bit is set to 1, reception is enabled.

3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only

when the MP bit in SMR is 1 in asynchronous

mode)

When this bit is set to 1, receive data in which the

multiprocessor bit is 0 is skipped, and setting of

the RDRF, F ER, and ORER status flags in SSR is

prohibited. On receiving data in which the

mult ip r oc e s so r b it is 1 , th is b it is a ut o matical ly

cleared and normal reception is resumed. For

details, refer to 14.5, Multiprocessor

Communication Function.

2 TEIE 0 R/W Transmit End Interrupt Enable

This bit is set to 1, TEI inter rupt reques t is

enabled.

Section 14 Serial Communication Interface (SCI)

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Bit Bit Name Initial Value R/W Description

0CKE1

CKE0 0

0R/W

R/W Clock Enable 0 and 1

Selects the clock source and SCK pin function.

Asynchronous mode

00: Internal baud rate generator

SCK pin functions as I/O port

01: Internal baud rate generator

Outputs a clock of the same frequency as the

bit rate from the SCK pin.

1×: External clock

Inputs a clock with a frequency 16 times the

bit rate from the SCK pin.

Clocked synchronous mode

0×: Internal clock (SCK pin functions as clock

output)

1×: External clock (SCK pin functions as clock

input)

Legend:

×: Don’t care

Section 14 Serial Communication Interface (SCI)

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• Smart Card Interface Mode (When SMIF in SCMR Is 1)

Bit Bit Name Initial Value R/W Description

7 TIE 0 R/W Transmit Interrupt Enable

When this bit is set to 1, TXI interrupt request is

enabled.

6 RIE 0 R/ W Receive Interrupt Enab le

When this bit is set to 1, RXI and ERI interrupt

requests are enabled.

5 TE 0 R/W Transmit Enable

When this bit is set to 1, transmission is enabled.

4 RE 0 R/W Receive Enable

When this bit is set to 1, reception is enabled.

3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only

when the MP bit in SMR is 1 in asynchronous

mode)

Write 0 to thi s bit in Smart Card interface mode.

2 TEIE 0 R/W Transmit End Interrupt Enable

Write 0 to thi s bit in Smart Card interface mode.

0CKE1

CKE0 0

0R/W

R/W Clock Enable 1 and 0

Enables or disables clock output from the SCK

pin. The clock output can be dynamically switched

in GSM mode. For details, refer to section 14.7.8,

Clock Output Control.

When the GM bit in SMR is 0

00: Output disabled (SCK pi n can be used as an

I/O port pin)

01: Clock output

1×: Reserved

When the GM bit in SMR is 1

00: Output fixed low

01: Clock output

10: Output fixed high

11: Clock output

Legend:

×: Don’t care

Section 14 Serial Communication Interface (SCI)

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14.3.7 Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot

be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit

functions of SSR differ between normal serial communication interface mode and Smart Card

interface mode.

• Normal Serial Communication Interface Mode (When SMIF in SCMR Is 0)

Bit Bit Name Initial Value R/W Description

7 TDRE 1 R/W Transmit Data Register Empty

Displays whether TDR contains transmit data.

[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR

and data can be written to TDR

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE

= 1

• When the DTC is activated by a TXI interrupt

request and writes data to TDR

6 RDRF 0 R/W Receive Data Register Full

Indicates that the received data is stored in RDR.

[Setting condition]

• When serial reception ends normal ly and

receive data is transferred from RSR to RDR

[Clearing conditions]

• When 0 is written to RDRF after reading

RDRF = 1

• When the DTC is activated by an RXI interrupt

and transferred data from RDR

The RDRF flag is not affected and retains their

previous values when the RE bit in SCR is cleared

to 0.

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Bit Bit Name Initial Value R/W Description

5 ORER 0 R/W Overrun Error

[Setting condition]

• When the next serial reception is completed

while RDRF = 1

[Clearing condition]

• When 0 is written to ORER after reading

ORER = 1

4 FER 0 R/W Framing Error

[Setting condition]

• When the stop bit is 0

[Clearing condition]

• When 0 is written to FER after reading FER =

In 2-stop-bit mode, only the first stop bit is

checked.

3 PER 0 R/W Parity Error

[Setting condition]

• When a parity error is detected during

reception

[Clearing condition]

• When 0 is written to PER after reading PER =

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Bit Bit Name Initial Value R/W Description

2 TEND 1 R Transmit End

[Setting conditions]

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit

of a 1-byte serial transmit character

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE

= 1

• When the DTC is activated by a TXI interrupt

and writes data to TDR

1 MPB 0 R Multiprocessor Bit

MPB stores the multiprocessor bit in the receive

data. When the RE bit in SCR is cleared to 0 its

previous state is retained.

0 MPBT 0 R/W Multiprocessor Bit Transfer

MPBT stores the multiprocessor bit to be added to

the transmit data.

Section 14 Serial Communication Interface (SCI)

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• Smart Card Interface Mode (When SMIF in SCMR Is 1)

Bit Bit Name Initial Value R/W Description

7 TDRE 1 R/W Transmit Data Register Empty

Displays whether TDR contains transmit data.

[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR

and data can be written to TDR

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE

= 1

• When the DTC is activated by a TXI interrupt

request and writes data to TDR

6 RDRF 0 R/W Receive Data Register Full

Indicates that the received data is stored in RDR.

[Setting condition]

• When serial reception ends normal ly and

receive data is transferred from RSR to RDR

[Clearing conditions]

• When 0 is written to RDRF after reading

RDRF = 1

• When the DTC is activated by an RXI interrupt

and transferred data from RDR

The RDRF flag is not affected and retains their

previous values when the RE bit in SCR is cleared

to 0.

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Bit Bit Name Initial Value R/W Description

5 ORER 0 R/W Overrun Error

[Setting condition]

• When the next serial reception is completed

while RDRF = 1

[Clearing condition]

• When 0 is written to ORER after reading

ORER = 1

4 ERS 0 R/W Error Signal Status

[Setting condition]

• When the low level of the error signal is

sampled

[Clearing condition]

• When 0 is written to ERS after reading ERS =

3 PER 0 R/W Parity Error

[Setting condition]

• When a parity error is detected during

reception

[Clearing condition]

• When 0 is written to PER after reading PER =

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Bit Bit Name Initial Value R/W Description

2 TEND 1 R Transmit End

This bit is set to 1 when no error signal has been

sent back from the receiving end and the next

transmit data is ready to be transferred to TDR.

[Setting conditions]

• When the TE bit in SCR is 0 and the ERS bit

is also 0

• When the ERS bit is 0 and the TDRE bit is 1

after the specified interval following

transmission of 1-byte data.

The timing of bit setting differs according to

the register setting as follows:

When GM = 0 and BLK = 0, 2.5 etu after

transmission starts

When GM = 0 and BLK = 1, 1.5 etu after

transmission starts

When GM = 1 and BLK = 0, 1.0 etu after

transmission starts

When GM = 1 and BLK = 1, 1.0 etu after

transmission starts

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE

= 1

• When the DTC is activated by a TXI interrupt

and writes data to TDR

1 MPB 0 R Multiprocessor Bit

This bi t is not used in Smart Card interface mode.

0 MPBT 0 R/W Multiprocessor Bit Transfer

Write 0 to thi s bit in Smart Card interface mode.

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14.3.8 Smart Card Mode Register (SCMR)

SCMR is a register that selects Smart Card interface mode and its format.

Bit Bit Name Initial Value R/W Description

7 to

4All 1 Reserved

These bits are always read as 1.

3 SDIR 0 R/W Smart Card Data Transfer Direction

Selects the serial/parallel conversion format.

0: LSB-first in transfer

1: MSB-first in transfer

The bit setting is valid only when the transfer

data format is 8 bits. For 7-bit data, LSB-first is

fixed.

2 SINV 0 R/W Smart Card Data Invert

Specifies inversion of the data logic level. The

SINV bit does not affect the logic level of the

parity bit. To invert the parity bit, invert the O/

bit

in SMR.

0: TDR contents are transmitted as they are.

Receive data is stored as it is in RDR

1: TDR contents are inverted before being

transm itted. Receive data is stored in invert ed

form in RDR

11Reserved

This bit is always read as 1.

0 SMIF 0 R/W Smart Card Interface Mode Select

This bit is set to 1 to make the SCI operate in

Smart Card interface mode.

0: Normal asynchronous mode or clocked

synchronous mode

1: Smart card interface mode

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14.3.9 Bit Rate Register (BRR)

BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control

independ en tly for each channel, differ ent bit rates can be set for each channel . Table 14.2 show s

the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,

clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and

it can be read or written to by the CPU at all times.

Table 14.2 The Relationships between The N Setting in BRR and Bit Rate B

Mode BRR Setting N Error

Asynchronous

Mode

N =64 × 2 2n−1 × B

φ × 106− 1

Error (%) = { B × 64 × 2

2n−1

× (N + 1) − 1 } × 100

φ × 10

Clocked

Synchronous

Mode

N =8 × 2 2n−1 × B

φ × 106− 1

Smart Card

Interface Mode

N =S × 2

2n+1

× B

φ × 10

− 1

Error (%) = { B × S × 2

2n+1

× (N + 1) − 1 } × 100

φ × 10

Legend: B: Bit rate (bit/s)

N: BRR setting for baud rate generator (0 ≤ N ≤ 255)

φ: Operating frequency (MHz)

n and S: Determined by the SMR settings shown in the following tables.

SMR Setting SMR Setting

CKS1 CKS0 nBCP1 BCP0 S

000 0032

011 0164

102 10372

113 11256

Table 14.3 shows sample N settings in BRR in normal asynchronous mode. Table 14.4 shows the

maximum bit rate for each frequency in normal asynchronous mode. Table 14.6 shows sample N

settings in BRR in clocked synchronous mode. Table 14.8 shows sample N settings in BRR in

Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in

a 1-bit transfer interval) can be selected. For details, refer to section 14.7.4, Receive Data

Sampling Timing and Reception Margin in Smart Card Interface Mode. Tables 14.5 and 14.7

show the maximum bit rates with external clock input.

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Table 14.3 BRR Setting s for Various Bit Rates (A sy nchro nous Mod e) (1)

Operating Frequency φ

φφ

φ (MHz)

4 4.9152 5

Bit Rate

(bit/s ) n N Error (%) n N Error (%) n N Error (%)

110 2 70 0.03 2 86 0.31 2 88 –0.25

150 1 207 0.16 1 255 0.00 2 64 0.16

300 1 103 0.16 1 127 0.00 1 129 0.16

600 0 207 0.16 0 255 0.00 1 64 0.16

1200 0 103 0.16 0 127 0.00 0 129 0.16

2400 0 51 0.16 0 63 0.00 0 64 0.16

4800 0 25 0.16 0 31 0.00 0 32 –1.36

9600 0 12 0.16 0 15 0.00 0 15 1.73

19200  0 7 0.00 0 7 1.73

31250 0 3 0.00 0 4 –1.70 0 4 0.00

38400  0 3 0.00 0 3 1.73

Operating Frequency φ

φφ

φ (MHz)

6 6.144 7.3728 8

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03

150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16

300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16

600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16

1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16

2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16

4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16

9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16

19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16

31250 0 5 0.00 0 5 2.40  0 7 0.00

38400 0 4 –2.34040.00050.00

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Table 14.3 BRR Setting s for Various Bit Rates (A sy nchro nous Mod e) (2)

Operating Frequency φ

φφ

φ (MHz)

9.8304 10 12 12.288

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08

150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00

300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00

600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00

1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00

2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00

4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00

9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00

19200 0 15 0.00 0 15 1.73 0 19 –2.34 0 19 0.00

31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40

38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00

Operating Frequency φ

φφ

φ (MHz)

14 14.7456 16 17.2032

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 248 –0.17 3 64 0.70 3 70 0.03 3 75 0.48

150 2 181 0.13 2 191 0.00 2 207 0.13 2 223 0.00

300 2 90 0.13 2 95 0.00 2 103 0.13 2 111 0.00

600 1 181 0.13 1 191 0.00 1 207 0.13 1 223 0.00

1200 1 90 0.13 1 95 0.00 1 103 0.13 1 111 0.00

2400 0 181 0.13 0 191 0.00 0 207 0.13 0 223 0.00

4800 0 90 0.13 0 95 0.00 0 103 0.13 0 111 0.00

9600 0 45 –0.93 0 47 0.00 0 51 0.13 0 55 0.00

19200 0 22 –0.93 0 23 0.00 0 25 0.13 0 27 0.00

31250 0 13 0.00 0 14 –1.70 0 15 0.00 0 13 1.20

38400  0 11 0.00 0 12 0.13 0 13 0.00

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Table 14.3 BRR Setting s for Various Bit Rates (A sy nchro nous Mod e) (3)

Operating Frequency φ

φφ

φ (MHz)

18 19.6608 20 24

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 3 79 –0.12 3 86 0.31 3 88 –0.25 3 106 –0.44

150 2 233 0.16 2 255 0.00 3 64 0.16 3 77 0.16

300 2 116 0.16 2 127 0.00 2 129 0.16 2 155 0.16

600 1 233 0.16 1 255 0.00 2 64 0.16 2 77 0.16

1200 1 116 0.16 1 127 0.00 1 129 0.16 1 155 0.16

2400 0 233 0.16 0 255 0.00 1 64 0.16 1 77 0.16

4800 0 116 0.16 0 127 0.00 0 129 0.16 0 155 0.16

9600 0 58 –0.69 0 63 0.00 0 64 0.16 0 77 0.16

19200 0 28 1.02 0 31 0.00 0 32 –1.36 0 38 0.16

31250 0 17 0.00 0 19 –1.70 0 19 0.00 0 23 0

38400 0 14 –2.34 0 15 0.00 0 15 1.73 0 19 –2.34

Table 14.4 Maximum Bit Rate for Each Frequ ency (Asynchr onous Mode)

φφ

φ (MHz) Maximum Bit

Rate (bit/s) n N φ

φφ

φ (MHz) Maximum Bit

Rate (bit/s) n N

4 125000 0 0 12 375000 0 0

4.9152 153600 0 0 12.288 384000 0 0

5 156250 0 0 14 437500 0 0

6 187500 0 0 14.7456 460800 0 0

6.144 192000 0 0 16 500000 0 0

7.3728 230400 0 0 17.2032 537600 0 0

8 250000 0 0 18 562500 0 0

9.8304 307200 0 0 19.6608 614400 0 0

10 312500 0 0 20 625000 0 0

24 750000 0 0

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Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)

φφ

φ (MHz) External Input

Clock (MHz) Maximu m Bit

Rate (bit/s) φ

φφ

φ (MHz) External Input

Clock (MHz) Maximum Bi t

Rate (bit/s)

4 1.0000 62500 12 3.0000 187500

4.9152 1.2288 76800 12.288 3.0720 192000

5 1.2500 78125 14 3.5000 218750

6 1.5000 93750 14.7456 3.6864 230400

6.144 1.5360 96000 16 4.0000 250000

7.3728 1.8432 115200 17.2032 4.3008 268800

8 2.0000 125000 18 4.5000 281250

9.8304 2.4576 153600 19.6608 4.9152 307200

10 2.5000 156250 20 5.0000 312500

24 6.0000 375000

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Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)

Operating Frequency φ

φφ

φ (MHz)

4 8 10 16 20 24

Bit Rate

(bit/s)nNnNnNnNnNnN

110 

250 2 249 3 124  3 249

500 2 124 2 249  3 124  

1 k 1 249 2 124  2 249  

2.5 k 1 99 1 199 1 249 2 99 2 124 2 149

5 k 0 199 1 99 1 124 1 199 1 249 2 74

10 k 0 99 0 199 0 249 1 99 1 124 1 149

25 k 0 39 0 79 0 99 0 159 0 199 1 59

50 k 0 19 0 39 0 49 0 79 0 99 1 29

100 k 0 9 0 19 0 24 0 39 0 49 0 59

250 k 0 3 0 7 0 9 0 15 0 19 0 23

500 k 0 1 0 3 0 4 0 7 0 9 0 11

1 M 0 0*01 03 04 05

2.5 M 0 0*01 

5 M 0 0*

Legend:

Blank: Setting prohibited.

: Can be set, but there will be a degree of error.

*: Continuous transfer is not possible.

Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)

φφ

φ (MHz) External Input

Clock (MHz) Maximu m Bit

Rate (bit/s) φ

φφ

φ (MHz) External Input

Clock (MHz) Maximum Bi t

Rate (bit/s)

4 0.6667 666666.7 14 2.3333 2333333.3

6 1.0000 1.000000.0 16 2.6667 2666666.7

8 1.3333 1333333.3 18 3.0000 3000000.0

10 1.6667 1666666.7 20 3.3333 3333333.3

12 2.0000 2000000.0 24 4 4000000.0

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Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)

(When n = 0 and S = 372)

Operating Frequency φ

φφ

φ (MHz)

7.1424 10.00 10.7136 13.00

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

9600 0 0 0.00 0 1 30 0 1 25 0 1 8.99

Operating Frequency φ

φφ

φ (MHz)

14.2848 16.00 18.00 20.00 24.00

Bit Rate

(bit/s) n N Error

(%) n N Error

(%) nNError

(%)

9600 0 1 0.00 0 1 12.01 0 2 15.99 0 2 6.60 0 2 12.01

Table 14.9 Maxi mum Bit R ate at Various Freque nc ies (S mart Card In terfac e Mode )

(When S = 372)

φφ

φ (MHz) Maximum Bit

Rate (bit/s) n N φ

φφ

φ (MHz) Maximum Bit

Rate (bit/s) n N

7.1424 9600 0 0 14.2848 19200 0 0

10.00 13441 0 0 16.00 21505 0 0

10.7136 14400 0 0 18.00 24194 0 0

13.00 17473 0 0 20.00 26882 0 0

24.00 32258 0 0

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14.4 Operation in Asynchronous Mode

Figure 14.2 shows the general format for asynchronous serial communication. One frame consists

of a start bit (low level), followed by transfer/receive data (in LSB-first order), a parity bit (high or

low level), and finally stop bits (high level). In asynchronous serial communication, the

transmission line is usually held in the mark state (high level). The SCI monitors the transmission

line. When the transmission line goes to the space state (low level), the SCI recognizes a start bit

and starts serial communication. Inside the SCI, the transmitter and receiver are independent units,

enabling full-duplex. Both the transmitter and the receiver also have a double-buffered structure,

so data can be read or written during transmission or reception, enabling continuous data transfer.

LSB

Start

bit

MSB

Idle state

(mark state)

Stop bit

Transmit/receive data

D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1

1 1

Serial

data Parity

bit

1 bit 2 or

1 bits

8 or 7 bits 1 bit,

or none

One unit of transfer data (character or frame)

Figure 14.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits)

14.4.1 Data Transfer Format

Table 14.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12

transfer formats can be selected according to the SMR setting. For details on the multiprocessor

bit, refer to section 14.5, Multiprocessor Communication Function.

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Table 14.10 Serial Trans fer Forma ts (Asy nchron ous Mod e)

—

S 8-bit data

STOP

S 7-bit data

STOP

S 8-bit data

STOP STOP

S 8-bit data P

STOP

S 7-bit data

STOP

S 8-bit data

MPB STOP

S 8-bit data

MPB STOPSTOP

S 7-bit data

STOPMPB

S 7-bit data

STOPMPB STOP

S 7-bit data

STOPSTOP

CHR

STOP

SMR Settings

123456789101112

Serial Transfer Format and Frame Length

STOP

S 8-bit data P

STOP

S 7-bit data

STOP

Legend:

S: Start bit

STOP: Stop bit

P: Parity bit

MPB: Multiprocessor bit

Section 14 Serial Communication Interface (SCI)

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14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer

rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and

performs internal synchronization. Receive data is latched internally at the rising edge of the 8th

pulse of the basic clock as shown in figure 14.3. Thus, the reception margin in asynchronous mode

is given by formula (1) below.

M = { (0.5 – ) –– (L – 0.5) F} × 100 [%]

2N D – 0.5

... Formula (1)

Where N: Ratio of bit rate to clock (N = 16)

D: Clock duty cycle (D = 0.5 to 1.0)

L: Frame length (L = 9 to 12)

F: Absolute value of clock rate deviation

Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty cycle) = 0.5

in formula (1), the reception margin can be given by the formula.

M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%

However, this is only the computed value, and a margin of 30% to 20% should be allowed for in

system design.

Internal basic

clock

16 clocks

8 clocks

Receive data

(RxD)

Synchronization

sampling timing

Start bit D0 D1

Data sampling

timing

15 0 7 15 007

Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode

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14.4.3 Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input at

the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/

bit in

SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the

clock frequency should be 16 times the bit rate used.

When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The

frequency of the clock output in this case is equal to the bit rate, and the phase is such that the

rising edge of the clock is in the middle of the transmit data, as shown in figure 14.4.

1 frame

D0 D1 D2 D3 D4 D5 D6 D7 0/1 11

SCK

TxD

Figure 14.4 Relationship between Output Clock and Transfer Data Phase

(Asynchrono us Mode )

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14.4.4 SCI Init ializat ion (Asy nchron ous Mode )

Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize

the SCI as described below. When the operating mode, or transfer format, is changed for example,

the TE and RE bits must be cleared to 0 before making the change using the following procedure.

When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does

not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.

When the external clock is used in asynchronous mode, the clock must be supplied even during

initialization.

Wait

Start initialization

Set data transfer format in

SMR and SCMR

[1]

Set CKE1 and CKE0 bits in SCR

(TE and RE bits are cleared to 0.)

Yes

Set value in BRR

Clear TE and RE bits in SCR to 0

[2]

[3]

Set TE and RE bits in

SCR to 1, and set RIE, TIE, TEIE,

and MPIE bits [4]

1-bit interval elapsed?

[1] Set the clock selection in SCR.

Be sure to clear bits RIE, TIE,

TEIE, and MPIE, and bits TE and

RE, to 0.

When the clock is selected in

asynchronous mode, it is output

immediately after SCR settings are

made.

[2] Set the data transfer format in SMR

and SCMR.

[3] Write a value corresponding to the

bit rate to BRR. Not necessary if

an external clock is used.

[4] Wait at least one bit interval, then

set the TE bit or RE bit in SCR to 1.

Also set the RIE, TIE, TEIE, and

MPIE bits.

Setting the TE and RE bits enables

the TxD and RxD pins to be used.

Figure 14.5 Sample SCI Initialization Flowchart

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14.4.5 Data Trans miss ion (Asynchronous Mode)

Figure 14.6 shows an example of operation for transmission in asynchronous mode. In

transmission, the SCI operates as described below.

1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that

data has been written to TDR, and transfers the data from TDR to TSR.

2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI)

is generated. Continuous transmission is possible because the TXI interrupt routine writes next

transmit data to TDR before transmission of the current transmit data has been completed.

3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or

multiprocessor bit (may be omitted depending on the format), and stop bit.

4. The SCI checks the TDRE flag at the timing for sending the stop bit.

5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then

serial transmission of the next frame is started.

6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark

state” is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI

interrupt request is generated.

Figure 14.7 shows a sample flowchart for transmission in asynchronous mode.

TDRE

TEND

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1

1 1

DataStart

bit Parity

bit Stop

bit Start

bit Data Parity

bit Stop

bit

TXI interrupt

request generated Data written to TDR and

TDRE flag cleared to 0 in

TXI interrupt service routine TEI interrupt

request generated

Idle state

(mark state)

TXI interrupt

request generated

Figure 14.6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit)

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 336 of 598

REJ09B0155-0300

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR [2]

Write transmit data to TDR

and clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR

[3]

Yes

[4]

Clear DR to 0 and

set DDR to 1

Clear TE bit in SCR to 0

TDRE = 1

All data transmitted?

TEND = 1

Break output?

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data

output pin.

After the TE bit is set to 1, a frame

of 1s is output, and transmission is

enabled.

[2] SCI status check and transmit data

write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR and clear the

TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission,

read 1 from the TDRE flag to

confirm that writing is possible,

then write data to TDR, and then

clear the TDRE flag to 0. Checking

and clearing of the TDRE flag is

automatic when the DTC is

activated by a transmit data empty

interrupt (TXI) request, and data is

written to TDR.

[4] Break output at the end of serial

transmission:

To output a break in serial

transmission, set DDR for the port

corresponding to the TxD pin to 1,

clear DR to 0, then clear the TE bit

in SCR to 0.

Figure 14.7 Sample Serial Transmission Flowchart

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 337 of 598

REJ09B0155-0300

14.4.6 Serial Data Reception (Asynchronous Mode)

Figure 14.8 shows an example of operation for reception in asynchronous mode. In serial

reception, the SCI operates as described below.

1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal

synchronization, receives receive data in RSR, and checks the parity bit and stop bit.

2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag

is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an

ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag

remains to be set to 1.

3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to

RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.

4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive

data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt

request is generated.

5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is

transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is

generated. Continuous reception is possible because the RXI interrupt routine reads the receive

data transferred to RDR before reception of the next receive data has been completed.

RDRF

FER

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0

1 1

DataStart

bit Parity

bit Stop

bit Start

bit Data Parity

bit Stop

bit

ERI interrupt request

generated by framing

error

Idle state

(mark state)

RDR data read and RDRF

flag cleared to 0 in RXI

interrupt service routine

RXI interrupt

request

generated

Figure 14.8 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit)

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 338 of 598

REJ09B0155-0300

Table 14.11 shows the states of the SSR status flags and receive data handling when a receive

error is detected. If a receive error is detected, the RDRF flag retains its state before receiving

data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the

ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.9 shows a sample

flowchart for serial data reception.

Table 14.11 SSR Status Flags and Receive Data Handling

SSR Status Flag

RDRF*ORER FER PER Receive Data Receive Error Type

1100Lost Overrun error

0010Transferred to RDRFraming error

0001Transferred to RDRParity error

1110Lost Overrun error + framing error

1101Lost Overrun error + parity error

0011Transferred to RDRFraming error + parity error

1111Lost Overrun error + framing error +

parity error

Note: *The RDRF flag retains the state it had before data reception.

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 339 of 598

REJ09B0155-0300

Yes

<End>

[1]

Initialization

Start reception

[2]

Yes

Read RDRF flag in SSR [4]

[5]

Clear RE bit in SCR to 0

Read ORER, PER, and

FER flags in SSR

Error processing

(Continued on next page)

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

PER∨FER∨ORER = 1

RDRF = 1

All data received?

[1] SCI initialization:

The RxD pin is automatically

designated as the receive data input

pin.

[2] [3] Receive error processing and break

detection:

If a receive error occurs, read the

ORER, PER, and FER flags in SSR to

identify the error. After performing the

appropriate error processing, ensure

that the ORER, PER, and FER flags are

all cleared to 0. Reception cannot be

resumed if any of these flags are set to

1. In the case of a framing error, a

break can be detected by reading the

value of the input port corresponding to

the RxD pin.

[4] SCI status check and receive data read:

Read SSR and check that RDRF = 1,

then read the receive data in RDR and

clear the RDRF flag to 0. Transition of

the RDRF flag from 0 to 1 can also be

identified by an RXI interrupt.

[5] Serial reception continuation procedure:

To continue serial reception, before the

stop bit for the current frame is

received, read the RDRF flag, read

RDR, and clear the RDRF flag to 0.

The RDRF flag is cleared automatically

when DTC is activated by an RXI

interrupt and the RDR value is read.

Figure 14.9 Sample Serial Reception Data Flowchart (1)

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 340 of 598

REJ09B0155-0300

<End>

[3]

Error processing

Parity error processing

Yes

Clear ORER, PER, and

FER flags in SSR to 0

Yes

Framing error processing

Yes

Overrun error processing

ORER = 1

FER = 1

Break?

PER = 1

Clear RE bit in SCR to 0

Figure 14.9 Sample Serial Reception Data Flowchart (2)

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 341 of 598

REJ09B0155-0300

14.5 Multi pro cessor Communication Function

Use of the multiprocessor communication function enables data transfer between a number of

processors sharing communication lines by asynchronous serial communication using the

multiprocessor format, in which a multiprocessor bit is added to the transfer data. When

multiprocessor communication is performed, each receiving station is addressed by a unique ID

code. The serial communication cycle consists of two component cycles; an ID transmission cycle

that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to

differentiate between the ID transmission cycle and the data transmission cycle. If the

multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the

cycle is a data transmission cycle. Figure 14.10 shows an example of inter-processor

communication using the multiprocessor format. The transmitting station first sends the ID code

of the receiving station with which it wants to perform serial communication as data with a 1

multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.

When data with a 1 multiprocessor bit is received, the receiving station compares that data with its

own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not

match continue to skip data until data with a 1 multiprocessor bit is again received.

The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,

transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,

RDRF, FER, and ORER to 1, are inhibited until data with a 1 multiprocessor bit is received. On

reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the

MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to

1 at this time, an RXI interrupt is generated.

When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit

settings are the same as those in normal asynchronous mode. The clock used for multiprocessor

communication is the same as that in normal asynchronous mode.

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 342 of 598

REJ09B0155-0300

Transmitting

station

Receiving

station A Receiving

station B Receiving

station C Receiving

station D

(ID = 01) (ID = 02) (ID = 03) (ID = 04)

Serial transmission line

Serial

data

ID transmission cycle =

receiving station

specification

Data transmission cycle =

Data transmission to

receiving station specified by ID

(MPB = 1) (MPB = 0)

H'01 H'AA

Legend:

MPB: Multiprocessor bit

Figure 14.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)

14.5.1 Multiprocessor Serial Data Transmission

Figure 14.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID

transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission

cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same

as those in asynchronous mode.

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 343 of 598

REJ09B0155-0300

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR [2]

Write transmit data to TDR and

set MPBT bit in SSR

Yes

Read TEND flag in SSR

[3]

Yes

[4]

Clear DR to 0 and set DDR to 1

Clear TE bit in SCR to 0

TDRE = 1

All data transmitted?

TEND = 1

Break output?

Clear TDRE flag to 0

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data

output pin.

After the TE bit is set to 1, a

frame of 1s is output, and

transmission is enabled.

[2] SCI status check and transmit

data write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR. Set the

MPBT bit in SSR to 0 or 1.

Finally, clear the TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission,

be sure to read 1 from the TDRE

flag to confirm that writing is

possible, then write data to TDR,

and then clear the TDRE flag to

0. Checking and clearing of the

TDRE flag is automatic when the

DTC is activated by a transmit

data empty interrupt (TXI)

request, and data is written to

TDR.

[4] Break output at the end of serial

transmission:

To output a break in serial

transmission, set the port DDR to

1, clear DR to 0, then clear the

TE bit in SCR to 0.

Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart

14.5.2 Multiprocessor Serial Data Reception

Figure 14.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in

SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 344 of 598

REJ09B0155-0300

with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is

generated at this time. All other SCI operations are the same as in asynchronous mode. Figure

14.12 shows an example of SCI operation for multiprocessor format reception.

MPIE

RDR

value

0 D0 D1 D7 1 1 0 D0 D1 D7 0 1

Data (ID1)Start

bit MPB Stop

bit Start

bit Data (Data1) MPB Stop

bit

Data (ID2)Start

bit Stop

bit Start

bit Data (Data2) Stop

bit

RXI interrupt

request

(multiprocessor

interrupt)

generated

Idle state

(mark state)

RDRF

RDR data read

and RDRF flag

cleared to 0 in

RXI interrupt

service routine

If not this station’s ID,

MPIE bit is set to 1

again

RXI interrupt request is

not generated, and RDR

retains its state

ID1

(a) Data does not match station’s ID

MPIE

RDR

value

0 D0 D1 D7 1 1 0 D0 D1 D7 0 1

MPB MPB

RXI interrupt

request

(multiprocessor

interrupt)

generated

Idle state

(mark state)

RDRF

RDR data read and

RDRF flag cleared

to 0 in RXI interrupt

service routine

Matches this station’s ID,

so reception continues, and

data is received in RXI

interrupt service routine

MPIE bit set to 1

again

ID2

(b) Data matches station’s ID

Data2ID1

MPIE = 0

Figure 14.12 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 345 of 598

REJ09B0155-0300

Yes

<End>

[1]

Initialization

Start reception

Yes

[4]

Clear RE bit in SCR to 0

Error processing

(Continued on

next page)

[5]

Yes

FER ∨ ORER = 1

RDRF = 1

All data received?

Read MPIE bit in SCR [2]

Read ORER and FER flags in SSR

Read RDRF flag in SSR [3]

Read receive data in RDR

Yes

This station’s ID?

Read ORER and FER flags in SSR

Yes

Read RDRF flag in SSR

Yes

FER ∨ ORER = 1

Read receive data in RDR

RDRF = 1

[1] SCI initialization:

The RxD pin is automatically designated

as the receive data input pin.

[2] ID reception cycle:

Set the MPIE bit in SCR to 1.

[3] SCI status check, ID reception and

comparison:

Read SSR and check that the RDRF

flag is set to 1, then read the receive

data in RDR and compare it with this

station’s ID.

If the data is not this station’s ID, set the

MPIE bit to 1 again, and clear the RDRF

flag to 0.

If the data is this station’s ID, clear the

RDRF flag to 0.

[4] SCI status check and data reception:

Read SSR and check that the RDRF

flag is set to 1, then read the data in

RDR.

[5] Receive error processing and break

detection:

If a receive error occurs, read the ORER

and FER flags in SSR to identify the

error. After performing the appropriate

error processing, ensure that the ORER

and FER flags are all cleared to 0.

Reception cannot be resumed if either

of these flags is set to 1.

In the case of a framing error, a break

can be detected by reading the RxD pin

value.

Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (1)

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 346 of 598

REJ09B0155-0300

<End>

Error processing

Yes

Clear ORER, PER, and

FER flags in SSR to 0

Yes

Framing error processing

Overrun error processing

ORER = 1

FER = 1

Break?

Clear RE bit in SCR to 0

[5]

Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2)

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 347 of 598

REJ09B0155-0300

14.6 Operation in Clo cked Sync hro nous Mode

Figure 14.14 shows the general format for clocked synchronous communication. In clocked

synchronous mode, data is transmitted or received synchronous with clock pulses. Each character

of data transferred consists of 8 bits. In clocked synchronous serial communication, data on the

transmission line is output from one falling edge of the serial clock to the next. In clocked

synchronous mode, the SCI receives data in synchronous with the rising edge of the serial clock.

After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous

mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are

independent units, enabling full-duplex communication through the use of a common clock. Both

the transmitter and the receiver also have a double-buffered structure, so data can be read or

written during transmission or reception, enabling continuous data transfer.

Don’t

care

Don’t

care

One unit of transfer data (character or frame)

Bit 0

Serial data

Synchronization

clock

Bit 1 Bit 3 Bit 4 Bit 5

LSB MSB

Bit 2 Bit 6 Bit 7

Note: * High except in continuous transfer

Figure 14.14 Data Format in Synchronous Communication (For LSB-First)

14.6.1 Clock

Either an internal clock generated by the on-chip baud rate generator or an external

synchronization clock input at the SCK pin can be selected, according to the setting of CKE0 and

CKE1 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from

the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no

transfer is performed the clock is fixed high.

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 348 of 598

REJ09B0155-0300

14.6.2 SCI Initialization (Clocked Synchronous Mode)

Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, then the

SCI should be initialized as described in a sample flowchart in figure 14.15. When the operating

mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before

making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag

is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER,

FER, and ORER flags, or the contents of RDR.

Wait

Start initialization

Set data transfer format in

SMR and SCMR

Yes

Set value in BRR

Clear TE and RE bits in SCR to 0

[2]

[3]

Set TE and RE bits in SCR to 1, and

set RIE, TIE, TEIE, and MPIE bits [4]

1-bit interval elapsed?

Set CKE1 and CKE0 bits in SCR

(TE, RE bits 0) [1]

[1] Set the clock selection in SCR. Be sure

to clear bits RIE, TIE, TEIE, MPIE, TE,

and RE, to 0.

[2] Set the data transfer format in SMR and

SCMR.

[3] Write a value corresponding to the bit

rate to BRR. Not necessary if an

external clock is used.

[4] Wait at least one bit interval, then set

the TE bit or RE bit in SCR to 1.

Also set the RIE, TIE, TEIE, and MPIE

bits.

Setting the TE and RE bits enables the

TxD and RxD pins to be used.

Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be

cleared to 0 or set to 1 simultaneously.

Figure 14.15 Sample SCI Initialization Flowchart

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 349 of 598

REJ09B0155-0300

14.6.3 Serial Data Transmission (Clocked Synchronous Mode)

Figure 14.16 shows an example of SCI operation for transmission in clocked synchronous mode.

In serial transmission, the SCI operates as described below.

1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has

been written to TDR, and transfers the data from TDR to TSR.

2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI)

is generated. Continuous transmission is possible because the TXI interrupt routine writes the

next transmit data to TDR before transmission of the current transmit data has been completed.

3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock

mode has been specified, and synchronized with the input clock when use of an external clock

has been specified.

4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).

5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission

of the next frame is started.

6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the

output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request

is generated. The SCK pin is fixed high.

Figure 14.17 shows a sample flow chart for serial data transmission. Even if the TDRE flag is

cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.

Make sure that the receive error flags are cleared to 0 before starting transmission. Note that

clearing the RE bit to 0 does not clear the receive error flags.

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 350 of 598

REJ09B0155-0300

Transfer direction

Bit 0

Serial data

Synchronization

clock

1 frame

TDRE

TEND

Data written to TDR

and TDRE flag cleared

to 0 in TXI interrupt

service routine

TXI interrupt

request generated

Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

TXI interrupt

request generated TEI interrupt request

generated

Figure 14.16 Sample SCI Transmission Operation in Clocked Synchronous Mode

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 351 of 598

REJ09B0155-0300

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR [2]

Write transmit data to TDR and

clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR

[3]

Clear TE bit in SCR to 0

TDRE = 1

All data transmitted?

TEND = 1

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data output

pin.

[2] SCI status check and transmit data

write:

Read SSR and check that the TDRE

flag is set to 1, then write transmit data

to TDR and clear the TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission, be

sure to read 1 from the TDRE flag to

confirm that writing is possible, then

write data to TDR, and then clear the

TDRE flag to 0.

Checking and clearing of the TDRE

flag is automatic when the DTC is

activated by a transmit data empty

interrupt (TXI) request and data is

written to TDR.

Figure 14.17 Sample Serial Transmission Flowchart

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 352 of 598

REJ09B0155-0300

14.6.4 Serial Data Reception (Clocked Synchronous Mode)

Figure 14.18 shows an example of SCI operation for reception in clocked synchronous mode. In

serial reception, the SCI operates as described below.

1. The SCI performs internal initialization synchronous with a synchronous clock input or output,

starts receiving data, and stores the received data in RSR.

2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag

in SSR is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this

time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the

RDRF flag remains to be set to 1.

3. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is

transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is

generated. Continuous reception is possible because the RXI interrupt routine reads the receive

data transferred to RDR before reception of the next receive data has finished.

Bit 7

Serial data

Synchronization

clock

1 frame

RDRF

ORER

ERI interrupt request

generated by overrun

error

RXI interrupt

request generated

RDR data read and

RDRF flag cleared

to 0 in RXI interrupt

service routine

RXI interrupt

request

generated

Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

Figure 14.18 Example of SCI Operation in Reception

Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,

FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.19 shows a sample flow

chart for se rial data recepti on.

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 353 of 598

REJ09B0155-0300

Yes

<End>

[1]

Initialization

Start reception

[2]

Yes

Read RDRF flag in SSR [4]

[5]

Clear RE bit in SCR to 0

Error processing

(Continued below)

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

ORER = 1

RDRF = 1

All data received?

Read ORER flag in SSR

<End>

Error processing

Overrun error processing

Clear ORER flag in SSR to 0

[3]

[1] SCI initialization:

The RxD pin is automatically

designated as the receive data input

pin.

[2] [3] Receive error processing:

If a receive error occurs, read the

ORER flag in SSR, and after

performing the appropriate error

processing, clear the ORER flag to 0.

Transfer cannot be resumed if the

ORER flag is set to 1.

[4] SCI status check and receive data

read:

Read SSR and check that the RDRF

flag is set to 1, then read the receive

data in RDR and clear the RDRF flag

to 0.

Transition of the RDRF flag from 0 to 1

can also be identified by an RXI

interrupt.

[5] Serial reception continuation

procedure:

To continue serial reception, before

the MSB (bit 7) of the current frame is

received, reading the RDRF flag,

reading RDR, and clearing the RDRF

flag to 0 should be finished. The

RDRF flag is cleared automatically

when the DTC is activated by a

receive data full interrupt (RXI) request

and the RDR value is read.

Figure 14.19 Sample Serial Reception Flowchart

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 354 of 598

REJ09B0155-0300

14.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous

Mode)

Figure 14.20 shows a sample flowchart for simultaneous serial transmit and receive operations.

The following procedure should be used for simultaneous serial data transmit and receive

operations after initializing the SCI. To switch from transmit mode to simultaneous transmit and

receive mode, after checking that the SCI has finished transmission and the TDRE and TEND

flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction.

To switch from receive mode to simultaneous transmit and receive mode, after checking that the

SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error

flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single

instruction.

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 355 of 598

REJ09B0155-0300

Yes

<End>

[1]

Initialization

Start transmission/reception

[5]

Error processing

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

ORER = 1

All data received?

[2]

Read TDRE flag in SSR

Yes

TDRE = 1

Write transmit data to TDR and

clear TDRE flag in SSR to 0

Yes

RDRF = 1

Read ORER flag in SSR

[4]

Read RDRF flag in SSR

Clear TE and RE bits in SCR to 0

[1] SCI initialization:

The TxD pin is designated as the

transmit data output pin, and the RxD

pin is designated as the receive data

input pin, enabling simultaneous

transmit and receive operations.

[2] SCI status check and transmit data

write:

Read SSR and check that the TDRE

flag is set to 1, then write transmit

data to TDR and clear the TDRE flag

to 0.

Transition of the TDRE flag from 0 to

1 can also be identified by a TXI

interrupt.

[3] Receive error processing:

If a receive error occurs, read the

ORER flag in SSR, and after

performing the appropriate error

processing, clear the ORER flag to 0.

Transmission/reception cannot be

resumed if the ORER flag is set to 1.

[4] SCI status check and receive data

read:

Read SSR and check that the RDRF

flag is set to 1, then read the receive

data in RDR and clear the RDRF flag

to 0. Transition of the RDRF flag from

0 to 1 can also be identified by an RXI

interrupt.

[5] Serial transmission/reception

continuation procedure:

To continue serial transmission/

reception, before the MSB (bit 7) of

the current frame is received, finish

reading the RDRF flag, reading RDR,

and clearing the RDRF flag to 0.

Also, before the MSB (bit 7) of the

current frame is transmitted, read 1

from the TDRE flag to confirm that

writing is possible. Then write data to

TDR and clear the TDRE flag to 0.

Checking and clearing of the TDRE

flag is automatic when the DTC is

activated by a transmit data empty

interrupt (TXI) request and data is

written to TDR. Also, the RDRF flag

is cleared automatically when the

DTC is activated by a receive data full

interrupt (RXI) request and the RDR

value is read.

Note: * When switching from transmit or receive operation to simultaneous

transmit and receive operations, first clear the TE bit and RE bit to 0,

then set both these bits to 1 simultaneously.

Figure 14.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

Section 14 Serial Communication Interface (SCI)

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14.7 Operatio n in Smart Card Interface

The SCI supports an IC card (Smart Card) interface that conforms to ISO/IEC 7816-3

(Identification Card) as a serial communication interface extension function. Switching between

the normal serial communication interface and the Smart Card interface mode is carried out by

means of a register setting.

14.7.1 Pin Connection Example

Figure 14.21 shows an example of connection with the Smart Card. In communication with an IC

card, as both transmission and reception are carried out on a single data transmission line, the TxD

pin and RxD pin should be connected to the LSI pin. The data transmission line should be pulled

up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and RE bits

are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried

out. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin

output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal.

TxD

RxD

This LSI

I/O

Connected equipment

IC card

Data line

Clock line

Reset line

CLK

RST

SCK

Rx (port)

Figure 14.21 Schematic Diagram of Smart Card Interface Pin Connections

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14.7.2 Data For mat (Except for Blo ck Transf er Mode )

Figure 14.22 shows the transfer data format in Smart Card interface mode.

• One frame consists of 8-bit data plus a parity bit in asynchronous mode.

• In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of

one bit) is left between the end of the parity bit and the start of the next frame.

• If a parity error is detected during reception, a low error signal level is output for one etu

period, 10.5 etu after the start bit.

• If an error signal is sampled during transmission, the same data is retransmitted automatically

after a delay of 2 etu or longer.

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

When there is no parity error

Transmitting station output

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

When a parity error occurs

Transmitting station output

Receiving station

output

Start bit

Data bits

Parity bit

Error signal

Legend:

DS:

D0 to D7:

Dp:

DE:

Figure 14.22 Normal Smart Card Interface Data Format

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Data transfe r wi th other types of IC cards (direct conv en tion and inv erse conv en tion) are

performed as described in the following.

AZZAZZ ZZAA(Z) (Z) State

D0 D1 D2 D3 D4 D5 D6 D7 Dp

Figure 14.23 Direct Convention (SDIR = SINV = O/

= 0)

With the direction convention type IC and the above sample start character, the logic 1 level

corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.

The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV

bits in SCMR to 0. According to Smart Card regulations, clear the O/

bit in SMR to 0 to select

even parity mode.

AZZAAA ZAAA(Z) (Z) State

D7 D6 D5 D4 D3 D2 D1 D0 Dp

Figure 14.24 Inverse Convention (SDIR = SINV = O/

= 1)

With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to

state Z, and transfer is performed in MSB-first order. The start character data for the above is

H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to

Smart Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to

state Z. In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/

bit in

SMR to 1 to invert the parity bit for both transmission and reception.

Section 14 Serial Communication Interface (SCI)

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14.7.3 Block Transfer Mode

Operation in block transfer mode is the same as that in SCI asynchronous mode, except for the

following points.

• In reception, though the parity check is performed, no error signal is output even if an error is

detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the

parity bit of the next frame.

• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the

start of the next frame.

• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu

after transm i s si on start.

• As with the normal Smart Card interface, the ERS flag indicates the error signal status, but

since error signal transfer is not performed, this flag is always cleared to 0.

14.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface

Mode

In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372,

or 256 times the transfer rate (fixed at 16 times in normal asynchronous mode) as determined by

bits BCP1 and BCP0. In reception, the SCI samples the falling edge of the start bit using the basic

clock, and performs internal synchronization. As shown in figure 14.25, by sampling receive data

at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at

the middle of the bit. The reception margin is given by the following formula.

M = | (0.5 – ) – (L – 0.5) F – (1 + F) | × 100%

2N | D – 0.5 |

Where M: Reception margin (%)

N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)

D: Clock duty cycle (D = 0 to 1.0)

L: Frame length (L = 10)

F: Absolute value of clock frequency deviation

Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin

formul a is as fo ll ows.

M = (0.5 – 1/2 × 372) × 100%

= 49.866%

Section 14 Serial Communication Interface (SCI)

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Internal

basic clock

372 clocks

186 clocks

Receive data

(RxD)

Synchronization

sampling timing

D0 D1

Data sampling

timing

185 371 0

371

185 0

Start bit

Figure 14.25 Receive Data Sampling Timing in Smart Card Mode

(Using Clock of 372 Times the Transfer Rate)

14.7.5 Initialization

Before transmitting and receiving data, initialize the SCI as described below. Initialization is also

necessary when switching from transmit mode to receive mode, or vice versa.

1. Clear the TE and RE bits in SCR to 0.

2. Clear the error flags ERS, PER, and ORER in SSR to 0.

3. Set the GM, BLK, O/

, BCP0, BCP1, CKS0, CKS1 bits in SMR. Set the PE bit to 1.

4. Set the SMIF, SDIR, and SINV bits in SCMR.

When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins,

and are placed in the high-impedance state.

5. Set the value corresponding to the bit rate in BRR.

6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0.

If the CKE0 bit is set to 1, the clock is output from the SCK pin.

7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE

bit and RE bit at the same time, except for self-diagnosis.

To switch from receive mode to transmit mode, after checking that the SCI has finished reception,

initialize the SCI, and set RE to 0 and TE to 1. Whether SCI has finished reception or not can be

checked with the RDRF, PER, or ORER flags. To switch from transmit mode to receive mode,

Section 14 Serial Communication Interface (SCI)

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after checking that the SCI has finished transmission, initialize the SCI, and set TE to 0 and RE to

1. Whether SCI has finished transmission or not can be checked with the TEND flag.

14.7.6 Data Trans mission (Exce pt for Block Transf er Mode )

As data transmission in Smart Card interface mode involves error signal sampling and

retransmission processing, the operations are different from those in normal serial communication

interface mode (except for block transfer mode). Figure 14.26 illustrates the retransfer operation

when the SCI is in transmit mode.

1. If an error signal is sent back from the receiving end after transmission of one frame is

complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI

interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next

parity bit is sampled.

2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality

is received. Data is retransferred from TDR to TSR, and retransmitted automatically.

3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.

Transmission of one frame, including a retransfer, is judged to have been completed, and the

TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt

request is generated. Writing transmit data to TDR transfers the next transmit data.

Figure 14.28 shows a flowchart for transmission. The sequence of transmit operations can be

performed automatically by specifying the DTC to be activated with a TXI interrupt source. In a

transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in SSR is set, and

a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI request is

designated beforehand as a DTC activation source, the DTC will be activated by the TXI request,

and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically

cleared to 0 when data is transferred by the DTC. In the event of an error, the SCI retransmits the

same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC is

not activated. Therefore, the SCI and DTC will automatically transmit the specified number of

bytes in the event of an error, including retransmission. However, the ERS flag is not cleared

automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an

ERI request will be generated in the event of an error, and the ERS flag will be cleared.

When performing transfer using the DTC, it is essential to set and enable the DTC before carrying

out SCI setting. For details of the DTC setting procedures, refer to section 8, Data Transfer

Controller (DTC).

Section 14 Serial Communication Interface (SCI)

Rev. 3.00 Oct 04, 2005 page 362 of 598

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D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4Ds

Transfer

frame n+1

Retransferred framenth transfer frame

TDRE

TEND

[6]

FER/ERS

Transfer to TSR from TDR Transfer to TSR from TDR

Transfer to TSR

from TDR

[7] [9]

[8]

Figure 14.26 Retransfer Operation in SCI Transmit Mode

The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag

set timing is shown in figure 14.27.

Ds D0 D1 D2 D3 D4 D5 D6 D7 DpI/O data

12.5 etu

TXI

(TEND interrupt)

11.0 etu

Guard

time

When GM = 0

When GM = 1

Start bit

Data bits

Parity bit

Error signal

Legend:

Ds:

D0 to D7:

Dp:

DE:

Figure 14.27 TEND Flag Generation Timing in Transmission Operation

Section 14 Serial Communication Interface (SCI)

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Initialization

Yes

Clear TE bit to 0

Start transmission

Start

Yes

End

Write data to TDR,

and clear TDRE flag

in SSR to 0

Error processing

TEND = 1?

All data transmitted ?

TEND = 1?

ERS = 0?

Figure 14.28 Example of Transmission Processing Flow

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14.7.7 Serial Data Reception (Except for Block Transfer Mode)

Data reception in Smart Card interface mode uses the same operation procedure as for normal

serial communication interface mode. Figure 14.29 illustrates the retransfer operation when the

SCI is in receive mode.

1. If an error is found when the received parity bit is checked, the PER bit in SSR is

automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is

generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.

2. The RDRF bit in SSR is not set for a frame in which an error has occurred.

3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1,

the receive operation is judged to have been completed normally, and the RDRF flag in SSR is

automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is

generated.

Figure 14.30 shows a flowchart for reception. A sequence of receive operations can be performed

automatically by specifying the DTC to be activated using an RXI interrupt source. In a receive

operation, an RXI interrupt request is generated when the RDRF flag is set to 1 if the RIE bit is set

to 1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be

activated by the RXI request, and the receive data will be transferred. The RDRF flag is cleared to

0 automatically when data is transferred by the DTC. If an error occurs in receive mode and the

ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. Hence, so

the error flag must be cleared to 0. In the event of an error, the DTC is not activated and receive

data is skipped. Therefore, receive data is transferred for only the specified number of bytes in the

event of an error. Even when a parity error occurs in receive mode and the PER flag is set to 1, the

data that has been received is transferred to RDR and can be read from there.

Note: For details on receive operations in block transfer mode, refer to 14.4, Operation in

A synchronous Mod e.

D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

(DE)

Ds D0 D1 D2 D3 D4Ds

Transfer

frame n+1

Retransferred framenth transfer frame

RDRF

[1]

PER

[2]

[3]

[4]

Figure 14.29 Retransfer Operation in SCI Receive Mode

Section 14 Serial Communication Interface (SCI)

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Initialization

Read RDR and clear

RDRF flag in SSR to 0

Clear RE bit to 0

Start reception

Start

Error processing

Yes

ORER = 0 and

PER = 0

RDRF = 1?

All data received?

Yes

Figure 14.30 Example of Reception Processing Flow

Section 14 Serial Communication Interface (SCI)

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14.7.8 Clock Output Control

When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and

CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width.

Figure 14.31 shows the timing for fixing the clock output level. In this example, GM is set to 1,

CKE1 is cleared to 0, and the CKE0 bit is controlled.

Specified pulse width

SCK

CKE0

Specified pulse width

Figure 14.31 Timing for Fixing Clock Output Level

When turning on the power or switching between Smart Card interface mode and software standby

mode, the following procedures should be followed in order to maintain the clock duty cycle.

Poweri ng On: To secure clock duty cycle from power-on, the following switching procedure

should be followed.

1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down

resistor to fix the potential.

2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.

3. Set SMR and SCMR, and switch to smart card mode operation.

4. Set the CKE0 bit in SCR to 1 to start clock output.

Section 14 Serial Communication Interface (SCI)

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When changing from smart card interface mode to software standby mode:

1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin

to the value for the fixed output state in software standby mode.

2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive

operation. At the same time, set the CKE1 bit to the value for the fixed output state in

software standby mode.

3. Write 0 to the CKE0 bit in SCR to halt the clock.

4. Wait for one serial clock period.

During this interval, clock output is fixed at the specified level, with the duty cycle

preserved.

5. Make the tran siti on to the softw are standby stat e.

When returning to smart card interface mode from software standby mode:

1. Exit the software standby state.

2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the

normal duty cycle.

[1] [2] [3] [4] [5] [7]

Software

standby

Normal operation Normal operation

[6]

Figure 14.32 Clock Halt and Restart Procedure

Section 14 Serial Communication Interface (SCI)

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14.8 Interrupt Sources

14.8.1 Interrupts in Normal Serial Communication Interface Mode

Table 14.12 shows the interrupt sources in normal serial communication interface mode. A

different interrupt vector is assigned to each interrupt source, and individual interrupt sources can

be enabled or disabled using the enable bits in SCR.

When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag

in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to

perform data transfer. The TDRE flag is cleared to 0 automatically when data is transferred by the

DTC.

When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,

PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt

request can activate the DTC to transfer data. The RDRF flag is cleared to 0 automatically when

data is transferred by the DTC.

A TEI interrupt is requested when the TEND flag is set to 1 and the TEIE bit is set to 1. If a TEI

interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for

acceptance. However, if the TDRE and TEND flags are cleared simultaneously by the TXI

interrupt routine, the SCI cannot branch to the TEI interrupt routine later.

Table 14.12 SCI Interrupt Sources

Channel Name Interrupt Source Interrupt Flag DTC Activation

ERI_0 Receive Error ORER, FER, PER Not possible

RXI_0 Receive Data Full RDRF Possible

TXI_0 Transmit Data Empty T DRE Possible

TEI_0 Transmission End TEND Not possible

ERI_2 Receive Error ORER, FER, PER Not possible

RXI_2 Receive Data Full RDRF Possible

TXI_2 Transmit Data Empty T DRE Possible

TEI_2 Transmission End TEND Not possible

Section 14 Serial Communication Interface (SCI)

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14.8.2 Interrupts in Smart Card Interface Mode

Table 14.13 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt

(TEI) request cannot be used in this mode.

Table 14.13 SCI Interrupt Sources

Channel Name Interrupt Source Interrupt Flag DTC Activation

ERI_0 Receive Error, error

signal detection ORER, PER, ERS Not possible

RXI_0 Receive Data Full RDRF Possible

TXI_0 Transmit Data Empty TEND Possible

ERI_2 Receive Error, error

signal detection ORER, PER, ERS Not possible

RXI_2 Receive Data Full RDRF Possible

TXI_2 Transmit Data Empty TEND Possible

In Smart Card interface mode, as in normal serial communication interface mode, transfer can be

carried out using the DTC. In transmit operations, the TDRE flag is also set to 1 at the same time

as the TEND flag in SSR is set, and a TXI interrupt is generated. If the TXI request is designated

beforehand as a DTC activation source, the DTC will be activated by the TXI request, and

transmit data will be transferred. The TDRE and TEND flags are automatically cleared to 0 when

data is transferred by the DTC. In the event of an error, the SCI retransmits the same data

automatically. During this period, the TEND flag remains cleared to 0 and the DTC is not

activated. Therefore, the SCI and DTC will automatically transmit the specified number of bytes

in the event of an error, including retransmission. However, the ERS flag is not cleared

automatically when an error occurs. Hence, the RIE bit should be set to 1 beforehand so that an

ERI request will be generated in the event of an error, and the ERS flag will be cleared.

When transferring using the DTC, it is essential to set and enable the DTC before carrying out SCI

setting. For details of the DTC setting procedures, refer to section 8, Data Transfer Controller

(DTC).

In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to

1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be

activated by the RXI request, and the receive data will be transferred. The RDRF flag is cleared to

0 automatically when data is transferred by the DTC. If an error occurs, an error flag is set but the

RDRF flag is not. Consequently, the DTC is not activated, instead, an ERI interrupt request is sent

to the CPU. Therefore, the error flag should be cleared.

Section 14 Serial Communication Interface (SCI)

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14.9 Usage Notes

14.9.1 Module Stop Mode Setti ng

SCI operation can be disabled or enabled using the module stop control register. The initial setting

is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For

details, refer to section 21, Pow er-D ow n Modes.

14.9.2 Break Detection and Processing

When framing error detection is performed, a break can be detected by reading the RxD pin value

directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly

the PER flag. Note that as the SCI continues the receive operation after receiving a break, even if

the FER flag is cleared to 0, it will be set to 1 again.

14.9.3 Mark State and Break Detection

When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are

determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send

a break during serial data transmission. To maintain the communication line at mark state until TE

is set to 1, set both DDR and DR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an

I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set

DDR to 1 and DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is

initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is

output from the TxD pin.

14.9.4 Receive Er ror Flags and Trans mit Opera tions (C locked Sy nchronou s Mode On ly )

Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if

the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting

transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared

to 0.

Section 15 Controller Area Network (HCAN)

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Section 15 C ontroller Ar ea Network (HC AN)

The HCAN is a module for controlling a controller area network (CAN) for realtime

communication in vehicular and industrial equipment systems, etc. For details on CAN

specification, refer to Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH.

The block diagram of the HCAN is shown in figure 15.1.

15.1 Features

• CAN version: Bosch 2.0B active compatible

 Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function)

 Broadcast communication system

 Transmission path: Bidirectional 2-wire serial communication

 Communication speed: Max. 1 Mbps

 Data length: 8 to 0 bytes

• Number of channels: 1

• Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception)

• Data transm i ssion: Tw o methods

 Mailbox (buffer) number order (low-to-high)

 Message priority (identifier) reverse-order (high-to-low)

• Data reception: Two methods

 Message identifier match (transmit/receive-setting buffers)

 Reception with message identifier masked (receive-only)

• CPU interrupts: 12

 Error interrupt

 Reset processing interrupt

 Message reception interrupt

 Message transmission interrupt

• HCAN operating modes

• Support for various modes

 Hardware res et

 Software reset

 Normal status (error-active, error-passive)

 Bus off status

 HCAN configuration mode

IFCAN00C_000020020900

Section 15 Controller Area Network (HCAN)

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 HCAN sleep mode

 HCAN halt mode

• Other features

 DTC can be activated by message reception mailbox (HCAN mailbox 0 only)

• Module stop mode can be set

Peripheral address bus

Peripheral data bus

HTxD

MBI

HRxD

CAN

Data Link Controller

MPI

(CDLC)

Tx buffer

Rx buffer

Message buffer

Message control

Message data

MC15 to MC0, MD15 to MD0 LAFM

Mailboxes

Microprocessor interface

CPU interface

Control register

Status register

HCAN

Bosch CAN 2.0B active

Figure 15.1 HCAN Block Diagram

• Message Buffer Interface (MBI)

The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN

transmit/receive messages (identifiers, data, etc.) Transmit messages are written by the CPU.

For receive messages, the data received by the CDLC is stored automatically.

• Microprocessor Interface (MPI)

The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN

internal data, status, and so forth.

• CAN Data Link Controller (CDLC)

The CDLC, conforming to the Bosch CAN Ver. 2.0B active standard, performs transmission

and reception of messages (data frames, remote frames, error frames, overload frames, inter-

frame spacing), as well as CRC checking, bus arbitration, and other functions.

Section 15 Controller Area Network (HCAN)

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15.2 Input/Output Pins

Table 15.1 shows the HCAN’s pins.

When using HCAN pins, settings must be made in the HCAN configuration mode (during

initialization: MCR0 = 1 and GSR3 = 1).

Table 15.1 HCAN Pins

Name Abbreviation Input/Output Function

HCAN transmit data pin HTxD Output CAN bus transmissi on pin

HCAN receive data pin HRxD Input CAN bus reception pin

A bus driver is necessary for the interface between the pins and the CAN bus. A Philips

PCA82C250 compatible model is recommended.

15.3 Register Descriptions

The HCAN has the following registers.

• Master control register (MCR)

• General status register (GSR)

• Bit configuration register (BCR)

• Mailbox configuration register (MBCR)

• Transmit wait register (TXPR)

• Transmit wait cancel register (TXCR)

• Transmit acknowledge register (TXACK)

• Abort acknowledge register (ABACK)

• Receive complete register (RXPR)

• Re mo te req ues t register (RF PR )

• Interrupt register (IRR)

• Mailbox interrupt mask register (MBIMR)

• Interrupt mask register (IMR)

• Receive error counter (REC)

• Transmit error counter (TEC)

• Unread message status register (UMSR)

• Local acceptance filter mask L (LAFML)

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• Local acceptance filter mask H (LAFMH)

• Message control (8 bit × 8 regi ster s × 16 sets) (MC15 to MC0)

• Message data (8 bit × 8 registers × 16 sets) (MD15 to MD0)

• HCAN Monitor Register (HCANMON)

15.3.1 Master Control Register (MCR)

MCR is an 8-bit register that controls the HCAN.

Bit Bit Name Initial Value R/W Description

7 MCR7 0 R/W HCAN Sleep Mode Release

When this bit is set to 1, the HCAN automatically

exits HCAN sleep mode on detection of CAN bus

operation.

60RReserved

This bit is always read as 0. The wri te value should

always be 0.

5 MCR5 0 R/W HCAN Sleep Mode

When this bit is set to 1, the HCAN transits to

HCAN sleep mode. When this bit is cleared to 0,

HCAN sleep mode is released.

4, 3 All 0 R Rese rved

These bits are always read as 0. The write value

should always be 0.

2 MCR2 0 R/W Message Transmission Method

0: Transmission order determined by message

identifier priority

1: Transmission order determined by mail box

(buffer) number priority (TXPR1 > TXPR15)

1 MCR1 0 R/W Halt Request

When this bit is set to 1, the HCAN transits to

HCAN HALT mode. When this bit is cleared to 0,

HCAN HALT mode is released.

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Bit Bit Name Initial Value R/W Description

0 MCR0 1 R/W Reset Request

When this bit is set to 1, the HCAN transits to reset

mode. For details, refer to 15.4.1, Hardware and

Software Resets.

[Setting condition]

• 1-write (software reset)

[Clearing condition]

• When 0 is written to this bit whil e the GSR3 bit

in GSR is 1

15.3.2 General Status Register (GSR)

GSR is an 8-bit register that indicates the status of the CAN bus.

Bit Bit Name Initial Value R/W Description

7 to

4All 0 R Reserved

These bits are always read as 0. The write value

should always be 0.

3 GSR3 1 R Reset Status Bit

Indicates whether the HCAN module is in the

normal operation state or the reset state. This bit

cannot be modified.

[Setting conditions]

• When entering configuration mode after the

HCAN internal reset has finished

• Sleep mode

[Clearing condition]

• When entering the normal operation state after

the MCR0 bi t in MCR is cleared to 0 (Note that

there is a delay between clearing of the MCR0

bit and the GSR3 bit).

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Bit Bit Name Initial Value R/W Description

2 GSR2 1 R Message Transmission Status Fl ag

Flag that indicates whether the module is currently

in the message transmission period. This bit

cannot be modified.

[Setting condition]

• Third bit of Intermission after EOF (End of

Frame)

[Clearing condition]

• Start of message transmission (SOF)

1 GSR1 0 R Transm it/Rece ive Warning Flag

This bit cannot be modified.

[Clearing condition]

• When TEC < 96 and REC < 96 or TEC ≥ 256

(bus off state)

[Setting condition]

• When TEC ≥ 96 or REC ≥ 96

0 GSR0 0 R Bus Off Flag

This bit cannot be modified.

[Setting condition]

• When TEC ≥ 256 (bus off state)

[Clearing condition]

• Recovery from bus off state

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15.3.3 Bit Configuration Register (BCR)

BCR is a 16-bit register that is used to set HCAN bit timing parameters and the baud rate

prescaler. For details on parameters, refer to section 15.4.2, Initialization after Hardware Reset.

Bit Bit Name Initial Value R/W Description

14 BCR7

BCR6 0

0R/W

R/W Re-Synchronization Jump Width (SJW)

Set the maxi mum bit synchronization width.

00: 1 time quantum

01: 2 time quanta

10: 3 time quanta

11: 4 time quanta

BCR5

BCR4

BCR3

BCR2

BCR1

BCR0

R/W

Baud Rate Prescaler (BRP)

Set the length of time quanta.

000000: 2 × system clock

000001: 4 × system clock

000010: 6 × system clock

111111: 128 × system clock

7 BCR15 0 R/W Bi t Sample Po int (BSP)

Sets the point at which data is sampled.

0: Bi t sampling at one point (end of time segment 1

(TSEG1))

1: Bit sampling at three points (end of TSEG1 and

preceding and following time quanta)

BCR14

BCR13

BCR12

R/W

Time Segment 2 (TSEG2)

Set the TSEG2 width wi thin a range of 2 to 8 time

quanta.

000: Setting prohibited

001: 2 time quanta

010: 3 time quanta

011: 4 time quanta

100: 5 time quanta

101: 6 time quanta

110: 7 time quanta

111: 8 time quanta

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Bit Bit Name Initial Value R/W Description

BCR11

BCR10

BCR9

BCR8

R/W

Time Segment 1 (TSEG1)

Set the TSEG1 (PRSEG + PHSEG1) wi dth to

between 16 and 4 time quanta.

0000: Setting prohibited

0001: Setting prohibited

0010: Setting prohibited

0011: 4 time quanta

0100: 5 time quanta

0101: 6 time quanta

0110: 7 time quanta

0111: 8 time quanta

1000: 9 time quanta

1001: 10 time quanta

1010: 11 time quanta

1011: 12 time quanta

1100: 13 time quanta

1101: 14 time quanta

1110: 15 time quanta

1111: 16 time quanta

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15.3.4 Mailbox Configuration Register (MBCR)

MBCR is a 16-bit register that is used to set the transfer direction for each mailbox.

Bit Bit Name Initial Value R/W Description

MBCR7

MBCR6

MBCR5

MBCR4

MBCR3

MBCR2

MBCR1



MBCR15

MBCR14

MBCR13

MBCR12

MBCR11

MBCR10

MBCR9

MBCR8

R/W

These bits set the transfer direction for the

corresponding mailboxes 15 to 1. MBCRn

determines the transfer direction for mailbox n (n =

15 to 1).

0: Corresponding mailbox is set for transmission

1: Corresponding mailbox is set for reception

Bit 8 is reserved. This bit is always read as 1. The

write value should always be 1.

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15.3.5 Transmit Wait Register (TXPR)

TXPR is a 16-bit register that is used to set a transmit wait after a transmit message is stored in a

mailbox (buffer) (CAN bus arbitration wait).

Bit Bit Name Initial Value R/W Description

TXPR7

TXPR6

TXPR5

TXPR4

TXPR3

TXPR2

TXPR1



TXPR15

TXPR14

TXPR13

TXPR12

TXPR11

TXPR10

TXPR9

TXPR8

R/W

These bits set a transmit wait (CAN bus arbitration

wait) for the corresponding mailboxes 15 to 1.

When TXPRn (n = 15 to 1) is set to 1, the message

in mailbox n becomes the transmit wait state.

[Clearing conditions]

• Completion of message transmission

• Completion of transmission cancellation

Bit 8 is reserved. This bit is always read as 1. The

write value should always be 1.

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15.3.6 Transmit Wait Cancel Register (TXCR)

TXCR is a 16-bit register that controls the cancellation of transmit wait messages in mailboxes

(buffers).

Bit Bit Name Initial Value R/W Description

TXCR7

TXCR6

TXCR5

TXCR4

TXCR3

TXCR2

TXCR1



TXCR15

TXCR14

TXCR13

TXCR12

TXCR11

TXCR10

TXCR9

TXCR8

R/W

These bits cancel the transmit wai t message in the

corresponding mail boxes 15 to 1. When TXCRn (n

= 15 to 1) is set to 1, the transmit wait message in

mailbox n is canceled.

[Clearing condition]

• Completion of TXPR clearing when transmit

message is canceled normall y

Bit 8 is reserved. This bit is always read as 0. The

write value should always be 0.

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15.3.7 Transmit Acknowledge Register (TXACK)

TXACK is a 16-bit register containing status flags that indicate the normal transmission of

mailbox (buffer) transmit messages.

Bit Bit Name Initial Value R/W Description

TXACK7

TXACK6

TXACK5

TXACK4

TXACK3

TXACK2

TXACK1



TXACK15

TXACK14

TXACK13

TXACK12

TXACK11

TXACK10

TXACK9

TXACK8

R/(W)*

These bits are status flags that indicate error-free

transmission of the transmit message in the

corresponding mailboxes 15 to 1. When the

message in mailbox n (n = 15 to 1) has been

transmitted error-free, TXACKn is set to 1.

[Setting condition]

• Completion of message transmission for

corresponding mailbox

[Clearing condition]

• Writing 1

Bit 8 is reserved. This bit is always read as 0.

The write value should al ways be 0.

Note: *Only 1 can be written to clear the flag.

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15.3.8 Abort Acknowledge Register (ABACK)

ABACK is a 16-bit register containing status flags that indicate the normal cancellation (aborting)

of mailbox (buffer) transmit messages.

Bit Bit Name Initial Value R/W Description

ABACK7

ABACK6

ABACK5

ABACK4

ABACK3

ABACK2

ABACK1



ABACK15

ABACK14

ABACK13

ABACK12

ABACK11

ABACK10

ABACK9

ABACK8

R/(W)*

These bits are status flags that indicate error-free

cancellation (abortion) of the transmit message in

the corresponding mailboxes 15 to 1. When the

message in mailbox n (n = 15 to 1) has been

canceled error-free, ABACKn is set to 1.

[Setting condition]

• Completion of transmit message cancellation

for corresponding mailbox

[Clearing condition]

• Writing 1

Bit 8 is reserved. This bit is always read as 0.

The write value should al ways be 0.

Note: *Only 1 can be written to clear the flag.

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15.3.9 Receive Complete Register (RXPR)

RXPR is a 16-bit register containing status flags that indicate the normal reception of messages in

mailboxes (buffers). For reception of a remote frame, when a bit in this register is set to 1, the

corresponding remote request register (RFPR) bit is also set to 1 simultaneously.

Bit Bit Name Initial Value R/W Description

RXPR7

RXPR6

RXPR5

RXPR4

RXPR3

RXPR2

RXPR1

RXPR0

RXPR15

RXPR14

RXPR13

RXPR12

RXPR11

RXPR10

RXPR9

RXPR8

R/(W)*

When the message in mailbox n (n = 15 to 1) has

been received error-free, RXPRn is set to 1.

[Setting condition]

• Completi on of message (data frame or

remote frame) reception in corresponding

mailbox

[Clearing condition]

• Writing 1

Note: *Only 1 can be written to clear the flag.

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15.3.10 Remote Request Register (RFPR)

RFPR is a 16-bit register containing status flags that indicate normal reception of remote frames in

mailboxes (buffers). When a bit in this register is set to 1, the corresponding receive complete

Bit Bit Name Initial Value R/W Description

RFPR7

RFPR6

RFPR5

RFPR4

RFPR3

RFPR2

RFPR1

RFPR0

RFPR15

RFPR14

RFPR13

RFPR12

RFPR11

RFPR10

RFPR9

RFPR8

R/(W)*

When mailbox n (n = 15 to 0) has received the

remote frame error-free, RFPRn (n = 15 to 1) is

set to 1.

[Setting condition]

• Completion of remote frame reception in

corresponding mailbox

[Clearing condition]

• Writing 1

Note: *Only 1 can be written to clear the flag.

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15.3.11 Interrupt Register (IRR)

IRR is a 16-bit interrupt status flag register.

Bit Bit Name Initial Value R/W Description

15 IRR7 0 R/(W)*Overload Frame Interrupt Flag

Status flag indicating on overload frame has been

transmitted by HCAN.

[Setting condition]

• When an overload frame is transmitted in error

active/passive state

[Clearing condition]

• Writing 1

14 IRR6 0 R/(W)*Bus Off Interrupt Flag

Status flag indicating the bus off state caused by

the transmit error counter.

[Setting condition]

• When TEC ≥ 256

[Clearing condition]

• Writing 1

13 IRR5 0 R/(W)*Error Passive Interrupt Flag

Status flag indicating the error passive state

caused by the transmit/receive error counter.

[Setting condition]

• When TEC ≥ 128 or REC ≥ 128

[Clearing condition]

• Writing 1

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Bit Bit Name Initial Value R/W Description

12 IRR4 0 R/(W)*Receive Overload Warning Interrupt Flag

Status flag indicating the error warning state

caused by the receive error counter.

[Setting condition]

• When REC ≥ 96

[Clearing condition]

• Writing 1

11 IRR3 0 R/(W)*Transmit Overload W arning Interrupt Flag

Status flag indicating the error warning state

caused by the transmit error counter.

[Setting condition]

• When TEC ≥ 96

[Clearing condition]

• Writing 1

10 IRR2 0 R Remote Frame Request Interrupt Flag

Status flag indicating that a remote frame has

been received in a mailbox (buffer), when MBIMR

= 0.

[Setting condition]

• When remote frame reception is completed,

when corresponding MBIMR = 0

[Clearing condition]

• Clearing of all bits in RFPR (remote request

9 IRR1 0 R Receive Message Interrupt Flag

Status flag indicating that a mailbox (buffer)

receive message has been received normally,

when MBIMR = 0.

[Setting condition]

• When data frame or remote frame reception is

completed, when corresponding MBIMR = 0

[Clearing condition]

• Clearing of all bits in RXPR (receive complete

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Bit Bit Name Initial Value R/W Description

8 IRR0 1 R/(W)*Reset Interrupt Flag

Status flag indicating that the HCAN module has

been reset. This bit cannot be masked by the

interrupt mask register (IMR). If this bit is not

cleared to 0 after entering power-on reset or

returning from software standby mode, interrupt

processing will start immediately when the

interrupt controller enables interrupts.

[Setting condition]

• When the reset operation has finished after

entering power-on reset or software standby

mode

[Clearing condition]

• Writing 1

7 to

5All 0 Reserved

These bits are always read as 0. The write value

should always be 0.

4 IRR12 0 R/(W)*Bus Operation Interrupt Flag

Status flag indicating detection of a dominant bit

due to bus operation when the HCAN module is in

HCAN sleep mode.

[Setting condition]

• Bus operation (dominant bit) detection in

HCAN sleep mode

[Clearing condition]

• Writing 1

3, 2 All 0 Reserved

These bits are always read as 0. The write value

should always be 0.

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Bit Bit Name Initial Value R/W Description

1 IRR9 0 R Unread Interrupt Flag

Status flag indicating that a receive message has

been overwritten before being read.

[Setting condition]

• When UMSR (unread message status

[Clearing condition]

• Clearing of all bits in UMSR (unread message

status register)

0 IRR8 0 R/(W)*Mailbox Empty Interrupt Flag

Status flag indicating that the next transmit

message can be stored in the mailbox.

[Setting condition]

• When TXPR (transmit wait register) is cleared

by completion of transmission or completion of

transmission abort

[Clearing condition]

• Writing 1

Note: *Only 1 can be written to clear the flag.

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15.3.12 Mailbox Interrupt Mask Register (MBIMR)

MBIMR is a 16-bit register that controls the enabling or disabling of individual mailbox (buffer)

interrupt requests.

Bit Bit Name Initial Value R/W Description

MBIMR7

MBIMR6

MBIMR5

MBIMR4

MBIMR3

MBIMR2

MBIMR1

MBIMR0

MBIMR15

MBIMR14

MBIMR13

MBIMR12

MBIMR11

MBIMR10

MBIMR9

MBIMR8

R/W

Mailbox Interrupt Mask (MBIMRx)

When MBIMRn (n = 15 to 1) is cleared to 0, the

interrupt request in mailbox n is enabled. When set

to 1, the interrupt request is masked.

The interrupt source in a transmit mailbox is TXPR

clearing caused by transmission end or

transmission cancellation. The interrupt source in a

receive mailbox is RXPR setting on reception end.

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15.3.13 Interrupt Mask Register (IMR)

IMR is a 16-bit register containing flags that enable or disable requests by individual interrupt

sources . The rese t interrupt flag canno t be masked.

Bit Bit Name Initial Value R/W Description

15 IMR7 1 R/W Overload Frame Interrupt Mask

When this bit is cleared to 0, an interrupt request

by IRR7 (OVR0) is enabled. When set to 1, it is

masked.

14 IMR6 1 R/W Bus Off Interrupt Mask

When this bit is cleared to 0, an interrupt request

by IRR6 (ERS0) is enabled. When set to 1, it is

masked.

13 IMR5 1 R/W Error Passive Interrupt Mask

When this bit is cleared to 0, an interrupt request

by IRR5 (ERS0) is enabled. When set to 1, it is

masked.

12 IMR4 1 R/W Receive Overload Warning Interrupt Mask

When this bit is cleared to 0, an interrupt request

by IRR4 (OVR0) is enabled. When set to 1, it is

masked.

11 IMR3 1 R/W Transmit Overload Warning Interrupt Mask

When this bit is cleared to 0, an interrupt request

by IRR3 (OVR0) is enabled. When set to 1, it is

masked.

10 IMR2 1 R/W Remote Frame Request Interrupt Mask

When this bit is cleared to 0, an interrupt request

by IRR2 (OVR0) is enabled. When set to 1, it is

masked.

9 IMR1 1 R/W Receive Message Interrupt Mask

When this bit is cleared to 0, an interrupt request

by IRR1 (RM1) is enabled. When set to 1, it is

masked.

80RReserved

This bit is always read as 0. The wri te value should

always be 0.

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Bit Bit Name Initial Value R/W Description

7 to

5All 1 R Reserved

These bits are always read as 1. The write value

should always be 0.

4 IMR12 1 R/W Bus Operation Interrupt Mask

When this bit is cleared to 0, an interrupt request

by IRR12 (OVR0) is enabled. When set to 1, it is

masked.

3, 2 All 1 R Rese rved

These bits are always read as 1. The write value

should always be 0.

1 IMR9 1 R/W Unread Interrupt Mask

When this bit is cleared to 0, an interrupt request

by IRR9 (OVR0) is enabled. When set to 1, it is

masked.

0 IMR8 1 R/W Mailbox Empty Interrupt Mask

When this bit is cleared to 0, an interrupt request

by IRR8 (SLE0) is enabled. When set to 1, it is

masked.

15.3.14 Receive Error Counter (REC)

The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating

the number of receive message errors on the CAN bus. The count value is stipulated in the CAN

protocol.

15.3.15 Transmit Error Counter (TEC)

The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter

indicating the number of transmit message errors on the CAN bus. The count value is stipulated in

the CAN protocol.

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15.3.16 Unread Message Status Register (UMSR)

UMSR is a 16-bit register containing status flags that indicate, for individual mailboxes (buffers),

that a received message has been overwritten by a new receive message before being read. When

overwritten by a new message, data in the unread receive message is lost.

Bit Bit Name Initial Value R/W Description

UMSR7

UMSR6

UMSR5

UMSR4

UMSR3

UMSR2

UMSR1

UMSR0

UMSR15

UMSR14

UMSR13

UMSR12

UMSR11

UMSR10

UMSR9

UMSR8

R/(W)*

The received message has been overwritten by a

new message before being read.

[Setting condition]

• When a new message is received before

RXPR is cleared

[Clearing condition]

• Writing 1

Note: *Only 1 can be written to clear the flag.

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15.3.17 Local Accep tan ce Fil ter Ma sks (LA FML, LAFMH )

LAFML and LAFMH are 16-bit registers that individually set the identifier bits of the message to

be stored in mailbox 0 as Don’t Care. For details, refer to section 15.4.4, Message Reception. The

relationship between the identifier bits and mask bits are shown in the following.

• LAFML

Bit Bit Name Initial Value R/W Description

LAFML7

LAFML6

LAFML5

LAFML4

LAFML3

LAFML2

LAFML1

LAFML0

LAFML15

LAFML14

LAFML13

LAFML12

LAFML11

LAFML10

LAFML9

LAFML8

R/W

When this bit is set to 1, ID-7 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-6 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-5 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-4 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-3 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-2 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-1 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-0 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-15 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-14 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-13 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-12 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-11 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-10 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-9 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-8 of the receive

m essage identifier is not com pared.

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• LAFMH

Bit Bit Name Initial Value R/W Description

LAFMH7

LAFMH6

LAFMH5

R/W

When this bit is set to 1, ID-20 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-19 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-18 of the receive

m essage identifier is not com pared.

12 to 10 All 0 R Reserve d

These bits are always read as 0. The write value

should always be 0.

LAFMH1

LAFMH0

LAFMH15

LAFMH14

LAFMH13

LAFMH12

LAFMH11

LAFMH10

LAFMH9

LAFMH8

R/W

When this bit is set to 1, ID-17 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-16 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-28 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-27 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-26 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-25 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-24 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-23 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-22 of the receive

m essage identifier is not com pared.

When this bit is set to 1, ID-21 of the receive

m essage identifier is not com pared.

Section 15 Controller Area Network (HCAN)

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15.3.18 Message Control (MC15 to MC0)

The message control register sets consist of eight 8-bit registers for one mailbox. The HCAN has

16 sets of these registers. Because message control registers are in RAM, their initial values after

power-on are undefined. Be sure to initialize them by writing 1 or 0. Figure 15.2 shows the

MC0[1]

MC1[1]

MC2[1]

MC3[1]

MC15[1]

MC0[2]

MC1[2]

MC2[2]

MC3[2]

MC15[2]

MC0[3]

MC1[3]

MC2[3]

MC3[3]

MC15[3]

MC0[4]

MC1[4]

MC2[4]

MC3[4]

MC15[4]

MC0[5]

MC1[5]

MC2[5]

MC3[5]

MC15[5]

MC0[6]

MC1[6]

MC2[6]

MC3[6]

MC15[6]

MC0[7]

MC1[7]

MC2[7]

MC3[7]

MC15[7]

MC0[8]

MC1[8]

MC2[8]

MC3[8]

MC15[8]

Mail box 0

Mail box 1

Mail box 2

Mail box 3

Mail box 15

Figure 15.2 Message Control Register Configuration

The setting of message control registers are shown in the following. Figures 15.3 and 15.4 show

the correspondence between the identifiers and register bit names.

SOF ID-28 ID-27 ID-18 RTR IDE R0

identifier

Figure 15.3 Standard Format

SOF ID-28 ID-27 ID-18 SRR IDE ID-17 ID-16 ID-0 RTR R1

Standard identifier Extended identifier

Figure 15.4 Extended Format

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Name Bit Bit Name R/W Description

7 to 4 R/W The initial value of these bits is undefined. They

must be initialized by writing 0 or 1.

MCx[1]

3 to 0 DLC3 to DLC0 R/W Data Length Code

Set the data length of a data frame or the data

length requested in a remote frame within the

range of 0 to 8 bits.

0000: 0 bytes

0001: 1 byte

0010: 2 bytes

0011: 3 bytes

0100: 4 bytes

0101: 5 bytes

0110: 6 bytes

0111: 7 bytes

1***: 8 bytes

MCx[2]

MCx[3]

MCx[4]

7 to 0



R/W

The initial value of these bits is undefined; they

must be initialized by writing 0 or 1.

7 to 5 ID-20 to ID-18 R/W Sets ID-20 to ID-18 in the identifier.

4 RTR R/W Remote Transmission Request

Used to di stinguish between data frames and

remote frames.

0: Data frame

1: Remote fra me

3 IDE R/W Identifier Extension

Used to distinguish between the standard format

and extended format of data frames and remote

frames.

0: Standard format

1: Extended format

2R/W The initial value of this bit is undefined. It must be

initialized by writing 0 or 1.

MCx[5]

1 to 0 ID-17 to ID-16 R/W Sets ID-17 and ID-16 in the identifier.

MCx[6] 7 to 0 ID-28 to ID-21 R/W Sets ID-28 to ID-21 in the identifier.

MCx[7] 7 to 0 ID-7 to ID-0 R/W Sets ID-7 to ID-0 in the identifier.

MCx[8] 7 to 0 ID-15 to ID-8 R/W Sets ID-15 to ID-8 in the identifier.

Note: x: Mailbox number

Section 15 Controller Area Network (HCAN)

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15.3.19 Message Data (MD15 to MD0)

The message data register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16

sets of these registers. Because message data registers are in RAM, their initial values after power-

on are undefined. Be sure to initialize them by writing 1 or 0. Figure 15.5 shows the register

names for each mailbox.

MD0[1]

MD1[1]

MD2[1]

MD3[1]

MD15[1]

MD0[2]

MD1[2]

MD2[2]

MD3[2]

MD15[2]

MD0[3]

MD1[3]

MD2[3]

MD3[3]

MD15[3]

MD0[4]

MD1[4]

MD2[4]

MD3[4]

MD15[4]

MD0[5]

MD1[5]

MD2[5]

MD3[5]

MD15[5]

MD0[6]

MD1[6]

MD2[6]

MD3[6]

MD15[6]

MD0[7]

MD1[7]

MD2[7]

MD3[7]

MD15[7]

MD0[8]

MD1[8]

MD2[8]

MD3[8]

MD15[8]

Mail box 0

Mail box 1

Mail box 2

Mail box 3

Mail box 15

Figure 15.5 Message Data Configuration

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15.3.20 HCAN Monitor Register (HCANMON)

HCANMON is an 8-bit register that enables/disables an HCAN receive interrupt, controls

transmission stop of the HTxD pin, and reflects the states of the HCAN pins.

Bit Bit Name Initial Value R/W Description

7 RxDIE 0 R/W HRxD Interrupt Enable

Selects whether an

IRQ2

interrupt is caused by

PF0 or HRxD pin.

0: An

IRQ2

interrupt is caused by pin PF0

1: An

IRQ2

interrupt is caused by the HRxD pin

6 TxSTP 0 R/W HTxD Transmission Stop

Controls transmission stop of the HTxD pin.

0: Enabl es transmission from the HTxD pin

1: Fixes an output level of the HTxD pin at 1 and

transmission is stopped

5 to 2 Undefined Reserved

These bits are always read as undefined values

and cannot be modified.

1 TxD Undefined R Transmission pin

The state of the HTxD pin is read.

This bit cannot be modified.

0 RxD Undefined R Reception pin

The state of the HRxD pin is read.

This bit cannot be modified.

Section 15 Controller Area Network (HCAN)

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15.4 Operation

15.4.1 Hardware and Software Resets

The HCAN can be reset by a hardware reset or software reset.

• Hardware Reset

At power-on reset, or in hardware or software standby mode, the HCAN is initialized by

automatically setting the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3)

in GSR. At the same time, all internal registers, except for message control and message data

registers, are initialized by a hardware reset.

• Software Reset

The HCAN can be reset by setting the MCR reset request bit (MCR0) in MCR via software. In

a software reset, the error counters (TEC and REC) are initialized, however other registers are

not. If the MCR0 bit is set while the CAN controller is performing a communication operation

(transmission or reception), the initialization state is not entered until message transfer has

been completed. The reset status bit (GSR3) in GSR is set on completion of initialization.

15.4.2 Initialization after Hardware Reset

After a hardware reset, the following initialization processing should be carried out:

1. Clearing of IRR0 bit in the interrupt register (IRR)

2. Bit rate setting

3. Mailbox transmit/receive settings

4. Mailbox (RAM) initialization

5. Message transmission method setting

These initial settings must be made while the HCAN is in bit configuration mode. Configuration

mode is a state in which the GSR3 bit in GSR is set to 1 by a reset. Configuration mode is exited

by clearing the MCR0 bit in MCR to 0; when the MCR0 bit is cleared to 0, the HCAN

automatically clears the GSR3 bit in GSR. There is a delay between clearing the MCR0 bit and

clearing the GSR3 bit because the HCAN needs time to be internally reset. After the HCAN exits

configuration mode, the power-up sequence begins, and communication with the CAN bus is

possible as soon as 11 consecutive recessive bits have been detected.

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IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery

from software standby mode. Since an HCAN interrupt is initiated immediately when interrupts

are enabled, IRR0 should be cleared.

Hardware reset

MCR0 = 1 (automatic)

IRR0 = 1 (automatic)

GSR3 = 1 (automatic)

MCR0 = 0

GSR3 = 0?

Yes

GSR3 = 0 & 11

recessive bits received?

Can bus communication enabled

Yes

Bit configuration mode

Period in which BCR, MBCR, etc.,

are initialized

: Settings by user

: Processing by hardware

Initialization of HCAN module

Clear IRR0

BCR setting

MBCR setting

Mailbox initialization

Message transmission method initialization

IMR setting (interrupt mask setting)

MBIMR setting (interrupt mask setting)

MC[x] setting (receive identifier setting)

LAFM setting (receive identifier mask setting)

Figure 15.6 Hardware Reset Flowchart

Section 15 Controller Area Network (HCAN)

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MCR0 = 1

MCR0 = 0

GSR3 = 0?

CAN bus communication enabled

Bus idle?

Yes

Correction

Yes

Correction

: Settings by user

: Processing by hardware

Yes

GSR3 = 1?

BCR setting

MBCR setting

Mailbox (RAM) initialization

Message transmission method

initialization

OK?

IMR setting

MBIMR setting

MC[x] setting

LAFM setting

OK?

GSR3 = 0 &

11 recessive bits received?

Yes

Initialization of REC and TEC only

GSR3 = 1 (automatic)

Yes

Figure 15.7 Software Reset Flowchart

Section 15 Controller Area Network (HCAN)

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Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit

configuration register (BCR). Settings should be made such that all CAN controllers connected to

the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the

settable time quanta (tq).

SYNC_SEG PRSEG PHSEG1 PHSEG2

Time segment 2

(TSEG2)

Time segment 1 (TSEG1)

1-bit time (25 to 8 time quanta)

4 to 16 time quanta 2 to 8 time quanta1 time quanta

Figure 15.8 Detailed Description of One Bit

SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal

bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical

delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This

segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer

segment for correcting phase drift (negative). This segment is shortened when synchronization

(resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, BSP, and

SJW) are shown in table 15.2.

Table 15.2 Limits for the Settable Value

Name Abbreviation Min. Value Max. Value

Time segment 1 TSEG1 B'0011*2B'1111

Time segment 2 TSEG2 B'001*3B'111

Baud rate prescaler BRP B'000000 B'111111

Bit sample point BSP B'0 B'1

Re-synchronization jump width SJW*1B'00 B'11

Notes: 1. SJW is stipulated in the CAN specifications:

3 ≥ SJW ≥ 0

2. The minimum value of TSEG2 is stipulated in the CAN specifications:

TSEG2 ≥ SJW

3. The minimum value of TSEG1 is stipulated in the CAN specifications:

TSEG1 > TSEG2

Section 15 Controller Area Network (HCAN)

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Time quanta (tq) is an integer multiple of the number of system clocks, and is determined by the

baud rate prescaler (BRP) as follows. fCLK is the system clock frequency.

tq = 2 × (BPR setting + 1)/fCLK

The following formula is used to calculate the 1-bit time and bit rate.

1-bit time = tq × (3 + TSEG1 + TSEG2)

Bit rate = 1/Bit time

= fCLK/{2 × (BPR setting + 1) × (3 + TSEG1 + TSEG2)}

Note: fCLK = φ (system clock)

A BCR value is used for BRP, TSEG1, and TSEG2.

Example: With a system clock of 24 MHz, a BRP setting of B'000000, a TSEG1 setting of

B'0101, and a TSEG2 setting of B'100:

Bit rate = 24/{2 × (0 + 1) × (3 + 5 + 4 )} = 1 Mbps

Table 15.3 Setting Range for TSEG1 and TSEG2 in BCR

TSEG2 (BCR14 to BCR12)

001 010 011 100 101 110 111

0011 No Yes No No No No NoTSEG1

(BCR11 to BCR8) 0100 Yes*Yes Yes No No No No

0101 Yes*Yes Yes Yes No No No

0110 Yes*Yes Yes Yes Yes No No

0111 Yes*Yes Yes Yes Yes Yes No

1000 Yes*Yes Yes Yes Yes Yes Yes

1001 Yes*Yes Yes Yes Yes Yes Yes

1010 Yes*Yes Yes Yes Yes Yes Yes

1011 Yes*Yes Yes Yes Yes Yes Yes

1100 Yes*Yes Yes Yes Yes Yes Yes

1101 Yes*Yes Yes Yes Yes Yes Yes

1110 Yes*Yes Yes Yes Yes Yes Yes

1111 Yes*Yes Yes Yes Yes Yes Yes

Note: The time quantum values for TSEG1 and TSEG2 are determined by TSEG value + 1.

* Settable when bits BRP is not B'000000.

Section 15 Controller Area Network (HCAN)

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Mailbox Transmit/Receive Settings: The HCAN has 16 mailboxes. Mailbox 0 is receive-only,

while mailboxes 15 to 1 can be set for transmission or reception. The initial status of mailboxes 15

to 1 is for transmission. Mailbox transmit/receive settings are not initialized by a software reset.

Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding

mailbox for transmission use, whereas a setting of 1 in MBCR designates the corresponding

mailbox for reception use. When setting mailboxes for reception, in order to improve message

reception efficiency, high-priority messages should be set in low-to-high mailbox order.

Mailbox (Message Control/Data) Initial Settings: Message control/data are held in RAM, and

so their initial values are undefined after power is supplied. Initial values must therefore be set in

all the mailboxes (by writing 0s or 1s).

Setting the Messa ge Trans miss ion Me thod : The following two kinds of message transmission

methods are available.

• Transmission order determined by message identifier priority

• Transmission order determined by mailbox number priority

Either of the message transmission methods can be selected with the message transmission method

bit (MCR2) in the master control register (MCR): When messages are set to be transmitted

according to the message identifier priority, if several messages are designated as waiting for

transmission (TXPR = 1), the message with the highest priority in the message identifier is stored

in the transmit buffer. CAN bus arbitration is then carried out for the message stored in the

transmit buffer, and the message is transmitted when the transmission right is acquired. When the

TXPR bit is set, the highest-priority message is found and stored in the transmit buffer.

When messages are set to be transmitted according to the mailbox number priority, if several

messages are designated as waiting for transmission (TXPR = 1), messages are stored in the

transmit buffer in low-to-high mailbox order. CAN bus arbitration is then carried out for the

message stored in the transmit buffer, and the message is transmitted when the transmission right

is acquired.

15.4.3 Message Transmission

Messages are transmitted using mailboxes 15 to 1. The transmission procedure after initial settings

is described below, and a transmission flowchart is shown in figure 15.9.

Section 15 Controller Area Network (HCAN)

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Initialization (after hardware reset only)

Clear IRR0

BCR setting

MBCR setting

Mailbox initialization

Message transmission method setting

Yes

: Settings by user

: Processing by hardware

Interrupt settings

Transmit data setting

Arbitration field setting

Control field setting

Data field setting

Message transmission

GSR2 = 0 (during transmission only)

TXACK = 1

IRR8 = 1

Clear TXACK

Clear IRR8

Message transmission wait

TXPR setting

Bus idle?

Transmission completed?

IMR8 = 1?

Interrupt to CPU

End of transmission

Figure 15.9 Transmission Flowchart

CPU Interrupt Source Settings: The CPU interrupt source is set by the interrupt mask register

(IMR) and mailbox interrupt mask register (MBIMR). Transmission acknowledge and

Section 15 Controller Area Network (HCAN)

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transmission abort acknowledge interrupts can be generated for individual mailboxes in the

mailbox interrupt mask register (MBIMR).

Arbitration Field Set ting: The arbitration field is set by the message control registers MCx[8] to

MCx[5] in a transmit mailbox. For a standard format, an 11-bit identifier (ID-28 to ID-18) and the

RTR bit are set, and the IDE bit is cleared to 0. For an extended format, a 29-bit identifier (ID-28

to ID-0) and the RTR bit are set, and the IDE bit is set to 1.

Control Field Setting: In the control field, the byte length of the data to be transmitted is set

within the range of zero to eight bytes. The register to be set is the message control register

MCx[1] in a transmit mailbox.

Data Field Setting: In the data field, the data to be transmitted is set within the range zero to

eight. The registers to be set are the message data registers MDx[8] to MDx[1]. The byte length of

the data to be transmitted is determined by the data length code in the control field. Even if data

exceeding the value set in the control field is set in the data field, up to the byte length set in the

control field will actually be transmitted.

Message Transmission: If the corresponding mailbox transmit wait bit (TXPR15 to TXPR1) in

the transmit wait register (TXPR) is set to 1 after message control and message data registers have

been set, the message enters transmit wait state. If the message is transmitted error-free, the

corresponding acknowledge bit (TXACK15 to TXACK1) in the transmit acknowledge register

(TXACK) is set to 1, and the corresponding transmit wait bit (TXPR15 to TXPR1) in the transmit

wait register (TXPR) is automatically cleared to 0. Also, if the corresponding bit (MBIMR1 to

MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit

(IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts,

inte r rup ts ma y be sen t to th e C PU.

If transmission of a transmit message is aborted in the following cases, the message is

retransmitted automatically:

• CAN bus arbitration failure (failure to acquire the bus)

• Error during transmission (bit error, stuff error, CRC error, frame error, or ACK error)

Message Transmission Cancellation: Transmission cancellation can be specified for a message

stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the

bit for the corresponding mailbox (TXCR15 to TXCR1) to 1 in the transmit cancel register

(TXCR). Clearing the transmit wait register (TXPR) does not cancel transmission. When

cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the

corresponding bit is set to 1 in the abort acknowledge register (ABACK), and then an interrupt to

the CPU can be requested. Also, if the corresponding bit (MBIMR15 to MBIMR1) in the mailbox

Section 15 Controller Area Network (HCAN)

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interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask

However, a transmit wait message cannot be canceled at the following times:

• During internal arbitration or CAN bus arbitration

• During data frame or remote frame transmission

Figure 15.10 shows a flowchart for transmit message cancellation.

Message transmit wait TXPR setting

Yes

: Settings by user

: Processing by hardware

Set TXCR bit corresponding to

message to be canceled

Message not sent

Clear TXCR, TXPR

ABACK = 1

IRR8 = 1

Clear TXACK

Clear ABACK

Clear IRR8

Completion of message transmission

TXACK = 1

Clear TXCR, TXPR

IRR8 = 1

Cancellation possible?

IMR8 = 1?

End of transmission/transmission

cancellation

Interrupt to CPU

Figure 15.10 Transmit Message Cancellation Flowchart

Section 15 Controller Area Network (HCAN)

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15.4.4 Message Reception

The reception procedure after initial settings is described below. A reception flowchart is shown in

Figure 15.11.

RXPR

IRR1 = 1

IMR2 = 1?

Interrupt to CPU

Yes

Yes Yes

: Settings by user

: Processing by hardware

Yes

InitializationClear IRR0

BCR setting

MBCR setting

Mailbox (RAM) initialization

Receive data setting

Arbitration field setting

Local acceptance filter settings

Interrupt settings

Message reception

(Match of identifier

in mailbox?)

Same RXPR = 1?

IMR1 = 1?

Data frame?

Interrupt to CPU

Clear IRR1

End of reception

Clear IRR2, IRR1

Unread message

RXPR, RFPR = 1

IRR2 = 1, IRR1 = 1

Message control read

Message data read Message control read

Message data read

Transmission of data frame corresponding

to remote frame

Figure 15.11 Reception Flowchart

Section 15 Controller Area Network (HCAN)

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CPU Interrupt Source Settings: CPU interrupt source settings are made in the interrupt mask

specified. Data frame and remote frame receive wait interrupt requests can be generated for

individual mailboxes in the MBIMR.

Arbitration Field Set ting: To receive a message, the message identifier must be set in advance in

the message control registers (MCx[8] to MCx[1]) for the receiving mailbox. When a message is

received, all the bits in the receive message identifier are compared with those in each message

control register identifier, and if a complete match is found, the message is stored in the matching

mailbox. Mailbox 0 has a local acceptance filter mask (LAFM) that allows Don’t Care settings.

The LAFM setting can be made only for mailbox 0. By setting the Don’t Care for all the bits in the

receive message identifier, messages of multiple identifiers can be received.

Examples:

• When the identifier of mailbox 1 is 010_1010_1010 (standard format), only one kind of

message identifier can be received by mailbox 1:

Identifier 1: 010_1010_1010

• When the identifier of mailbox 0 is 010_1010_1010 (standard format) and the LAFM setting is

000_0000_0011 (0: Care, 1: Don’t Care), a total of four kinds of message identifiers can be

received by mailbox 0:

Identifier 1: 010_1010_1000

Identifier 2: 010_1010_1001

Identifier 3: 010_1010_1010

Identifier 4: 010_1010_1011

Message Reception: When a message is received, a CRC check is performed automatically. If the

result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether

the message can be received or not.

• Data fr am e rece ption

If the received message is confirmed to be error-free by the CRC check, the identifier in the

mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive

message are compared. If a complete match is found, the message is stored in the matching

mailbox. The message identifier comparison is carried out on each mailbox in turn, starting

with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison

ends at that point, the message is stored in the matching mailbox, and the corresponding

receive complete bit (RXPR15 to RXPR0) in the receive complete register (RXPR) is set.

However, if the identifier matches that of mailbox 0 LAFM, the mailbox comparison sequence

does not end at that point, but continues from mailbox 1. Therefore, the message for mailbox 0

Section 15 Controller Area Network (HCAN)

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can also be received by another mailbox. Note that the same message cannot be stored in two

or more mailbox of the mailboxes 15 to 1. On receiving a message, a CPU interrupt request

may be generated according to the settings of the mailbox interrupt mask register (MBIMR)

and interrupt mask register (IMR).

• Rem ote fr am e recepti on

A mailbox can store two kinds of messages: data frames and remote frames. A remote frame

differs from a data frame in the value of the remote transmission request bit (RTR) in the

message control register and its 0-byte data field. The data length to be returned in a data frame

must be stored in the data length code (DLC) in the message control.

When a remote frame (RTR = recessive) is received, the corresponding bit in the remote

request wait register (RFPR) is set. Interrupts can be sent to the CPU according to the settings

of the corresponding bit (MBIMR15 to MBIMR0) in the mailbox interrupt mask register

(MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register

(IMR).

Unread Mes sag e Overw ri te : If the receive message identifier matches the mailbox identifier, the

receive message is stored in the mailbox regardless of whether the mailbox contains an unread

message or not. If a message overwrite occurs, the corresponding bit (UMSR15 to UMSR0) in the

unread message register (UMSR) is set. In overwriting an unread message, the unread message

complete register (RXPR) has been cleared. If the unread interrupt flag (IRR9) in the interrupt

mask register (IMR) is set to enable interrupts at this time, an interrupt can be sent to the CPU.

Figure 15.12 shows a flowchart for unread message overwriting.

Section 15 Controller Area Network (HCAN)

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: Settings by user

Unread message overwrite

Interrupt to CPU

End

IMR9 = 1?

UMSR = 1

IRR9 = 1

Clear IRR9

Message control/message data read

: Processing by hardware

Yes

Figure 15.12 Unread Message Overwrite Flowchart

15.4.5 HCAN Sleep Mode

The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep

state in order to reduce current consumption. Figure 15.13 shows a flowchart of the HCAN sleep

mode.

Section 15 Controller Area Network (HCAN)

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IRR12 = 1

Yes

MCR5 = 0

Clear sleep mode?

Yes

Yes (manual)

No (automatic)

MCR5 = 1

Bus idle?

Initialize TEC and REC

Bus operation?

: Settings by user

MB should

not be

accessed.

: Processing by hardware

Yes

GSR3 = 1?

IMR12 = 1?

Sleep mode clearing method

MCR7 = 0?

11 recessive bits

received?

CAN bus communication possible

CPU interrupt

GSR3 = 1?

MCR5 = 0

Figure 15.13 HCAN Sleep Mode Flowchart

Section 15 Controller Area Network (HCAN)

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HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master

control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is

delayed until the bus becomes idle.

Either of the following methods of clearing HCAN sleep mode can be selected:

• Clearing by software

• Clearing by CAN bus operation

In order to re-enter CAN bus communication enabled state, eleven recessive bits must be received

after HCAN sleep mode was cleared.

Clearing by Software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU.

Clearing by CAN Bus Operation: The cancellation method is selected by the MCR7 bit setting

in MCR. Clearing by CAN bus operation occurs automatically when the CAN bus performs an

operation and this change is detected. In this case, the first message is not stored in a mailbox;

messages will be received normally from the second message onward. When a change is detected

on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the

interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is

set to enable interrupts at this time, an interrupt can be sent to the CPU.

Section 15 Controller Area Network (HCAN)

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15.4.6 HCAN Halt Mode

The HCAN halt mode is provided to enable mailbox settings to be changed without performing an

HCAN hardware or software reset. Figure 15.14 shows a flowchart of the HCAN halt mode.

MCR1 = 1

Yes

: Settings by user

: Processing by hardware

Bus idle?

Set MBCR

MCR1 = 0

CAN bus communication possible

Figure 15.14 HCAN Halt Mode Flowchart

HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control

the bus becomes idle.

HCAN halt mode is cleared by clearing MCR1 to 0.

Section 15 Controller Area Network (HCAN)

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15.5 Interrupt Sources

Table 15.4 lists the HCAN interrupt sources. These sources can be masked except the reset

processing interrupt by power-on reset (IRR0). Masking is implemented using the mailbox

interrupt mask register (MBIMR), interrupt mask register (IMR), and IRQ enable register (IER).

For details on the interrupt vector of each interrupt source, refer to section 5, Interrupt Controller.

Table 15.4 HCAN Interrupt Sources

Name Description Interrupt

Flag DTC

Activation

Error passiv e interrupt (TE C ≥ 128 or REC ≥ 128) IRR5

Bus off interrupt (TEC ≥ 256) IRR6

Reset processing interrupt by power-on reset IRR0

Remote frame reception IRR2

Error warning interrupt (TEC ≥ 96) IRR3

Error warning interrupt (REC ≥ 96) IRR4

Overload frame transmission interrupt IRR7

Unread message overwrite IRR9

ERS0/OVR0

Detection of CAN bus operation in HCAN sleep mode IRR12

Not possibl e

RM0 Mailbox 0 message reception IRR1 Possible

RM1 Mailbox 15 to 1 message reception IRR1 Not possible

SLE0 Message transmission/transmit cancellation IRR8 Not possible

IRQ2 Setting the RxDIE bit in HCANMON to 1 generates an

IRQ2 interrupt caused by an HRxD input signal. IRQ2F Possible

Section 15 Controller Area Network (HCAN)

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15.6 DTC Interface

The DTC can be activated by the reception of a message in HCAN mailbox 0. When the DTC

activation is set and DTC transfer ends, the RXPR0 and RFPR0 flags are automatically cleared.

An interrupt request is not sent to the CPU by a reception interrupt from the HCAN. Figure 15.15

shows a DTC transfer flowchart.

DTC initialization

DTC enable register setting

DTC register information setting

Yes

: Settings by user

: Processing by hardware

Message reception in HCAN’s

mailbox 0

Transfer counter = 0

or DISEL = 1?

DTC activation

End of DTC transfer?

RXPR and RFPR clearing

Interrupt to CPU

End

Figure 15.15 DTC Transfer Flowchart

Section 15 Controller Area Network (HCAN)

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15.7 CAN Bus Inte rface

A bus transceiver IC is necessary to connect the H8S/2628 Group to a CAN bus. A Philips

PCA82C250 transceiver IC is recommended. If any other product is used, confirm that it is

compatible with the PCA82C250. Figure 15.16 shows a sample connection diagram.

RxD

TxD

Vref

Vcc

CANH

CANL

GND

HRxD

Note: NC: No connection

HTxD

This LSI

CAN bus

124 Ω

Vcc

PCA82C250

Figure 15.16 High-Speed Interface Using PCA82C250

15.8 Usage Notes

15.8.1 Module Stop Mode Setti ng

HCAN operation can be disabled or enabled using the module stop control register. The HCAN

operation is set to be halted initially. Register access is enabled by clearing module stop mode. For

details, refer to section 21, Pow er-D ow n Modes.

15.8.2 Reset

The HCAN is reset by a power-on reset, in hardware standby mode, and in software standby

mode. All the registers are initialized by a reset, however mailboxes (message control

(MCx[x])/message data (MDx[x])) are not initialized. Mailboxes (message control

(MCx[x])/message data (MDx[x])) are initialized after power-on and at this time, their initial

values are undefined. Therefore, always initialize mailboxes after a power-on reset, a transition to

hardware standby mode, or softw are standby mode. After a power- on reset or recov ery from

software standby mode, the reset interrupt flag (IRR0) is automatically set. Since this bit cannot be

masked in the interrupt mask register (IMR), an HCAN interrupt will be initiated immediately

Section 15 Controller Area Network (HCAN)

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after an HCAN interrupt is enabled by the interrupt controller without clearing the flag. IRR0

should therefore be cleared at initialization.

15.8.3 HCAN Sleep Mode

The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus

operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep

mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set even

in sleep mode.

15.8.4 Interrupts

When the mailbox interrupt mask register (MBIMR) is set, the interrupt registers (IRR8, 2, 1) are

not set by reception completion, transmission completion, or transmission cancellation of the set

mailboxes.

15.8.5 Error Counters

In the case of error active and error passive, REC and TEC perform count up and down normally.

In the bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. When REC

reaches 96 during the count, IRR4 and GSR1 are set.

15.8.6 Register Access

Byte or word access can be performed for all HCAN registers. Longword access should be

avoided.

15.8.7 HCAN Medium-Spee d Mode

In medium-speed mode, the HCAN registers cannot be read/written.

15.8.8 Register Hold in Standby Modes

All HCAN registers are initialized in hardware standby mode and software standby mode.

15.8.9 Use on Bit Manipulation Instruc tions

Since the HCAN status flag is cleared by writing 1, do not use the bit manipulation instructions to

clear the flag. To clear the flag, use the MOV instructions and write 1 only to the bit to be cleared.

Section 15 Controller Area Network (HCAN)

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15.8.10 HCAN TXCR Operation

1. When the transmit wait cancel register (TXCR) is used to cancel a transmit wait message in a

transmit wait mailbox, the corresponding bit to TXCR and the transmit wait register (TXPR)

may not be cleared even if transmission is canceled. This occurs when the following conditions

are all satisfied.

Conditions:

• The HRxD pin is stacked to 1 because of a CAN bus error, etc.

• There is at least one mailbox waiting for transmission or being transmitted.

• The message transmission in a mailbox being transmitted is canceled by TXCR.

If this occu rs, transm i ssion is cancel ed. How ev er, since TX PR and TXCR sta te s are

indicated wrongly that a message is being cancelled, transmission cannot be restarted even

if the stack state of the HRxD pin is canceled and the CAN bus recovers the normal state. If

there are at least two transmission messages, a message which is not being transmitted is

canceled and a message being transmitted retains its state.

To avoid this, one of the following countermeasures must be executed.

Countermeasures:

• Transmission must not be canceled by TXCR. When transmission is normally completed

after the CAN bus has recovered, TXPR is cleared and the HCAN recovers the normal

state.

• To cancel transmission, the corresponding bit to TXCR must be written to 1 continuously

until the bit become s 0. TXPR and TXCR are clea red and the HCAN recovers the normal

state.

2. When the bus-off state is entered while TXPR is set and the transmit wait state is entered, the

internal state machine does not operate even if TXCR is set during the bus-off state. Therefore

transmission cannot be canceled. The message can be canceled when one message is

transmitted or a transmission error occurs after the bus-off state is recovered. To clear a

message after the bus-off state is recovered, the following countermeasure must be executed.

Countermeasure:

• A transmit wait message must be cleared by resetting the HCAN during the bus-off period.

To reset the HCAN, the module stop bit (MSTPC3 in MSTPCRC) must be set or cleared.

In this case, the HCAN is entirely reset. Therefore the initial settings must be made again.

Section 15 Controller Area Network (HCAN)

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15.8.11 HCAN Transmit Procedure

When transmission is set while the bus is in the idle state, if the next transmission is set or the set

transmission is canceled under the following conditions within 50 µs, the transmit message ID of

being set may be damaged.

• When the second transmission has the message whose priority is higher than the first one.

• When the massage of the highest priority is canceled in the first transmission.

Make whichever setting shown below to avoid the message IDs from being damaged.

• Set transmission in one TXPR. After transmission of all transmit messages is completed, set

transmission again (mass transmission setting). The interval between transmission settings

should be 50 µs or longer.

• Make the transmission setting according to the priority of transmit messages.

• Set the interval to be 50 µs or longer between TXPR and another TXPR or between TXPR and

TXCR.

Table 15.5 Interval Limitation between TXPR and TXPR or between TXPR and TXCR

Baud Rate (bps) Set Interval (µ

µµ

µs)

1 M 50

500 k 50

250 k 50

15.8.12 Canceling HCAN Reset and HCAN Sleep Mode

Before canceling the software reset for HCAN or HCAN sleep mode (MCR0 = 0 or MCR5 = 0),

confirm that the reset status bit (GSR3) is set to 1.

15.8.13 Accessin g Mailbox in HCAN Sleep Mode

The mailboxes should not be accessed in HCAN sleep mode. If mailboxes are accessed in HCAN

sleep mode, the CPU may stop. When registers are accessed in HCAN sleep mode, the CPU does

not stop. When mailboxes are accessed in modes other than HCAN sleep mode, the CPU does not

stop.

Section 15 Controller Area Network (HCAN)

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Section 16 Synchronous Serial Communication Unit (SSU)

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Section 16 Synchronou s Serial Communication U nit (SSU)

This LSI has two independent synchronous serial communication unit (SSU) channels. The SSU

has master mode in which this LSI outputs clocks as a master device for synchronous serial

communication and slave mode in which clocks are input from an external device for synchronous

serial communication. Synchronous serial communication can be performed with devices having

different clock polarity and clock phase. Figure 16.1 is a block diagram of the SSU.

16.1 Features

• Choice of master mode or slave mode

• Choice of standard mode or bidirectional mode

• Synchronous serial communication with devices with different clock polarity and clock phase

• Choice of 8/16/32-bit width of transmit/receive data

• Full-duplex communication capability

The shift register is incorporated, enabling transmission and reception to be executed

simultaneously.

• Continuous serial communication

• Choice of LSB-first or MSB-first transfer

• Choice of a clock source

φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128, φ/256, or external clock

• Five interrupt sources

transmit-end, transmit-data-register-empty, receive-data-register-full, overrun-error, and

conflict erro r

• Module stop mode can be set

SCISSU0A_000120020900

Section 16 Synchronous Serial Communication Unit (SSU)

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Figure 16.1 shows a block diagram of the SSU.

SSO SSCK (External clock)

Module data bus

SSCRH

CEI

SSTRSR

Selector

RXI

SSCRL

SSMR

SSER

SSSR

Control circuit

Clock φ

φ/2

φ/4

φ/8

φ/16

φ/32

φ/64

φ/128

φ/256

Clock

selector

Internal data bus

Bus interface

SCS

SSI

Shift-out

Shift-in

OEI

TXI

TEI

Legend:

SSCRH:

SSCRL:

SSMR:

SSER:

SSSR:

SSTDR3 to SSTDR0:

SSRDR3 to SSRDR0:

SSTRSR:

SS control register H

SS control register L

SS mode register

SS enable register

SS status register

SS transmit data register

SS receive data register

SS transmit/recive shift register

SSRDR 0

SSRDR 1

SSRDR 2

SSRDR 3

SSTDR 0

SSTDR 1

SSTDR 2

SSTDR 3

Figure 16.1 Block Diagram of SSU

Section 16 Synchronous Serial Communication Unit (SSU)

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16.2 Input/O utput Pins

Table 16.1 shows the SSU pin configuration.

Table 16.1 Pin Configura tion

Name Symbol I/O Function

SSU clock SSCK I/O SSU clock input/output

SSU receive data input SSI I/O SSU receive data i nput/output

SSU transmit data output SSO I/O SSU transmit data input/output

SSU chip select i nput/output

SCS

I/O SSU chip select i nput/output

16.3 Register Descriptions

The SSU has the following registers.

• SS control register H (SSCRH)

• SS control register L (SSCRL)

• SS mode register (SSMR)

• SS enable register (SSER)

• SS status register (SSSR)

• SS transmit data register 3 to 0 (SSTDR3 to SSTDR0)

• SS receive data register 3 to 0 (SSRDR3 to SSRDR0)

Section 16 Synchronous Serial Communication Unit (SSU)

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16.3.1 SS Control Register H (SSCRH)

SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value

selection, SSCK pin selection, and

SCS

pin selection.

Bit Bit Name Initial Value R/W Description

7 MSS 0 R/W Master/Sla ve Device Selection

Selects that this module is used in master mode

or slave mode. When master mode is selected,

transfer clocks are output from the SSCK pin.

When the CE bit in SSSR is set, this bit is

automatically cleared.

0: Slave mode is selected

1: Master mode is selected

6 BIDE 0 R/W Bidirectional Mode Enabl e

Selects that both serial data input pin and output

pin are used or one of them is used. However,

transmission and reception are not performed

simultaneously when bidirectional mode is

selected. For details, section 16.4.3, Relationship

between Data I/O Pins and Shift Register.

0: Standard mode (two pins are used as data

input and output)

1: Bidirectional mode (one pin is used for data

input and output)

50Reserved

The write value should al ways be 0.

4 SOL 0 R/W Serial Data Output Value Selection

The output level of serial data, which retains that

of the last bit, can be modified by operating this bit

before or after transmission. When modifying the

output level, use the MOV in struction after

clearing the SOLP bit to 0. Since writing to this bit

during data transmission causes malfunctions,

this bit should not be modified.

0: Serial data output is modified to low level

1: Serial data output is modified to high level

Section 16 Synchronous Serial Communication Unit (SSU)

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Bit Bit Name Initial Value R/W Description

3 SOLP 1 R/W SOL Bit Write Protect

When modifying the output level of serial data,

use the MOV instruction after setting SOL to 1

and clearing SOLP to 0, or by clearing SOL and

SOLP to 0.

0: Output level can be modified by the SOL value

1: Output level cannot be modified by the SOL

value. This bit is always read as 1

2 SCKS 0 R/W SSCK Pin Selection

Selects that the SSCK pin functions as a port or a

serial clock pin. When MSS = 1, the SSCK pin

functions as a serial clock output pin regardless of

the setting of this bit.

0: Functions as an I/O port

1: Functions as a serial cl ock

0CSS1

CSS0 0

0R/W

R/W

SCS

Pin Selection

Select that the

SCS

pin functi ons as a port or

input or output. However, when MSS = 0, the

SCS

pin functions as an input pin regard less of the

CSS1 and CSS0 settings.

00: I/O port

01: Functions as

SCS

input

10: Functions as

SCS

automatic input/output

(however, functions as

SCS

input before and

after transfer and outputs a low le vel during

transfer)

11: Functions as

SCS

automatic output (however,

outputs a high level before and after transf er

and outputs a low level during transfer)

Section 16 Synchronous Serial Communication Unit (SSU)

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16.3.2 SS Control Register L (SSCRL)

SSCRL selects software reset and transmit/receive data width.

Bit Bit Name Initial Value R/W Description

7, 6 All 0 Reserved

The write value should al ways be 0.

5 SRES 0 R/W Software Reset

Setting this bit to 1 forcibly resets the SSU internal

sequencer. After that, this bit is automatically

cleared. The ORER, TEND, TDRE, RDRF, and

CE bits in SSSR and the TE and RE bits in SSER

are also initialized. Values of other bits for SSU

registers are held.

To stop transfer, set this bit to 1 to reset the SSU

internal sequencer.

4 to

2All 0 Reserved

The write value should al ways be 0.

0DATS1

DATS0 0

0R/W

R/W Transmit/Receive Data Length Selection

Select seri al data length from 8, 16, and 32 bits.

00: 8 bits

01: 16 bits

10: 32 bits

11: Setti ng invalid

Section 16 Synchronous Serial Communication Unit (SSU)

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16.3.3 SS Mode Register (SSMR )

SSMR selects the MSB first/LSB first, clock phase, clock polarity, and clock rate of synchronous

serial communication.

Bit Bit Name Initial Value R/W Description

7 MLS 0 R/W MSB F irst/LSB First

Selects the serial data is transmitted in MSB first

or LSB first.

0: LSB first

1: MSB first

6 CPOS 0 R/W Clock Polarity Selection

Selects SSCK clock pola ri ty.

0: High output in idle mode, and low output in

active mode

1: Low output in i dle mode, and high output in

active mode

5 CPHS 0 R/W Clock Phase Selection

Selects SSCK clock phase.

0: Data changes at the first edge

1: Data is latched at the first edge

4, 3 All 0 Reserved

The write value should al ways be 0.

CKS2

CKS1

CKS0

R/W

Transfer Clock Rate Selection

Select the transfer clock rate (prescal er division

rate) when a master mode is selected.

000: φ/2

001: φ/4

010: φ/8

011: φ/16

100: φ/32

101: φ/64

110: φ/128

111: φ/256

Section 16 Synchronous Serial Communication Unit (SSU)

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16.3.4 SS Enable Register (SSER)

SSER performs transfer/receive control of synchronous serial communication and setting of

interrupt enable.

Bit Bit Name Initial Value R/W Description

7 TE 0 R/W Transmit Enable

When this bit is set to 1, transmission is enabled.

6 RE 0 R/W Receive Enable

When this bit is set to 1, reception is enabled.

5, 4 All 0 Reserved

The write value should al ways be 0.

3 TEIE 0 R/W Transmit End Interrupt Enable

When this bit is set to 1, TEI interrupt request is

enabled.

2 TIE 0 R/W Transmit Interrupt Enable

When this bit is set to 1, TXI interrupt request is

enabled.

1 RIE 0 R/ W Receive Interrupt Enab le

When this bit is set to 1, RXI interrupt request is

enabled.

0 CEIE 0 R/W Conflict Error Interrupt Enable

When this bit is set to 1, CEI interrupt request is

enabled.

Section 16 Synchronous Serial Communication Unit (SSU)

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16.3.5 SS Status Register (SSSR)

SSSR is a status flag register for interrupts.

Bit Bit Name Initial Value R/W Description

70Reserved

The write value should al ways be 0.

6 ORER 0 R/W Overrun Error

If the next data is received while RDRF = 1, an

overrun error occurs, indicating abnormal

termination. SSRDR stores 1-frame receive data

before an overrun error occurs and loses data

received later. While ORER = 1, continuous serial

reception cannot be continued. Serial

transmission cannot be continued, either.

[Setting condition]

• When the next reception data is transferred to

SSRDR whil e RDRF = 1

[Clearing condition]

• When 0 is written to ORER after reading

ORER = 1

5, 4 All 0 Reserved

The write value should al ways be 0.

3 TEND 1 R Transmit End

[Setting condition]

• When the last bit of transmit data is

transmitted with TDRE = 1

[Clearing conditions]

• When 0 is written to the TEND bit after reading

TEND = 1

• When data is written to SSTDR

Section 16 Synchronous Serial Communication Unit (SSU)

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Bit Bit Name Initial Value R/W Description

2 TDRE 1 R/W Transmit Data Register Empty

Indicates whether or not SSTDR contains transmit

data.

[Setting conditions]

• When the TE bi t in SSER is 0

• When data is transferred from SSTDR to

SSTRSR and SSTDR is ready to be written to.

[Clearing conditions]

• When 0 is wri tten to the TDRE bit after readin g

TDRE = 1

• When data is written to SSTDR with TE = 1

1 RDRF 0 R/W Receive Data Register Full

Indi cates whether or not SSRDR contains

received data.

[Setting condition]

• When receive data is transferred from

SSTRSR to SSRDR after successful dat a

reception

[Clearing conditions]

• When 0 is written to RDRF after reading

RDRF = 1

• When received data is read from SSRDR

Section 16 Synchronous Serial Communication Unit (SSU)

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Bit Bit Name Initial Value R/W Description

0 CE 0 R/W Conflict/Incomplete Error

Indicates that a conflict error has occurred when 0

is externally input via the

SCS

pin with MSS = 1.

If the

SCS

pin level changes to 1 during slave

operation, an incomplete error occurs because it

is determined that a master device has terminated

the transfer. Data reception does not continue

while the CE bit is set to 1. Reset the SSU internal

sequencer by setting the SRES bit in SSCRL to 1

before resuming transfer after incomplete error.

[Setting conditions]

• When a low level is input to the

SCS

pin in

master device mode (MSS in SSCRH = 1)

• When a 1 is in put to the

SCS

pin during slave

device mode (MSS in SSCRH = 0) transfer

[Clearing condition]

• When 0 is wri tten to the CE bit after reading

CE = 1

16.3.6 SS Transmit Data Register 3 to 0 (SSTDR3 to SSTDR0)

SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits

DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0

and SSTDR1 are valid. When 32-bit data length is selected, SSTDR3 to SSTDR0 are valid. Do not

attempt to access invalid SS transmit data registers.

When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to

SSTRSR and starts transmission. If the next transmit data has already been written to SSTDR

during serial transmission, the SSU transfers the written data to SSTRSR to continue transmission.

Although SSTDR can be read or written to by the CPU and DTC at all times, to achieve reliable

serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in SSSR is

set to 1. The initial value of this register is H'00.

Section 16 Synchronous Serial Communication Unit (SSU)

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16.3.7 SS Receive Data Register 3 to 0 (SSRDR3 to SSRDR0)

SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits

DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0

and SSRDR1 are valid. When 32-bit data length is selected, SSRDR3 to SSRDR0 are valid. Do

not attempt to access invalid SS receive data registers.

When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to

SSRDR where it is stored. After this, SSTRSR is receive-enabled. Since SSTRSR and SSRDR

function as a double buffer in this way, continuous receive operations can be performed. Read

SSRDR after confirming that the RDRF bit in SSSR is set to 1. SSRDR cannot be written to by

the CPU. The initial value of this register is H'00.

16.3.8 SS Shift Register (SSTRSR)

SSTRSR is a shift register that transmits and receives serial data.

When data from SSTDR to SSTRSR is transferred with MLS = 0, bit 0 of transmit data is bit 0 in

the SSTDR contents (LSB first communication). When data from SSTDR to SSTRSR is

transferred with MLS = 1, bit 0 of transmit data is bit 7 in the SSTDR contents (MSB first

communication). To perform serial data transmission, the SSU transfers data starting from LSB

(bit 0) in SSTRSR to the SSO pin.

In reception, the SSU sets serial data that has been input from the SSI pin to SSTRSR starting

from LSB (bit 0) and converts it into parallel data. When 1-byte data has been received, the

SSTRSR contents are automatically transferred to SSRDR. SSTRSR cannot be directly accessed

by the CPU.

Section 16 Synchronous Serial Communication Unit (SSU)

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16.4 Operation

16.4.1 Transfer Clock

A transfer clock can be selected from eight internal clocks and an external clock. When using this

module, set SCKS in SSCRH to 1 to select the SSCK pin as a serial clock. When MSS in SSCRH

is 1, an internal clock is selected and the SSCK pin is used as an output pin. When transfer is

started, the clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the

SSCK pin. When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin.

16.4.2 Relationship of Clock Phase, Polarity, and Data

The relationship of clock phase, polarity, and transfer data depends on the combination of CPOS

and CPHS in SSMR. Figure 16.2 shows the relationship.

Setting the MLS bit specifies that MSB or LSB first communication. When MLS = 0, data is

transferred from the LSB to MSB. When MLS = 1, data is transferred from the MSB to LSB.

SSCK

(CPOS = 0)

(1) When CPHS = 0

(2) When CPHS = 1

SSCK

(CPOS = 1)

SSI, SSO

SCS

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

SSCK

(CPOS = 0)

SSCK

(CPOS = 1)

SSI, SSO

SCS

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Figure 16.2 Relationship of Clock Phase, Polarity, and Data

Section 16 Synchronous Serial Communication Unit (SSU)

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16.4.3 Relationship between Data I/O Pins and the Shift Register

The connection between data I/O pins and the shift register (SSTRSR) depends on the

combination of the MSS and BIDE bits in SSCRH. Figure 16.3 shows the connection.

The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when

operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 16.3 (1)). The SSU

transmits serial data from the SSI pin and receives serial data from the SSO pin when operating

with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 16.3 (2)).

The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode

when operating with BIDE = 1 (bidirectional mode) (see figure 16.3 (3) and (4)).

However, even if both the TE and RE bits are set to 1, transmission and reception are not

performed simultaneously. Either the TE or RE bit must be selected.

SSCK

Shift register

(SSTRSR)

Shift register

(SSTRSR)

Shift register

(SSTRSR)

Shift register

(SSTRSR)

(1) When BIDE = 0 (standard mode), MSS = 1, TE = 1, and RE = 1 (2) When BIDE = 0 (standard mode), MSS = 0, TE = 1, and RE = 1

(3) When BIDE = 1 (bidirectional mode), MSS = 1, and TE or RE = 1 (4) When BIDE=1 (bidirectional mode), MSS = 0, and TE or RE = 1

SSO

SSI

SSCK

SSO

SSI

SSCK

SSO

SSI

SSCK

SSO

SSI

Figure 16.3 Relationship between Data I/O Pins and the Shift Register

Section 16 Synchronous Serial Communication Unit (SSU)

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16.4.4 Data Transmission and Data Reception

The SSU performs data communications using the bus with four lines: the clock line (SSCK), data

input (SSI or SSO), data output (SSI or SSO), and chip select (

SCS

The SSU also supports bidirectional mode in which the data is output and input using one pin.

SSU Initialization

Figure 16.4 shows an example of the SSU initialization. Before transmitting and receiving data,

first clear the TE and RE bits in SSER to 0, then initialize the SSU.

Note: When the operating mode or transfer format is changed for example, the TE and RE bits

must be cleared to 0. When the TE bit is cleared to 0, the TDRE bit is set to 1. Note that

clearing the RE bit to 0 does not initialize the values of the RDRF and ORER bits or the

contents of SSRDR.

Start initialization

[1]

[2]

[3]

[4]

[1] Specify master/slave device selection,

bidirectional mode enable, SSO pin

output value selection, SSCK pin selection,

and SCS pin selection.

[2] Specify transmit/receive data length.

[3] Specify MSB first/LSB first selection, clock

polarity selection, clock phase selection,

and transfer clock rate selection.

[4] Specify enable/disable of interrupt request

to the CPU.

End

Clear TE and RE bits in SSER to 0

Specify bits DATS1 and DATS0

Specify CSS1, CSS0, MSS, BIDE, SOL,

and SCKS bits

Specify CKS2 to CKS0, MLS, CPOS,

and CPHS bits

Specify TE, RE, TEIE, TIE, RIE,

and CEIE bits simultaneously

Figure 16.4 Example of SSU Initialization

Section 16 Synchronous Serial Communication Unit (SSU)

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Data Transmission

Figure 16.5 shows an example of transmission operation, and figure 16.6 shows an example of

data transmission flowchart.

When transmitting data, the SSU operates as shown below.

In master device mode, the SSU outputs a transfer clock and data. In slave device mode, when a

low level signal is input to the

SCS

pin and a transfer clock is input to the SSCK pin, the SSU

outputs data in synchronization with the transfer clock.

Writing transmit data to SSTDR after initialization of the SSU automatically clears the TDRE bit

in SSSR to 0, and the contents of SSTDR is transferred to SSTRSR. After that, the SSU sets the

TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI

interrupt is generated.

When 1-frame data has been transferred with the TDRE bit cleared to 0, the SSTDR contents are

transferred to SSTRSR to start the next transmission. When the 8th bit of transmit data has been

transferred with the TDRE bit set to 1, the TEND bit in SSSR is set to 1 and the state is retained.

At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output

level of the SSCK pin is fixed at a high level when CPOS = 0 and at a low level when CPOS = 1.

While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit

is cleared to 0.

Section 16 Synchronous Serial Communication Unit (SSU)

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SCS

SSCK

(1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0

(2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0

(3) When 32-bit data length is selected (SSTDR0, SSTDR1, SSTDR2, and SSTDR3 are valid) with CPOS = 0 and CPHS = 0

Bit

0Bit

Bit

1Bit

Bit

2Bit

Bit

3Bit

Bit

4Bit

Bit

5Bit

Bit

6Bit

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6Bit

Bit

7Bit

6Bit

5Bit

4Bit

3Bit

2Bit

1Bit

Bit

0to to to to

to to to to

Bit

7Bit

Bit

7Bit

Bit

7Bit

Bit

0Bit

7Bit

0Bit

7Bit

0Bit

Bit

SSO

TDRE

TEND

LSI operation

User operation

LSI operation

User operation

LSI operation

User operation

TXI

interrupt

generated

TEI

interrupt

generated

TEI

interrupt

generated

TXI

interrupt

generated

TEI

interrupt

generated

TXI

interrupt

generated

Data written to

SSTDR0

Data written to

SSTDR1 to SSTDR0

TEI interrupt generated

TXI interrupt generated

Data written to

SSTDR3 to SSTDR0

Data written to

SSTDR0

SSTDR1

SCS

SSCK

TDRE

TEND

SSO

(LSB first)

SSO

(MSB first)

SSO

(LSB first)

SSO

(MSB first)

SSTDR0

SSTDR0 SSTDR1

SCS

SSCK

TDRE

TEND

SSTDR0

SSTDR3

SSTDR1

SSTDR2

SSTDR1

SSTDR3

SSTDR0

1 frame

SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission)

1 frame

Figure 16.5 Example of Transmission Operation

Section 16 Synchronous Serial Communication Unit (SSU)

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Yes

Start

[1]

[2]

[3]

[4]

[1] Initialization:

Specify the settings such as transmit

data format.

Note: Hatching boxes represent SSU internal operations.

[2] Check the SSU state and write

transmit data:

Write transmit data to SSTDR after

reading and confirming that the TDRE bit

is 1. The TDRE bit is automatically cleared

to 0 and transmission is started by writing

data to SSTDR.

[3] Procedure for continuous data transmission:

To continue data transmission, confirm

that the TDRE bit is 1 meaning that SSTDR

is ready to be written to. After that, data can

be written to SSTDR. The TDRE bit is

automatically cleared to 0 by writing data to

SSTDR.

[4] Transmission end procedure:

To end transmission, confirm TEND = 1 and

wait until the last bit is surely transmitted,

then set TE to 0.

Initialization

Read TDRE in SSR

TDRE = 1?

Yes

Write transmit data to SSTDR

TDRE automatically cleared

Data transferd from SSTDR to SSTRSR

Set TDRE to 1 to start transmission

Continuous data transmission?

Read TEND in SSSR

TEND = 1?

Yes

Wait

Confirm TEND = 0

1-bit interval elapsed ?

Clear TEND to 0

Clear TE in SSER to 0

End transmission

Figure 16.6 Example of Data Transmission Flowchart

Section 16 Synchronous Serial Communication Unit (SSU)

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Data Reception

Figure 16.7 shows an example of reception operation, and figure 16.8 shows an example of data

reception flow char t.

When receiving data, the SSU operates as shown below.

After initialization, the SSU dummy-reads SSRDR and data reception is started.

In master device mode, the SSU outputs a transfer clock and receives data. In slave device mode,

when a low level signal is input to the

SCS

pin and a transfer clock is input to the SSCK pin, the

SSU receives data in synchronization with the transfer clock.

When 1-frame data has been received, the received data is stored in SSRDR. At this time, if the

RIE bit is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by

reading SSRDR.

Section 16 Synchronous Serial Communication Unit (SSU)

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SCS

SSCK

(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0

(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0

(3) When 32-bit data length is selected (SSRDR0, SSRDR1, SSRDR2, and SSRDR3 are valid) with CPOS = 0 and CPHS = 0

SSI

RDRF

SSRDR1

SCS

SSCK

RDRF

SSRDR0

SSRDR0 SSRDR1

SCS

SSCK

RDRF

SSRDR0

SSRDR3

SSRDR1

SSRDR2

SSRDR1

SSRDR3

SSRDR0

1 frame

Bit

0Bit

1Bit

Bit

2Bit

Bit

3Bit

Bit

4Bit

Bit

5Bit

Bit

6Bit

Bit

LSI operation

Dummy-read

SSRDR0

Dummy-read

SSRDR0

Dummy-read

SSRDR0

Read SSRDR0

User operation

LSI operation

User operation

LSI operation

User operation

SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission)

RXI

interrupt

generated

RXI

interrupt

generated

RXI

interrupt

generated

RXI

interrupt

generated

Bit

0Bit

1Bit

2Bit

3Bit

4Bit

5Bit

6Bit

7Bit

Bit

7Bit

6Bit

5Bit

4Bit

3Bit

2Bit

Bit

SSI

(LSB first)

SSI

(MSB first)

Bit

0to to to to

to to to to

Bit

7Bit

Bit

7Bit

Bit

7Bit

Bit

0Bit

7Bit

0Bit

7Bit

SSI

(LSB first)

SSI

(MSB first)

Bit

Figure 16.7 Example of Reception Operation

Section 16 Synchronous Serial Communication Unit (SSU)

Rev. 3.00 Oct 04, 2005 page 443 of 598

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Yes

[1]

[2]

[3]

[4]

[5]

[6]

[1] Initialization:

Specify the settings such as receive data format.

[2] Start reception:

When SSRDR is dummy-read with RE = 1,

reception is started.

[3], [6] Receive error processing:

When a receive error occurs execute the

designated error processing after reading the

ORER bit in SSSR. After that, clear the ORER

bit to 0. While the ORER bit is set to 1,

reception is not resumed.

[4] To continue single reception:

When continuing single reception, the next single

reception starts after reading received data in SSRDR.

[5] To complete reception:

To complete reception, read received data after

clearing the RE bit to 0. When reading SSRDR without

clearing the RE bit, reception is resumed.

No No

Yes

Start

Initialization

Dummy-read SSRDR

Read SSRDR

RDRF = 1?

ORER = 1?

Continuous data reception?

Read received data in SSRDR

RDRF automatically cleared

RE = 0

Read received data in SSRDR

End reception

Overrun error processing

Clear ORER in SSSR

End reception

Note: Hatching boxes represent SSU internal operations.

Figure 16.8 Example of Data Reception Flowchart

Section 16 Synchronous Serial Communication Unit (SSU)

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Data Transmission/Reception

Figure 16.9 shows an example of simultaneous transmission/reception operation. The data

transmission/reception is performed combining the data transmission and data reception as

mentioned above. The data transmission/reception is started by writing transmit data to SSTDR

with TE = RE = 1.

When the RDRF has been set to 1 at the 8th rising edge of the transfer clock (in a case of 8-bit

data length), the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has

occurred. At this time, data transmission/reception is stopped. While the ORER bit in SSSR is set

to 1, transmission/reception is not performed. To resume the transmission/reception, clear the

ORER bit to 0.

Before switching transmission mode (TE = 1) or receptio n mode (RE = 1) to

transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the

transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE and

RE bits to 1.

Section 16 Synchronous Serial Communication Unit (SSU)

Rev. 3.00 Oct 04, 2005 page 445 of 598

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Yes

Start

Initialization[1]

[2]

[1] Initialization:

Specify the settings such as transmit/receive

data format.

[2] Check the SSU state and write transmit data:

Write transmit data to SSTDR after reading

and confirming that the TDRE bit is 1. The

TDRE bit is automatically cleared to 0 and

transmission is started by writing data to

SSTDR.

[3] Check the SSU state:

Read SSSR and confirm that the RDRF bit is 1.

A change of the RDRF bit (from 0 to 1)

can be notified by RXI interrupt.

[4] Receive error processing:

When a receive error occurs, execute the

designated error processing after reading the

ORER bit in SSSR. After that, clear the ORER

bit to 0. While the ORER bit is set to 1,

transmission or reception is not resumed.

[5] Procedure for continuous data transmission/

reception:

To continue serial data transmission/reception,

confirm that the TDRE bit 1meaning that SSTDR

is ready to be written to. After that, data can be

written to SSTDR. The TDRE bit is automatically

cleared to 0 by writing data to SSTDR.

[4]

[5]

[3]

Read TDRE in SSSR

TDRE = 1?

Yes

Write transmit data to SSTDR

TDRE automatically cleared

Data transferred from SSTDR to SSTRSR

TDRE set to 1 to start transmission

Read SSSR

RDRF = 1?

ORER = 1?

Read received data in SSRDR

RDRF automatically cleared

Continuous data

transmission/reception

Yes

Read TEND in SSSR

TEND = 1?

1-bit internal elapsed?

Clear TEND in SSSR to 0

Clear TE and RE in SSER to 0

Error processing

End transmission/reception

Note: Hatching boxes represent SSU internal operations.

Figure 16.9 Example of Simultaneous Transmission/Reception Flowchart

Section 16 Synchronous Serial Communication Unit (SSU)

Rev. 3.00 Oct 04, 2005 page 446 of 598

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16.4.5

SCS

Pin Control and Conflict Error

When bits CSS1 and CSS0 in SSCRH are specified to B'10, the

SCS

pin functions as an input

(Hi-Z) to detect conflict error. The conflict detection period starts when setting the MSS bit in

SSCRH to 1 and ends when starting serial transfer. When a low level signal is input to the

SCS

within the period, a conflict error occurs. At this time, the CE bit in SSSR is set to 1 and the MSS

bit is cleared to 0.

Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0

before resuming the transmission or reception.

CE Data written

to SSTDR

Conflict error

detection period Worst time for

internally clocking SCS

MSS

Transfer enabled

internal signal

SCS output

External input to SCS

Internal-clocked SCS

(Hi-Z)

Figure 16.10 Conflict Error Detection Timing (Before Transfer Start)

Section 16 Synchronous Serial Communication Unit (SSU)

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SCS

MSS

Transfer enabled

internal signal

(Hi-Z)

Transfer

end

Conflict error detection period

Figure 16.11 Conflict Error Detection Timing (After Transfer End)

16.5 Inte rrupt Requests

The SSU interrupt requests consist of transmit data register empty, transmit end, receive data

empty, transmit end, re ceiv e data reg ister full can activ ate the DTC for data trans fer .

The TDRE, TEND, and RDRF bits are automatically cleared to 0 by the DTC data transfer. Since

these interrupt requests are allocated to four vector addresses: SSEr_i0, SSRx_i0, SSTx_i0 and

SSERT_i1, the interrupt sources must be distinguished by flags. Table 16.2 lists interrupt sources.

Section 16 Synchronous Serial Communication Unit (SSU)

Rev. 3.00 Oct 04, 2005 page 448 of 598

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Table 16.2 Interrup t Souses

Channel Abbreviation Interrupt Request Symbol Interrupt Condition

0 SSEr_i0 Overrun error OEI RI E = 1, ORER = 1

Conflict error CEI CEIE = 1, CE = 1

SSRx_i0 Receive data register full RXI R IE = 1, RDRF = 1

SSTx_i0 Transmit data register empty TXI TIE = 1, TDRE = 1

Transmit end TEI TEIE = 1, TEND = 1

1 SSERT_i1 Overrun error OEI RIE = 1, ORER = 1

Conflict error CEI CEIE = 1, CE = 1

Receive data register full RXI RIE = 1, RDRF = 1

Transmit data register empty TXI TIE = 1, TDRE = 1

Transmit end TEI TEIE = 1, TEND = 1

When interrupt conditions shown in table 16.2 are satisfied and the I bit in CCR is 0, the CPU

executes interrupt exception processing. Clear each interrupt source in the exception processing.

16.6 Usage Note

16.6.1 Setting of Module Stop Mode

The SSU can be enabled/disabled by the module stop control register setting and is disabled by the

initial value. Canceling module stop mode enables to access the SSU registers. For details, see

section 21, Power-Down Modes.

Section 17 A/D Converter

Rev. 3.00 Oct 04, 2005 page 449 of 598

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Section 17 A /D Converter

This LSI includes a successive approximation type 10-bit A/D converter that allows up to sixteen

analog input channels to be selected. The block diagram of the A/D converter is shown in figure

17.1.

17.1 Features

• 10-bit resolution

• Sixteen input channels

• Conversion time: 11.08 µs per channel (at 24 MHz operation)

• Two operating modes

 Single mode: Single-channel A/D conversion

 Scan mode: Continuous A/D conversion on 1 to 4 channels

• Four data registers

 Conversion results are held in a 16-bit data register for each channel

• Sample and hold function

• Three conversion start methods

 Software

 16-bit timer pulse unit (TPU) conversion start trigger

 External trigger signal

• Interrupt request

 An A/D conversion end interrupt request (ADI) can be generated

• Module stop mode can be set

ADCMS38A_000020020300

Section 17 A/D Converter

Rev. 3.00 Oct 04, 2005 page 450 of 598

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Module data bus

Control circuit

Internal data bus

10-bit D/A

Comparator

Sample-and-

hold circuit

ADI

interrupt

Bus interface

Successive approximations

Multiplexer

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13

AN14

AN15

Legend:

ADCR: A/D control register

ADCSR: A/D control/status register

ADDRA: A/D data register A

ADTRG

Conversion start

trigger from TPU

φ/2

φ/4

φ/8

φ/16

ref

ADDRB: A/D data register B

ADDRC: A/D data register C

ADDRD: A/D data register D

Figure 17.1 Block Diagram of A/D Converter

Section 17 A/D Converter

Rev. 3.00 Oct 04, 2005 page 451 of 598

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17.2 Input/Output Pins

Table 17.1 summarizes the input pins used by the A/D converter. 12 analog input pins are divided

into three groups, each of which includes four channels; analog input pins 3 to 0 (AN3 to AN0)

comprising group 0, analog input pins 7 to 4 (AN7 to AN4) comprising group 1, analog input pins

11 to 8 (AN11 to AN8) comprising group 2, and analog input pins 15 to 12 (AN15 to AN12)

comprising group 3. The AVcc and AVss pins are the power supply pins for the A/D converter

analog section. The Vref pin is the A/D conversion reference voltage pin.

Table 17.1 Pin Configura tion

Pin Name Symbol I/O Function

Analog power supply pin AVCC Input Analog section power supply and reference

voltage

Analog ground pin AVSS Input Analog section ground and reference

voltage

Reference voltage pin Vref Input Reference voltage of A/D conversion

Analog input pin 0 AN0 Input

Analog input pin 1 AN1 Input

Analog input pin 2 AN2 Input

Analog input pin 3 AN3 Input

Group 0 analog input p ins

Analog input pin 4 AN4 Input

Analog input pin 5 AN5 Input

Analog input pin 6 AN6 Input

Analog input pin 7 AN7 Input

Group 1 analog input p ins

Analog input pin 8 AN8 Input

Analog input pin 9 AN9 Input

Analog input pin 10 AN10 Input

Analog input pin 11 AN11 Input

Group 2 analog input p ins

Analog input pin 12 AN12 Input

Analog input pin 13 AN13 Input

Analog input pin 14 AN14 Input

Analog input pin 15 AN15 Input

Group 3 analog input p ins

A/D external trigger input pin

ADTRG

Input External trigger input pin for starting A/D

conversion

Section 17 A/D Converter

Rev. 3.00 Oct 04, 2005 page 452 of 598

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17.3 Register Description

The A/D converter has the following registers. Module stop mode for the A/D converter is

specified with the MSTPA1 bit in the module stop control register (MSTPCRA). For details on the

module stop control register A (MSTPCRA), refer to section 21.1.2, Module Stop Control

• A/D data register A (ADDRA)

• A/D data register B (ADDRB)

• A/D data register C (ADDRC)

• A/D data register D (ADDRD)

• A/D control/status register (ADCSR)

• A/D control register (ADCR)

17.3.1 A/D Data Registers A to D (ADDRA to ADDRD)

There are four 16-bit read-only ADDR registers ADDRA to ADDRD, used to store the results of

A/D conversion. The ADDR registers to store conversion results for each channel are shown in

table 17.2.

The converted 10-bit data is stored in bits 6 to 15 in ADDR. The lower 6 bits are always read as 0.

The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read

directly from the CPU, however the lower byte should be read via a temporary register. The

temporary register contents are transferred from the ADDR when the upper byte data is read.

When reading the ADDR, always read the upper byte first, and then read the lower byte, or read in

word unit. Otherwise, the read contents are not guaranteed.

Table 17.2 Analog Input Channels and Corresponding ADDR Registers

Analog Input Channel

CH3 = 0 CH3 = 1

Group 0

(CH2 = 0) Group 1

(CH2 = 1) Group 2

(CH2 = 0) Group 3

(CH2 = 1)

A/D Data Register to

Store the A/D

Conversion Results

AN0 AN4 AN8 AN12 ADDRA

AN1 AN5 AN9 AN13 ADDRB

AN2 AN6 AN10 AN14 ADDRC

AN3 AN7 AN11 AN15 ADDRD

Section 17 A/D Converter

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17.3.2 A/D Control/Status Register (ADCSR)

ADCSR controls A/D conversion operations.

Bit Bit Name Initial Value R/W Description

7 ADF 0 R/(W) A/D End Flag

A status flag that indicates the end of A/D

conversion.

[Setting conditions]

• When A/D conversion ends in single mode

• When A/D conversion ends on all specified

channels selected in scan mode

[Clearing conditions]

• When 0 is written after reading ADF = 1

• When the DTC is activated by an ADI interrupt

and ADDR is read

6 ADIE 0 R/W A/D Interrupt Enable

A/D conversion end interrupt (ADI) is enabled

when this bit is set to 1.

5 ADST 0 R/W A/D Start

Clearing this bit to 0 stops A/D conversion, and the

A/D converter enters the wait state.

Setting this bit to 1 starts A/D conversion. In si ngle

mode, this bits is automatically cleared to 0 when

conversion on the specified channel is complete. In

scan mode, conversion continues sequentially on

the specified channels until this bit is cleared to 0

by software, a reset, or a transition to software

standby mode, hardware standby mode or module

stop mode.

Section 17 A/D Converter

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Bit Bit Name Initial Value R/W Description

4 SCAN 0 R/W Scan Mode

Selects the A/D conversion operating mode.

0: Single mode

1: Scan mode

CH3

CH2

CH1

CH0

R/W

Channel Select 0 to 3

Select analog input channels.

When SCAN = 0 When SCAN = 1

0000: AN0 0000: AN0

0001: AN1 0001: AN1, AN0

0010: AN2 0010: AN2 to AN0

0011: AN3 0011: AN3 to AN0

0100: AN4 0100: AN4

0101: AN5 0101: AN5, AN4

0110: AN6 0110: AN6 to AN4

0111: AN7 0111: AN7 to AN4

1000: AN8 1000: AN8

1001: AN9 1001: AN9, AN8

1010: AN10 1010: AN10 to AN8

1011: AN11 1011: AN11 to AN8

1100: AN12 1100: AN12

1101: AN13 1101: AN13, AN12

1110: AN14 1110: AN14 to AN12

1111: AN15 1111: AN15 to AN12

Section 17 A/D Converter

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17.3.3 A/D Control Register (ADCR)

The ADCR enables A/D conversion started by an external trigger signal.

Bit Bit Name Initial Value R/W Description

6TRGS1

TRGS0 0

0R/W

R/W Timer Trigger Select 1 and 0

Enable the start of A/D conversion by a trigger

signal. Bits TRGS0 and TRGS1 should be set

while A/D conversion is stopped (ADST = 0).

00: A/D conversion is started by software

01: A/D conversion is started by TPU conversion

start trigger

10: Start of A/D conversion by 8-bit timer

conversion start trigger is allowed

11: A/D conversion is started by the

ADTRG

5, 4 All 1 Reserved

These bits are always read as 1.

2CKS1

CKS0 0

0R/W

R/W Clock Select 1 and 0

Specify the A/D conversion time. The conversion

time should be changed only when ADST = 0.

Specify a value within the range shown in table

23.7.

00: Conversion time = 530 states (max.)

01: Conversion time = 266 states (max.)

10: Conversion time = 134 states (max.)

11: Conversion time = 68 states (max.)

1, 0 All 1 Reserved

These bits are always read as 1.

Section 17 A/D Converter

Rev. 3.00 Oct 04, 2005 page 456 of 598

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17.4 Operation

The A/D converter operates by successive approximation with 10-bit resolution. It has two

operating modes; single mode and scan mode. When changing the operating mode or analog input

channel, clear the ADST bit in ADCSR to 0 first in order to prevent incorrect operation. The

ADST bit can be set at the same time as the operating mode or analog input channel is changed.

17.4.1 Single Mode

In single mode, A/D conversion is performed only once on the specified single channel as follows.

1. A/D conversion is started when the ADST bit is set to 1 by software or external trigger input.

2. When A/D conversion is completed, the result is transferred to the A/D data register

corresponding to the channel.

3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at

this time, an ADI interrupt request is generated.

4. The ADST bit retains 1 during A/D conversion. When A/D conversion ends, the ADST bit is

automatically cleared to 0 and the A/D converter enters the wait state. If the ADST bit is

cleared to 0 during A/D conversion, the conversion is stopped and the A/D converter enters the

wait state.

17.4.2 Scan Mode

In scan mode, A/D conversion is to be performed sequentially on the specified channels up to four

channels as follows.

1. When the ADST bit is set to 1 by software, TPU or external trigger input, A/D conversion

starts on the first channel in the group (for example, AN0 when CH3 and CH2 = 00, AN4

when CH3 and CH2 = 01, AN8 when CH3 and CH2 = 10, or AN12 when CH3 and CH2 =

11).

2. When the A/D conversion is completed on one channel, the result is sequentially transferred to

the A/D data register corresponding to the channel.

3. When the conversion is completed on all the selected channels, the ADF bit in ADCSR is set

to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion

ends. Then, the A/D converter restarts the conversion from the first channel in the group.

4. Steps 2 to 3 are repeated as long as the ADST bit is set to 1. When the ADST bit is cleared to

0, the A/D conversion stops and the A/D converter enters the wait state.

Section 17 A/D Converter

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17.4.3 Input Sampling and A/D Conversion Time

The A/D converter includes the sample-and-hold circuit. The A/D converter samples the analog

input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, and

then conversion is started. Figure 17.2 shows the A/D conversion timing. Table 17.3 shows the

A/D conversion time.

As shown in figure 17.2, the A/D conversion time (tCONV) includes tD and input sampling time

(tSPL). The length of tD varies depending on the timing of the write access to ADCSR. Therefore,

the total conversion time varies within the range shown in table 17.3.

In scan mode, the values given in table 17.3 indicate the first conversion time. The second and

subsequent conversion time is shown in table 17.4. In both cases, set bits CKS1 and CKS0 in

ADCR within the range shown in table 23.7.

(1)

(2)

SPL

CONV

Address

Write signal

Input sampling

timing

ADF

Legend:

(1): ADCSR write cycle

(2): ADCSR address

: A/D conversion start delay

SPL

: Input sampling time

CONV

: A/D conversion time

Figure 17.2 A/D Conversion Timing

Section 17 A/D Converter

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Table 17.3 A/D Conversion Time (Single Mode)

CKS1 = 0 CKS1 = 1

CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1

Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max

A/D conversion

start delay tD18 33 10 17 6 945

Input sampling

time tSPL 127 63 31 15 

A/D conversion

time tCONV 515 530 259 266 131 134 67 68

Note: All values represent the number of states.

Table 17.4 A/D Conversion Time (Scan Mode)

CKS1 CKS0 Conversion Ti me (State)

0 512 (Fixed)0

1 256 (Fixed)

0 128 (Fixed)1

1 64 (Fixed)

Section 17 A/D Converter

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17.4.4 External Trigger Input Timing

A/D conversion can be externally triggered. When bits TRGS0 and TRGS1 in ADCR are set to

11, an external trigger is input on the

ADTRG

pin. At the falling edge of the

ADTRG

pin, the

ADST bit in ADCSR is set to 1, and the A/D conversion starts. Other operations are the same as

when the ADST bit has been set to 1 by software in both single and scan modes. Figure 17.3

shows the timing.

ADTRG

Internal trigger signal

ADST A/D conversion

Figure 17.3 External Trigger Input Timing

17.5 Interrupt Source

When A/D conversion is completed, the A/D converter generates an A/D conversion end interrupt

(ADI). The ADI interrupt request is enabled when the ADIE bit is set to 1 while the ADF bit in

ADCSR is set to 1 after A/D conversion is completed. The DTC can be activated by an ADI

interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables

continuous conversion without imposing a load on software.

Table 17.5 A/D Converter Interrupt Source

Name Interrupt Source Interrupt Source Flag DTC Activation

ADI A/D conversion completed ADF Possible

Section 17 A/D Converter

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17.6 A/ D Conversion Acc uracy Defini tions

This LSI’s A/D conversion accuracy definitions are given below.

• Resolution

The number of A/D converter digital output codes

• Q uan ti z ati o n er ro r

The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.4).

• O ffs et er ror

The deviation of the analog input voltage value from the ideal A/D conversion characteristic

when the digital output changes from the minimum voltage value B'0000000000 (H'000) to

B'0000000001 (H'001) (see figure 17.5).

• Full-scale error

The deviation of the analog input voltage value from the ideal A/D conversion characteristic

when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see

figure 17.5).

• Nonlinearity error

The error with respect to the ideal A/D conversion characteristic between zero voltage and full-

scale voltage. Does not include offset error, full-scale error, or quantization error (see figure

17.5).

• Absolute accuracy

The deviation between the digital value and the analog input value. Includes offset error, full-

scale error, quantization error, and nonlinearity error.

Section 17 A/D Converter

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111

110

101

100

011

010

001

000 1

1024 2

1024 1022

1024 1023

1024 FS

Quantization error

Digital output

Ideal A/D conversion

characteristic

Analog

input voltage

Figure 17.4 A/D Conversion Accuracy Definitions

Digital output

Ideal A/D conversion

characteristic

Nonlinearity

error

Analog

input voltage

Offset error

Actual A/D conversion

characteristic

Full-scale error

Figure 17.5 A/D Conversion Accuracy Definitions

Section 17 A/D Converter

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17.7 Usage Notes

17.7.1 Module Stop Mode Setti ng

Operation of the A/D converter can be disabled or enabled using the module stop control register.

The initial setting is for operation of the A/D converter to be halted. Register access is enabled by

clearing module stop mode. For details, refer to section 21, Power-Down Modes.

17.7.2 Permissible Signal Source Impedance

This LSI’s analog input is designed such that conversion accuracy is guaranteed for an input signal

for which the signal source impedance is 5 kΩ o r less. This specification is provided to enable the

A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time;

if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be

possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with

a large capacitance provided externally, the input load will essentially comprise only the internal

input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-pass

filter effect is obtained in this case, it may not be possible to follow an analog signal with a large

differential coefficient (e.g., 5 mV/µs or greater) (see figure 17.6). When converting a high-speed

analog signal or converting in scan mode, a low-impedance buffer should be inserted.

17.7.3 Influences on Absolute Accuracy

Adding capacitance results in coupling with GND, and therefore noise in GND may adversely

affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as

AVss.

Care is also required to insure that filter circuits do not communicate with digital signals on the

mounting board (i.e., acting as antennas).

20 pF

10 kΩ

15 pF

Sensor output

impedance

to 5 kΩ

This LSI

Low-pass

filter C

to 0.1 µF

Sensor input

A/D converter

equivalent circuit

Figure 17.6 Example of Analog Input Circuit

Section 17 A/D Converter

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17.7.4 Range of Analog Power Supply and Other Pin Settings

If the conditions below are not met, the reliability of the device may be adversely affected.

• Analog input voltage range

The voltage applied to analog input pin ANn during A/D conversion should be in the range

AVss ≤ VNn ≤ AVcc.

• Relationship between AVcc, AVss and Vcc, Vss

Set AVss = Vss as the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is

not used, the AVcc and AVss pins must not be left open.

• Setting range of the Vref pin

The reference voltage set by the Vref pin should be in the range Vref ≤ AVcc.

17.7.5 Notes on Board Design

In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,

and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close

proximity should be avoided as far as possible. Failure to do so may result in incorrect operation

of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital

circuitry must be isolated from the analog input signals (AN15 to AN0) and analog power supply

(AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one

point to a stable digital ground (Vss) on the board.

17.7.6 Notes on Noise Countermeasures

A protection circuit should be connected in order to prevent damage due to abnormal voltage, such

as an excessive surge at the analog input pins (AN15 to AN0), between AVcc and AVss, as shown

in figure 17.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to

AN15 to AN0 must be connected to AVss.

If a filter capacitor is connected, the input currents at the analog input pins (AN15 to AN0) are

averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in

scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit

in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in

the analog input pin voltage. Careful consideration is therefore required when deciding circuit

constants.

Section 17 A/D Converter

Rev. 3.00 Oct 04, 2005 page 464 of 598

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AVCC

AN0 to AN15

AVSS

100 Ω

0.1 µF

0.01 µF10 µF

Notes: Values are reference values.

2. R

: Input impedance

Figure 17.7 Example of Analog Input Protection Circuit

Table 17.6 Analog Pin Spec ifications

Item Min Max Unit

Analog input capacitance 20 pF

Permissible signal source impedance 5kΩ

20 pF

AN15 to AN0

Note: Values are reference values.

10 kΩ

To A/D converter

Figure 17.8 Analog Input Pin Equivalent Circuit

Section 18 RAM

Rev. 3.00 Oct 04, 2005 page 465 of 598

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Section 18 R AM

The H8S/2628 has 8 kbytes, and the H8S/2627 has 6 kbytes of on-chip high-speed static RAM.

The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to

both byte data and w ord data.

The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control

(SYSCR).

Product Model ROM Type Capacity Address

H8S/2628 Group HD64F2628 Flash me mory

version 8 kbytes H'FFD000 to H'FFEFBF

HD6432628 8 kbytes H'FFD000 to H'FFEFBF

HD6432627

Masked ROM

version 6 kbytes H'FFD800 to H'FFEFBF

Section 18 RAM

Rev. 3.00 Oct 04, 2005 page 466 of 598

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Section 19 ROM

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Section 19 R OM

The features of the flash memory are summarized below.

The block diagram of the flash memory is shown in figure 19.1.

19.1 Features

• Size: 128 kbytes

• Programming/erase methods

 The flash memory is programmed 128 bytes at a time. Erase is performed in single-block

units. The flash memory is configured as follows: 32 kbytes × 2 blocks, 28 kbytes × 1

block, 16 kbytes × 1 block, 8 kbytes × 2 blocks, and 1 kbyte × 4 blocks. To erase th e enti re

flash memory, each block must be erased in turn.

• Reprogramming capability

 The flash memory can be reprogrammed up to 100 times.

• Three programming modes

 Boot mode

 User mode

 Programmer mode

 On-board programming/erasing can be done in boot mode, in which the boot program built

into the chip is started to erase or program of the entire flash memory. In normal user

program mode, individual blocks can be erased or programmed.

• Programmer mode

 Flash memory can be programmed/erased in programmer mode using a PROM

programmer, as well as in on-board programming mode.

• Automatic bit rate adjustment

 For data transfer in boot mode, this LSI’s bit rate can be automatically adjusted to match

the tr an s fe r bi t ra te o f the h os t.

• Programming/erasing protection

 Sets software protection against flash memory programming/erasing.

ROM3120B_000020020900

Section 19 ROM

Rev. 3.00 Oct 04, 2005 page 468 of 598

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Module bus

Bus interface/controller

Flash memory

(128 kbytes)

Operating

mode

FLMCR2

Internal address bus

Internal data bus (16 bits)

FWE pin

Mode pins

EBR1

EBR2

RAMER

FLMCR1

Flash memory control register 1

Flash memory control register 2

Erase block register 1

Erase block register 2

RAM emulation register

Legend:

FLMCR1:

FLMCR2:

EBR1:

EBR2:

RAMER:

Figure 19.1 Block Diagram of Flash Memory

19.2 Mode Transition s

When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, this

LSI enters an operating mode as shown in figure 19.2. In user mode, flash memory can be read but

not p rogram med or erased .

The boot, user program and programmer modes are provided as modes to write and erase the flash

memory.

The differences between boot mode and user program mode are shown in table 19.1.

Figure 19.3 shows the operation flow for boot mode and figure 19.4 shows that for user program

mode.

Section 19 ROM

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Boot mode

On-board programming mode

User

program mode

User mode

(on-chip ROM

enabled)

Reset state

Programmer

mode

RES = 0

FWE = 1 FWE = 0

Notes: Only make a transition between user mode and user program mode when the CPU is

not accessing the flash memory.

1. RAM emulation possible

2. This LSI transits to programmer mode by using the dedicated PROM programmer.

RES = 0

MD2 = 0,

MD1 = 1,

FWE = 1

RES = 0

MD1 = 1,

MD2 = 1,

FWE = 0

MD1 = 1,

MD2 = 1,

FWE = 1

Figure 19.2 Flash Memory State Transitions

Table 19.1 Differences between Boot Mode and User Program Mode

Boot Mode User Program Mode

Total erase Yes Yes

Block erase No Yes

Programming control program*(2) ( 1) (2) (3)

(1) Erase/erase-verify

(2) Program/program-verify

(3) Emulation

Note: *To be provided by the user, in accordance with the recommended algorithm.

Section 19 ROM

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Flash memory

This LSI

RAM

Host

Programming control

program

SCI

Application program

(old version)

New application

program

Flash memory

This LSI

RAM

Host

SCI

Boot program area

New application

program

Flash memory

This LSI

RAM

Host

SCI

Flash memory

preprogramming

erase

Boot program

New application

program

Flash memory

This LSI

Program execution state

RAM

Host

SCI

New application

program

Boot program

Programming control

program

1. Initial state

The old program version or data remains written

in the flash memory. The user should prepare the

programming control program and new

application program beforehand in the host.

2. Programming control program transfer

When boot mode is entered, the boot program in

this LSI (originally incorporated in the chip) is

started and the programming control program in

the host is transferred to RAM via SCI

communication. The boot program required for

flash memory erasing is automatically transferred

to the RAM boot program area.

3. Flash memory initialization

The erase program in the boot program area (in

RAM) is executed, and the flash memory is

initialized (to H'FF). In boot mode, total flash

memory erasure is performed, without regard to

blocks.

4. Writing new application program

The programming control program transferred

from the host to RAM is executed, and the new

application program in the host is written into the

flash memory.

Programming control

program

Boot programBoot program

Boot program area Boot program area

Programming control

program

Application program

(old version)

Figure 19.3 Boot Mode

Section 19 ROM

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Flash memory

This LSI

RAM

Host

Programming/

erase control program

SCI

Boot program

New application

program

Flash memory

This LSI

RAM

Host

SCI

New application

program

Flash memory

This LSI

RAM

Host

SCI

Flash memory

erase

Boot program

New application

program

Flash memory

This LSI

Program execution state

RAM

Host

SCI

Boot program

FWE assessment

program

Application program

(old version)

New application

program

1. Initial state

The FWE assessment program that confirms that

user program mode has been entered, and the

program that will transfer the programming/erase

control program from flash memory to on-chip

RAM should be written into the flash memory by

the user beforehand. The programming/erase

control program should be prepared in the host

or in the flash memory.

2. Programming/erase control program transfer

When user program mode is entered, user

software confirms this fact, executes transfer

program in the flash memory, and transfers the

programming/erase control program to RAM.

3. Flash memory initialization

The programming/erase program in RAM is

executed, and the flash memory is initialized (to

H'FF). Erasing can be performed in block units,

but not in byte units.

4. Writing new application program

Next, the new application program in the host is

written into the erased flash memory blocks. Do

not write to unerased blocks.

Programming/

erase control program

Programming/

erase control program

Programming/

erase control program

Transfer program

Application program

(old version)

Transfer program

FWE assessment

program

FWE assessment

program

Transfer program

FWE assessment

program

Transfer program

Figure 19.4 User Program Mode

Section 19 ROM

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19.3 Block Configuration

Figure 19.5 shows the block configuration of 128-kbyte flash memory. The thick lines indicate

erasing units, the narrow lines indicate programming units, and the values are addresses. The flash

memory is divided into 32 kbytes (2 blocks), 28 kbytes (1 block), 16 kbytes (1 block), 8 kbytes (2

blocks), and 1 kbyte (4 blocks). Erasing is performed in these units. Programming is performed in

128-byte units starting from an address with lower eight bits H'00 or H'80.

EB0

Erase unit

1 kbyte

EB1

Erase unit

1 kbyte

EB2

Erase unit

1 kbyte

EB3

Erase unit

1 kbyte

EB4

Erase unit

28 kbytes

EB5

Erase unit

16 kbytes

EB6

Erase unit

8 kbytes

EB7

Erase unit

8 kbytes

EB8

Erase unit

32 kbytes

EB9

Erase unit

32 kbytes

H'000000 H'000001 H'000002 H'00007F

H'0003FF

H'00047F

H'00087F

H'000C7F

H'00107F

H'007FFF

H'00807F

H'00BFFF

H'0007FF

H'000BFF

H'000FFF

H'01FFFF

H'00C07F

H'00DFFF

H'00E07F

H'00FFFF

H'01007F

H'017FFF

H'01807F

H'000400 H'000401 H'000402

H'000780 H'000781 H'000782

H'000800 H'000801 H'000802

H'000B80 H'000B81 H'000B82

H'000F80 H'000F81 H'000F82

H'007F80 H'007F81 H'007F82

H'00BF80 H'00BF81 H'00BF82

H'00DF80 H'00DF81 H'00DF82

H'00FF80 H'00FF81 H'00FF82

H'017F80 H'017F81 H'017F82

H'01FF80 H'01FF81 H'01FF82

H'000C00 H'000C01 H'000C02

H'001000 H'001001 H'001002

H'008000 H'008001 H'008002

H'00C000 H'00C001 H'00C002

H'00E000 H'00E001 H'00E002

H'010000 H'010001 H'010002

H'018000 H'018001 H'018002

H'000380 H'000381 H'000382

Programming unit: 128 bytes

Figure 19.5 Flash Memory Block Configuration

Section 19 ROM

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19.4 Input/Output Pins

The flash memory is controlled by means of the pins shown in table 19.2.

Table 19.2 Pin Configura tion

Pin Name I/O Function

RES

Input Reset

FWE Input Flash program/erase protection by hardware

MD2 Input Sets this LSI’s operating mode

MD1 Input Sets this LSI’s operating mode

MD0 Input Sets this LSI’s operating mode

TxD2 Output Serial transmit data output

Rx D2 Input Serial receive data input

19.5 Register Descriptions

The flash memory has the following registers.

Flash memory control register 1 (FLMCR1)

Flash memory control register 2 (FLMCR2)

Erase block register 1 (EBR1)

Erase block register 2 (EBR2)

RAM emulation register (RAMER)

19.5.1 Flash Memory Control Register 1 (FLMCR1)

FLMCR1 makes the flash memory enter program mode, program-verify mode, erase mode, or

erase-verify mode. For details on the register setting, refer to section 19.8, Flash Memory

Programming/

Erasing.

Section 19 ROM

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Bit Bit Name Initial Value R/W Description

7 FWE — R Reflects the input level at the FWE pin. It is set to 1

when a low level is input to the FWE pin, and

cleared to 0 when a high level is input.

6 SWE 0 R/W Softw are Write Ena ble

When this bit is set to 1, flash memory

programming/erasing is enabled. When this bit is

cleared to 0, other FLMCR1 register bits and all

EBR1 and EBR2 bits cannot be set.

5 ESU1 0 R/W Erase Setup

When this bit is set to 1, the flash me mory changes

to the erase setup state. When it is cleared to 0,

the erase setup state is cancelled.

4 PSU1 0 R/W Program Setup

When this bit is set to 1, the flash me mory changes

to the program setup state. W hen it is cleared to 0,

the program setup state is cancelled. Set this bit to

1 before setting the P1 bit in FLMCR1.

3 EV1 0 R/W Erase-Verify

When this bit is set to 1, the flash me mory changes

to erase-verify mode. When it is cleared to 0,

erase-verify mode is cancelled.

2 PV1 0 R/W Program-Verify

When this bit is set to 1, the flash me mory changes

to program-verify mode. When it is cleared to 0,

program-verify mode is cancelled.

1E1 0 R/WErase

When this bit is set to 1 while the SWE1 and ESU1

bits are 1, the flash memory changes to erase

mode. When it is cleared to 0, erase mode is

cancelled.

0 P1 0 R/W Program

When this bit is set to 1 while the SWE1 and PSU1

bits are 1, the flash memory changes to program

m ode. When it is cleared to 0, program mode is

cancelled.

Section 19 ROM

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19.5.2 Flash Memory Control Register 2 (FLMCR2)

FLMCR2 indicates the state of flash memory programming/erasing. FLMCR2 is a read-only

Bit Bit Name Initial Value R/W Description

7FLER 0 R Indicates that an error has occurred during flash

memory programming or erasing. When the flash

memory enters the error-protection state, this bit is

set to 1.

See section 19.9.3, Error Protection, for details.

6 to 0 — All 0 — Reserved

These bits are always read as 0.

19.5.3 Erase Bloc k Regis ter 1 (EBR1)

EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit

in FLMCR1 is 0. Do not set more than one bit at a time, otherwise, all the bits in EBR1 are

automatically cleared to 0.

Bit Bit Name Initial Value R/W Description

7 EB7 0 R/W When this bit is set to 1, 8 kbytes of EB7

(H'00E000 to H'00FFFF) will be erased.

6 EB6 0 R/W When this bit is set to 1, 8 kbytes of EB6

(H'00C000 to H'00DFFF) will be erased.

5 EB5 0 R/W When this bit is set to 1, 16 kbytes of EB5

(H'008000 to H'00BFFF) will be erased.

4 EB4 0 R/W When this bit is set to 1, 28 kbytes of EB4

(H'001000 to H'007FFF) will be erased.

3 EB3 0 R/W When this bit is set to 1, 1 kbyte of EB3 (H'000C00

to H'000FFF) will be erased.

2 EB2 0 R/W When this bit is set to 1, 1 kbyte of EB2 (H'000800

to H'000BFF) will be erased.

1 EB1 0 R/W When this bit is set to 1, 1 kbyte of EB1 (H'000400

to H'0007FF) will be erased.

0 EB0 0 R/W When this bit is set to 1, 1 kbyte of EB0 (H'000000

to H'0003FF) will be erased.

Section 19 ROM

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19.5.4 Erase Bloc k Register 2 (EBR2 )

EBR2 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit

in FLMCR1 is 0. Do not set more than one bit at a time, otherwise, all the bits in EBR1 are be

automatically cleared to 0.

Bit Bit Name Initial Value R/W Description

7 to

2—All 0—Reserved

These bits are always read as 0.

1 EB9 0 R/W When this bit is set to 1, 32 kbytes of EB9

(H'018000 to H'01FFFF) will be erased.

0 EB8 0 R/W When this bit is set to 1, 32 kbytes of EB8

(H'010000 to H'017FFF) will be erased.

19.5.5 RAM Emulation Register (RAMER)

RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating

real-time flash memory programming. RAMER settings should be made in user mode or user

program mode. To ensure correct operation of the emulation function, the ROM for which RAM

emulation is performed should not be accessed immediately after this register has been modified.

If accessed, normal access execution is not guaranteed.

Bit Bit Name Initial Value R/W Description

6—

—0

0—

—Reserved

These bits are always read as 0.

4—

—0

0R/W Reserved

Only 0 should be written to these bits.

3 R AMS 0 R/W RAM Select

Specifies selection or non-selection of flash

memory emulation in RAM. W h en RAMS = 1, the

flash memory is overlapped with part of RAM, and

all flash memory blocks are program/erase-

protected.

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Bit Bit Name Initial Value R/W Description

RAM2

RAM1

RAM0

R/W

Flash Memory Area Selection

Specifies one of the following flash memory areas

to overlap the RAM area of H'FFE000 to H'FFE3FF

when the RAMS bit is set to 1. The areas

correspond with 1-kbyte erase blocks.

00×: H'000000 to H'0003FF (EB0)

01×: H'000400 to H'0007FF (EB1)

10×: H'000800 to H'000BFF (EB2)

11×: H'000C00 to H'000FFF (EB3)

Legend: ×: Don’t care

19.6 On- Bo ard Programming Mode s

There are two modes for programming/erasing of the flash memory; boot mode enabling on-board

programming/erasing and programmer mode enabling programming/erasing with a PROM

programmer. On-board programming/erasing can also be performed in user program mode. At

reset-start in reset mode, this LSI changes to a mode depending on the MD pin settings and FWE

pin setting, as shown in table 19.3. The input level of each pin must be defined four states before

the reset ends.

When boot mode is entered, the boot program built into this LSI is initiated. The boot program

transfers the programming control program from the externally-connected host to on-chip RAM

via SCI_2. After erasing the entire flash memory, the programming control program is executed.

This can be used for programming initial values in the on-board state or for a forcible return in

case that programming/erasing cannot be performed in user program mode. In user program mode,

individual blocks can be erased and programmed by branching to the user program/erase control

program prepared by the user.

Table 19.3 Setting On-Boa rd Progra mmin g Modes

MD2 MD1 MD0 FWE LSI State after Reset End

1 1 1 1 User Mode

0 1 1 1 Boot Mode

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19.6.1 Boot Mode

Table 19.4 shows the boot mode operations from a reset end to a branch to the programming

control program.

1. In boot mode, the flash memory programming control program must be prepared in the host

beforehand. Pre par e a programming control program in accordance with the description in

section 19.8, Flash Memory Programming/Erasing.

2. SCI_2 should be set to asynchronous mode with the transfer format of 8-bit data, 1 stop bit,

and no parity.

3. When the boot program is initiated, the chip measures the low-level period of asynchronous

SCI communication data (H'00) transmitted continuously from the host. The chip then

calculates the bit rate of transmission from the host, and adjusts the SCI_2 bit rate to match

that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be

pulled up on the board if necessary. After the reset is complete, it takes approximately 100

states before the chip is ready to measure the low-level period.

4. When the bit rate matching is completed, the chip transmits 1-byte data H'00 to the host to

indicate the end of bit rat e adjustmen t. The host should con fi rm that this adjus tmen t end

indication (H'00) has been received normally, and transmit 1-byte data H'55 to the chip. If

reception could not be performed normally, initiate boot mode again by a reset. Depending on

the host’s transfer bit rate and system clock frequency of this LSI, there will be a discrepancy

between the bit rates of the host and the chip. To operate the SCI properly, set the host’s

transfer bit rate and system clock frequency of this LSI within the ranges listed in table 19.5.

5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFE800

to H'FFEFBF is used to store the programming control program to be transferred from the

host. The boot program area cannot be used until the execution is shifted to the programming

control program.

6. Before branching to the programming control program, the chip terminates transfer operations

by SCI_2 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value is

retained in BRR. Therefore, the programming control program can still use it for transfer of

write data or verify data with the host. At this time, the TxD pin is in the high level output

state. The contents of the CPU general registers are undefined immediately after branching to

the programming control program. These registers must be initialized at the beginning of the

programming control program, since the stack pointer (SP), in particular, is used implicitly in

subroutine calls, etc.

7. Boot mode can be cleared by a reset. End the reset by driving the reset pin low, waiting at least

20 states, and then setting the mode (MD) pins. Boot mode is also cleared when a WDT

overflow occurs.

8. Do not change the MD pin input level in boot mode.

Section 19 ROM

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9. All interrupts are disabled during programming or erasing of the flash memory.

Table 19.4 Boot Mode Opera tion

Item Host Operation Communications Contents LSI Operation

Boot mode

start Branches to boot program at reset-start

Processing Contents Processing Contents

Bit rate

adjustment Continuously transmits data H'00 at

specified bit rate H'00, H'00 ...... H'00

H'00

H'55

· Measures low-level period of receive data

H'00

· Calculates bit rate and sets it in BRR of

SCI_2

· Transmits data H'00 to host as adjustment

end indication

Transmits data H'AA to host when data

H'55 is received

Transmits data H'55 when data H'00

is received error-free

Transmits number of bytes (N) of

programming control program to be

transferred as 2-byte data (low-order

byte following high-order byte)

Receives data H'AA

Transmits 1-byte of programming

control program (repeated for

N times)

Receives data H'AA

Transfer of

programming

control

program

Flash memory

erase

Boot program initiation

Echobacks the 2-byte data received

Branches to programming control program

transferred to on-chip RAM and starts

execution

Echobacks received data to host and also

transfers it to RAM (repeated for N times)

Checks flash memory data, erases all

flash memory blocks in case of written

data existing, and transmits data H'AA to

host (If erase could not be done,

transmits data H'FF to host and aborts

operation)

High-order byte and

low-order byte

H'XX

H'AA

Echoback

H'FF

H'AA

Boot program

erase error

Table 19.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is

Possible

Host Bit Rate System Clock Frequency Range of LSI

19,200 bps 24 MHz

9,600 bps 24 to 8 MHz

4,800 bps 24 to 4 MHz

Section 19 ROM

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19.6.2 Progra mming/E ras ing in User Progr a m Mode

On-board programming/erasing of an individual flash memory block can also be performed in user

program mode by branching to a user program/erase control program. The user must set branching

conditions and provide on-board means of supplying programming data. The flash memory must

contain the user program/erase control program or a program that provides the user program/erase

control program from external memory. Since the flash memory itself cannot be read during

programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot

mode. Figure 19.6 shows a sample procedure for programming/erasing in user program mode.

Prepare a user program/erase control program in accordance with the description in section 19.8,

Flash Memory Programming/Erasing.

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Yes

Program/erase?

Transfer user program/erase control

program to RAM

Reset-start

Branch to user program/erase control

program in RAM

Execute user program/erase control

program (flash memory rewrite)

Branch to flash memory application

program

Branch to flash memory application

program

FWE = high*

Clear FWE

Do not constantly apply a high level to the FWE pin. Only apply a high level to the FWE pin

when programming or erasing the flash memory. To prevent excessive programming or

erasing, while a high level is being applied to the FWE pin, activate the watchdog timer in

case of handling CPU runaways.

Note: *

Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode

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19.7 Flash Memory Emulation in RAM

A setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto

the flash memory area so that data to be written to flash memory can be emulated in RAM in real

time. Emulation can be performed in user mode or user program mode. Figure 19.7 shows an

example of emulation of real-time flash memory programming.

1. Set RAMER to overlap part of RAM onto the area for which real-time programming is

required.

2. Emulation is performed using the overlapping RAM.

3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing the RAM

overlap.

4. The data written in the overlapping RAM is written into the flash memory space (EB0).

Start of emulation program

Set RAMER

Write tuning data to overlap

RAM

Execute application program

Tuning OK?

Clear RAMER

Write to flash memory

emulation block

End of emulation program

Yes

Figure 19.7 Flowchart for Flash Memory Emulation in RAM

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An example in which flash memory block area EB0 is overlapped is shown in figure 19.8.

1. The RAM area to be overlapped is fixed at a 1-kbyte area in the range H'FFE000 to H'FFE3FF.

2. The flash memory area to overlap is selected by RAMER from a 1-kbyte area of the EB0 to

EB3 blocks.

3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM

addresses.

4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash

memory blocks (emulation protection). In this state, setting the P1 or E1 bit in FLMCR1 to 1

does not make a transition to program mode or erase mode.

5. A RAM area cannot be erased by execution of software in accordance with the erase

algorithm.

6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table

is needed in the overlap RAM.

H'000000 Flash memory

(EB0) Flash memory

(EB0)

(EB1)

(EB2)

(EB3)

H'0003FF

H'000400

H'0007FF

H'000800

H'000BFF

H'000C00

H'000FFF

H'FFE000

H'FFE3FF

On-chip RAM

(1 kbyte)

On-chip RAM

(Shadow of

H'FFE000 to

H'FFE3FF)

Flash memory

(EB2)

On-chip RAM

(1 kbyte)

(EB3)

Normal memory map Memory map

with overlapped RAM

Figure 19.8 Example of RAM Overlap Operation

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19.8 Flash Memory Programming/Erasing

The flash memory is programmed or erased in on-board programming mode by a software method

using the CPU. Depending on the FLMCR1 setting, the flash memory operates in one of the

following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode.

The programming control program in boot mode and the user program/erase control program in

user program mode perform programming/erasing in combination with these modes. Flash

memory programming and erasing should be performed in accordance with the descriptions in

section 19.8.1, Program/Program-Verify, and section 19.8.2, Erase/Erase-Verify, respectively.

19.8.1 Program/Program-Verify

When writing data or programs to the flash memory, the program/program-verify flowchart shown

in figure 19.9 should be followed. Performing programming operations according to this flowchart

will enable data or programs to be written to the flash memory without subjecting the chip to

voltage stress or sacrificing program data reliability.

1. Programming must be done on erased addresses. Do not perform additional programming or

previously programmed addresses.

2. Programming should be performed in units of 128 bytes. A 128-byte data must be transferred

even if data to be written is fewer than 128 bytes. In this case, H'FF data must be written to the

extra addresses.

3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128-

byte reprogramming data area, and a 128-by te addition al - programming data area. Perform

reprogramming data computation and additional programming data computation according to

figure 19.9.

4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or

additional-programming data area to the flash memory. The program address and 128-byte

data are latched in the flash memory. The lower 8 bits of the start address in the flash memory

destination area must be H'00 or H'80.

5. The time during which the P1 bit is set to 1 is the programming time. Figure 19.9 shows the

allowable programming times.

6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.

Set the overflow cycle to approximately 6.6 ms.

7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2

bits are B'00. Verify data can be read in longwords from the address to which a dummy write

was performed.

8. The number of repetitions of the program/program-verify sequence for the same bit should be

less than 1,000.

Section 19 ROM

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START

End of programming

Set SWE bit in FLMCR1

Start of programming

Write pulse application subroutine

Wait (t

sswe

) µs

Apply Write Pulse

End Sub

Set PSU bit in FLMCR1

WDT enable

Disable WDT

Number of Writes n

998

999

1000

Note 6: Write Pulse Width

Write Time (tsp) µs

200

Wait (t

spsu

) µs

Set P bit in FLMCR1

Wait (t

) µs

Clear P bit in FLMCR1

Wait (t

) µs

Clear PSU bit in FLMCR1

Wait (t

cpsu

) µs

n = 1

m = 0

No No

Yes

Wait (t

spv

) µs

Wait (t

spvr

) µs

Start of programming

End of programming

Wait (t

cpv

) µs

Apply

Write pulse

Sub-Routine-Call

Set PV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Write data =

verify data?

Transfer reprogram data to reprogram data area

Reprogram data computation

Transfer additional-programming data to

additional-programming data area

Additional-programming data computation

Clear PV bit in FLMCR1

Clear SWE bit in FLMCR1

m = 1

Reprogram

See Note 6 for pulse width

m = 0 ?

Increment address

Programming failure

Yes

Clear SWE bit in FLMCR1

Wait (t

cswe

) µs

Yes

≥

Yes

≥

n ?

Wait (t

cswe

) µs

n ≥ (N) ?

n ← n + 1

Original Data

(D)

Verify Data

(V)

Reprogram Data

(X)

Comments

Programming completed

Programming incomplete; reprogram

Still in erased state; no action

Note: * Use a 10 µs write pulse for additional programming.

Write 128-byte data in RAM reprogram

data area consecutively to flash memory

RAM

Program data storage

area (128 bytes)

Reprogram data storage

area (128 bytes)

Additional-programming

data storage area

(128 bytes)

Store 128-byte program data in program

data area and reprogram data area

Apply Write Pulse (Additional programming)

Sub-Routine-Call

128-byte

data verification completed?

Successively write 128-byte data from additional-

programming data area in RAM to flash memory

Reprogram Data Computation Table

Reprogram Data

(X')

Verify Data

(V)

Additional-

Programming Data

(Y)

Comments

Additional programming to be executed

Additional programming not to be executed

Additional-Programming Data Computation Table

Perform programming in the erased state.

Do not perform additional programming

on previously programmed addresses.

Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to

must be H'00 or H'80.

A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case,

H'FF data must be written to the extra addresses.

2. Verify data is read in 16-bit (word) units.

3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are

programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG.

4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.

The contents of the reprogram data area and additional data area are modified as programming proceeds.

5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of additional-programming data is executed,

a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.

7. The wait times and value of N are shown in 23.5, Flash Memory Characteristics.

Figure 19.9 Program/Program-Verify Flowchart

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19.8.2 Erase/Erase-Verify

When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.10 should be

followed.

1. Prewriting (setting erase block data to all 0s) is not necessary.

2. Erasing is performed in block units. Specify a single block o be erased with the erase block

registers (EBR2 and EBR1). To erase multiple blocks, each block must be erased in turn.

3. The time during which the E bit is set to 1 is the flash memory erase time.

4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set the

overflow cycle to approximately 19.8 ms.

5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two

bits are B'00. Verify data can be read in longwords from the address to which a dummy write

was performed.

6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-

verify sequence as before. Note that the number of repetitions of the erase/erase-verify

sequence should be less than 100.

19.8.3 Interrup t Handlin g when Progra mming /Era sing Flash Memory

All interrupts, including the

NMI

interrupt, should be disabled while flash memory is being

programmed, erased, or the boot program is being executed, for the following three reasons:

1. Interrupt during programming/erasing may cause a violation of the programming or erasing

algorithm, with the result that normal operation cannot be assured.

2. If interrupt exception handling starts before the vector address is written or during

programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.

3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be

carried out.

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Erase start

Set EBR1 and EBR2

Enable WDT

Disable WDT

Read verify data

Increment address Verify data = all 1s?

Last address of block?

All erase block erased?

Set block start address as verify address

H'FF dummy write to verify address

SWE bit ← 1

n ← 1

ESU1 bit ← 1

E1 bit ← 1

Wait 1 µs

Wait 100 µs

E1 bit ← 0

EV1 bit ← 1

Wait 10 ms

ESU1 bit ← 0

Wait 10 µs

Wait 20 µs

EV1 bit ← 0

n ← n + 1

Wait 4 µs

SWE bit ← 0

Wait 100 µs

EV1 bit ← 0

n ≤ 100?

Wait 4 µs

SWE bit ← 0

Wait 100 µs

Erase failure

End of erasing

Wait 2 µs

Yes

Figure 19.10 Erase/Erase-Verify Flowchart

Section 19 ROM

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19.9 Program/Erase Protection

There are three kinds of flash memory program/erase protection; hardware protection, software

protection, and error protection.

19.9.1 Hardw are Pro tection

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly

disabled or aborted because of a transition to reset or standby mode. Flash memory control register

1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are

initialized. In a reset via the

RES

pin, the reset state is not entered unless the

RES

pin is held low

until oscillation settles after powering on. In the case of a reset during operation, hold the

RES

low for the

RES

pulse width specified in the AC characteristics section.

19.9.2 Software Prot ec tion

Software protection can be implemented against programming/erasing of all flash memory blocks

by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P1 or E1

bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase

block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to

H'00, erase protection is set for all blocks.

19.9.3 Error Prot ectio n

In error protection, an error is detected when CPU runaway occurs during flash memory

programming/erasing, or operation is not performed in accordance with the program/erase

algorithm, and the program/erase operation is aborted. Aborting the program/erase operation

prevents damage to the flash memory due to overprogramming or overerasing.

When the following errors are detected during programming/erasing of flash memory, the FLER

bit in FLMCR2 is set to 1, and the error protection state is entered.

• When the flash memory of the relevant address area is read during programming/erasing

(including vector read and instruction fetch)

• Immediately after exception handling (excluding a reset) during programming/erasing

• When a SLEEP instruction is executed during programming/erasing

The FLMCR2, FLMCR1, and EBR1 settings are retained, however program mode or erase mode

is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-

Section 19 ROM

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entered by re-setting the P1 or E1 bit. However, PV1 and EV1 bit setting is enabled, and a

transition can be made to verify mode. Error protection can be cleared only by a power-on reset.

19.10 Programmer Mode

In programmer mode, a PROM programmer can be used to perform programming/erasing via a

socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the

Renesas 128-kbyte flash memory on-chip MCU device type (FZTAT128V5A).

19.1 1 Po we r -D own St at es f or F l ash M emory

In user mode, the flash memory will operate in either of the following states:

• Normal operating mode

The flash memory can be read and written to.

• Standby mode

All flash memory circuits are halted.

Table 19.6 shows the correspondence between the operating modes of the H8S/2628 Group and

the flash memory. When the flash memory returns to its normal operating state from standby

mode, a period to settle the power supply circuits that were stopped is needed. When the flash

memory returns to its normal operating state, bits STS2 to STS0 in SBYCR must be set to provide

a wait time of at least 20 µs, even when the external clock is being used.

Table 19.6 Flash Memory Operating Sta tes

LSI Operating State Flash Memory Operating State

Active mode Normal operating mode

Standby mode Standby mode

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19.12 Note on Switching from F-ZTAT Version to Masked ROM Version

The masked ROM version does not have the internal registers for flash memory control that are

provided in the F-ZTAT version. Table 19.7 lists the registers that are present in the F-ZTAT

version but not in the masked ROM version. If a register listed in table 19.7 is read in the masked

ROM version, an undefined value will be returned. Therefore, if application software developed

on the F-ZTAT version is switched to a masked ROM version product, it must be modified to

ensure that the registers in table 19.7 have no effect.

Table 19.7 Registers Pres ent in F-ZTAT Vers ion but Absen t in Masked ROM Versi on

Flash memory control register 1 FLMCR1 H'FFA8

Flash memory control register 2 FLMCR2 H'FFA9

Erase block register 1 EBR1 H'FFAA

Erase block register 2 EBR2 H'FFAB

RAM emulation register RAMER H'FEDB

Section 20 Clock Pulse Generator

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Section 20 C lock Pulse Generator

This LSI has an on-chip clock pulse generator that generates the system clock (φ), the bus master

clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL circuit, clock

selection circuit, medium-speed clock divider, and bus master clock selection circuit. A block

diagram of the clock pulse generator is shown in figure 20.1.

EXTAL

XTAL

SCK2 to SCK0

SCKCR

STC1, STC0

LPWRCR

Legend:

LPWRCR: Low-power control register

SCKCR: System clock control register

Clock

oscillator PLL circuit

(×1, ×2, ×4) Clock

selection

circuit

System clock

to φ pin Internal clock to

peripheral modules Bus master cloc

to CPU and DTC

Medium-

speed

clock divider Bus

master

clock

selection

circuit

φ/32 to

φ/2

Figure 20.1 Block Diagram of Clock Pulse Generator

The frequency can be changed by means of the PLL circuit. Frequency changes are performed by

software by settings in the low-power control register (LPWRCR) and system clock control

CPG0100B_000020020900

Section 20 Clock Pulse Generator

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20.1 Register Descriptions

The on-chip clock pulse generator has the following registers.

• System clock control register (SCKCR)

• Low-power control register (LPWRCR)

20.1.1 System Clock Control Register (SCKCR)

SCKCR performs φ clock output control, selection of operation when the PLL circuit frequency

multiplication factor is changed, and medium-speed mode control.

Bit Bit Name Initial Value R/W Description

7 PSTOP 0 R/W φ Clock Output Disable

Controls φ output.

High-speed Mode, Medium-Speed Mode

0: φ output

1: Fixed high

Sleep Mode

0: φ output

1: Fixed high

Software Standby Mode

0: Fixed high

1: Fixed high

Hardware Standby Mode

0: High i mpedance

1: High i mpedance

6 to

4All 0 Reserved

These bits are always read as 0.

3 STCS 0 R/W Frequency Multiplication Factor Switching Mode

Select

Selects the operation when the PLL circuit

frequency multiplication factor is changed.

0: Speci fied multiplication factor i s valid after

transition to software standby mode

1: Specified multiplication factor is vali d

immediately after STC1 bit and STC0 bit are

rewritten

Section 20 Clock Pulse Generator

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Bit Bit Name Initial Value R/W Description

SCK2

SCK1

SCK0

R/W

System Clock Select 2 to 0

These bits select the bus master clock.

000: High-speed mode

001: Medium-speed clock is φ/2

010: Medium-speed clock is φ/4

011: Medium-speed clock is φ/8

100: Medium-speed clock is φ/16

101: Medium-speed clock is φ/32

11×: Setting prohibited

Legend:

×: Don’t care

20.1.2 Low-Power Control Register (LPWRCR)

Bit Bit Name Initial Value R/W Description

7 to

4All 0 Reserved

The write value should al ways be 0.

3, 2 All 0 R/W Reserved

These bits can be read from and write to, but

should not be set to 1.

0STC1

STC0 0

0R/W

R/W Frequency Multiplication Factor

The STC bits specify the frequency multiplication

factor of the PLL circuit.

00: ×1

01: ×2

10: ×4

11: Setting prohibited

Section 20 Clock Pulse Generator

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20.2 Oscillator

Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. In

either case, the input clock should not exceed 24 MH z.

20.2.1 Connecting a Crystal Resonator

Circuit Configuration: A crystal resonator can be connected as shown in the example in figure

20.2. Select the damping resistance Rd according to table 20.1. An AT-cut parallel-resonance

crystal should be used.

EXTAL

XTAL RdCL2

CL1

CL1 = CL2 = 22 to 10 pF

Figure 20.2 Connection of Crystal Resonator (Example)

Table 20.1 Damping Resistance Value

Frequency (MHz) 4 8 1012162024

Rd (Ω) 50020000000

Figure 20.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has

the characteristics shown in table 20.2.

XTAL

AT-cut parallel-resonance type

EXTAL

Figure 20.3 Crystal Resonator Equivalent Circuit

Section 20 Clock Pulse Generator

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Table 20.2 Crystal Resonator Characteristics

Frequency (MHz) 4 8 1012162024

RS max ( Ω) 120 80 70 60 50 40 30

C0 max (pF) 7777777

20.2.2 External Clock Input

Circuit Configuration: An external clock signal can be input as shown in the examples in figure

20.4. If the XTAL pin is left open, ensure that stray capacitance does not exceed 10 pF. When

complementary clock is input to the XTAL pin, the external clock input should be fixed high in

standby mode.

EXTAL

XTAL

EXTAL

XTAL

External clock input

Open

External clock input

(a) XTAL pin left open

(b) Complementary clock input at XTAL pin

Figure 20.4 External Clock Input (Examples)

Section 20 Clock Pulse Generator

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Table 20.3 shows the input conditions for the external clock.

Table 20.3 External Clock Input Conditions

VCC = 5.0 V ±

±±

± 10%

Item Symbol Min Max Unit Test Conditions

Ex ternal clock input low

pulse width tEXL 15 ns Figure 20.5

External clock input hi gh

pulse width tEXH 15 ns

External cl ock rise time tEXr 5ns

External clock fall time tEXf 5ns

EXH

EXL

EXr

EXf

× 0.5

EXTAL

Figure 20.5 External Clock Input Timing

Section 20 Clock Pulse Generator

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20.3 PLL Circuit

The PLL circuit multiplies the frequency of the clock from the oscillator by a factor of 1, 2, or 4.

The multiplication factor is set by the STC0 bit and the STC1 bit in LPWRCR. The phase of the

rising edge of the internal clock is controlled so as to match that at the EXTAL pin.

When the multiplication factor of the PLL circuit is changed, the operation varies according to the

setting of the STCS bit in SCKCR.

When STCS = 0, the setting becomes valid after a transition to software standby mode. The

transition time count is performed in accordance with the setting of bits STS2 to STS0 in SBYCR.

For details on SBYCR, refer to section 21.1.1, Standby Control Register (SBYCR).

1. The initial PLL circuit multiplication factor is 1.

2. STS2 to STS0 are set to give the specified transition time.

3. The target value is set in STC1 and STC0, and a transition is made to software standby mode.

4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.

5. Software standby mode is cleared, and a transition time is secured in accordance with the

setting in STS2 to STS0.

6. After the set transition time has elapsed, this LSI resumes operation using the target

multiplication factor.

If a PC break is set for the SLEEP instruction, software standby mode is entered and break

exception handling is executed after the oscillation settling time. In this case, the instruction

following the SLEEP instruction is executed after execution of the RTE instruction. When STCS =

1, this LSI operates on the changed multiplication factor immediately after bits STC1 and STC0

are rew ritt en.

20.4 Medium-Speed Clock Divider

The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.

20.5 Bus Master Clock Selection Circuit

The bus master clock selection circuit selects the clock supplied to the bus master by setting the

bits SCK2 to SCK0 in SCKCR. The bus master clock can be selected from high-speed mode, or

medium-speed clocks (φ/2, φ/4, φ/8, φ/16, φ/32).

Section 20 Clock Pulse Generator

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20.6 Usage Notes

20.6.1 Note on Crystal Resonator

As various characteristics related to the crystal resonator are closely linked to the user’s board

design, thorough evaluation is necessary on the user’s part, using the resonator connection

examples shown in this section as a guide. As the resonator circuit ratings will depend on the

floating capacitance of the resonator and the mounting circuit, the ratings should be determined in

consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the

maximum rating is not applied to the oscillator pin.

20.6.2 Note on Board Design

When designing the board, place the crystal resonator and its load capacitors as close as possible

to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator

circuit, as shown in figure 20.6. This is to prevent induction from interfering with correct

oscillation.

Avoid

Signal A Signal B

This LSI

XTAL

EXTAL

Figure 20.6 Note on Board Design of Oscillator Circuit

Figure 20.7 shows external circuitry recommended to be provided around the PLL circuit. Place

oscillation settling capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no other

signal lines cross this line. Separate PLLVss from the other Vcc and Vss lines at the board power

supply source, and be sure to insert bypass capacitors CB close to the pins.

Section 20 Clock Pulse Generator

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PLLCAP

PLLVSS

VCC

VCL

VSS

(Values are preliminary recommended values.)

Note: * CB is laminated ceramic.

R1 = 3 kΩC1 = 470 pF

CB = 0.1 µF*CB = 0.1 µF

Figure 20.7 External Circuitry Recommended for PLL Circuit

Section 20 Clock Pulse Generator

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Section 21 Power-Down Modes

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Section 21 Power-Down Modes

In addition to the normal program execution state, this LSI has five power-down modes in which

operation of the CPU and oscillator is halted and power consumption is reduced. Low-power

operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and

so on.

This LSI’s operating modes are as follows:

1. High-speed mode

2. Medium-speed mode

3. Sleep mode

4. Module stop mode

5. Software standby mode

6. Hardw are standby mode

2. to 6. are power-down modes. Sleep mode is a CPU state, medium-speed mode is a CPU and bus

master state, and module stop mode is an internal peripheral function (including bus masters other

than the CPU) state. Some of these states can be combined.

After a reset, the LSI is in high-speed mode.

Figure 21.1 shows possible transitions between modes. Table 21.1 shows the conditions of

transition made by the SLEEP instruction and recovery from power-down mode by an interrupt.

Table 21.2 shows the internal states in each mode.

Section 21 Power-Down Modes

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Program-halted state

Program execution state

SCK2 to

SCK0 = 0 SCK2 to

SCK0 ≠ 0

SLEEP command

Any interrupt

SLEEP

command

External

interrupt*

STBY pin = High,

RES pin = Low

STBY pin = Low

SSBY = 0

SSBY = 1

RES pin = High

: Transition after exception processing : Low power dissipation mode

Reset state

High-speed mode

(main clock)

Hardware

standby mode

Software

standby mode

Sleep mode

(main clock)

Medium-speed

mode

(main clock)

Notes: * NMI and IRQ5 to IRQ0

• When a transition is made between modes by means of an interrupt, the transition cannot be

made on interrupt source generation alone. Ensure that interrupt handling is performed after

accepting the interrupt request.

• From any state except hardware standby mode, a transition to the reset state occurs when RES

is driven low.

• From any state, a transition to hardware standby mode occurs when STBY is driven low.

Figure 21.1 Mode Transition Diagram

Table 21.1 Low Power Consumption Mode Transition Conditions

Status of Control

Bit at Transition

Pre-Transition

State SSBY

State after Transition

Invoked b y SLEEP

Command

State after Transition Back

from Low Power Mode

Invoked by Interrupt

0 Sleep High-speed/Medium-speedHigh-speed/

Medium-speed 1 Software standby High-speed/Medium-speed

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Table 21.2 LSI Internal States in Each Mode

Function High-Speed Medium-

Speed Sleep Module

Stop Software

Standby Hardware

Standby

System clock pulse

generator Operate Operate Operate Operate Halted Halted

CPU Instructions

Registers Operate Medium-

speed

operation

Halted

(retained) High/

medium-

speed

operation

Halted

(retained) Halted

(undefined)

NMIExternal

interrupts I RQ5 to IRQ0

Operate Operate Operate Operate Operate Halted

PBC

DTC

Operate Medium-

speed

operation

Operate Halted

(retained) Halted

(reset)

I/O Operate Operate Operate Operate Retained High

impedance

TPU

TMR

PPG

Operate Operate Operate Halted

(retained) Halted

(reset)

WDT Operate Operate Operate Operate Halted

(retained) Halted

(reset)

SCI

HCAN

A/D

Operate Operate Operate Halted*

(reset/

retained)

Halted

(reset) Halted

(reset)

RAM Operate Medium-

speed

operation

Operate

(DTC) Operate Retained Retained

Peripheral

functions

SSU Operate Operate Operate Halted

(reset) Halted

(reset)

Notes: Halted (retained) means that internal register values are retained. The internal state is in the

operation suspended state.

Halted (reset) means that internal register values and internal states are initialized.

In module stop mode, only modules for which a stop setting has been made are halted

(reset or retained).

*The SCI’s TDR, RDR, and SSR are halted (reset), and the other registers are halted

(retained).

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21.1 Register Descriptions

Registers related to the power down mode are shown below. For details on the system clock

control register (SCKCR), refer to section 20.1.1, System Clock Control Register (SCKCR).

• System clock control register (SCKCR)

• Standby control register (SBYCR)

• Module stop control register A (MSTPCRA)

• Module stop control register B (MSTPCRB)

• Module stop control register C (MSTPCRC)

21.1.1 Standby Control Register (SBYCR)

SBYCR is an 8-bit readable/writable register that performs software standby mode control.

Bit Bit Name Initial Value R/W Description

7 SSBY 0 R/W Software Standby

This bit specifies the transition mode after

execut ing the SLEEP instruction

0: Shi fts to sleep mode when the SLEEP

instruction is executed

1: Shi fts to software standby mode when the

SLEEP instruction is executed

This bit does not change when clearing the

software standby mode by using external interrupts

and shifting to normal operation. This bit should be

written with 0 when clearing.

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Bit Bit Name Initial Value R/W Description

STS2

STS1

STS0

R/W

Standby Timer Select 2 to 0

These bits select the MCU wait time for clock

settling when software standby mode is cancelled

by an external interrupt. With a crystal oscillator

(table 21.3), select a wait time of 8 ms (oscillati on

settling time) or more, depending on the operating

frequency. With an external clock, select a wait

time of 2 ms or more.

000: Standby time = 8,192 states

001: Standby time = 16,384 states

010: Standby time = 32,768 states

011: Standby time = 65,536 states

100: Standby time = 131,072 states

101: Standby time = 262,144 states

110: Reserved

111: Standby time = 16 states

31R/WReserved

The write value should al ways be 0.

2 to

0All 0 Reserved

These bits are always read as 0 and cannot be

modified.

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21.1.2 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)

MSTPCR is comprised of three 8-bit readable/writable registers, and performs module stop mode

control. Setting a bit to 1 causes the corresponding module to enter module stop mode. Clearing

the bit to 0 clears the module stop mode.

• MSTPCRA

Bit Bit Name Initial Value R/W Module

7 MSTPA7*0R/W

6 MSTPA6 0 R/W Data transfer controller (DTC)

5 MSTPA5 1 R/W 16-bit timer pulse unit (TPU)

4 MSTPA4 1 R/W 8-bit timer (TMR_1, TMR_0)

3 MSTPA3 1 R/W Programmable pulse generator (PPG)

2 MSTPA2*1R/W

1 MSTPA1 1 R /W A/D converter

0 MSTPA0 1 R/W 8-bit timer (TMR_3, TMR_2)

• MSTPCRB

Bit Bit Name Initial Value R/W Module

7 MSTPB7 1 R/W Serial communication interface 0 (SCI0)

6 MSTPB6*1R/W

5 MSTPB5 1 R/W Serial communication interface 2 (SCI2)

4 MSTPB4*1R/W

3 MSTPB3*1R/W

2 MSTPB2*1R/W

1 MSTPB1*1R/W

0 MSTPB0*1R/W

Section 21 Power-Down Modes

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• MSTPCRC

Bit Bit Name Initial Value R/W Module

7 MSTPC7*1R/W

6 MSTPC6*1R/W

5 MSTPC5*1R/W

4 MSTPC4 1 R/W PC break controller (PBC)

3 MSTPC 3 1 R/W Contro ller area netw ork (HCAN)

2 MSTPC2 1 R/W Synchronous serial communication uni t (SSU)

1 MSTPC1*1R/W

0 MSTPC0*1R/W

Note: *MSTPA7 is a readable/writable bit with an initial value of 0. The write value should

always be 0.

MSTPA2, MSTPB6, MSTPB4 to MSTPB0, MSTPC7 to MSTPC5, MSTPC1, and

MSTPC0 are readable/writable bits with an initial value of 1. The write value should

always be 1.

21.2 Me dium-Spee d Mode

When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-

speed mode as soon as the curre nt bus cy cle ends. In medium - speed mode, the CPU opera tes on

the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. Bus masters

(DTC) other than the CPU also operate in medium-speed mode. On-chip peripheral modules other

than bus masters always operate on the high-speed clock (φ).

In medium-speed mode, a bus access is executed in the specified number of states with respect to

the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip

memory is accessed in 4 states, and internal I/O registers in 8 states.

Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to

high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.

If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is

made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.

When the SLEEP instruction is executed with the SSBY bit = 1, operation shifts to the software

standby mode. When software standby mode is cleared by an external interrupt, medium-speed

mode is restored.

Section 21 Power-Down Modes

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When the

RES

pin is set low and medium-speed mode is cancelled, operation shifts to the reset

state. The same applies in the case of a reset caused by overflow of the watchdog timer.

When the

STBY

pin is driven low, a transition is made to hardware standby mode.

Figure 21.2 shows the timing for transition to and clearance of medium-speed mode.

SCKCR SCKCR

φ,

peripheral module clock

Bus master clock

Internal address bus

Internal write signal

Medium-speed mode

Figure 21.2 Medium-Speed Mode Transition and Clearance Timing

21.3 Sleep Mode

21.3.1 Transit ion to Sleep Mode

If SLEEP instruction is executed when the SBYCR SSBY bit = 0, the CPU enters the sleep mode.

In sleep mode, CPU operation stops, however the contents of the CPU’s internal registers are

retained. Other peripheral modules do not stop.

21.3.2 Clearing Sleep Mode

Sleep mode is cleared by any interrupt, or signals at the

RES

, or

STBY

pins.

• Exiting Sleep Mode by Interrupts:

When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep

mode is not exited if the interrupt is disabled, or if interrupts other than NMI are masked by the

CPU.

• Exiting Sleep Mode by

RES

pin:

Setting the

RES

pin low level selects the reset state. After the stipulated reset input duration,

driving the

RES

pin high level restart the CPU performing reset exception processing.

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• Exiting Sleep Mode by

STBY

Pi n:

When the

STBY

pin level is driven low, a transition is made to hardware standby mode.

21.4 Software Sta ndby Mode

21.4.1 Transition to Software Standby Mode

A transition is made to software standby mode if the SLEEP instruction is executed when the

SBYCR SSBY bit is set to 1. In this mode, the CPU, on-chip peripheral modules, and oscillator,

all stop. However, the contents of the CPU’s internal registers, on-chip RAM data, and the states

of on-chip peripheral modules other than the SCI, SSU, HCAN, A/D converter, and the states of

I/O ports, are retained. In this mode, the oscillator stops, and therefore power consumption is

significantly reduced.

21.4.2 Clearing Software Standby Mode

Software standby mode is cleared by an external interrupt (NMI pin, or pins

IRQ5

IRQ0

), or by

means of the

RES

pin or

STBY

pin.

• Clearing with an interrupt

When an NMI or IRQ5 to IRQ0 interrupt request signal is input, clock oscillation starts, and

after the time set in bits STS2 to STS0 in SBYCR has elapsed, stable clocks are supplied to the

entire chip, software standby mode is cleared, and interrupt exception handling is started.

When clearing software standby mode with an IRQ5 to IRQ0 interrupt, set the corresponding

enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ5 to IRQ0

is generated. Software standby mode cannot be cleared if the interrupt has been masked on the

CPU side or has been designated as a DTC activation source.

• Clearing with the

RES

When the

RES

pin is driven low, clock oscillation is started. At the same time as clock

oscillation starts, clocks are supplied to the entire chip. Not e that the

RES

pin must be held low

until clock oscillation settles. When the

RES

pin goes high, the CPU begins reset exception

handling.

• Clearing with the

STBY

When the

STBY

pin is driven low, a transition is made to hardware standby mode.

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21.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode

Bits STS2 to STS0 in SBYCR should be set as described below.

• Using a Crystal Oscillator:

Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation settling time).

Table 21.3 shows the standby times for different operating frequencies and settings of bits

STS2 to STS0.

• Using an External Clock

The PLL circuit requires a time for settling. Set bits STS2 to STS0 so that the standby time is

at least 2 ms(the oscillation settling time).

Table 21.3 Oscillation Stabilization Time Settings

STS2 STS1 STS0 Standby Time 24

MHz 20

MHz 16

MHz 12

MHz 10

MHz 8

MHz 6

MHz 4

MHz Unit

0 8,192 states 0.34 0.41 0.51 0.68 0.8 1.0 1.3 2 .00

1 16,384 states 0.68 0.82 1.0 1.3 1.6 2.0 2.7 4.1

0 32,768 states 1.4 1.6 2.0 2.7 3.3 4.1 5.5 8.2

1 65,536 states 2.7 3.3 4.1 5.5 6.6 8.2 10.9 16.4

0 131,072 states 5.5 6.6 8.2 10.9 13.1 16.4 21.8 32.80

1 262,144 states 10.9 13.1 16.4 21.8 26.2 32.8 43.6 65.6

0 Reserved 

1 16 states*0.7 0.8 1.0 1.3 1.6 2.0 1.7 4.0 µs

: Recommended time setting

Note: *Cannot be used in this LSI.

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21.4.4 Software Standby Mode Application Example

Figure 21.3 shows an example in which a transition is made to software standby mode at the

falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI

pin.

In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling

edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set

to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.

Software standby mode is then cleared at the rising edge on the NMI pin.

Oscillator

NMI

NMIEG

SSBY

NMI exception

handling

NMIEG = 1

SSBY = 1 Oscillation

stabilization

time t

OSC2

Software standby mode

(power-down mode) NMI exception

handling

SLEEP instruction

Figure 21.3 Software Standby Mode Application Example

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21.5 Har dware Standby Mode

21.5.1 Transition to Hardw are Standby Mode

When the

STBY

pin is driven low, a transition is made to hardware standby mode from any mode.

In hardware standby mode, all functions enter the reset state and stop operation, resulting in a

significant reduction in power consumption. As long as the prescribed voltage is supplied, on-chip

RAM data is retained. I/O ports are set to the high-impedance state.

In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before

driving the

STBY

pin low.

Do not change the state of the mode pins (MD2 to MD0) while this LSI is in hardware standby

mode.

21.5.2 Clearing Hardware Standby Mode

Hardware standby mode is cleared by means of the

STBY

pin and the

RES

pin. When the

STBY

pin is driven high while the

RES

pin is low, the reset state is set and clock oscillation is started.

Ensure that the

RES

pin is held low until the clock oscillator settles (at least 8 msthe oscillation

settling timewhen using a crystal oscillator). When the

RES

pin is subsequently driven high, a

transition is made to the program execution state via the reset exception handling state.

21.5.3 Hardware Standby Mode Timings

Timing of Transition to Hardware Standby Mode

1. To retain RAM contents with the RAME bit set to 1 in SYSCR

Drive the

RES

signal low at least 10 states before the

STBY

signal goes low, as shown in

figure 21.4. After

STBY

has gone low,

RES

has to wait for at least 0 ns before becoming high.

STBY

RES

≥ 0 ns

≥ 10 t

cyc

Figure 21.4 Timing of Transition to Hardware Standby Mode

Section 21 Power-Down Modes

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2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents

do not need to be retained

RES

does not have to be driven low as in the above case.

Timing of Recovery from Hardware Standby Mode

Drive the

RES

signal low approximately 100 ns or more before

STBY

goes high to execute a

power-on reset.

tOSC1

t ≥ 100 ns

STBY

RES

Figure 21.5 Timing of Recovery from Hardware Standby Mode

21.6 Module Stop Mode

Module stop mode can be set for individual on-chip peripheral modules.

When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of

the bus cycle and a transition is made to module stop mode. The CPU continues operating

independently.

When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module

starts operating at the end of the bus cycle. In module stop mode, the internal states of modules

other than the SCI*, HCAN, and A/D converter are retained.

After reset clearance, all modules other than DTC are in module stop mode.

When an on-chip peripheral module is in module stop mode, read/write access to its registers is

disabled.

Note: * The internal states of some SCI registers are retained.

Section 21 Power-Down Modes

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21.7 φ

φφ

φ Clock Output Disabling Function

The output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for

the corresponding port. When the PSTOP bit is set to 1, the φ cl ock stops at the end of the bus

cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When

DDR for the correspon di ng port is clea red to 0, φ clock output is disabled and input port mode is

set. Table 21.4 shows the state of the φ pin in each processing state.

Table 21.4 φ

φφ

φ Pin State in Each Processing State

DDR PSTOP Normal Mode Sleep Mode Software

Standby Mode Hardware

Standby Mode

0×High impedance High impedance High im pedance High im pedance

10φ output φ output Fixed high High impedance

1 1 Fixed high Fixed high Fixed high High impedance

Section 21 Power-Down Modes

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21.8 Usage Notes

21.8.1 I/O Port Status

In software standby mode, I/O port states are retained. Therefore, there is no reduction in current

consumption for the output current when a high-level signal is output.

21.8.2 Current Consumption during Oscillation Stabilization Wait Period

Current consumption increases during the oscillation settling wait period.

21.8.3 DTC Module Stop

Depending on the operating status of the DTC, MSTPA6 bit may not be set to 1. Setting of the

DTC module stop mode should be carried out only when the respective module is not activated.

For details, refer to section 8, Data Transfer Controller (DTC).

21.8.4 On-Chip Per ipheral Modu le Interrupt

Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module

stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU

interrupt source or the DTC activation source.

Interrupts should therefore be disabled before entering module stop mode.

21.8.5 Writing to MSTPCR

MSTPCR should only be written to by the CPU.

Section 21 Power-Down Modes

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REJ09B0155-0300

Section 22 List of Registers

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REJ09B0155-0300

Section 22 List o f Registers

The register list gives information on the on-chip I/O register addresses, how the register bits are

configured, and the register states in each operating mode. The information is given as shown

below.

1. Reg ister addr ess es (addre ss ord er )

• Registers are listed from the lower allocation addresses.

• When the address is 16-bit wide, the address of the upper byte is given in the list.

• Registers are classified by functional modules.

• The access size is indicated.

2. Register bits

• Bit configurations of the registers are described in the same order as the register addresses.

• Reserved bits are indicated by  in the bit name column.

• Bit number in the bit-name column indicates that the whole register is allocated as a counter or

for holding data.

• When registers consist of 16 bits, bits are described from the MSB side.

3. Register states in each operating mode

• Register states are described in the same order as the register addresses.

• The register states described here are for the basic operating modes. If there is a specific reset

for an on-chip peripheral module, refer to the section on that on-chip peripheral module.

Section 22 List of Registers

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22.1 Register Addresses (Address Order)

The data-bus width column indicates the number of bits. The access-state column shows the

number of states of the selected basic clock that is required for access to the register.

of Bits Address*Module Data

Width Access

State

Master control register MCR 8 H'F800 HCAN 16 4

General status register GSR 8 H'F801 HCAN 16 4

Bit configuration register BCR 16 H'F802 HCAN 16 4

Mailbox configuration register MBCR 16 H'F804 HCAN 16 4

Transmit wait register TXPR 16 H'F806 HCAN 16 4

Transmit wait cancel register TXCR 16 H'F808 HCAN 16 4

Transmit acknowledge register TXACK 16 H'F80A HCAN 16 4

Abort ackn owledge register ABACK 16 H'F80C HCAN 16 4

Receive com plete register RXPR 16 H'F80E HCAN 16 4

Remote request register RFPR 16 H'F810 HCAN 16 4

Interrupt register IRR 16 H'F812 HCAN 16 4

Mailbox interrupt mask register MBIMR 1 6 H'F814 HCAN 16 4

Interrupt mask register IMR 16 H'F816 HCAN 16 4

Receive error counter REC 8 H'F818 HCAN 16 4

Transmit error counter TEC 8 H'F819 HCAN 16 4

Unread message status register UMSR 16 H'F81A HCAN 16 4

Local acceptance filter mask L LAFML 16 H'F81C HCAN 1 6 4

Local acceptance filter mask H LAFMH 16 H'F81E HCAN 16 4

Message control 0[1] MC0[1] 8 H'F820 HCAN 16 4

Message control 0[2] MC0[2] 8 H'F821 HCAN 16 4

Message control 0[3] MC0[3] 8 H'F822 HCAN 16 4

Message control 0[4] MC0[4] 8 H'F823 HCAN 16 4

Message control 0[5] MC0[5] 8 H'F824 HCAN 16 4

Message control 0[6] MC0[6] 8 H'F825 HCAN 16 4

Message control 0[7] MC0[7] 8 H'F826 HCAN 16 4

Message control 0[8] MC0[8] 8 H'F827 HCAN 16 4

Section 22 List of Registers

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REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Message control 1[1] MC1[1] 8 H'F828 HCAN 16 4

Message control 1[2] MC1[2] 8 H'F829 HCAN 16 4

Message control 1[3] MC1[3] 8 H'F82A HCAN 16 4

Message control 1[4] MC1[4] 8 H'F82B HCAN 16 4

Message control 1[5] MC1[5] 8 H'F82C HCAN 16 4

Message control 1[6] MC1[6] 8 H'F82D HCAN 16 4

Message control 1[7] MC1[7] 8 H'F82E HCAN 16 4

Message control 1[8] MC1[8] 8 H'F82F HCAN 16 4

Message control 2[1] MC2[1] 8 H'F830 HCAN 16 4

Message control 2[2] MC2[2] 8 H'F831 HCAN 16 4

Message control 2[3] MC2[3] 8 H'F832 HCAN 16 4

Message control 2[4] MC2[4] 8 H'F833 HCAN 16 4

Message control 2[5] MC2[5] 8 H'F834 HCAN 16 4

Message control 2[6] MC2[6] 8 H'F835 HCAN 16 4

Message control 2[7] MC2[7] 8 H'F836 HCAN 16 4

Message control 2[8] MC2[8] 8 H'F837 HCAN 16 4

Message control 3[1] MC3[1] 8 H'F838 HCAN 16 4

Message control 3[2] MC3[2] 8 H'F839 HCAN 16 4

Message control 3[3] MC3[3] 8 H'F83A HCAN 16 4

Message control 3[4] MC3[4] 8 H'F83B HCAN 16 4

Message control 3[5] MC3[5] 8 H'F83C HCAN 16 4

Message control 3[6] MC3[6] 8 H'F83D HCAN 16 4

Message control 3[7] MC3[7] 8 H'F83E HCAN 16 4

Message control 3[8] MC3[8] 8 H'F83F HCAN 16 4

Message control 4[1] MC4[1] 8 H'F840 HCAN 16 4

Message control 4[2] MC4[2] 8 H'F841 HCAN 16 4

Message control 4[3] MC4[3] 8 H'F842 HCAN 16 4

Message control 4[4] MC4[4] 8 H'F843 HCAN 16 4

Message control 4[5] MC4[5] 8 H'F844 HCAN 16 4

Message control 4[6] MC4[6] 8 H'F845 HCAN 16 4

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 520 of 598

REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Message control 4[7] MC4[7] 8 H'F846 HCAN 16 4

Message control 4[8] MC4[8] 8 H'F847 HCAN 16 4

Message control 5[1] MC5[1] 8 H'F848 HCAN 16 4

Message control 5[2] MC5[2] 8 H'F849 HCAN 16 4

Message control 5[3] MC5[3] 8 H'F84A HCAN 16 4

Message control 5[4] MC5[4] 8 H'F84B HCAN 16 4

Message control 5[5] MC5[5] 8 H'F84C HCAN 16 4

Message control 5[6] MC5[6] 8 H'F84D HCAN 16 4

Message control 5[7] MC5[7] 8 H'F84E HCAN 16 4

Message control 5[8] MC5[8] 8 H'F84F HCAN 16 4

Message control 6[1] MC6[1] 8 H'F850 HCAN 16 4

Message control 6[2] MC6[2] 8 H'F851 HCAN 16 4

Message control 6[3] MC6[3] 8 H'F852 HCAN 16 4

Message control 6[4] MC6[4] 8 H'F853 HCAN 16 4

Message control 6[5] MC6[5] 8 H'F854 HCAN 16 4

Message control 6[6] MC6[6] 8 H'F855 HCAN 16 4

Message control 6[7] MC6[7] 8 H'F856 HCAN 16 4

Message control 6[8] MC6[8] 8 H'F857 HCAN 16 4

Message control 7[1] MC7[1] 8 H'F858 HCAN 16 4

Message control 7[2] MC7[2] 8 H'F859 HCAN 16 4

Message control 7[3] MC7[3] 8 H'F85A HCAN 16 4

Message control 7[4] MC7[4] 8 H'F85B HCAN 16 4

Message control 7[5] MC7[5] 8 H'F85C HCAN 16 4

Message control 7[6] MC7[6] 8 H'F85D HCAN 16 4

Message control 7[7] MC7[7] 8 H'F85E HCAN 16 4

Message control 7[8] MC7[8] 8 H'F85F HCAN 16 4

Message control 8[1] MC8[1] 8 H'F860 HCAN 16 4

Message control 8[2] MC8[2] 8 H'F861 HCAN 16 4

Message control 8[3] MC8[3] 8 H'F862 HCAN 16 4

Message control 8[4] MC8[4] 8 H'F863 HCAN 16 4

Section 22 List of Registers

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REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Message control 8[5] MC8[5] 8 H'F864 HCAN 16 4

Message control 8[6] MC8[6] 8 H'F865 HCAN 16 4

Message control 8[7] MC8[7] 8 H'F866 HCAN 16 4

Message control 8[8] MC8[8] 8 H'F867 HCAN 16 4

Message control 9[1] MC9[1] 8 H'F868 HCAN 16 4

Message control 9[2] MC9[2] 8 H'F869 HCAN 16 4

Message control 9[3] MC9[3] 8 H'F86A HCAN 16 4

Message control 9[4] MC9[4] 8 H'F86B HCAN 16 4

Message control 9[5] MC9[5] 8 H'F86C HCAN 16 4

Message control 9[6] MC9[6] 8 H'F86D HCAN 16 4

Message control 9[7] MC9[7] 8 H'F86E HCAN 16 4

Message control 9[8] MC9[8] 8 H'F86F HCAN 16 4

Message control 10[1] MC10[1] 8 H'F870 HCAN 16 4

Message control 10[2] MC10[2] 8 H'F871 HCAN 16 4

Message control 10[3] MC10[3] 8 H'F872 HCAN 16 4

Message control 10[4] MC10[4] 8 H'F873 HCAN 16 4

Message control 10[5] MC10[5] 8 H'F874 HCAN 16 4

Message control 10[6] MC10[6] 8 H'F875 HCAN 16 4

Message control 10[7] MC10[7] 8 H'F876 HCAN 16 4

Message control 10[8] MC10[8] 8 H'F877 HCAN 16 4

Message control 11[1] MC11[1] 8 H'F878 HCAN 16 4

Message control 11[2] MC11[2] 8 H'F879 HCAN 16 4

Message control 11[3] MC11[3] 8 H'F87A HCAN 16 4

Message control 11[4] MC11[4] 8 H'F87B HCAN 16 4

Message control 11[5] MC11[5] 8 H'F87C HCAN 16 4

Message control 11[6] MC11[6] 8 H'F87D HCAN 16 4

Message control 11[7] MC11[7] 8 H'F87E HCAN 16 4

Message control 11[8] MC11[8] 8 H'F87F HCAN 16 4

Message control 12[1] MC12[1] 8 H'F880 HCAN 16 4

Message control 12[2] MC12[2] 8 H'F881 HCAN 16 4

Section 22 List of Registers

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REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Message control 12[3] MC12[3] 8 H'F882 HCAN 16 4

Message control 12[4] MC12[4] 8 H'F883 HCAN 16 4

Message control 12[5] MC12[5] 8 H'F884 HCAN 16 4

Message control 12[6] MC12[6] 8 H'F885 HCAN 16 4

Message control 12[7] MC12[7] 8 H'F886 HCAN 16 4

Message control 12[8] MC12[8] 8 H'F887 HCAN 16 4

Message control 13[1] MC13[1] 8 H'F888 HCAN 16 4

Message control 13[2] MC13[2] 8 H'F889 HCAN 16 4

Message control 13[3] MC13[3] 8 H'F88A HCAN 16 4

Message control 13[4] MC13[4] 8 H'F88B HCAN 16 4

Message control 13[5] MC13[5] 8 H'F88C HCAN 16 4

Message control 13[6] MC13[6] 8 H'F88D HCAN 16 4

Message control 13[7] MC13[7] 8 H'F88E HCAN 16 4

Message control 13[8] MC13[8] 8 H'F88F HCAN 16 4

Message control 14[1] MC14[1] 8 H'F890 HCAN 16 4

Message control 14[2] MC14[2] 8 H'F891 HCAN 16 4

Message control 14[3] MC14[3] 8 H'F892 HCAN 16 4

Message control 14[4] MC14[4] 8 H'F893 HCAN 16 4

Message control 14[5] MC14[5] 8 H'F894 HCAN 16 4

Message control 14[6] MC14[6] 8 H'F895 HCAN 16 4

Message control 14[7] MC14[7] 8 H'F896 HCAN 16 4

Message control 14[8] MC14[8] 8 H'F897 HCAN 16 4

Message control 15[1] MC15[1] 8 H'F898 HCAN 16 4

Message control 15[2] MC15[2] 8 H'F899 HCAN 16 4

Message control 15[3] MC15[3] 8 H'F89A HCAN 16 4

Message control 15[4] MC15[4] 8 H'F89B HCAN 16 4

Message control 15[5] MC15[5] 8 H'F89C HCAN 16 4

Message control 15[6] MC15[6] 8 H'F89D HCAN 16 4

Message control 15[7] MC15[7] 8 H'F89E HCAN 16 4

Message control 15[8] MC15[8] 8 H'F89F HCAN 16 4

Section 22 List of Registers

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REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Message data 0[1] MD0[1] 8 H'F8B0 HCAN 16 4

Message data 0[2] MD0[2] 8 H'F8B1 HCAN 16 4

Message data 0[3] MD0[3] 8 H'F8B2 HCAN 16 4

Message data 0[4] MD0[4] 8 H'F8B3 HCAN 16 4

Message data 0[5] MD0[5] 8 H'F8B4 HCAN 16 4

Message data 0[6] MD0[6] 8 H'F8B5 HCAN 16 4

Message data 0[7] MD0[7] 8 H'F8B6 HCAN 16 4

Message data 0[8] MD0[8] 8 H'F8B7 HCAN 16 4

Message data 1[1] MD1[1] 8 H'F8B8 HCAN 16 4

Message data 1[2] MD1[2] 8 H'F8B9 HCAN 16 4

Message data 1[3] MD1[3] 8 H'F8BA HCAN 16 4

Message data 1[4] MD1[4] 8 H'F8BB HCAN 16 4

Message data 1[5] MD1[5] 8 H'F8BC HCAN 16 4

Message data 1[6] MD1[6] 8 H'F8BD HCAN 16 4

Message data 1[7] MD1[7] 8 H'F8BE HCAN 16 4

Message data 1[8] MD1[8] 8 H'F8BF HCAN 16 4

Message data 2[1] MD2[1] 8 H'F8C0 HCAN 16 4

Message data 2[2] MD2[2] 8 H'F8C1 HCAN 16 4

Message data 2[3] MD2[3] 8 H'F8C2 HCAN 16 4

Message data 2[4] MD2[4] 8 H'F8C3 HCAN 16 4

Message data 2[5] MD2[5] 8 H'F8C4 HCAN 16 4

Message data 2[6] MD2[6] 8 H'F8C5 HCAN 16 4

Message data 2[7] MD2[7] 8 H'F8C6 HCAN 16 4

Message data 2[8] MD2[8] 8 H'F8C7 HCAN 16 4

Message data 3[1] MD3[1] 8 H'F8C8 HCAN 16 4

Message data 3[2] MD3[2] 8 H'F8C9 HCAN 16 4

Message data 3[3] MD3[3] 8 H'F8CA HCAN 16 4

Message data 3[4] MD3[4] 8 H'F8CB HCAN 16 4

Message data 3[5] MD3[5] 8 H'F8CC HCAN 16 4

Message data 3[6] MD3[6] 8 H'F8CD HCAN 16 4

Section 22 List of Registers

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of Bits Address*Module Data

Width Access

State

Message data 3[7] MD3[7] 8 H'F8CE HCAN 16 4

Message data 3[8] MD3[8] 8 H'F8CF HCAN 16 4

Message data 4[1] MD4[1] 8 H'F8D0 HCAN 16 4

Message data 4[2] MD4[2] 8 H'F8D1 HCAN 16 4

Message data 4[3] MD4[3] 8 H'F8D2 HCAN 16 4

Message data 4[4] MD4[4] 8 H'F8D3 HCAN 16 4

Message data 4[5] MD4[5] 8 H'F8D4 HCAN 16 4

Message data 4[6] MD4[6] 8 H'F8D5 HCAN 16 4

Message data 4[7] MD4[7] 8 H'F8D6 HCAN 16 4

Message data 4[8] MD4[8] 8 H'F8D7 HCAN 16 4

Message data 5[1] MD5[1] 8 H'F8D8 HCAN 16 4

Message data 5[2] MD5[2] 8 H'F8D9 HCAN 16 4

Message data 5[3] MD5[3] 8 H'F8DA HCAN 16 4

Message data 5[4] MD5[4] 8 H'F8DB HCAN 16 4

Message data 5[5] MD5[5] 8 H'F8DC HCAN 16 4

Message data 5[6] MD5[6] 8 H'F8DD HCAN 16 4

Message data 5[7] MD5[7] 8 H'F8DE HCAN 16 4

Message data 5[8] MD5[8] 8 H'F8DF HCAN 16 4

Message data 6[1] MD6[1] 8 H'F8E0 HCAN 16 4

Message data 6[2] MD6[2] 8 H'F8E1 HCAN 16 4

Message data 6[3] MD6[3] 8 H'F8E2 HCAN 16 4

Message data 6[4] MD6[4] 8 H'F8E3 HCAN 16 4

Message data 6[5] MD6[5] 8 H'F8E4 HCAN 16 4

Message data 6[6] MD6[6] 8 H'F8E5 HCAN 16 4

Message data 6[7] MD6[7] 8 H'F8E6 HCAN 16 4

Message data 6[8] MD6[8] 8 H'F8E7 HCAN 16 4

Message data 7[1] MD7[1] 8 H'F8E8 HCAN 16 4

Message data 7[2] MD7[2] 8 H'F8E9 HCAN 16 4

Message data 7[3] MD7[3] 8 H'F8EA HCAN 16 4

Message data 7[4] MD7[4] 8 H'F8EB HCAN 16 4

Section 22 List of Registers

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REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Message data 7[5] MD7[5] 8 H'F8EC HCAN 16 4

Message data 7[6] MD7[6] 8 H'F8ED HCAN 16 4

Message data 7[7] MD7[7] 8 H'F8EE HCAN 16 4

Message data 7[8] MD7[8] 8 H'F8EF HCAN 16 4

Message data 8[1] MD8[1] 8 H'F8F0 HCAN 16 4

Message data 8[2] MD8[2] 8 H'F8F1 HCAN 16 4

Message data 8[3] MD8[3] 8 H'F8F2 HCAN 16 4

Message data 8[4] MD8[4] 8 H'F8F3 HCAN 16 4

Message data 8[5] MD8[5] 8 H'F8F4 HCAN 16 4

Message data 8[6] MD8[6] 8 H'F8F5 HCAN 16 4

Message data 8[7] MD8[7] 8 H'F8F6 HCAN 16 4

Message data 8[8] MD8[8] 8 H'F8F7 HCAN 16 4

Message data 9[1] MD9[1] 8 H'F8F8 HCAN 16 4

Message data 9[2] MD9[2] 8 H'F8F9 HCAN 16 4

Message data 9[3] MD9[3] 8 H'F8FA HCAN 16 4

Message data 9[4] MD9[4] 8 H'F8FB HCAN 16 4

Message data 9[5] MD9[5] 8 H'F8FC HCAN 16 4

Message data 9[6] MD9[6] 8 H'F8FD HCAN 16 4

Message data 9[7] MD9[7] 8 H'F8FE HCAN 16 4

Message data 9[8] MD9[8] 8 H'F8FF HCAN 16 4

Message data 10[1] MD10[1] 8 H'F900 HCAN 16 4

Message data 10[2] MD10[2] 8 H'F901 HCAN 16 4

Message data 10[3] MD10[3] 8 H'F902 HCAN 16 4

Message data 10[4] MD10[4] 8 H'F903 HCAN 16 4

Message data 10[5] MD10[5] 8 H'F904 HCAN 16 4

Message data 10[6] MD10[6] 8 H'F905 HCAN 16 4

Message data 10[7] MD10[7] 8 H'F906 HCAN 16 4

Message data 10[8] MD10[8] 8 H'F907 HCAN 16 4

Message data 11[1] MD11[1] 8 H'F908 HCAN 16 4

Message data 11[2] MD11[2] 8 H'F909 HCAN 16 4

Section 22 List of Registers

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REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Message data 11[3] MD11[3] 8 H'F90A HCAN 16 4

Message data 11[4] MD11[4] 8 H'F90B HCAN 16 4

Message data 11[5] MD11[5] 8 H'F90C HCAN 16 4

Message data 11[6] MD11[6] 8 H'F90D HCAN 16 4

Message data 11[7] MD11[7] 8 H'F90E HCAN 16 4

Message data 11[8] MD11[8] 8 H'F90F HCAN 16 4

Message data 12[1] MD12[1] 8 H'F910 HCAN 16 4

Message data 12[2] MD12[2] 8 H'F911 HCAN 16 4

Message data 12[3] MD12[3] 8 H'F912 HCAN 16 4

Message data 12[4] MD12[4] 8 H'F913 HCAN 16 4

Message data 12[5] MD12[5] 8 H'F914 HCAN 16 4

Message data 12[6] MD12[6] 8 H'F915 HCAN 16 4

Message data 12[7] MD12[7] 8 H'F916 HCAN 16 4

Message data 12[8] MD12[8] 8 H'F917 HCAN 16 4

Message data 13[1] MD13[1] 8 H'F918 HCAN 16 4

Message data 13[2] MD13[2] 8 H'F919 HCAN 16 4

Message data 13[3] MD13[3] 8 H'F91A HCAN 16 4

Message data 13[4] MD13[4] 8 H'F91B HCAN 16 4

Message data 13[5] MD13[5] 8 H'F91C HCAN 16 4

Message data 13[6] MD13[6] 8 H'F91D HCAN 16 4

Message data 13[7] MD13[7] 8 H'F91E HCAN 16 4

Message data 13[8] MD13[8] 8 H'F91F HCAN 16 4

Message data 14[1] MD14[1] 8 H'F920 HCAN 16 4

Message data 14[2] MD14[2] 8 H'F921 HCAN 16 4

Message data 14[3] MD14[3] 8 H'F922 HCAN 16 4

Message data 14[4] MD14[4] 8 H'F923 HCAN 16 4

Message data 14[5] MD14[5] 8 H'F924 HCAN 16 4

Message data 14[6] MD14[6] 8 H'F925 HCAN 16 4

Message data 14[7] MD14[7] 8 H'F926 HCAN 16 4

Message data 14[8] MD14[8] 8 H'F927 HCAN 16 4

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 527 of 598

REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Message data 15[1] MD15[1] 8 H'F928 HCAN 16 4

Message data 15[2] MD15[2] 8 H'F929 HCAN 16 4

Message data 15[3] MD15[3] 8 H'F92A HCAN 16 4

Message data 15[4] MD15[4] 8 H'F92B HCAN 16 4

Message data 15[5] MD15[5] 8 H'F92C HCAN 16 4

Message data 15[6] MD15[6] 8 H'F92D HCAN 16 4

Message data 15[7] MD15[7] 8 H'F92E HCAN 16 4

Message data 15[8] MD15[8] 8 H'F92F HCAN 16 4

HCAN moni tor regi ster HCANMON 8 H' FA00 HCAN 16 4

SS control register H_0 SSCRH_0 8 H'FB00 SSU_0 16 3

SS control register L_0 SSCRL_0 8 H'FB01 SSU_0 16 3

SS mode register_0 SSMR_0 8 H'FB02 SSU_0 16 3

SS enable register_0 SSER_0 8 H'FB03 SSU_0 16 3

SS status register_0 SSSR_ 0 8 H' FB04 SSU_0 16 3

SS transmit data register 0_0 SSTDR0_0 8 H'FB06 SSU_0 16 3

SS transmit data register 1_0 SSTDR1_0 8 H'FB07 SSU_0 16 3

SS transmit data register 2_0 SSTDR2_0 8 H'FB08 SSU_0 16 3

SS transmit data register 3_0 SSTDR3_0 8 H'FB09 SSU_0 16 3

SS receive data register 0_0 SSRDR0_0 8 H'FB0A SSU _0 16 3

SS receive data register 1_0 SSRDR1_0 8 H'FB0B SSU _0 16 3

SS receive data register 2_0 SSRDR2_0 8 H'FB0C SS U_0 16 3

SS receive data register 3_0 SSRDR3_0 8 H'FB0D SS U_0 16 3

SS control register H_1 SSCRH_1 8 H'FB10 SSU_1 16 3

SS control register L_1 SSCRL_1 8 H'FB11 SSU_1 16 3

SS mode register_1 SSMR_1 8 H'FB12 SSU_1 16 3

SS enable register_1 SSER_1 8 H'FB13 SSU_1 16 3

SS status register_1 SSSR_ 1 8 H' FB14 SSU_1 16 3

SS transmit data register 0_1 SSTDR0_1 8 H'FB16 SSU_1 16 3

SS transmit data register 1_1 SSTDR1_1 8 H'FB17 SSU_1 16 3

SS transmit data register 2_1 SSTDR2_1 8 H'FB18 SSU_1 16 3

Section 22 List of Registers

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REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

SS transmit data register 3_1 SSTDR3_1 8 H'FB19 SSU_1 16 3

SS receive data register 0_1 SSRDR0_1 8 H'FB1A SSU _1 16 3

SS receive data register 1_1 SSRDR1_1 8 H'FB1B SSU _1 16 3

SS receive data register 2_1 SSRDR2_1 8 H'FB1C SS U_1 16 3

SS receive data register 3_1 SSRDR3_1 8 H'FB1D SS U_1 16 3

Port D realtime input data register PDRTIDR 8 H'FB40 PORT 16 3

Ti mer control register_2 TCR_2 8 H' FDC0 TMR_2 8 2

Ti mer control register_3 TCR_3 8 H' FDC1 TMR_3 8 2

Timer control/status register_2 TCSR_2 8 H'FDC2 TMR_2 8 2

Timer control/status register_3 TCSR_3 8 H'FDC3 TMR_3 8 2

Timer constant register A_2 TCORA_2 8 H'FDC4 T MR_2 8 2

Timer constant register A_3 TCORA_3 8 H'FDC5 T MR_3 8 2

Timer constant register B_2 TCORB_2 8 H'FDC6 T MR_2 8 2

Timer constant register B_3 TCORB_3 8 H'FDC7 T MR_3 8 2

Timer counter_2 TCNT_2 8 H'FDC8 TMR_2 8 2

Timer counter_3 TCNT_3 8 H'FDC9 TMR_3 8 2

Standby control register SBYCR 8 H'FDE4 SYSTEM 8 2

System control regist er SYSCR 8 H'FDE5 SYSTEM 8 2

System clock control register SCKCR 8 H'FDE6 SYSTEM 8 2

Mode control register MDCR 8 H'FDE7 SYSTEM 8 2

Module stop control register A MSTPCRA 8 H'FDE8 SYSTEM 8 2

Module stop control register B MSTPCRB 8 H'FDE9 SYSTEM 8 2

Module stop control register C MSTPCRC 8 H'FDEA SYSTEM 8 2

Low-power control register LPWRCR 8 H'FDEC SYSTEM 8 2

Break address register A BARA 32 H'FE00 PBC 32 2

Break address register B BARB 32 H'FE04 PBC 32 2

Break control register A BCRA 8 H'FE08 PBC 8 2

Break control register B BCRB 8 H'FE09 PBC 8 2

IRQ sense control register H ISCRH 8 H'FE12 INT 8 2

IRQ sense control regi ster L ISCRL 8 H'FE13 INT 8 2

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 529 of 598

REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

IRQ enable register IER 8 H'FE14 INT 8 2

IRQ status regi ster ISR 8 H'FE15 INT 8 2

DTC enable register A DTCERA 8 H'FE16 DTC 8 2

DTC enable register B DTCERB 8 H'FE17 DTC 8 2

DTC enable register C DTCERC 8 H'FE18 DTC 8 2

DTC enable register D DTCERD 8 H'FE19 DTC 8 2

DTC enable register E DTCERE 8 H'FE1A DTC 8 2

DTC enable register F DTCERF 8 H'FE1B DTC 8 2

DTC enable register G DTCERG 8 H'FE1C DTC 8 2

DTC vector register DTVECR 8 H'FE1F DTC 8 2

PPG output control register PCR 8 H'FE26 PPG 8 2

PPG output mode register PMR 8 H'FE27 PPG 8 2

Next data enable register H NDERH 8 H'FE28 PPG 8 2

Next data enable register L NDERL 8 H'FE29 PPG 8 2

Output data register H PODRH 8 H'FE2A PPG 8 2

Output data register L PODRL 8 H'FE2B PPG 8 2

Next data register H NDRH 8 H'FE2C PPG 8 2

Next data register L NDRL 8 H'FE2D PPG 8 2

Next data register H NDRH 8 H'FE2E PPG 8 2

Next data register L NDRL 8 H'FE2F PPG 8 2

Port 1 data direction register P1DDR 8 H'FE30 PORT 8 2

Port 3 data direction register P3DDR 8 H'FE32 PORT 8 2

Port 7 data direction register P7DDR 8 H'FE36 PORT 8 2

Port A data direction register PADDR 8 H'FE39 PORT 8 2

Port B data direction register PBDDR 8 H'FE3A PORT 8 2

Port C data direction register PCDDR 8 H'FE3 B PORT 8 2

Port D data direction register PDDDR 8 H'FE3 C PORT 8 2

Port F data direction register PFDDR 8 H'FE3E PORT 8 2

Port A pull-u p MOS control regis ter PAPCR 8 H'FE40 PORT 8 2

Port B pull-u p MOS control regis ter PBPCR 8 H'FE41 PORT 8 2

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 530 of 598

REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Port C pull-up MOS control register PCPCR 8 H'FE42 PORT 8 2

Port D pull-up MOS control register PDPCR 8 H'FE43 PORT 8 2

Port 3 open drain control register P3ODR 8 H'FE46 PORT 8 2

Port A open drain control register PAODR 8 H'FE47 PORT 8 2

Port B open drain control register PBODR 8 H'FE48 PORT 8 2

Port C open drain control register PCODR 8 H'FE49 PORT 8 2

Timer control register_3 TCR_3 8 H'FE80 TPU_3 16 2

Timer mode register_3 TMDR_3 8 H'FE81 TPU_3 16 2

Timer I/O control register H_3 TIORH_3 8 H'FE82 T PU_3 16 2

Timer I/O control register L_3 TIORL_3 8 H'FE83 TPU_3 16 2

Timer interrupt enable register_3 TIER_3 8 H'FE84 TPU_3 16 2

Timer status register_3 TSR_3 8 H'FE85 TPU_3 16 2

Timer counter H_3 TCNTH_3 8 H'FE86 TPU_3 16 2

Timer counter L_3 TCNTL_3 8 H'FE87 TPU_3 16 2

Timer general register AH_3 TGRAH_3 8 H'FE88 TPU_3 16 2

Timer general register AL_3 TGRAL_3 8 H'FE89 TPU_3 16 2

Timer general register BH_3 TGRBH_3 8 H'FE8A TPU_3 16 2

Timer general register BL_3 TGRBL_3 8 H'FE8B TPU_3 16 2

Timer general register CH_3 TGRCH_3 8 H'FE8C TPU_3 16 2

Timer general register CL_3 TGRCL_3 8 H'FE8D TPU_3 16 2

Timer general register DH_3 TGRDH_3 8 H'FE8E TPU_3 16 2

Timer general register DL_3 TGRDL_3 8 H'FE8F TPU_3 16 2

Timer control register_4 TCR_4 8 H'FE90 TPU_4 16 2

Timer mode register_4 TMDR_4 8 H'FE91 TPU_4 16 2

Timer I/O control register_4 TIOR_4 8 H'FE92 TPU_4 16 2

Timer interrupt enable register_4 TIER_4 8 H'FE94 TPU_4 16 2

Timer status register_4 TSR_4 8 H'FE95 TPU_4 16 2

Timer counter H_4 TCNTH_4 8 H'FE96 TPU_4 16 2

Timer counter L_4 TCNTL_4 8 H'FE97 TPU_4 16 2

Timer general register AH_4 TGRAH_4 8 H'FE98 TPU_4 16 2

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 531 of 598

REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Timer general register AL_4 TGRAL_4 8 H'FE99 TPU_4 16 2

Timer general register BH_4 TGRBH_4 8 H'FE9A TPU_4 16 2

Timer general register BL_4 TGRBL_4 8 H'FE9B TPU_4 16 2

Timer control register_5 TCR_5 8 H'FEA0 TPU_5 16 2

Timer mode register_5 TMDR_5 8 H'FEA1 TPU_5 16 2

Timer I/O control register_5 TIOR_5 8 H'FEA2 TPU_5 16 2

Timer interrupt enable register_5 TIER_5 8 H'FEA4 TPU_5 16 2

Timer status register_5 TSR_5 8 H'FEA5 TPU_5 16 2

Timer counter H_5 TCNTH_5 8 H'FEA6 TPU_5 16 2

Timer counter L_5 TCNTL_5 8 H'FEA7 TPU_5 16 2

Timer general register AH_5 TGRAH_5 8 H'FEA8 TPU_5 16 2

Timer general register AL_5 TGRAL_5 8 H'FEA9 TPU_5 16 2

Timer general register BH_5 TGRBH_5 8 H'FEAA TPU_5 16 2

Timer general register BL_5 TGRBL_5 8 H'FEAB TPU_5 16 2

Timer start register TSTR 8 H'FEB0 TPU

common 16 2

Timer synchro register TSYR 8 H'FEB1 TPU

common 16 2

Interrupt priority register A IPRA 8 H'FEC0 INT 8 2

Interrupt priority register B IPRB 8 H'FEC1 INT 8 2

Interrupt priority register C IPRC 8 H'FEC2 INT 8 2

Interrupt priority register D IPRD 8 H'FEC3 INT 8 2

Interrupt priority register E IPRE 8 H'FEC4 INT 8 2

Interrupt priority register F IPRF 8 H'FEC5 INT 8 2

Interrupt priority register G IPRG 8 H'FEC6 INT 8 2

Interrupt priority register H IPRH 8 H'FEC7 INT 8 2

Interrupt priority register J IPRJ 8 H'F EC9 INT 8 2

Interrupt priority register K IPRK 8 H'FECA INT 8 2

Interrupt priority register M IPRM 8 H'FECC INT 8 2

RAM emulation register RAMER 8 H'FEDB ROM 8 2

Port 1 data register P1DR 8 H'FF00 PORT 8 2

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 532 of 598

REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Port 3 data register P3DR 8 H'FF02 PORT 8 2

Port 7 data register P7DR 8 H'FF06 PORT 8 2

Port A data register PADR 8 H'FF09 PORT 8 2

Port B data register PBDR 8 H'FF0A PORT 8 2

Port C data register PCDR 8 H'FF0B PORT 8 2

Port D data register PDDR 8 H'FF0C PORT 8 2

Port F data register PFDR 8 H'FF0E PORT 8 2

Timer control register_0 TCR_0 8 H'FF10 TPU_0 16 2

Timer mode register_0 TMDR_0 8 H'FF11 TPU_0 16 2

Timer I/O control register H_0 TIORH_0 8 H'FF12 TPU_0 16 2

Timer I/O control register L_0 TIORL_0 8 H'FF13 TPU_0 16 2

Timer interrupt enable register_0 TIER_0 8 H'FF14 TPU_0 16 2

Timer status register_0 TSR_0 8 H'FF15 TPU_0 16 2

Timer counter H_0 TCNTH_0 8 H'FF16 TPU_0 16 2

Timer counter L_0 TCNTL_0 8 H'FF17 TPU_0 16 2

Timer general register AH_0 TGRAH_0 8 H'FF18 TPU_0 16 2

Timer general register AL_0 TGRAL_0 8 H'FF19 TPU_0 16 2

Timer general register BH_0 TGRBH_0 8 H'FF1A TPU_0 16 2

Timer general register BL_0 TGRBL_0 8 H'FF1B TPU_0 16 2

Timer general register CH_0 TGRCH_0 8 H'FF1C TPU_0 16 2

Timer general register CL_0 TGRCL_0 8 H'FF1D TPU_0 16 2

Timer general register DH_0 TGRDH_0 8 H'FF1E TPU_0 16 2

Timer general register DL_0 TGRDL_0 8 H'FF1F TPU_0 16 2

Timer control register_1 TCR_1 8 H'FF20 TPU_1 16 2

Timer mode register_1 TMDR_1 8 H'FF21 TPU_1 16 2

Timer I/O control register_1 TIOR_1 8 H'FF22 TPU_1 16 2

Timer interrupt enable register_1 TIER_1 8 H'FF24 TPU_1 16 2

Timer status register_1 TSR_1 8 H'FF25 TPU_1 16 2

Timer counter H_1 TCNTH_1 8 H'FF26 TPU_1 16 2

Timer counter L_1 TCNTL_1 8 H'FF27 TPU_1 16 2

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 533 of 598

REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Timer general register AH_1 TGRAH_1 8 H'FF28 TPU_1 16 2

Timer general register AL_1 TGRAL_1 8 H'FF29 TPU_1 16 2

Timer general register BH_1 TGRBH_1 8 H'FF2A TPU_1 16 2

Timer general register BL_1 TGRBL_1 8 H'FF2B TPU_1 16 2

Timer control register_2 TCR_2 8 H'FF30 TPU_2 16 2

Timer mode register_2 TMDR_2 8 H'FF31 TPU_2 16 2

Timer I/O control register_2 TIOR_2 8 H'FF32 TPU_2 16 2

Timer interrupt enable register_2 TIER_2 8 H'FF34 TPU_2 16 2

Timer status register_2 TSR_2 8 H'FF35 TPU_2 16 2

Timer counterH_2 TCNTH_2 8 H'FF36 TPU_2 16 2

Timer counter L_2 TCNTL_2 8 H'FF37 TPU_2 16 2

Timer general register AH_2 TGRAH_2 8 H'FF38 TPU_2 16 2

Timer general register AL_2 TGRAL_2 8 H'FF39 TPU_2 16 2

Timer general register BH_2 TGRBH_2 8 H'FF3A TPU_2 16 2

Timer general register BL_2 TGRBL_2 8 H'FF3B TPU_2 16 2

Timer control register_0 TCR_0 8 H'FF68 TMR_0 8 2

Timer control register_1 TCR_1 8 H'FF69 TMR_1 8 2

Timer control/status register_0 TCSR_0 8 H'FF6A TMR_0 8 2

Timer control/status register_1 TCSR_1 8 H'FF6B TMR_1 8 2

Time constant register A_0 TCORA_0 8 H'FF6C TMR_0 8 2

Time constant register A_1 TCORA_1 8 H'FF6D TMR_1 8 2

Time constant register B_0 TCORB_0 8 H'FF6E TMR_0 8 2

Time constant register B_1 TCORB_1 8 H'FF6F TMR_1 8 2

Timer counter_0 TCNT_0 8 H'FF70 TMR_0 8 2

Timer counter_1 TCNT_1 8 H'FF71 TMR_1 8 2

Timer control/status register_0 TCSR_0 8 H'FF74 WDT_0 16 2

Timer counter_0 TCNT_0 8 H'FF75 WDT_0 16 2

Reset control/status register RSTCSR 8 H'FF77 WDT 16 2

Serial mode register_0 SMR_0 8 H'FF78 SCI_0 8 2

Bit rate register_0 BRR_0 8 H'FF79 SCI_0 8 2

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 534 of 598

REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Serial control register_0 SCR_0 8 H'FF7A SCI_0 8 2

Transmit data register_0 TDR_0 8 H'FF7B SCI_0 8 2

Serial status register_0 SSR_0 8 H'FF7C SCI_0 8 2

Receive data register_0 RDR_0 8 H'FF7D SCI_0 8 2

Smart card mode register_0 SCMR_0 8 H'FF7E SCI_0 8 2

Serial mode register_2 SMR_2 8 H'FF88 SCI_2 8 2

Bit rate register_2 BRR_2 8 H'FF89 SCI_2 8 2

Serial control register_2 SCR_2 8 H'FF8A SCI_2 8 2

Transmit data register_2 TDR_2 8 H'FF8B SCI_2 8 2

Serial status register_2 SSR_2 8 H'FF8C SCI_2 8 2

Receive data register_2 RDR_2 8 H'FF8D SCI_2 8 2

Smart card mode register_2 SCMR_2 8 H'FF8E SCI_2 8 2

A/D data register AH ADDRAH 8 H'FF90 A/D 8 2

A/D data register AL ADDRAL 8 H'FF91 A/D 8 2

A/D data register BH ADDRBH 8 H'FF92 A/D 8 2

A/D data register BL ADDRBL 8 H'FF93 A/D 8 2

A/D data register CH ADDRCH 8 H'FF94 A/D 8 2

A/D data register CL ADDRCL 8 H'FF95 A/D 8 2

A/D data register DH ADDRDH 8 H'FF96 A/D 8 2

A/D data register DL ADDRDL 8 H'FF97 A/D 8 2

A/D control/status register ADCSR 8 H'FF98 A/D 8 2

A/D control register ADCR 8 H'FF99 A/D 8 2

Flash memory control register 1 FLMCR1 8 H'FFA8 ROM 8 2

Flash memory control register 2 FLMCR2 8 H'FFA9 ROM 8 2

Erase block register 1 EBR1 8 H'FFAA ROM 8 2

Erase block register 2 EBR2 8 H'FFAB ROM 8 2

Port 1 register PORT1 8 H'FFB0 PORT 8 2

Port 3 register PORT3 8 H'FFB2 PORT 8 2

Port 4 register PORT4 8 H'FFB3 PORT 8 2

Port 7 register PORT7 8 H'FFB6 PORT 8 2

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 535 of 598

REJ09B0155-0300

of Bits Address*Module Data

Width Access

State

Port 9 register PORT9 8 H'FFB8 PORT 8 2

Port A register PORTA 8 H'FFB9 PORT 8 2

Port B register PORTB 8 H'FFBA PORT 8 2

Port C register PORTC 8 H'FFBB PORT 8 2

Port D register PORTD 8 H'FFBC PORT 8 2

Port F register PORTF 8 H'FFBE PORT 8 2

Note: *Lower 16 bits of the address.

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 536 of 598

REJ09B0155-0300

22.2 Register Bits

The bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

MCR MCR7 MCR5 MCR2 MCR1 MCR0 HCAN

GSR GSR3 GSR2 GSR1 GSR0

BCR BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0

BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8

MBCR MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 

MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8

TXPR TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 

TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8

TXCR TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 

TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8

TXACK TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 

TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8

ABACK ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 

ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8

RXPR RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0

RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8

RFPR RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0

RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8

IRR IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0

IRR12 IRR9 IRR8

MBIMR MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0

MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8

IMR IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 

IMR12 IMR9 IMR8

REC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TEC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 537 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

UMSR UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 HCAN

UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8

LAFML LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0

LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8

LAFMH LAFMH7 LAFMH6 LAFMH5 LAFMH1 LAFMH0

LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8

MC0[1] DLC3 DLC2 DLC1 DLC0

MC0[2] 

MC0[3] 

MC0[4] 

MC0[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC0[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC0[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC0[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC1[1] DLC3 DLC2 DLC1 DLC0

MC1[2] 

MC1[3] 

MC1[4] 

MC1[5] ID−20 ID−19 ID−18 RTR IDE −ID−17 ID−16

MC1[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC1[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC1[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC2[1] DLC3 DLC2 DLC1 DLC0

MC2[2] 

MC2[3] 

MC2[4] 

MC2[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC2[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC2[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC2[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 538 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

MC3[1] DLC3 DLC2 DLC1 DLC0 HCAN

MC3[2] 

MC3[3] 

MC3[4] 

MC3[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC3[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC3[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC3[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC4[1] DLC3 DLC2 DLC1 DLC0

MC4[2] 

MC4[3] 

MC4[4] 

MC4[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC4[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC4[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC4[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC5[1] DLC3 DLC2 DLC1 DLC0

MC5[2] 

MC5[3] 

MC5[4] 

MC5[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC5[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC5[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC5[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC6[1] DLC3 DLC2 DLC1 DLC0

MC6[2] 

MC6[3] 

MC6[4] 

MC6[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC6[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 539 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

MC6[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0 HCAN

MC6[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC7[1] DLC3 DLC2 DLC1 DLC0

MC7[2] 

MC7[3] 

MC7[4] 

MC7[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC7[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC7[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC7[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC8[1] DLC3 DLC2 DLC1 DLC0

MC8[2] 

MC8[3] 

MC8[4] 

MC8[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC8[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC8[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC8[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC9[1] DLC3 DLC2 DLC1 DLC0

MC9[2] 

MC9[3] 

MC9[4] 

MC9[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC9[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC9[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC9[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC10[1] DLC3 DLC2 DLC1 DLC0

MC10[2] 

MC10[3] 

MC10[4] 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 540 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

MC10[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16 HCAN

MC10[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC10[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC10[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC11[1] DLC3 DLC2 DLC1 DLC0

MC11[2] 

MC11[3] 

MC11[4] 

MC11[5] ID−20 ID−19 ID−18 RTR IDE −ID−17 ID−16

MC11[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC11[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC11[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC12[1] DLC3 DLC2 DLC1 DLC0

MC12[2] 

MC12[3] 

MC12[4] 

MC12[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC12[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC12[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC12[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC13[1] DLC3 DLC2 DLC1 DLC0

MC13[2] 

MC13[3] 

MC13[4] 

MC13[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC13[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC13[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC13[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC14[1] DLC3 DLC2 DLC1 DLC0

MC14[2] 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 541 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

MC14[3] HCAN

MC14[4] 

MC14[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC14[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC14[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC14[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MC15[1] DLC3 DLC2 DLC1 DLC0

MC15[2] 

MC15[3] 

MC15[4] 

MC15[5] ID−20 ID−19 ID−18 RTR IDE ID−17 ID−16

MC15[6] ID−28 ID−27 ID−26 ID−25 ID−24 ID−23 ID−22 ID−21

MC15[7] ID−7ID−6ID−5ID−4ID−3ID−2ID−1ID−0

MC15[8] ID−15 ID−14 ID−13 ID−12 ID−11 ID−10 ID−9ID−8

MD0[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD0[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD0[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD0[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD0[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD0[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD0[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD0[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD1[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD1[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD1[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD1[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD1[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD1[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD1[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD1[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 542 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

MD2[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HCAN

MD2[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD2[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD2[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD2[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD2[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD2[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD2[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD3[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD3[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD3[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD3[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD3[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD3[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD3[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD3[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD4[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD4[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD4[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD4[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD4[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD4[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD4[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD4[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD5[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD5[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD5[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD5[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD5[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD5[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 543 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

MD5[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HCAN

MD5[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD6[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD6[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD6[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD6[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD6[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD6[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD6[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD6[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD7[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD7[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD7[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD7[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD7[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD7[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD7[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD7[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD8[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD8[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD8[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD8[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD8[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD8[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD8[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD8[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD9[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD9[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD9[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD9[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 544 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

MD9[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HCAN

MD9[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD9[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD9[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD10[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD10[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD10[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD10[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD10[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD10[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD10[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD10[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD11[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD11[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD11[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD11[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD11[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD11[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD11[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD11[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD12[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD12[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD12[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD12[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD12[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD12[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD12[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD12[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD13[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD13[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 545 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

MD13[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HCAN

MD13[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD13[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD13[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD13[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD13[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD14[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD14[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD14[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD14[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD14[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD14[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD14[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD14[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD15[1] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD15[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD15[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD15[4] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD15[5] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD15[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD15[7] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MD15[8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

HCAN

MON RXDIE TxSTP TxD RxD

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 546 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

SSCRH

_0 MSS BIDE SOL SOLP SCKS CSS1 CSS0 SSU_0

SSCRL

_0 SRES DATS1 DATS0

SSMR

_0 MLS CPOS CPHS CKS2 CKS1 CKS0

SSER

_0 TE RE TEIE TIE RIE CEIE

SSSR

_0 ORER TEND TDRE RDRF CE

SSTDR0

_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSTDR1

_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSTDR2

_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSTDR3

_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSRDR0

_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSRDR1

_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSRDR2

_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSRDR3

_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 547 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

SSCRH

_1 MSS BIDE SOL SOLP SCKS CSS1 CSS0 SSU_1

SSCRL

_1 SRES DATS1 DATS0

SSMR_1 MLS CPOS CPHS CKS2 CKS1 CKS0

SSER_1 TE RE TEIE TIE RIE CEIE

SSSR_1 ORER TEND TDRE RDRF CE

SSTDR0

_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSTDR1

_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSTDR2

_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSTDR3

_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSRDR0

_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSRDR1

_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSRDR2

_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSRDR3

_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PDRTIDR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORT

TCR_2 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

TCR_3 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

TMR_2,

TMR_3

TCSR_2 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0

TCSR_3 CMFB CMFA OVF OS3 OS2 OS1 OS0

TCORA

_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCORA

_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 548 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

TCORB

_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_2,

TMR_3

TCORB

_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCNT_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCNT_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SBYCR SSBY STS2 STS1 STS0 SYSTEM

SYSCR MACS INTM1 INTM0 NMIEG RAME

SCKCR PSTOP STCS SCK2 SCK1 SCK0

MDCR MDS2 MDS1 MDS0

MSTP

CRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0

MSTP

CRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0

MSTP

CRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0

LPWR

CR STC1 STC0

BARA PBC

BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16

BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8

BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0

BARB 

BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16

BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8

BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0

BCRA CMFA CDA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA

BCRB CMFB CDB BAMRB2 BAMRB1 BAMRB0 CSELB1 CSELB0 BIEB

ISCRH IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA INT

ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA

IER IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E

ISR IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 549 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

DTCERA DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTC

DTCERB DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0

DTCERC DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0

DTCERD DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0

DTCERE DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0

DTCERF DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEF1 DTCEF0

DTCERG DTCEG7 DTCEG6 DTCEG5 DTCEG4 DTCEG3 DTCEG2 DTCEG1 DTCEG0

DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0

PCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 PPG

PMR G3INV G2INV G3NOV G2NOV 

NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8

NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0

PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8

PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0

NDRH NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8

NDRL NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0

NDRH NDR11 NDR10 NDR9 NDR8

NDRL NDR3 NDR2 NDR1 NDR0

P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR PORT

P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR

P7DDR P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR

PADDR PA3DDR PA2DDR PA1DDR PA0DDR

PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR

PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR

PDDDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR

PFDDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR

PAPCR PA3PCR PA2PCR PA1PCR PA0PCR

PBPCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR

PCPCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR

PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 550 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

P3ODR P37ODR P36ODR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR PORT

PAODR PA3ODR PA2ODR PA1ODR PA0ODR

PBODR PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR

PCODR PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR

TCR_3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_3

TMDR_3 BFB BFA MD3 MD2 MD1 MD0

TIORH_3 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

TIORL_3 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

TIER_3 TTGE TCIEV TGIED TGIEC TGIEB TGIEA

TSR_3 TCFV TGFD TGFC TGFB TGFA

TCNTH_3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TCNTL_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRAH_3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TGRAL_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRBH_3 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TGRBL_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRC H_3 Bit 1 5 Bit 1 4 Bi t 1 3 Bit 1 2 Bit 11 Bit 1 0 Bit 9 Bi t 8

TGRCL_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRD H_3 Bit 1 5 Bit 1 4 Bi t 1 3 Bit 1 2 Bit 11 Bit 1 0 Bit 9 Bi t 8

TGRDL_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCR_4 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_4

TMDR_4 MD3 MD2 MD1 MD0

TIOR_4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

TIER_4 TTGE TCIEU TCIEV TGIEB TGIEA

TSR_4 TCFD TCFU TCFV TGFB TGFA

TCNTH_4 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TCNTL_4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRAH_4 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TGRAL_4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRBH_4 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TGRBL_4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 551 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

TCR_5 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_5

TMDR_5 MD3 MD2 MD1 MD0

TIOR_5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

TIER_5 TTGE TCIEU TCIEV TGIEB TGIEA

TSR_5 TCFD TCFU TCFV TGFB TGFA

TCNTH_5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TCNTL_5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRAH_5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TGRAL_5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRBH_5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TGRBL_5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TSTR CST5 CST4 CST3 CST2 CST1 CST0

TSYR SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0

TPU

common

IPRA IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 INT

IPRB IPR6 IPR5 IPR4 IPR2 IPR1 IPR0

IPRC IPR6 IPR5 IPR4 IPR2 IPR1 IPR0

IPRD IPR6 IPR5 IPR4 IPR2 IPR1 IPR0

IPRE IPR6 IPR5 IPR4 IPR2 IPR1 IPR0

IPRF IPR6 IPR5 IPR4 IPR2 IPR1 IPR0

IPRG IPR6 IPR5 IPR4 IPR2 IPR1 IPR0

IPRH IPR6 IPR5 IPR4 IPR2 IPR1 IPR0

IPRJ IPR6 IPR5 IPR4 IPR2 IPR1 IPR0

IPRK IPR6 IPR5 IPR4 IPR2 IPR1 IPR0

IPRM IPR6 IPR5 IPR4 IPR2 IPR1 IPR0

RAMER RAMS RAM2 RAM1 RAM0 FLASH

(F-ZTAT

Version)

P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR PORT

P3DR P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR

P7DR P77DR P76DR P75DR P74DR P73DR P72DR P71DR P70DR

PADR PA3DR PA2DR PA1DR PA0DR

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 552 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

PBDR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR PORT

PCDR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR

PDDR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR

PFDR PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR

TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_0

TMDR_0 BFB BFA MD3 MD2 MD1 MD0

TIORH_0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

TIER_0 TTGE TCIEV TGIED TGIEC TGIEB TGIEA

TSR_0 TCFV TGFD TGFC TGFB TGFA

TCNTH_0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TCNTL_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRAH_0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TGRAL_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRBH_0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TGRBL_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRCH_0 Bit 15 Bit 1 4 Bi t 1 3 Bit 1 2 Bit 11 Bit 1 0 Bit 9 Bi t 8

TGRCL_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRDH_0 Bit 15 Bit 1 4 Bi t 1 3 Bit 1 2 Bit 11 Bit 1 0 Bit 9 Bi t 8

TGRDL_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCR_1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_1

TMDR_1 MD3 MD2 MD1 MD0

TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

TIER_1 TTGE TCIEU TCIEV TGIEB TGIEA

TSR_1 TCFD TCFU TCFV TGFB TGFA

TCNTH_1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TCNTL_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRAH_1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TGRAL_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRBH_1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TGRBL_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 553 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

TCR_2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_2

TMDR_2 MD3 MD2 MD1 MD0

TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

TIER_2 TTGE TCIEU TCIEV TGIEB TGIEA

TSR_2 TCFD TCFU TCFV TGFB TGFA

TCNTH_2 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TCNTL_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRAH_2 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TGRAL_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TGRBH_2 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

TGRBL_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

TCR_1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

TMR_0,

TMR_1

TCSR_0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0

TCSR_1 CMFB CMFA OVF OS3 OS2 OS1 OS0

TCORA_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCORA_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCORB_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCORB_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCNT_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCNT_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TCSR_0 OVF WT/IT TME CKS2 CKS1 CKS0 WDT_0

TCNT_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RSTCSR WOVF RSTE RSTS 

SMR_0*1C/A CHR PE O/E STOP MP CKS1 CKS0 SCI_0

(SMR_0*2)(GM) (BLK) (PE) (O/E) (BCP1) (BCP0) (CKS1) (CKS0)

BRR_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SCR_0 TIE RIE TE RE MPIE TEIE CKE1 CKE0

TDR_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSR_0*1TDRE RDRF ORER FER PER TEND MPB MPBT

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 554 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

(SSR_0*2)(TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT) SCI_0

RDR_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SCMR_0 SDIR SINV SMIF

SMR_2*1C/A CHR PE O/E STOP MP CKS1 CKS0 SCI_2

(SMR_2*2)(GM) (BLK) (PE) (O/E) (BCP1) (BCP0) (CKS1) (CKS0)

BRR_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SCR_2 TIE RIE TE RE MPIE TEIE CKE1 CKE0

TDR_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SSR_2*1TDRE RDRF ORER FER PER TEND MPB MPBT

(SSR_2*2)(TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT)

RDR_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SCMR_2 SDIR SINV SMIF

ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D

ADDRAL AD1 AD0 

ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

ADDRBL AD1 AD0 

ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

ADDRCL AD1 AD0 

ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

ADDRDL AD1 AD0 

ADCSR ADF ADIE ADST SCAN CH3 CH2 CH1 CH0

ADCR TRGS1 TRGS0 CKS1 CKS0 

FLMCR1 FWE SWE ESU1 PSU1 EV1 PV1 E1 P1

FLMCR2 FLER 

EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

FLASH

(F-ZTAT

Version)

EBR2 EB9 EB8

PORT1 P17 P16 P15 P14 P13 P12 P11 P10 PORT

PORT3 P37 P36 P35 P34 P33 P32 P31 P30

PORT4 P47 P46 P45 P44 P43 P42 P41 P40

PORT7 P77 P76 P75 P74 P73 P72 P71 P70

PORT9 P97 P96 P95 P94 P93 P92 P91 P90

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 555 of 598

REJ09B0155-0300

Abbrevia-

tion Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

PORTA PA3 PA2 PA1 PA0 PORT

PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PORTF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

Notes: 1. Normal serial communication interface mode.

2. Smart Card interface mode.

Some bit functions of SMR differ in normal serial communication interface mode and

Smart Card interface mode.

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 556 of 598

REJ09B0155-0300

22.3 Register States in Each Operating Mode

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

MCR Initialized Initialized Initialized Initialized HCAN

GSR Initialized Initialized Initialized Initialized

BCR Initialized Initialized Initialized Initialized

MBCR Initialized Initialized Initialized Initialized

TXPR Initialized Initialized Initialized Initialized

TXCR Initialized Initialized Initialized Initialized

TXACK Initialized Initialized Initialized Initialized

ABACK Initialized Initialized Initialized Initialized

RXPR Initialized Initialized Initialized Initialized

RFPR Initialized Initialized Initialized Initialized

IRR Initialized Initialized Initialized Initialized

MBIMR Initialized Initialized Initialized Initialized

IMR Initialized Initialized Initialized Initialized

REC Initialized Initialized Initialized Initialized

TEC Initialized Initialized Initialized Initialized

UMSR Initialized Initialized Initialized Initialized

LAFML Initialized Initialized Initialized Initialized

LAFMH Initialized Initialized Initialized Initialized

MC0[1] 

MC0[2] 

MC0[3] 

MC0[4] 

MC0[5] 

MC0[6] 

MC0[7] 

MC0[8] 

MC1[1] 

MC1[2] 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 557 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

MC1[3] HCAN

MC1[4] 

MC1[5] 

MC1[6] 

MC1[7] 

MC1[8] 

MC2[1] 

MC2[2] 

MC2[3] 

MC2[4] 

MC2[5] 

MC2[6] 

MC2[7] 

MC2[8] 

MC3[1] 

MC3[2] 

MC3[3] 

MC3[4] 

MC3[5] 

MC3[6] 

MC3[7] 

MC3[8] 

MC4[1] 

MC4[2] 

MC4[3] 

MC4[4] 

MC4[5] 

MC4[6] 

MC4[7] 

MC4[8] 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 558 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

MC5[1] HCAN

MC5[2] 

MC5[3] 

MC5[4] 

MC5[5] 

MC5[6] 

MC5[7] 

MC5[8] 

MC6[1] 

MC6[2] 

MC6[3] 

MC6[4] 

MC6[5] 

MC6[6] 

MC6[7] 

MC6[8] 

MC7[1] 

MC7[2] 

MC7[3] 

MC7[4] 

MC7[5] 

MC7[6] 

MC7[7] 

MC7[8] 

MC8[1] 

MC8[2] 

MC8[3] 

MC8[4] 

MC8[5] 

MC8[6] 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 559 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

MC8[7] HCAN

MC8[8] 

MC9[1] 

MC9[2] 

MC9[3] 

MC9[4] 

MC9[5] 

MC9[6] 

MC9[7] 

MC9[8] 

MC10[1] 

MC10[2] 

MC10[3] 

MC10[4] 

MC10[5] 

MC10[6] 

MC10[7] 

MC10[8] 

MC11[1] 

MC11[2] 

MC11[3] 

MC11[4] 

MC11[5] 

MC11[6] 

MC11[7] 

MC11[8] 

MC12[1] 

MC12[2] 

MC12[3] 

MC12[4] 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 560 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

MC12[5] HCAN

MC12[6] 

MC12[7] 

MC12[8] 

MC13[1] 

MC13[2] 

MC13[3] 

MC13[4] 

MC13[5] 

MC13[6] 

MC13[7] 

MC13[8] 

MC14[1] 

MC14[2] 

MC14[3] 

MC14[4] 

MC14[5] 

MC14[6] 

MC14[7] 

MC14[8] 

MC15[1] 

MC15[2] 

MC15[3] 

MC15[4] 

MC15[5] 

MC15[6] 

MC15[7] 

MC15[8] 

MD0[1] 

MD0[2] 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 561 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

MD0[3] HCAN

MD0[4] 

MD0[5] 

MD0[6] 

MD0[7] 

MD0[8] 

MD1[1] 

MD1[2] 

MD1[3] 

MD1[4] 

MD1[5] 

MD1[6] 

MD1[7] 

MD1[8] 

MD2[1] 

MD2[2] 

MD2[3] 

MD2[4] 

MD2[5] 

MD2[6] 

MD2[7] 

MD2[8] 

MD3[1] 

MD3[2] 

MD3[3] 

MD3[4] 

MD3[5] 

MD3[6] 

MD3[7] 

MD3[8] 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 562 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

MD4[1] HCAN

MD4[2] 

MD4[3] 

MD4[4] 

MD4[5] 

MD4[6] 

MD4[7] 

MD4[8] 

MD5[1] 

MD5[2] 

MD5[3] 

MD5[4] 

MD5[5] 

MD5[6] 

MD5[7] 

MD5[8] 

MD6[1] 

MD6[2] 

MD6[3] 

MD6[4] 

MD6[5] 

MD6[6] 

MD6[7] 

MD6[8] 

MD7[1] 

MD7[2] 

MD7[3] 

MD7[4] 

MD7[5] 

MD7[6] 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 563 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

MD7[7] HCAN

MD7[8] 

MD8[1] 

MD8[2] 

MD8[3] 

MD8[4] 

MD8[5] 

MD8[6] 

MD8[7] 

MD8[8] 

MD9[1] 

MD9[2] 

MD9[3] 

MD9[4] 

MD9[5] 

MD9[6] 

MD9[7] 

MD9[8] 

MD10[1] 

MD10[2] 

MD10[3] 

MD10[4] 

MD10[5] 

MD10[6] 

MD10[7] 

MD10[8] 

MD11[1] 

MD11[2] 

MD11[3] 

MD11[4] 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 564 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

MD11[5] HCAN

MD11[6] 

MD11[7] 

MD11[8] 

MD12[1] 

MD12[2] 

MD12[3] 

MD12[4] 

MD12[5] 

MD12[6] 

MD12[7] 

MD12[8] 

MD13[1] 

MD13[2] 

MD13[3] 

MD13[4] 

MD13[5] 

MD13[6] 

MD13[7] 

MD13[8] 

MD14[1] 

MD14[2] 

MD14[3] 

MD14[4] 

MD14[5] 

MD14[6] 

MD14[7] 

MD14[8] 

MD15[1] 

MD15[2] 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 565 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

MD15[3] HCAN

MD15[4] 

MD15[5] 

MD15[6] 

MD15[7] 

MD15[8] 

HCANMON Initialized Initialized

SSCRH_0 Initialized Initialized Initialized Initialized SSU_0

SSCRL_0 Initialized Initialized Initialized Initialized

SSMR_0 Initialized Initialized Initialized Initialized

SSER_0 Initialized Initialized Initialized Initialized

SSSR_0 Initialized Initialized Initialized Initialized

SSTDR0_0 Initialized Initialized Initialized Initialized

SSTDR1_0 Initialized Initialized Initialized Initialized

SSTDR2_0 Initialized Initialized Initialized Initialized

SSTDR3_0 Initialized Initialized Initialized Initialized

SSRDR0_0 Initialized Initialized Initialized Initialized

SSRDR1_0 Initialized Initialized Initialized Initialized

SSRDR2_0 Initialized Initialized Initialized Initialized

SSRDR3_0 Initialized Initialized Initialized Initialized

SSCRH_1 Initialized Initialized Initialized Initialized SSU_1

SSCRL_1 Initialized Initialized Initialized Initialized

SSMR_1 Initialized Initialized Initialized Initialized

SSER_1 Initialized Initialized Initialized Initialized

SSSR_1 Initialized Initialized Initialized Initialized

SSTDR0_1 Initialized Initialized Initialized Initialized

SSTDR1_1 Initialized Initialized Initialized Initialized

SSTDR2_1 Initialized Initialized Initialized Initialized

SSTDR3_1 Initialized Initialized Initialized Initialized

SSRDR0_1 Initialized Initialized Initialized Initialized

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 566 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

SSRDR1_1 Initialized Initialized Initialized Initialized SSU_1

SSRDR2_1 Initialized Initialized Initialized Initialized

SSRDR3_1 Initialized Initialized Initialized Initialized

PDRTIDR Initialized Initialized PORT

TCR_2 Initialized Initialized

TCR_3 Initialized Initialized

TMR_2,

TMR_3

TCSR_2 Initialized Initialized

TCSR_3 Initialized Initialized

TCORA_2 Initialized Initialized

TCORA_3 Initialized Initialized

TCORB_2 Initialized Initialized

TCORB_3 Initialized Initialized

TCNT_2 Initialized Initialized

TCNT_3 Initialized Initialized

SBYCR Initialized SYSTEM

SYSCR Initialized 

SCKCR Initialized 

MDCR Initialized 

MSTPCRA Initialized 

MSTPCRB Initialized 

MSTPCRC Initialized 

LPWRCR Initialized 

BARA Initialized Initialized PBC

BARB Initialized Initialized

BCRA Initialized Initialized

BCRB Initialized Initialized

ISCRH Initialized Initialized INT

ISCRL Initialized Initialized

IER Initialized Initialized

ISR Initialized Initialized

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 567 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

DTCERA Initialized Initialized DTC

DTCERB Initialized Initialized

DTCERC Initialized Initialized

DTCERD Initialized Initialized

DTCERE Initialized Initialized

DTCERF Initialized Initialized

DTCERG Initialized Initialized

DTVECR Initialized Initialized

PCR Initialized Initialized PPG

PMR Initialized Initialized

NDERH Initialized Initialized

NDERL Initialized Initialized

PODRH Initialized Initialized

PODRL Initialized Initialized

NDRH Initialized Initialized

NDRL Initialized Initialized

NDRH Initialized Initialized

NDRL Initialized Initialized

P1DDR Initialized PORT

P3DDR Initialized 

P7DDR Initialized 

PADDR Initialized 

PBDDR Initialized 

PCDDR Initialized 

PDDDR Initialized 

PFDDR Initialized 

PAPCR Initialized 

PBPCR Initialized 

PCPCR Initialized 

PDPCR Initialized 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 568 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

P3ODR Initialized PORT

PAODR Initialized 

PBODR Initialized 

PCODR Initialized 

TCR_3 Initialized Initialized TPU_3

TMDR_3 Initialized Initialized

TIORH_3 Initialized Initialized

TIORL_3 Initialized Initialized

TIER_3 Initialized Initialized

TSR_3 Initialized Initialized

TCNTH_3 Initialized Initialized

TCNTL_3 Initialized Initialized

TGRAH_3 Initialized Initialized

TGRAL_3 Initialized Initialized

TGRBH_3 Initialized Initialized

TGRBL_3 Initialized Initialized

TGRCH_3 Initialized Initialized

TGRCL_3 Initialized Initialized

TGRDH_3 Initialized Initialized

TGRDL_3 Initialized Initialized

TCR_4 Initialized Initialized TPU_4

TMDR_4 Initialized Initialized

TIOR_4 Initialized Initialized

TIER_4 Initialized Initialized

TSR_4 Initialized Initialized

TCNTH_4 Initialized Initialized

TCNTL_4 Initialized Initialized

TGRAH_4 Initialized Initialized

TGRAL_4 Initialized Initialized

TGRBH_3 Initialized Initialized

TGRBL_4 Initialized Initialized

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 569 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

TCR_5 Initialized Initialized TPU_5

TMDR_5 Initialized Initialized

TIOR_5 Initialized Initialized

TIER_5 Initialized Initialized

TSR_5 Initialized Initialized

TCNTH_5 Initialized Initialized

TCNTL_5 Initialized Initialized

TGRAH_5 Initialized Initialized

TGRAL_5 Initialized Initialized

TGRBH_5 Initialized Initialized

TGRBL_5 Initialized Initialized

TSTR Initialized Initialized

TSYR Initialized Initialized

TPU

common

IPRA Initialized Initialized INT

IPRB Initialized Initialized

IPRC Initialized Initialized

IPRD Initialized Initialized

IPRE Initialized Initialized

IPRF Initialized Initialized

IPRG Initialized Initialized

IPRH Initialized Initialized

IPRJ Initialized Initialized

IPRK Initialized Initialized

IPRM Initialized Initialized

RAMER Initialized Initialized ROM

P1DR Initialized PORT

P3DR Initialized 

P7DR Initialized 

PADR Initialized 

PBDR Initialized 

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 570 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

PCDR Initialized PORT

PDDR Initialized 

PFDR Initialized 

TCR_0 Initialized Initialized TPU_0

TMDR_0 Initialized Initialized

TIORH_0 Initialized Initialized

TIORL_0 Initialized Initialized

TIER_0 Initialized Initialized

TSR_0 Initialized Initialized

TCNTH_0 Initialized Initialized

TCNTL_0 Initialized Initialized

TGRAH_0 Initialized Initialized

TGRAL_0 Initialized Initialized

TGRBH_0 Initialized Initialized

TGRBL_0 Initialized Initialized

TGRCH_0 Initialized Initialized

TGRCL_0 Initialized Initialized

TGRDH_0 Initialized Initialized

TGRDL_0 Initialized Initialized

TCR_1 Initialized Initialized TPU_1

TMDR_1 Initialized Initialized

TIOR_1 Initialized Initialized

TIER_1 Initialized Initialized

TSR_1 Initialized Initialized

TCNTH_1 Initialized Initialized

TCNTL_1 Initialized Initialized

TGRAH_1 Initialized Initialized

TGRAL_1 Initialized Initialized

TGRBH_1 Initialized Initialized

TGRBL_1 Initialized Initialized

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 571 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

TCR_2 Initialized Initialized TPU_2

TMDR_2 Initialized Initialized

TIOR_2 Initialized Initialized

TIER_2 Initialized Initialized

TSR_2 Initialized Initialized

TCNTH_2 Initialized Initialized

TCNTL_2 Initialized Initialized

TGRAH_2 Initialized Initialized

TGRAL_2 Initialized Initialized

TGRBH_2 Initialized Initialized

TGRBL_2 Initialized Initialized

TCR_0 Initialized Initialized

TCR_1 Initialized Initialized

TMR_0,

TMR_1

TCSR_0 Initialized Initialized

TCSR_1 Initialized Initialized

TCORA_0 Initialized Initialized

TCORA_1 Initialized Initialized

TCORB_0 Initialized Initialized

TCORB_1 Initialized Initialized

TCNT_0 Initialized Initialized

TCNT_1 Initialized Initialized

TCSR_0 Initialized Initialized WDT_0

TCNT_0 Initialized Initialized

RSTCSR Initialized Initialized

SMR_0 Initialized Initialized SCI_0

BRR_0 Initialized Initialized

SCR_0 Initialized Initialized

TDR_0 Initialized Initialized Initialized Initialized

SSR_0 Initialized Initialized Initialized Initialized

RDR_0 Initialized Initialized Initialized Initialized

SCMR_0 Initialized Initialized

Section 22 List of Registers

Rev. 3.00 Oct 04, 2005 page 572 of 598

REJ09B0155-0300

Abbreviation Reset High

Speed Medium

Speed Sleep Module

Stop Software

Standby Hardware

Standby Module

SMR_2 Initialized Initialized SCI_2

BRR_2 Initialized Initialized

SCR_2 Initialized Initialized

TDR_2 Initialized Initialized Initialized Initialized

SSR_2 Initialized Initialized Initialized Initialized

RDR_2 Initialized Initialized Initialized Initialized

SCMR_2 Initialized Initialized

ADDRAH Initialized Initialized Initialized Initialized A/D

ADDRAL Initialized Initialized Initialized Initialized

ADDRBH Initialized Initialized Initialized Initialized

ADDRBL Initialized Initialized Initialized Initialized

ADDRCH Initialized Initialized Initialized Initialized

ADDRCL Initialized Initialized Initialized Initialized

ADDRDH Initialized Initialized Initialized Initialized

ADDRDL Initialized Initialized Initialized Initialized

ADCSR Initialized Initialized Initialized Initialized

ADCR Initialized Initialized Initialized Initialized

FLMCR1 Initialized Initialized ROM

FLMCR2 Initialized Initialized

EBR1 Initialized Initialized

EBR2 Initialized Initialized

PORT1 Initialized PORT

PORT3 Initialized 

PORT4 Initialized 

PORT7 Initialized 

PORT9 Initialized 

PORTA Initialized 

PORTB Initialized 

PORTC Initialized 

PORTD Initialized 

PORTF Initialized 

Note:  is not initialized.

Section 23 Electrical Characteristics

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Section 23 E lectrical Charac teristics

23.1 Absolute Maximum Ratings

Table 23.1 lists the absolute maximum ratings.

Table 23.1 Absolute Max imu m Ratings

Item Symbol Value Unit

Power supply voltage VCC –0.3 to +7.0 V

Input voltage (XTAL, EXTAL) Vin –0.3 to VCC +0.3 V

Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.3 V

Input voltage (except XTAL,

EXTAL, ports 4 and 9) Vin –0.3 to VCC +0.3 V

Analog power supply voltage AVCC –0.3 to +7.0 V

Analog input voltage VAN –0.3 to AVCC +0.3 V

Operating temperature Topr Regular specifications: –20 to +75 °C

Wide-range specifications: –40 to +85 °C

Storage temperature Tstg –55 to +125 °C

Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded.

Section 23 Electrical Characteristics

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23.2 DC Characteristics

Table 23.2 lists the DC characteristics. Table 23.3 lists the permissible output currents.

Table 23.2 DC Character istics

Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V,

Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range

specifications)*1

Item Symbol Min Typ Max Unit Test

Conditions

IRQ5

IRQ0

VT–VCC × 0.2 V

VT+VCC × 0.7 V

Schmitt

trigger input

voltage VT+ – VT–VCC × 0.05 V

Input high

voltage

RES

STBY

NMI,

MD2 to MD0,

FWE

VIH VCC × 0.9 VCC + 0.3 V

EXTAL VCC × 0.7 VCC + 0.3 V

Ports 7, 3, 1,

A to D, F,

HRxD

VCC × 0.7 VCC + 0. 3 V

Ports 9 and 4 AVCC × 0.7 AVCC + 0.3 V

Input low

voltage

RES

STBY

NMI,

MD2 to MD0,

FWE

VIL –0.3 VCC × 0.1 V

EXTAL –0.3 VCC × 0.2 V

Ports 7, 3, 1,

A to D, F,

HRxD

–0.3 VCC × 0.2 V

Ports 9, 4 –0.3 AVCC × 0.2 V

All output pins VOH VCC – 0.5 VI

OH = –200 µAOutput high

voltage VCC – 1.0 VI

OH = –1 mA

Output low

voltage All output pins VOL 0.4 V IOL = 1.6 mA

Section 23 Electrical Characteristics

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REJ09B0155-0300

Item Symbol Min Typ Max Unit Test

Conditions

RES

| Iin | 1.0 µAInput leakage

current

STBY

, NMI,

MD2 to MD0,

FW E, HRxD

1.0 µA

Vin = 0.5 to

VCC – 0.5 V

Ports 9, 4 1.0 µA Vin = 0.5 to

AVCC – 0.5 V

Input pull-up

MOS current Ports A to D –IP30 300 µA Vin = 0 V

RES

Cin 30 pF

Input

capacitance NMI 30 pF

All input pins

except

RES

and NMI

15 pF

Vin = 0 V

f = 1 MHz

Ta = 25°C

Current

consumption*2Normal

operation ICC*380

VCC = 5.0 V 90

VCC = 5.5 V mA f = 24 MHz

Sleep mode 60

VCC = 5.0 V 70

VCC = 5.5 V mA f = 24 MHz

All modules

stopped 55 mA f = 24 MHz,

VCC = 5.0 V

(reference

values)

Medium-

speed mode

(φ/32)

65 mA f = 24 MHz,

VCC = 5.0 V

(reference

values)

Standby 2.0 5.0 µA Ta ≤ 50°C

mode 200 µA 50°C < Ta

During A/D

conversion AlCC 1.0 2.0 mA AVCC = 5.0 V

Analog

power supply

current Idle 5.0 µA

During A/D

conversion AlCC 1.0 2.0 mA Vref = 5.0 VReference

power supply

current Idle 5.0 µA

RAM standby vol tage VRAM 2.0 V

Notes: 1. If the A/D converter is not used, do not leave the AVCC, Vref, and AVSS pins open. Apply

a voltage between 4.5 V and 5.5 V to the AVCC pin by connecting them to VCC, for

instance.

Section 23 Electrical Characteristics

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REJ09B0155-0300

2. Current consumption values are for VIH = VCC (EXTAL), AVCC (ports 4 and 9), or VCC

(other), and VIL = 0 V, with all output pins unloaded and the on-chip pull-up MOS

transistors in the off state.

3. ICC depends on VCC and f as follows:

ICC (max) = 27 + 0.435 × VCC × f (normal operation)

ICC (max) = 27 + 0.3 × VCC × f (sleep mode)

Table 23.3 Permissible Output Currents

Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V,

Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range

specifications)*

Item Symbol Min Typ Max Unit

Permissible output

low current (per pin) All output

pins VCC = 4.5 to 5.5 V IOL 10 mA

Permissible output

low current (total) Total of all

output pins VCC = 4.5 to 5.5 V

∑

IOL 100 mA

Permissible output

high current (per pin) All output

pins VCC = 4.5 to 5.5 V –IOH 2.0 mA

Permissible output

high current (total) Total of all

output pins VCC = 4.5 to 5.5 V

∑

–IOH 30 mA

Note: * To protect chip reliability, do not exceed the output current values in table 23.3.

23.3 AC Characteristics

Figure 23.1 shows the test conditions for the AC characteristics.

5 V

LSI output pin

C=30 pF

= 2.4 kΩ

=12 kΩ

Input/output timing measurement levels

• Low level : 0.8 V

• High level : 2.0 V

Figure 23.1 Output Load Circuit

Section 23 Electrical Characteristics

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REJ09B0155-0300

23.3.1 Clock Timing

Table 23.4 lists the clock timing

Table 23.4 Clock T iming

Conditions : VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V,

φ = 4 MHz to 24 MHz, Ta = –20°C to +75°C (regul ar specifica tions ),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min Max Unit Test Conditions

Clock cycle time tcyc 41.6 250 ns Figure 23.2

Clock high pul se width tCH 8ns

Clock low pulse width tCL 8ns

Clock rise time tCr 13 ns

Clock fall time tCf 13 ns

Oscillation settling time at reset

(crystal) tOSC1 20 ms Figure 23.3

Oscillation settling time in

software standby (crystal) tOSC2 8m s Figure 21.3

External clock output settling

delay time tDEXT 2m s Figure 23.3

cyc

Figure 23.2 System Clock Timing

Section 23 Electrical Characteristics

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REJ09B0155-0300

tOSC1

EXTAL

VCC

STBY

RES

tDEXT tDEXT

Figure 23.3 Oscillation Settling Timing

23.3.2 Control Signal Timing

Table 23.5 lists the control signal timing.

Table 23.5 Control Signal Timing

Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V,

φ = 4 MHz to 24 MHz, Ta = –20°C to +75°C (regul ar specifica tions ),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min Max Unit Test Conditions

RES

setup time tRESS 200 ns Figure 23.4

RES

pulse width tRESW 20 tcyc

NMI setup time tNMIS 150 ns Figure 23.5

NMI hold ti me tNMIH 10 ns

NMI pulse width (exiting

software standby mode) tNMIW 200 ns

IRQ

setup time tIRQS 150 ns

IRQ

hold time tIRQH 10 ns

IRQ

pulse width (exiting

software standby mode) tIRQW 200 ns

Section 23 Electrical Characteristics

Rev. 3.00 Oct 04, 2005 page 579 of 598

REJ09B0155-0300

RESW

RESS

RES

Figure 23.4 Reset Input Timing

tIRQS

IRQ

Edge input

tIRQH

tNMIS tNMIH

tIRQS

IRQ

Level input

NMI

IRQi

(i = 5 to 0)

tNMIW

tIRQW

Figure 23.5 Interrupt Input Timing

Section 23 Electrical Characteristics

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REJ09B0155-0300

23.3.3 Timing of On-Chip Peripheral Modu les

Table 23.6 lists the timing of on-chip peripheral modules.

Table 23.6 Timing of On -Chip Peripheral Modu les

Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 , φ = 4 MHz to 24

MHz,

Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range

specifications)

Item Symbol Min Max Unit Test

Conditions

I/O port Output data delay time tPWD 40 ns Figure 23.6

Input data setup time tPRS 25 

Input data hold time tPRH 25 

Realtime input port data

hold ti me tRTIPH 4tcyc Figure 23.7

TPU Timer output delay time tTOCD 40 ns Figure 23.8

Timer input setup time tTICS 25 

Timer clock input setup

time tTCKS 25 ns Figure 23.9

Single edge tTCKWH 1.5 tcyc

Timer clock

pulse width Both edges tTCKWL 2.5 

SCI Asynchronous tScyc 4tcyc Figure 23.10

Input clock

cycle Synchronous 6 

Input clock pulse width tSCKW 0.4 0.6 tScyc

Input clock rise time t SCKr 1.5 tcyc

Input clock fall time tSCKf 1.5

Transmit data delay time tTXD 40 ns Figure 23.11

Receive data setup time

(synchronous) tRXS 40 

Receive data hold time

(synchronous) tRXH 40 

Section 23 Electrical Characteristics

Rev. 3.00 Oct 04, 2005 page 581 of 598

REJ09B0155-0300

Item Symbol Min Max Unit Test

Conditions

A/D

converter Trigger input setup time tTRGS 30 ns Figure 23.12

HCAN*Transmit data delay time tHTXD 80 ns Figure 23.13

Receive data setup time tHRXS 80 

Receive data hold time tHRXH 80 

PPG Pulse output delay time tPOD 40 ns Figure 23.14

TMR Ti mer output delay time tTMOD 40 ns Figure 23.15

Timer reset input setup

time tTMRS 25 ns Figure 23.17

Timer clock input setup

time tTMCS 25 ns Figure 23.16

Single edge tTMCWH 1.5 tCYC

Timer clock

pulse width Both edges tTMCWL 2.5 

Note: *The HCAN input signal is asynchronous. However, its state is judged to have changed

at the rising-edge (two clock cycles) of the φ clock signal shown in figure 23.13. The

HCAN output signal is also asynchronous. Its state changes based on the ri sing-edge

(two clock cycles) of the φ clock signal shown in figure 23.13.

Section 23 Electrical Characteristics

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REJ09B0155-0300

Table 23.7 Timing of SSU

Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 , φ = 4 MHz to 24

MHz,

Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range

specifications)

Item Symbol Min Max Unit Test Conditions

SSU Clock cycle Master

Slave tSUCYC 2

4256

256 tCYC

Clock high

level pulse

width

Master

Slave tHI 20

60 

ns

Figure 23.18

Figure 23.19

Figure 23.20

Figure 23.21

Clock low

level pulse

width

Master

Slave tLO 20

60 

ns

Clock rise time tRISE 20 ns

Clock fall time tFALL 20 ns

Data input

setup time Master

Slave tSU 30

30 

ns

Data input

hold ti me Master

Slave tH10

10 

ns

SCS setup

time Master

Slave tLEAD 1.5

1.5 

tCYC

SCS hold time Master

Slave tLAG 1.5

1.5 

tCYC

Data output

delay time Master

Slave tOD 

40

40 ns

Data output

hold ti me Master

Slave tOH 30

30 

ns

Continuous

transmit delay

time

Master

Slave tTD 1.5

1.5 

tCYC

Slave access time tSA 1t

CYC

Slave out release time tREL 1t

CYC

Section 23 Electrical Characteristics

Rev. 3.00 Oct 04, 2005 page 583 of 598

REJ09B0155-0300

Ports 9, 7, 4, 3, 1,

A to D, F (read)

tPRS

PWD

PRH

Ports 7, 3, 1, A to D, F

(write)

Figure 23.6 I/O Port Input/Output Timing

IRQ3

tRTIPH

Port D input

Figure 23.7 Realtime Input Port Data Input Timing

TICS

TOCD

Output compare

output*

Input capture

input*

Note: * TIOCA5 to TIOCA0, TIOCB5 to TIOCB0, TIOCC3, TIOCC0, TIOCD3, TIOCD0

Figure 23.8 TPU Input/Output Timing

Section 23 Electrical Characteristics

Rev. 3.00 Oct 04, 2005 page 584 of 598

REJ09B0155-0300

TCKS

TCLKA to TCLKD

TCKWH

TCKWL

Figure 23.9 TPU Clock Input Timing

Scyc

SCKr

SCKW

SCK2, SCK0

SCKf

Figure 23.10 SCK Clock Input Timing

SCK2, SCK0

TxD2, TxD0

(transmit data)

RxD2, RxD0

(receive data)

TXD

RXH

RXS

Figure 23.11 SCI Input/Output Timing (Clocked Synchronous Mode)

TRGS

ADTRG

Figure 23.12 A/D Converter External Trigger Input Timing

Section 23 Electrical Characteristics

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REJ09B0155-0300

HTxD

(transmit data)

HRxD

(receive data)

tHTXD

tHRXS tHRXH

Figure 23.13 HCAN Input/Output Timing

PO15 to 8

POD

Figure 23.14 PPG Output Timing

tTMOD

TMO3, TMO2

TMO1, TMO0

Figure 23.15 8-Bit Timer Output Timing

tTMCS

TMCI23, TMCI01

tTMCWH

tTMCWL

Figure 23.16 8-Bit Timer Clock Input Timing

Section 23 Electrical Characteristics

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REJ09B0155-0300

TMRS

TMRI23, TMRI01

Figure 23.17 8-Bit Timer Reset Input Timing

LEAD

SUCYC

FALL

RISE

LAG

SCS (output)

SSCK (output)

CPOS = 1

SSCK (output)

CPOS = 0

SSO (output)

SSI (input)

Figure 23.18 SSU Timing (Master, CPHS =

= 1)

Section 23 Electrical Characteristics

Rev. 3.00 Oct 04, 2005 page 587 of 598

REJ09B0155-0300

tLEAD

tSUCYC

tFALL tRISE tLAG

tHI

tOH

tLO

tHI

tOD

tSU

SCS (output)

SSCK (output)

CPOS = 1

SSCK (output)

CPOS = 0

SSO (output)

SSI (input)

tTD

Figure 23.19 SSU Timing (Master, CPHS =

= 0)

LEAD

SUCYC

FALL

RISE

LAG

REL

SCS (input)

SSCK (input)

CPOS = 1

SSCK (input)

CPOS = 0

SSO (input)

SSI (output)

Figure 23.20 SSU Timing (Slave, CPHS =

= 1)

Section 23 Electrical Characteristics

Rev. 3.00 Oct 04, 2005 page 588 of 598

REJ09B0155-0300

tLEAD

tSUCYC

tFALL tRISE tLAG

tHI tTD

tHtREL

tOH

tLO

tHI

tOD

tSU

SCS (input)

SSCK (input)

CPOS = 1

SSCK (input)

CPOS = 0

SSO (input)

SSI (output)

tSA

Figure 23.21 SSU Timing (Slave, CPHS =

= 0)

Section 23 Electrical Characteristics

Rev. 3.00 Oct 04, 2005 page 589 of 598

REJ09B0155-0300

23.4 A/D Conversio n Characteri stics

Table 23.8 lists the A/D conversion characteristics.

Table 23.8 A/D Conversion Characteristics

Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0V,

φ = 4 MHz to 24 MHz, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Min Typ Max Unit

Resolution 10 10 10 bits

Conversion time 10 200 µs

Analog input capacitance 20 pF

Permissible signal-source impedance 5kΩ

Nonlinearity error ±3.5 LSB

Offset error ±3.5 LSB

Full-scale error ±3.5 LSB

Quantization ±0.5 LSB

Absolute accuracy ±4.0 LSB

Section 23 Electrical Characteristics

Rev. 3.00 Oct 04, 2005 page 590 of 598

REJ09B0155-0300

23.5 Flash Memory Characteristics

Table 23.9 lists the flash memory characteristics.

Table 23.9 Flash Memory Character istics

Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,

VSS = PLLVSS = AVSS = 0 V,

Ta = 0 to +75°C (Programming/erasing operating temperature range)

Ite m Sy mbol Min Typ Max Unit Test Condition

Programming time *1*2*4tP10 200 ms/

128 bytes

Erase time *1*3*5tE100 1200 ms/block

Reprogramming count NWEC 100 Times

Programming Wait time after SWE bit setting*1tsswe 11µs

Wait time after PSU1 bit setting*1tspsu 50 50 µs

Wait time after P1 bit setting*1*4tsp30 28 30 32 µs Programming

time wait

tsp200 198 200 202 µs Programming

time wait

tsp10 8 10 12 µs Additional-

programming

time wait

Wait time after P1 bit clear*1tcp 55µs

Wait time after PSU1 bit clear*1tcpsu 55µs

Wait time after PV1 bit setting*1tspv 44µs

Wait time after H'FF dumm y write*1tspvr 22µs

Wait time after PV1 bit clear*1tcpv 22µs

Wait time after SWE bit clear*1tcswe 100 100 µs

Maximum programming count*1*4N1000 Times

Erase Wait time after SWE bit setting*1tsswe 11µs

Wait time after ESU1 bit setting*1tsesu 100 100 µs

Wait time after E1 bit setting*1*5tse 10 10 100 ms E r ase time w ai t

Wait time after E1 bit clear*1tce 10 10 µs

Wait time after ESU1 bit clear*1tcesu 10 10 µs

Wait time after EV1 bit setting*1tsev 20 20 µs

Wait time after H'FF dumm y write*1tsevr 22µs

Wait time after EV1 bit clear*1tcev 44µs

Wait time after SWE bit clear*1tcswe 100 100 µs

Maximum erase count*1*5N12120 Times

Section 23 Electrical Characteristics

Rev. 3.00 Oct 04, 2005 page 591 of 598

REJ09B0155-0300

Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or

erase/erase-verify flowchart.

2. Programming time per 128 bytes (shows the total period for which the P1 bit in the flash

memory control register (FLMCR1) is set. It does not include the programmi ng

verification time.)

3. Block erase time (shows the total period for which the E1-bit FLMCR1 is set. It does not

include the erase verification time.)

4. To specify the maximum programming time value (tp (max)) in the 128-bytes

programming algorithm, set the max. value (1000) for the maximum programming

count (n).

The wait time after P1 bit setting should be changed as follows according to the value of

the programming counter (n).

Programming counter (n) = 1 to 6: tsp30 = 30 µs

Programming counter (n) = 7 to 1000: tsp200 = 200 µs

[In additi onal programming]

Programming counter (n) = 1 to 6: tsp10 = 10 µs

5. For the maximum erase time (tE (max)), the following relationship applies between the

wait time after E1 bit setting (tse) and the maximum erase count (N):

tE (max) = Wait time after E1 bit setting (tse) × maximum erase count (N)

To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy

the above formula.

Examples: When tse = 100 ms, N = 12 times

When tse = 10 ms, N = 120 times

Section 23 Electrical Characteristics

Rev. 3.00 Oct 04, 2005 page 592 of 598

REJ09B0155-0300

Appendix

Rev. 3.00 Oct 04, 2005 page 593 of 598

REJ09B0155-0300

Appendix

A. I/O Port States in Each Pin State

Port Name

MCU

Operating

Mode Reset

Hardware

Standby

Mode Software

Standby Mode Program Execution

State Sleep Mode

Port 1 7 T T Keep I/O port

Port 3 7 T T Keep I/O port

Port 4 7 T T T Input port

Port 7 7 T T Keep I/O port

Port 9 7 T T T Input port

Port A 7 T T Keep I/O port

Port B 7 T T Keep I/O port

Port C 7 T T Keep I/O port

Port D 7 T T Keep I/O port

PF7 7 T T [DDR = 0]

[DDR = 1]

[DDR = 0]

[DDR = 1]

Clock output

PF6

PF5

PF4

PF3

PF2

PF1

PF0

7 T T Keep I/O port

HTxD 7 H T H Output

HRxD 7 Input T T Input

Legend:

H: High level

T: High im pedance

Keep: Input port becomes high-impedance, output port retains state

Appendix

Rev. 3.00 Oct 04, 2005 page 594 of 598

REJ09B0155-0300

B . Produc t Code L ineup

Pr odu ct Type Type Nam e Package

(Package Code)

H8S/2628 F-ZTAT version Standard product HD64F2628

Masked ROM version Standard product HD6432628

H8S/2627 Masked ROM version Standard product HD6432627

QFP-100

(FP-100M)

C. Package Dimensions

The package dimension that is shown in the Renesas Technology Semiconductor Package Data

Book has priority.

NOTE)

1. DIMENSIONS"*1"AND"*2"

DO NOT INCLUDE MOLD FLASH

2. DIMENSION"*3"DOES NOT

INCLUDE TRIM OFFSET.

PRQP0100KB-AP-QFP100-14x14-0.50

MASS[Typ.]

1.2g

Reference

Symbol

Dimension in Millimeters

Min Nom Max

Previous CodeJEITA Package Code RENESAS Code

FP-100M/FP-100MV

1.0

0.10

0.5

0.12 0.17 0.22

0.17 0.22 0.27

0.00 0.12 0.25

3.05

15.8 16.0 16.2

2.70

0.20

0.15

0.4 0.5 0.6

0.08

16.216.015.8

1.0

*3p

5175

251

100

Terminal cross section

Detail F

Figure C.1 FP-100M Package Dimensions

Index

Rev. 3.00 Oct 04, 2005 page 595 of 598

REJ09B0155-0300

Index

16-Bit Timer Pulse Unit (TPU).............. 167

Buffer Operation.............................. 212

Cascaded Operation......................... 217

Free-running count operation.......... 206

Input Capture................................... 209

periodic count operation.................. 206

Phase Counting Mode ..................... 224

PWM Modes ................................... 219

Synchronous Operation................... 211

toggle output.................................... 207

Waveform Output by Compare Match

......................................................... 207

8-Bit Timers ........................................... 251

16-Bit Count Mode.......................... 267

Cascaded Connection ...................... 267

Compare-Match Count Mode.......... 267

Pulse Output.................................... 262

TCNT Incrementation Timing......... 263

Toggle output .................................. 271

A/D Converter........................................ 449

A/D Converter Activation ............... 233

A/D trigger input............................. 165

Conversi on Time............................. 457

External Trig g er............................... 459

Scan Mode....................................... 456

Single Mode .................................... 456

A ddress Map............................................. 53

Address Space .......................................... 18

Addressing Modes.................................... 39

Absolute Address .............................. 41

Immediate.......................................... 42

Memory Indirect................................ 42

Program-Counter Relative................. 42

Regi ster Indirect................................ 40

Reg ister Indire ct with Post-In crem ent41

Reg i ster Indire ct wi th Pre- Decr em en t41

Bcc......................................................27, 36

Bit Rate...................................................403

break address ......................................87, 90

break conditions........................................90

Bus Arbitration .........................................99

bus cycle ...................................................95

Bus Masters ..............................................99

Clock Pulse Generator............................491

Condition Field.........................................38

Condition-Code Register (CCR)...............22

CPU Operating Modes..............................14

A dvanced Mode.................................15

Normal Mode.....................................14

data direction register..............................127

data register.............................................127

Data Transfer Cont roll er.........................101

Activation by Software....................121

Block Transfer Mode.......................115

Chain Transfer.........................117, 123

DTC Vector Table...........................109

Normal Mode...........................113, 122

Regi ster Informa tion........................109

Repeat Mode....................................114

software activation...........................118

Software Activation.........................124

vecto r num ber for the sof tware

activation interrupt...........................107

Effective Address................................39, 43

Effective Address Extension.....................38

Exception Handling ..................................55

Interrupts............................................61

Reset Exception Handling .................57

Stack Status........................................63

Traces ................................................60

Trap Instruction .................................62

Extended Control Register (EXR) ............21

Index

Rev. 3.00 Oct 04, 2005 page 596 of 598

REJ09B0155-0300

Flash memory......................................... 467

Flash Memory

Boot Mode....................................... 478

Emulation........................................ 482

Erase/Erase-Verify .......................... 486

erasing units..................................... 472

Program/Program-Verify................. 484

programming units .......................... 472

Programming/Erasing in User Program

Mode ............................................... 480

General Registers...................................... 20

HCAN............................................... 97, 371

11 consecutive recessive bits........... 400

A rbitration field....................... 407, 41 0

buffer segm ent................................. 403

Configuration mode......................... 400

Control field .................................... 407

Data field......................................... 407

Data frame....................................... 410

DTC Interface.................................. 417

HCAN Halt Mode ........................... 415

HCAN Sleep Mode ......................... 412

mailbox............................................ 396

Message Control (MC0 to MC15)... 396

Messag e Data (MD0 to MD15 )....... 398

Message transmission cancellation.. 407

Messag e Transm issi on Meth od....... 405

Remote frame.................................. 411

remote transmission request bit....... 411

Unread message overwrite .............. 411

input pull-up MOS.................................. 127

Instruction Set........................................... 27

Arithmetic Operations Instructions ... 30

Bit Manipulation Instructions............ 34

Block Data Transfer Instructions....... 38

Branch Instructions............................ 36

Data Transfer Instr uc tions................. 29

Logic Operations Instructions ........... 32

Shift Instructions ............................... 33

System Control Instructions .............. 37

Interrupt Control Modes ...........................78

Interrupt Controller...................................65

Interrupt Exception Handling Vector Table

..................................................................74

Interrupt Mask Bit.....................................22

interrupt mask level ..................................21

interrupt priority register (IPR).................65

Interrupts

ADI..................................................459

CMIA...............................................268

CMIB...............................................268

ERS0/OVR0 ....................................416

NMI ...................................................73

OVI..................................................268

RM0.................................................416

RM1.................................................416

SLE0................................................416

SWDTEND......................................118

TCIU_1............................................232

TCIU_2............................................232

TCIU_4............................................232

TCIU_5............................................232

TCIV_0............................................232

TCIV_1............................................232

TCIV_2............................................232

TCIV_3............................................232

TCIV_4............................................232

TCIV_5............................................232

TGIA_0............................................232

TGIA_1............................................232

TGIA_2............................................232

TGIA_3............................................232

TGIA_4............................................232

TGIA_5............................................232

TGIB_0............................................232

TGIB_1............................................232

TGIB_2............................................232

TGIB_3............................................232

TGIB_4............................................232

TGIB_5............................................232

Index

Rev. 3.00 Oct 04, 2005 page 597 of 598

REJ09B0155-0300

TGIC_0............................................ 232

TGIC_3............................................ 232

TGID_0 ........................................... 232

TGID_3 ........................................... 232

WOVI.............................................. 301

MAC instruction....................................... 51

memory cycle........................................... 95

Multiply-Accumulate Register (MAC)..... 23

On-Board Programming ......................... 477

open-drain control register...................... 127

Operating Mode Selection........................ 49

Operation Field......................................... 38

PC Break Controller................................. 87

Pin Arrangement......................................... 3

PLL Circuit............................................. 497

port register............................................. 127

Program Counter (PC).............................. 21

Program/E rase Protec tion....................... 488

Programmabl e Pulse Gen erato r.............. 275

Non-Overlapping Pulse Output....... 288

output trigg er................................... 282

Programmer Mo de.................................. 489

Registers

ABACK....................383, 518, 536, 556

ADCR.......................455, 534, 554, 572

ADCSR.....................453, 534, 554, 572

ADDR.......................452, 534, 554, 572

BARA.........................88, 528, 548, 566

BARB.........................89, 528, 548, 566

BCR..........................377, 518, 536, 556

BCRA.........................89, 528, 548, 566

BCRB.........................90, 528, 548, 566

BRR..........................323, 534, 553, 571

CRA................................................. 105

CRB................................................. 106

DAR................................................. 105

DTCER.....................106, 529, 549, 567

DTVECR..................107, 529, 549, 567

EBR1........................475, 534, 554, 572

EBR2 ....................... 476, 534, 554, 572

FLMCR1.................. 473, 534, 554, 572

FLMCR2.................. 475, 534, 554, 572

GSR ......................... 375, 518, 536, 556

HCANMON............. 399, 527, 545, 565

IER.............................69, 529, 548, 566

IMR.......................... 391, 518, 536, 556

IPR............................. 68, 531, 551, 569

IRR ..........................386, 518, 536, 556

ISCR..........................70, 528, 548, 566

ISR............................. 72, 529, 548, 566

LAFMH ................... 394, 518, 537, 556

LAFML.................... 394, 518, 537, 556

LPWRCR.................493, 528, 548, 566

MBCR......................379, 518, 536, 556

MBIMR ................... 390, 518, 536, 556

MC........................... 396, 518, 537, 556

MCR........................374, 518, 536, 556

MD...........................398, 523, 541, 560

MDCR ....................... 50, 528, 548, 566

MRA................................................104

MRB................................................105

MSTPCR ................. 506, 528, 548, 566

NDER......................278, 529, 549, 567

NDR.........................280, 529, 549, 567

P1DDR ....................131, 529, 549, 567

P1DR ....................... 132, 531, 551, 569

PADDR.................... 145, 529, 549, 567

PADR.......................146, 532, 551, 569

PAODR.................... 147, 530, 550, 568

PAPCR ....................147, 529, 549, 567

PBDDR....................149, 529, 549, 567

PBDR.......................150, 532, 552, 569

PBODR....................151, 530, 550, 568

PBPCR.....................151, 529, 549, 567

PCDDR....................154, 529, 549, 567

PCDR.......................155, 532, 552, 570

PCODR....................156, 530, 550, 568

PCPCR.....................156, 530, 549, 567

PCR..........................282, 529, 549, 567

Index

Rev. 3.00 Oct 04, 2005 page 598 of 598

REJ09B0155-0300

PDDDR ....................160, 529, 549, 567

PDDR.......................161, 532, 552, 570

PDPCR.....................162, 530, 549, 567

PFDDR.....................163, 529, 549, 567

PFDR........................164, 532, 552, 570

PMR .........................283, 529, 549, 567

PODR.......................279, 529, 549, 567

PORT1......................132, 534, 554, 572

PORT4......................140, 534, 554, 572

PORT9......................144, 535, 554, 572

PORTA.....................146, 535, 555, 572

PORTB.....................150, 535, 555, 572

PORTC.....................155, 535, 555, 572

PORTD.....................161, 535, 555, 572

PORTF .....................164, 535, 555, 572

RAMER....................476, 531, 551, 569

RDR..........................308, 534, 554, 571

REC..........................392, 518, 536, 556

RFPR........................385, 518, 536, 556

RSR ................................................. 308

RSTCSR...................299, 533, 553, 571

RXPR .......................384, 518, 536, 556

SAR................................................. 105

SBYCR.....................504, 528, 548, 566

SCKCR.....................492, 528, 548, 566

SCMR.......................322, 534, 554, 571

SCR ..........................313, 534, 553, 571

SMR .........................309, 534, 553, 571

SSR...........................316, 534, 553, 571

SYSCR .......................51, 528, 548, 566

TCNT ......................203, 254, 296, 532,

533, 550, 553, 571

TCNTH............................................552

TCOR ......................254, 528, 547, 566

TCR ......................... 255, 528, 547, 566

TCSR....................... 257, 528, 547, 566

TDR......................... 308, 534, 553, 571

TEC.......................... 392, 518, 536, 556

TGR......................... 213, 530, 550, 568

TIER........................198, 530, 550, 568

TIOR........................181, 530, 550, 568

TMDR...................... 179, 530, 550, 568

TSR..........................308, 530, 550, 568

TSTR ....................... 203, 531, 551, 569

TSYR....................... 204, 531, 551, 569

TXACK ................... 382, 518, 536, 556

TXCR ......................381, 518, 536, 556

TXPR....................... 380, 518, 536, 556

UMSR......................393, 518, 537, 556

Reset .........................................................57

Serial Communication Interface.............305

A synchronous Mod e........................330

bit rate..............................................323

Break................................................370

framing error....................................337

Mark State........................................370

overrun error....................................337

parity error.......................................337

stack pointer (SP)......................................20

Time Quanta (TQ) ..................................404

Trace Bit ...................................................21

TRAPA instruction.............................42, 62

Watchdog Timer.....................................295

Interval Timer Mode........................300

Renesas 16-Bit Single-Chip Microcomputer

Hardware Manual

H8S/2628 Group

Publication Date: 1st Edition, September 2002

Rev.3.00, October 04, 2005

Published by: Sales Strategic Planning Div.

Renesas Technol ogy Corp.

Edited by: Customer Support Department

G lobal S trategic Com municatio n Di v.

Renesas Soluti ons Corp.

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.

Renesas Technology America, Inc.

450 Holger Way, San Jose, CA 95134-1368, U.S.A

Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501

Renesas Technology Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom

Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900

Renesas Technology Hong Kong Ltd.

7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong

Tel: <852> 2265-6688, Fax: <852> 2730-6071

Renesas Technology Taiwan Co., Ltd.

10th Floor, No.99, Fushing North Road, Taipei, Taiwan

Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999

Renesas Technology (Shanghai) Co., Ltd.

Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China

Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952

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1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

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Tel: <82> 2-796-3115, Fax: <82> 2-796-2145

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Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: <603> 7955-9390, Fax: <603> 7955-9510

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Hardware Manual