1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5710/3
AUGUST 2001
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
1,024 x 1,024
IDT72V70810
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc.
FUNCTIONAL BLOCK DIAGRAM
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
ODE
F0i
V
CC
CS
DS/
RD R/W/
WR A0-A7
GND
CCO
DTA D8-D15/
AD0-AD7
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
AS/
ALE IMCLK FE/
HCLK WFPS
RESET
5710 drw01
Receive
Serial Data
Streams
Output
MUX
Loopback
Data Memory
Internal
Registers
Microprocessor Interface
Timing Unit
Connection
Memory
Transmit
Serial Data
Streams
FEATURES:
•1,024 x 1,024 channel non-blocking switching at 8.192 Mb/s
•Per-channel variable or constant throughput delay
•Automatic identification of ST-BUS®/GCI interfaces
•Accepts 8 Serial Data Streams of 8.192 Mb/s
•Automatic frame offset delay measurement
•Per-stream frame delay offset programming
•Per-channel high impedance output control
•Per-channel Processor Mode
•Control interface compatible to Intel/Motorola CPUs
•Connection memory block programming
•Available in 64-pin Thin Plastic Quad Flatpack (TQFP) and
64-pin Small Thin Quad Flatpack (STQFP)
•3.3V Power Supply
•Operating Temperature Range -40°°
°°
°C to +85°°
°°
°C
DESCRIPTION:
The IDT72V70810 is a non-blocking digital switch that has a capacity of
1,024 x 1,024 channels at a serial bit rate of 8.192 Mb/s. Some of the main
features are: programmable stream and channel control, Processor Mode,
input offset delay and high-impedance output control.
Per-stream input delay control is provided for managing large multi-chip
switches that transport both voice channel and concatenated data channels. In
addition, input streams can be individually calibrated for input frame offset.
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COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
PIN CONFIGURATION
TQFP 0.80mm pitch, 14mm x 14mm (PN64-1, order code: PF)
STQFP 0.50 pitch, 10mm x 10mm (PP64-1, order code: TF)
TOP VIEW
NOTES:
1. DNC - Do Not Connect.
2. All I/O pins are 5V tolerant.
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
GND
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
GND
CCO
DTA
D15
D14
ODE
D13
D12
D11
D10
D9
D8
GND
VCC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
F0i
FE/HCLK
GND
CLK
VCC
DNC
DNC
RESET
WFPS
A0
A1
A2
A3
A4
A5
A6
A7
DS/RD
CS
AS/ALE
IM
GND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
5710 drw02
R/W/RW
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
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COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
PIN DESCRIPTION
SYMBOL NAME I/O DESCRIPTION
GND Ground. Ground Rail.
Vcc Vcc +3.3 Volt Power Supply.
TX0-7 TX Output 0 to 7 O Serial data output stream. These streams have a data rate of 8.192 Mb/s.
(Three-state Outputs)
RX0-7 RX Input 0 to 7 I Serial data input stream. These streams have a data rate of 8.192 Mb/s.
F0i Frame Pulse I When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted
according to ST-BUS® and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame
pulse which conforms to WFPS formats.
FE/HCLK Frame Evaluation/ I When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK
HCLK Clock (4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode.
C LK Clock I Serial clock for shifting data in/out on the serial streams (RX/TX 0-7). This input accepts a 16.384 MHz clock.
RESET Device Reset I This input (active LOW) puts the IDT72V70810 in its reset state that clears the device internal counters, registers
(Schmitt Trigger Input) and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a power
up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the
RESET pin must be held LOW for a minimum of 100ns to reset the device.
WFPS Wide Frame I When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in
Pulse Select ST-BUS®/GCI mode.
A0-7 Address 0-7 I When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
DS/RD Data Strobe/Read I For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with CS
to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This
active LOW input works in conjunction with CS to enable the read and write operations. For Intel multiplexed bus
operation, this input is RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
R/W / WR Read/Write / Write I In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls
the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus
operation, this input is WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs.
CS Chip Select I Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70810.
AS/ALE Address Strobe or I This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed
Latch Enable bus operation, connect this pin to ground.
I M CPU Interface Mode I When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
port is in non-multiplexed mode.
AD0-7 Address/Data Bus 0 to 7 I/O These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor port.
D8-15 Data Bus 8-15 I/O These pins are the eight most significant data bits of the microprocessor port.
DTA Data Transfer O This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
Acknowledgment drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
C CO Control Output O This is a 16.384 Mb/s output containing 2.048 bits per frame respectively. The level of each bit is determined
by the CCO bit in the connection memory. See External Drive Control Section.
ODE Output Drive Enable I This is the output enable control for the TX0 to TX7 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-7 are in a high-impedance state. If this input is HIGH, the TX0-7
output drivers are enabled. However, each channel may still be put into a high-impedance state by using
the per channel control bit in the connection memory.
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COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
FUNCTIONAL DESCRIPTION
The IDT72V70810 is capable of switching up to 1,024 x 1,024, 64 Kbit/s
PCM or N x 64 Kbit/s channel data. The device maintains frame integrity in data
applications and minimum throughput delay for voice applications on a per
channel basis.
The serial input streams of the IDT72V70810 have a bit rate of 8.192 Mb/s
and are arranged in 125ms wide frames, which contain 128 channels. The data
rates on input and output streams are identical.
In Processor Mode, the microprocessor can access input and output time-
slots on a per channel basis allowing for transfer of control and status information.
The IDT72V70810 automatically identifies the polarity of the frame synchroni-
zation input signal and configures the serial streams to either ST-BUS® or GCI
formats.
With the variety of different microprocessor interfaces, IDT72V70810 has
provided an Input Mode pin (IM) to help integrate the device into different
microprocessor based environments: Non-multiplexed or Multiplexed. These
interfaces provide compatibility with multiplexed and Motorola non-multiplexed
buses. The device can also resolve different control signals eliminating the use
of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE).
The frame offset calibration function allows users to measure the frame offset
delay using a frame evaluation pin (FE). The input offset delay can be
programmed for individual streams using internal frame input offset registers, see
Table 8.
The internal loopback allows the TX output data to be looped around to the
RX inputs for diagnostic purposes.
A functional Block Diagram of the IDT72V70810 is shown in Figure 1.
DATA AND CONNECTION MEMORY
The received serial data is converted to parallel format by internal serial-
to-parallel converters and stored sequentially in the data memory. The 8 KHz
input frame pulse (F0i) is used to generate channel and frame boundaries of
the input serial data. Depending on the interface mode select (IMS) register,
the usable data memory may be as large as 1,024 bytes.
Data to be output on the serial streams (TX0-7) may come from either the
data memory or connection memory. For data output from data memory
(connection mode), addresses in the connection memory are used. For data
to be output from connection memory, the connection memory control bits must
set the particular TX output in Processor Mode. One time-slot before the data
is to be output, data from either connection memory or data memory is read
internally. This allows enough time for memory access and parallel-to-serial
conversion.
CONNECTION AND PROCESSOR MODES
In the Connection Mode, the addresses of the input source data for all output
channels are stored in the connection memory. The connection memory is
mapped in such a way that each location corresponds to an output channel on
the output streams. For details on the use of the source address data (CAB and
SAB bits), see Table 10. Once the source address bits are programmed by the
microprocessor, the contents of the data memory at the selected address are
transferred to the parallel-to-serial converters and then onto a TX output stream.
By having the each location in the connection memory specify an input
channel, multiple outputs can specify the same input address. This can be a
powerful tool used for broadcasting data.
In Processor Mode, the microprocessor writes data to the connection
memory. Each location in the connection memory corresponds to a particular
output stream and channel number and is transferred directly to the parallel-to-
serial converter one time-slot before it is to be output. This data will be output
on the TX streams in every frame until the data is changed by the microprocessor.
As the IDT72V70810 can be used in a wide variety of applications, the device
also has memory locations to control the outputs based on operating mode.
Specifically, the IDT72V70810 provides five per-channel control bits for the
following functions: processor or connection mode, constant or variable delay,
enables/three-state the TX output drivers and enables/disable the loopback
function. In addition, one of these bits allows the user to control the CCO output.
If an output channel is set to a high-impedance state through the connection
memory, the TX output will be in a high-impedance state for the duration of that
channel. In addition to the per-channel control, all channels on the ST-BUS®
outputs can be placed in a high impedance state by either pulling the ODE input
pin low or programming the Output Stand-By (OSB) bit in the interface mode
selection register. This action overrides the per-channel programming in the
connection memory bits.
The connection memory data can be accessed via the microprocessor
interface. The addressing of the devices internal registers, data and connection
memories is performed through the address input pins and the Memory Select
(MS) bit of the control register. For details on device addressing, see Software
Control and Control Register bits description (Table 3 and 5).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate. For serial
data rates of 8.192 Mb/s, the master clock (CLK) must be 16.384 MHz. The input
and output stream data rates will always be identical.
The IDT72V70810 provides two different interface timing modes ST-BUS®/
GCI and WFP (wide frame pulse). If the WFPS pin is high, the IDT72V70810
is in the wide frame pulse (WFP) frame alignment mode.
In ST-BUS®/GCI mode, the input 8 KHz frame pulse can be in either
ST-BUS® or GCI format. The IDT72V70810 automatically detects the presence
of an input frame pulse and identifies it as either ST-BUS® or GCI. In ST-BUS®
format, every second falling edge of the master clock marks a bit boundary and
the data is clocked in on the rising edge of CLK, three quarters of the way into
the bit cell, see Figure 7. In GCI format, every second rising edge of the master
clock marks the bit boundary and data is clocked in on the falling edge of CLK
at three quarters of the way into the bit cell, see Figure 8.
WIDE FRAME PULSE (WFP) FRAME ALIGNMENT TIMING
When the device is in WFP frame alignment mode, the CLK input must be
at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 KHz frame pulse
is in ST-BUS® format. The timing relationship between CLK, HCLK and the frame
pulse is shown in Figure 9.
When WFPS pin is high, the frame alignment evaluation feature is disabled.
However, the frame input offset registers may still be programmed to compensate
for the varying frame delays on the serial input streams.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streams to be offset with respect to the output stream channel alignment (i.e. F0i).
Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implemented in large centralized and distributed switching systems. Because
data is often delayed, this feature is useful in compensating for the skew between
clocks.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR). The maximum allowable skew is +4.5 master
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COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
clock (CLK) periods forward with resolution of ½ clock period. The output frame
offset cannot be offset or adjusted. See Figure 5, Table 8 and 9 for delay offset
programming.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V70810 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse F0i.
A measurement cycle is started by setting the start frame evaluation (SFE)
bit low for at least one frame. When the SFE bit in the IMS register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
to 11 of the FAR register. The SFE bit must be set to zero before a new
measurement cycle started.
In ST-BUS® mode, the falling edge of the frame measurement signal (FE)
is evaluated against the falling edge of the ST-BUS® frame pulse. In GCI mode,
the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.
See Table 7 & Figure 4 for the description of the frame alignment register.
This feature is not available when the WFP Frame Alignment mode is
enabled (i.e., when the WFPS pin is connected to VCC).
MEMORY BLOCK PROGRAMMING
The IDT72V70810 provides users with the capability of initializing the entire
connection memory block in two frames. To set bits 11 to 15 of every connection
memory location, first program the desired pattern in bits 5 to 9 of the IMS register.
The block programming mode is enabled by setting the memory block
program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into the bits 11 to 15 of every connection memory location. The
other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the
memory block programming is complete, the device resets the BPE bit to zero.
LOOPBACK CONTROL
The loopback control (LPBK) bit of each connection memory location allows
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data from TX n channel m routes to
the RX n channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.
DELAY THROUGH THE IDT72V70810
The switching of information from the input serial streams to the output serial
streams results in a throughput delay. The device can be programmed to
perform time-slot interchange functions with different throughput delay capabili-
ties on the per-channel basis. For voice applications, variable throughput delay
is best as it ensures minimum delay between input and output data. In wideband
data applications, constant throughput delay is best as the frame integrity of the
information is maintained through the switch.
The delay through the device varies according to the type of throughput
delay selected in the V/C bit of the connection memory.
VARIABLE DELAY MODE (V/C BIT = 0)
In this mode, the delay is dependent only on the combination of source and
destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT72V70810 is three time-slots. If the input
channel data is switched to the same output channel (channel n, frame p), it will
be output in the following frame (channel n, frame p+1). The same is true if input
channel n is switched to output channel n+1 or n+2. If the input channel n is
switched to output channel n+3, n+4,..., the new output data will appear in the
same frame. Table 1 shows the possible delays for the IDT72V70810 in the
variable delay mode.
CONSTANT DELAY MODE (V/C BIT = 1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V70810, the minimum throughput delay achievable in the constant
delay mode will be one frame. See Table 2 for possible delays in constant delay
mode.
MICROPROCESSOR INTERFACE
The IDT72V70810 provides a parallel microprocessor interface for multi-
plexed or non-multiplexed bus structures. This interface is compatible with
Motorola non-multiplexed and multiplexed buses.
If the IM pin is low a Motorola non-multiplexed bus should be connected to
the device. If the IM pin is high, the device monitors the AS/ALE and DS/RD to
determine what mode the IDT72V70810 should operate in.
If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed
timing is selected. If DS/RD is high at the rising edge of AS/ALE, then the mode
2 multiplexed bus timing is selected.
For multiplexed operation, the required signals are the 8-bit data and
address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch
enable (AS/ ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR),
Chip select (CS) and Data transfer acknowledge (DTA). See Figure 12 and
Figure 13 for multiplexed parallel microport timing.
For the Motorola non-multiplexed bus, the required signals are the 16-bit
data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines
(CS, DS, R/W and DTA). See Figure 14 and 15 for Motorola non-multiplexed
microport timing.
The IDT72V70810 microport provides access to the internal registers,
connection and data memories. All locations provide read/write access except
for the data memory and the frame alignment register which are read only.
MEMORY MAPPING
The address bus on the microprocessor interface selects the internal
registers and memories of the IDT72V70810.
If the A7 address input is low, then A6 through A0 are used to address the
interface mode selection (IMS), control (CR), frame alignment (FAR) and frame
input offset (FOR) registers (Table 4). If the A7 is high, then A6 through A0 are
used to select 128 locations corresponding to data rate of the ST-BUS®. The
address input lines and the stream address bits (STA) of the control register allow
access to the entire data and connection memories. The control and IMS
registers together control all the major functions of the device, see Figure 3.
As explained in the Serial Data Interface Timing and Switching Configura-
tions sections, after system power-up, the IMS register should be programmed
immediately to establish the desired switching configuration.
The data in the control register consists of the memory block programming
bit (MBP), the memory select bit (MS) and the stream address bits (STA). As
explained in the Memory Block Programming section, the MBP bit allows the
entire connection memory block to be programmed. The memory select bit is
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COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
used to designate the connection memory or the data Memory. The stream
address bits select internal memory subsections corresponding to input or output
serial streams.
The data in the IMS register consists of block programming bits (BPD0-
BPD4), block programming enable bit (BPE), output stand by bit (OSB) and start
frame evaluation bit (SFE). The block programming and the block programming
enable bits allows users to program the entire connection memory (see Memory
Block Programming section). If the ODE pin is low, the OSB bit enables (if high)
or disables (if low) all ST-BUS® output drivers. If the ODE pin is high, the contents
of the OSB bit is ignored and all TX output drivers are enabled.
CONNECTION MEMORY CONTROL
The CCO pin is a 16.384 Mb/s output, which carries 2,048 bits. The contents
of the CCO bit of each connection memory location are output on the CCO pin
once every frame. The contents of the CCO bits of the connection memory are
transmitted sequentially on to the CCO pin (2 bit cells for each bit in connection
memory) and are synchronous with the data rates on the other serial streams.
The CCO bit is output one channel before the corresponding channel on the
serial streams.
If the ODE pin or the OSB bit is high, the OE bit of each connection memory
location controls the output drivers-enables (if high) or disables (if low). See
Table 4 for detail.
The processor channel (PC) bit of the connection memory selects between
Processor Mode and Connection Mode. If high, the contents of the connection
memory are output on the TX streams. If low, the stream address bit (SAB) and
the channel address bit (CAB) of the connection memory defines the source
information (stream and channel) of the time-slot that will be switched to the output
from data memory.
The V/C (Variable/Constant Delay) bit in each connection memory location
allows the per-channel selection between variable and constant throughput
delay modes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., RX n channel m data comes from the
TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.
INITIALIZATION OF THE IDT72V70810
After power up, the state of the connection memory is unknown. As such,
the outputs should be put in high impedance by holding the ODE low. While the
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.
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COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
Connection Memory
Channel 0 Channel 1 Channel 2 Channel 127
Channel 0 Channel 1 Channel 2 Channel 127
Channel 0 Channel 1 Channel 2 Channel 127
Channel 0 Channel 1 Channel 2 Channel 127
Channel 0 Channel 1 Channel 2 Channel 127
Channel 0 Channel 1 Channel 2 Channel 127
Channel 0 Channel 1 Channel 2 Channel 127
Channel 0 Channel 1 Channel 2 Channel 127
10000001 10000010
Data Memory
000 0
0011
010 2
0 1 1 3
100 4
101 5
1 1 0 6
1 1 1 7
Stream
Control Register CR
b
7
5710 drw03
10000000
The Control Register is only accessed when A7-A0
are all zeroed. When A7 =1, up to 128 bytes are
randomly accessable via A0-A6 at any one instant.
Of which stream these bytes (channels) are accessed
is determined by the state of CRb2 -CRb0.
CR
b
6CR
b
5CR
b
4CR
b
3CR
b
2CR
b
1CR
b
0
CR
b
2CR
b
1CR
b
0
0
1
CR
b
4
11111111 External Address Bits A7-A0
Figure 3. Addressing Internal Memories
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COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
TABLE 4 OUTPUT HIGH IMPEDANCE CONTROL
TABLE 3 INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
TABLE 2 CONSTANT THROUGHPUT
DELAY VALUE
TABLE 1 VARIABLE THROUGHPUT
DELAY VALUE
NOTE:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
Delay for Variable Throughput Delay Mode
Input Rate (m – output channel number)
(n – input channel number)
m < n m = n, n+1, n+2 m > n+2
8.192 Mb/s 128 – (n-m) time-slots m-n + 128 time-slots m-n time-slots
Delay for Constant Throughput Delay Mode
Input Rate (m – output channel number)
(n – input channel number)
8.192 Mb/s 128 + (128 – n) + m time-slots
A7(1) A6 A5 A4 A3 A2 A1 A0 Location
00000000Control Register, CR
00000001Interface Mode Selection Register, IMS
00000010Frame Alignment Register, FAR
00000011Frame Input Offset Register 0, FOR0
00000100Frame Input Offset Register 1, FOR1
10000000Ch0
10000001Ch1
100......
10011110Ch30
10011111Ch31
10100000Ch32
10100001Ch33
101......
10111110Ch62
10111111Ch63
11000000Ch64
11000001Ch65
110......
11111110Ch126
11111111Ch127
OE bit in Connection ODE pin OSB bit in IMS TX Output Driver
Memory Register Status
0 Don’t Care Don’t Care Per Channel
High-Impedance
1 0 0 High-Impedance
1 0 1 Enable
1 1 1 Enable
1 1 0 Enable
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COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
TABLE 5 CONTROL REGISTER (CR) BITS
TABLE 6 INTERFACE MODE SELECTION (IMS) REGISTER BITS
Read/Write Address: 01H,
Reset Value: 0000H.
Bit Name Description
15-10 Unused Must be zero for normal operation.
9-5 BPD4-0 These bits carry the value to be loaded into the connection memory block whenever the memory block
(Block Programming Data) programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is
set to 1, the contents of the bits BPD4-0 are loaded into bit 15 and 11 of the connection memory. Bit 10 to
bit 0 of the connection memory are set to 0.
4 BPE A zero to one transition of this bit enables the memory block programming function. The BPE and
(Begin Block Programming BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set
Enable) HIGH, the device requires two frames to complete the block programming. After the programming function
has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE
or MBP can be set to 0 to abort to ensure proper operation. When BPE = 1, the other bit in the IMS register
must not be changed for two frames to ensure proper operation.
3 O SB When ODE = 0 and OSB = 0, the output drivers of TX0 to TX7 are in high impedance mode. When
(Output Stand By) ODE= 0 and OSB = 1, the output driver of TX0 to TX7 function normally. When ODE = 1, TX0 to TX7
output drivers function normally.
2 SFE A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR
(Start Frame Evaluation) register changes from zero to one, the evaluation procedure stops. To start another fame evaluation
cycle, set this bit to zero for at least one frame.
1-0 Unused For normal operation, bit 1 = 1 and bit 0 = 0.
1514131211109876543210
000000BPD4 BPD3 BPD2 BPD1 BPD0 BPE OSB SFE 1 0
Read/Write Address: 00H,
Reset Value: 0000H.
1514131211109876543210
0000000000MBPMS0STA2 STA1 STA0
Bit Name Description
15-6 Unused Must be zero for normal operation.
5 MBP When 1, the connection memory block programming feature is ready for the programming of Connection
(Memory Block Program) Memory high bits, bit 11 to bit 15. When 0, this feature is disabled.
4 MS When 0, connection memory is selected for read or write operations. When 1, the data memory is selected
(Memory Select) for read operations and connection memory is selected for write operations.
(No microprocessor write operation is allowed for the data memory.)
3 Unused Must be zero for normal operation.
2-0 STA2-0 The binary value expressed by these bits refers to the input or output data stream, which corresponds
(Stream Address Bits) to the subsection of memory made accessible for subsequent operations. (STA2 = MSB, STA0 = LSB)
10
COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
0123 45678 910111213141516
ST-BUS
Frame
CLK
Offset Value
FE Input
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GCI Frame
CLK
Offset Value
FE Input
(FD[10:0] = 06
H
)
(FD11 = 0, sample at CLK LOW phase)
(FD[10:0] = 09
H
)
(FD11 = 1, sample at CLK HIGH phase)
5710 drw04
TABLE 7 FRAME ALIGNMENT REGISTER (FAR) BITS
Figure 4. Example for Frame Alignment Measurement
Bit Name Description
15-13 Unused Must be zero for normal operation.
12 CFE When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment
(Complete Frame Evaluation) offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0.
11 FD11 The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1)
(Frame Delay Bit 11) or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.
10-0 FD10-0 The binary value expressed in these bits refers to the measured input offset value. These bits are rest to
(Frame Delay Bits) zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
Read/Write Address: 02H,
Reset Value: 0000H.
1514131211109876543210
0 0 0 CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
11
COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
TABLE 8 FRAME INPUT OFFSET REGISTER (FOR) BITS
NOTE:
1. n denotes an input stream number from 0 to 7.
Name(1) Description
OFn2, OFn1, OFn0 These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to
(Offset Bits 2, 1 & 0) start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse
input signal is applied to the F0i input of the device. See Figure 5.
DLEn
(Data Latch Edge) ST-BUS® mode: DLEn = 0, if clock rising edge is at the ¾ point of the bit cell.
DLEn = 1, if when clock falling edge is at the ¾ of the bit cell.
GCI mode: DLEn = 0, if clock falling edge is at the ¾ point of the bit cell.
DLEn = 1, if when clock rising edge is at the ¾ of the bit cell.
Read/Write Address: 03H for FOR0 register,
04H for FOR1 register,
Reset Value: 0000H for all FOR registers.
1514131211109876543210
OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0
FOR0 Register
1514131211109876543210
OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4
FOR1 Register
12
COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
ST-BUS
F0i
RX Stream
5710 drw05
Bit 7
Bit 7
CLK
Bit 7
Bit 7
denotes the 3/4 point of the bit cell
offset = 0, DLE = 0
offset = 1, DLE = 0
offset = 0, DLE = 1
offset = 1, DLE = 1
GCI F0i
Bit 0
Bit 0
CLK
Bit 0
Bit 0
denotes the 3/4 point of the bit cell
offset = 0, DLE = 0
offset = 1, DLE = 0
offset = 0, DLE = 1
offset = 1, DLE = 1
RX Stream
RX Stream
RX Stream
RX Stream
RX Stream
RX Stream
RX Stream
TABLE 9 OFFSET BITS (OFN2, OFN1, OFN0, DLEN) & FRAME DELAY BITS
(FD11, FD2-0)
Figure 5. Examples for Input Offset Delay Timing
Measurement Result from Corresponding
Input Stream Frame Delay Bits Offset Bits
Offset FD11 FD2 FD1 FD0 OFn2 OFn1 OFn0 DLEn
No clock period shift (Default) 1000000 0
+ 0.5 clock period shift 0000000 1
+ 1.0 clock period shift 1001001 0
+ 1.5 clock period shift 0001001 1
+ 2.0 clock period shift 1010010 0
+ 2.5 clock period shift 0010010 1
+ 3.0 clock period shift 1011011 0
+ 3.5 clock period shift 0011011 1
+ 4.0 clock period shift 1100100 0
+ 4.5 clock period shift 0100100 1
13
COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
TABLE 10 CONNECTION MEMORY BITS
NOTE:
1 . If bit 13 (PC) of the corresponding connection memory location is 1 (device in processor mode), then these entire 8 bits (SAB0, CAB6 - CAB0) are output on the output channel
and stream associated with this location.
Bit Name Description
15 LPBK When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback
(Per Channel Loopback) operations, set the delay offset register bits OFn[2:0] to zero for the streams which are in the loopback mode.
14 V/C This bit is used to select between the variable (LOW) and constant delay (HIGH) mode on a
(Variable/Constant per-channel basis.
Throughput Delay)
13 PC When 1, the contents of the connection memory are output on the corresponding output channel and stream.
(Processor Channel) Only the lower byte (bit 7 – bit 0) will be output to the TX output pins. When 0, the contents of the connection
memory are the data memory address of the switched input channel and stream.
12 CCO This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first.
(Control Channel Output)
11 OE This bit enables the TX output drivers on a per-channel basis. When 1, the output driver functions
(Output Enable) normally. When 0, the output driver is in a high-impedance state.
10 Unused Must be zero for normal operation.
9,8,7(1) SAB2-0 The binary value is the number of the data stream for the source of the connection.
(Source Stream Address Bits)
6-0(1) CAB6-0 The binary value is the number of the channel for the source of the connection.
(Source Channel Address Bits)
1514131211109876543210
LPBK V/C PC CCO OE 0 SAB2 SAB1 SAB0 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0
14
COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
RECOMMENDED DC OPERATING
CONDITIONS
DC ELECTRICAL CHARACTERISTICS
NOTE:
1. Voltages are with respect to ground unless other wise stated.
NOTE:
1. Outputs Unloaded.
Test Point
Output
Pin
C
L
GND
S
1
R
L
VCC
GND
5710 drw06
S
2
Symbol Parameter Min. Typ. Max. Units
VCC Positive Supply 3.0 3.6 V
VIH Input HIGH Voltage 2.0 Vcc V
VIL Input LOW Voltage GND 0.8 V
TOP Operating Temperature -40 +85 °C
Commercial
Symbol Characteristics Min. Typ. Max. Units
ICC(1) Supply Current 30 45 mA
IIL Input Leakage (input pins) 15 µA
IBL Input Leakage (I/O pins) 50 µA
CIInput Pin Capacitance 10 pF
IOZ High-impedance Leakage 5µA
VOH Output HIGH Voltage 2.4 V
VOL Output LOW Voltage 0.4 V
COOutput Pin Capacitance 10 pF
Figure 6. Output Load
S1 is open circuit except when testing output
levels or high impedance states.
S2 is switched to VCC or GND when testing
output levels or high impedance states.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage -0.3 5.0 V
Vi Voltage on Digital Inputs GND -0.3 5.5 V
IOCurrent at Digital Outputs 20 mA
TSStorage Temperature -65 +125 °C
PDPackage Power Dissapation 1W
NOTE:
1. Exceeding these values may cause permanent damage. Functional operation under
these conditions is not implied.
ABSOLUTE MAXIMUM RATINGS(1)
15
COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLK
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
Symbol Characteristics Min. Typ. Max. Units
tFPW Frame Pulse Width (ST-BUS®, GCI) Bit rate = 8.192 Mb/s 26 80 ns
tFPS Frame Pulse Setup time before CLK falling (ST-BUS® or GCI) 5 ns
tFPH Frame Pulse Hold Time from CLK falling (ST-BUS® or GCI) 10 ns
tCP CLK Period Bit rate = 8.192 Mb/s 55 70 ns
tCH CLK Pulse Width HIGH Bit rate = 8.192 Mb/s 20 40 ns
tCL CLK Pulse Width LOW Bit rate = 8.192 Mb/s 20 40 ns
tr, tfClock Rise/Fall Time 10 ns
tHFPW Wide Frame Pulse Width Bit rate = 8.192 Mb/s 1 95 295 ns
tHFPS Frame Pulse Setup Time before HCLK falling 5 150 ns
tHFPH Frame Pulse Hold Time from HCLK falling 1 0 150 ns
tHCP HCLK (4.096 MHz) Period Bit rate = 8.192 Mb/s 1 90 300 ns
tHCH HCLK (4.096 MHz) Pulse Width HIGH Bit rate = 8.192 Mb/s 85 150 ns
tHCL HCLK (4.096 MHz) Pulse Width LOW Bit rate = 8.192 Mb/s 85 150 ns
tHr, tHf HCLK Rise/Fall Time 10 ns
tDIF Delay between falling edge of HCLK and falling edge of CLK -10 10 ns
Symbol Characteristics Min. Typ. Max. Unit Test Conditions
tSIS RX Setup Time 0 ns
tSIH RX Hold Time 1 0 ns
tSOD TX Delay – Active to Active 30 ns CL = 30pF
40 ns CL = 200pF
tDZ TX Delay – Active to High-Z 32 ns RL = 1KΩ, CL = 200pF
tZD TX Delay – High-Z to Active 32 ns RL = 1KΩ, CL = 200pF
tODE Output Driver Enable (ODE) Delay 32 ns RL = 1KΩ, CL = 200pF
tXCD CCO Output Delay 30 ns CL = 30pF
40 ns CL = 200pF
AC ELECTRICAL CHARACTERISTICS - SERIAL STREAMS (1)
16
COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
Bit 1, Channel 0Bit 0, Channel 0
Bit 7, Last Ch
(1)
Bit 2, Channel 0
Bit 1, Channel 0Bit 0, Channel 0
Bit 7, Last Ch
(1)
Bit 2, Channel 0
tFPW
tFPH tCH tCL tftr
tFPS
tSOD
tSIS tSIH
F0i
CLK
TX
RX
tCP
5710 drw08
NOTE:
1. last channel = ch 127. Figure 8. GCI Timing when WFPS pin = 0
t
FPW
t
FPH
t
CH
t
CL
t
f
t
r
t
FPS
t
SOD
t
SIS
t
SIH
F0i
CLK
TX
RX
t
CP
5710 drw07
Bit 6, Channel 0Bit 7, Channel 0
Bit 0, Last Ch
(1) Bit 5, Channel 0
Bit 6, Channel 0Bit 7, Channel 0
Bit 0, Last Ch(1) Bit 5, Channel 0
NOTE:
1. last channel = ch 127. Figure 7. ST-BUS® Timing when WFPS pin = 0.
17
COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
tXCD
tZD
CLK
(ST-BUS
or
WFPS mode)
CLK
(GCI mode)
CCO
5710 drw10
TX
TX
VALID DATA
VALID DATA
tDZ
ODE
TX
VALID DATA
5710 drw11
t
ODE
t
ODE
Figure 10. Serial Output and External Control Figure 11. Output Driver Enable (ODE)
t
HFPH
t
DIF
F0i
TX
RX
5710 drw09
Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0 Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0
Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0 Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0
t
HFPS
t
HFPW
CLK
16.384 MHz
HCLK
4.096 MHz
t
HCH
t
HCP
t
CP
t
CH
t
CL
t
r
t
SOD
t
f
t
SIS
t
SIH
t
HCL
t
Hf
t
Hr
Figure 9. WFP Bus Timing for High Speed Serial Interface (8.192 Mb/s), when WFPS pin = 1
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
18
COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
tALW
ADDRESS DATA
tADS tADH
ALE
5710 drw12
tRW
tWW
tCSRW
tALRD
tCSR
tCSW tDHW
tDHR
tAKH
tDDR
tDSW
tSWDtALWR tAKD
AD0-AD7
D8-D15
CS
RD
WR
DTA
Figure 12. Multiplexed Bus Timing (Intel Mode)
AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (INTEL)
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
Symbol Parameter Min. Typ. Max. Units Test Conditions
tALW ALE Pulse Width 2 0 n s
tADS Address Setup from ALE falling 3 ns
tADH Address Hold from ALE falling 3 ns
tALRD RD Active after ALE falling 3 ns
tDDR Data Setup from DTA LOW on Read 5 ns CL = 150pF
tCSRW CS Hold after RD/WR 5ns
tRW RD Pulse Width (Fast Read) 4 5 ns
tCSR CS Setup from RD 0ns
tDHR(1) Data Hold after RD 10 20 ns CL = 150pF, RL = 1K
tWW WR Pulse Width (Fast Write) 45 ns
tALWR WR Delay after ALE falling 3 ns
tCSW CS Setup from WR 0ns
tDSW Data Setup from WR (Fast Write) 20 ns
tSWD Valid Data Delay on Write (Slow Write) 1 22 ns
tDHW Data Hold after WR Inactive 5 ns
tAKD Acknowledgment Delay:
Reading/Writing Registers 43/43 ns CL = 150pF
Reading/Writing Memory 220/210 ns CL = 150pF
tAKH (1) Acknowledgment Hold Time 22 ns CL = 150pF, RL = 1K
19
COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
DS
5710 drw13
ADDRESS
t
CSS
t
DSH
t
ASW
t
CSH
t
DDR
t
ADS
t
ADH
AD0-AD7
D8-D15
WR
CS
DTA
DATA
ADDRESS DATA
t
RWS
t
DWS
t
SWD
t
DHW
t
AKD
AD0-AD7
D8-D15
RD
R/W
AS
t
RWH
t
DHR
t
AKH
AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (MOTOROLA)
Figure 13. Multiplexed Bus Timing (Motorola Mode)
Symbol Parameter Min. Typ. Max. Units Test Conditions
tASW ALE Pulse Width 2 0 ns
tADS Address Setup from AS falling 3 ns
tADH Address Hold from AS falling 3 ns
tDDR Data Setup from DTA LOW on Read 5 ns CL = 150pF
tCSH CS Hold after DS falling 0 ns
tCSS CS Setup from DS rising 0 ns
tDHW Data Hold after Write 5 ns
tDWS Data Setup from DS – Write (Fast Write) 2 0 ns
tSWD Valid Data Delay on Write (Slow Write) 1 22 ns
tRWS R/W Setup from DS Rising 6 0 n s
tRWH R/W Hold from DS Rising 5 ns
tDHR(1) Data Hold after Read 10 20 ns CL = 150pF, RL = 1K
tDSH DS Delay after AS falling 1 0 ns
tAKD Acknowledgment Delay:
Reading/Writing Registers 43/43 ns CL = 150pF
Reading/Writing Memory 220/210 ns CL = 150pF
tAKH(1) Acknowledgment Hold Time 22 ns CL = 150pF, RL = 1K
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
20
COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
DS
CS
VALID WRITE ADDRESS
A0-A7
tCSS tCSH
R/W
tRWS tRWH
tADS tADH
VALID WRITE
DATA
AD0-AD7/
D8-D15
tDSW tDHW
DTA
tAKD tAKH
tCSS tCSH
tRWS tRWH
VALID READ ADDRESS
tADS tADH
VALID READ DATA
tDDR
tDHR
tAKD tAKH
5710 drw14
Figure 14. Motorola Non-Multiplexed Asyncronous Bus Timing
AC ELECTRICAL CHARACTERISTICS-MOTOROLA NON-MULTIPLEXED BUS MODE
Symbol Parameter Min. Typ. Max. Units Test Conditions
tCSS CS Setup from DS falling 0 ns
tRWS R/W Setup from DS falling 1 0 ns
tADS Address Setup from DS falling 2 ns
tCSH CS Hold after DS rising 0 n s
tRWH R/W Hold after DS Rising 2 n s
tADH Address Hold after DS Rising 2 n s
tDDR Data Setup from DTA LOW on Read 2 ns CL = 150pF
tDHR Data Hold on Read 1 0 2 0 ns CL = 150pF, RL = 1K
tDSW Data Setup on Write (Fast Write) 5 ns
tSWD Valid Data Delay on Write (Slow Write) 1 22 ns
tDHW Data Hold on Write 5 ns
tAKD Acknowledgment Delay:
Reading/Writing Registers 43/43 ns CL = 150pF
Reading/Writing Memory 220/210 ns CL = 150pF
tAKH(1) Acknowledgment Hold Time 22 ns CL = 150pF, RL = 1K
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
21
COMMERCIAL TEMPERATURE RANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
5710 drw15
AD0-AD7/
D8-D15
CS
DTA
VALID WRITE
ADDRESS
R/W
A0-A7
DS
CLK GCI
CLK ST-BUStDSS
tCSS tCSH
tRWS tRWH
VALID READ
ADDRESS
tADS tADH
VALID READ
DATA
tDHR
tCKAK tAKH
tDDR
tDSPW
tDSS
tCSS tCSH
tRWS tRWH
tADS tADH
VALID WRITE
DATA
tDHW
tCKAK tAKH
tSWD
Figure 15. Motorola Non-Multiplexed Syncronous Bus Timing
22
CORPORATE HEADQUARTER for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 408-330-1753
Santa Clara, CA 95054 fax: 408-492-8674 em ail: FIF Ohelp@idt.com
www.idt.com
5710 drw16
XXXXXX
IDT Device Type X
Package Process/
Temperature
Range
XX
BLANK Commercial (-40°C to +85°C)
72V70810 1,024 x 1,024 3.3V Time Slot Interchange Digital Switch
PF
TF Thin Plastic Quad Flatpack (TQFP, PN64-1)
Small Thin Quad Flat Pack (STQFP, PP64-1)
ORDERING INFORMATION
DATA SHEET DOCUMENT HISTORY
5/02/2000 pg.1
1/04/2001 pgs. 4, 5, 10, 11, 14, 17, 19 and 20.
1/25/2001 pgs. 14 and 20.
08/06/2001 pg. 1
