
IMI145158
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 2.1 5/29/2000
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Page 7 of 10
http://www.imicorp.com
Dual Modulus Prescaling
Dual Modulus prescaling is a wide spread method
used to effectively extend the operating frequency of
a digital counter without sacrificing any frequency
resolution. The key to understanding this method is
to remember the basics of division: When any two
integers are divided, a quotient and a remainder will
result.
When used here in a PLL, the numerator is the
required PLL total feedback divider ratio, called Ntot.
The denominator is the base modulus of the dual
modulus prescaler, P. The quotient is applied dir ectly
to the N counter, and the rem ainder is applied direc tly
to the A counter. Both counters count down together
toward zero. While the A counter counts, the MC
(modulus control) output signal is LOW, setting the
prescaler to divide by P + 1. When the A counter
reaches zero, the MC output is set HIGH while the N
counter continues to count down to zero. When the N
counter reaches zero, both counters are reset to the
programmed inputs and the cycle is repeated.
Two particular things should be noticed about this
process. First, the remainder counts are spread
among an equal number of quotient counts by the use
of the pres caler modulus P +1. W hen the remainder
has been counted, any remaining quotient counts are
handled normally by prescaling by modulus P. This
counter is thus performing
Ntot = A(P+1) + (N-A)P
Some algebra on this relation yields
Ntot = AP+A + NP-AP
= NP + A
which is just the definition of integer division. Second,
for this to work, there must be more quotient counts
than remainder counts for all possible values of Ntot in
the synthesizer design. If this were not true, then the N
counter will reach zero and cause the entire divider to
be reset before the A counter is finished. There is a
minimum value for Ntot for which this requirement will
always hold:
Ntot > P2 - P.
Programming Guidelines
The s ys tem total divide value (Ntotal) will be dictated by
the application:
frequency into the prescaler
frequency into the phase detector
N is the number progr amm ed into the ÷ N counter; A is
the number programmed into ÷ A counter. P and P +
1 are two selectable divide ratios available in the two
modulus prescalers. To have a range of Ntotal values
in sequence, the ÷ A counter is pr ogr amm ed fr om zero
through P-1 for a particular value N in the ÷ N counter.
N is then incremented to N + 1k, and the ÷ A is
sequenced from zero through P - 1 again.
To maximize system frequency capability, the dual
modulus prescaler’s output must go from low to high
after each group of P or P + 1 input cycles. The
prescaler should divide by P when its modulus control
line is high, and by P + 1 when its modulus control is
low.
For the maximum frequency into the prescaler (FVCO
max), the value used for P must be large enough so
that:
A. FVCO max divided by P may not exceed the
frequency capability of Pin 8 of the IMI145158.
B. The period of FVCO divided by P must be greater
than the sum of the times:
a. Propagation delay through the dual modulus
prescaler.
b. Prescaler setup or release time relative to its
modulus control signal.
c. Propagation time from fin to the modulus
control signal.
A useful simplification in the IMI145158 programming
code can be achieved by choosing the values for P or
8, 16, 32, or 64, or 128. For these cases, the desired
value for Ntotal in binary is us ed as the progr am code to
the ÷ A counters in the following manner:
Ntotal == N*P+A