UC1709, UC2709, UC3709 DUAL HIGH- SPEED FET DRIVER SLUS196C -- NOVEMBER 1996 -- REVISED FEBRUARY 2008 D D D D D D 1.5 Amp Source/Sink Drive Pin Compatible with 0026 Products 40 ns Rise and Fall into 1000pF Low Quiescent Current 5 V to 40 V Operation Thermal Protection simplified schematic (only one driver shown) VCC 5 VOLT REGULATOR description The UC3709 family of power drivers is an effective low-cost solution to the problem of providing fast turn-on and off for the capacitive gates of power MOSFETs. Made with a high-speed Schottky process, these devices will provide up to 1.5 A of either source or sink current from a totem--pole output stage configured for minimal cross-conduction current spike. THERMAL SENSE INPUT A OR B 6k INPUT A OR B 5.6 V The UC3709 is pin compatible with the MMH0026 or DS0026, and while the delay times are longer, the supply current is much less than these older devices. GND UDG--00068 With inverting logic, these units feature complete TTL compatibility at the inputs with an output stage that can swing over 30 V. This design also includes thermal shutdown protection. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)} Parameter DW PACKAGE J PACKAGE L PACKAGE N PACKAGE UNIT 40 40 40 40 V . . . . . . . . Steady--State 500 500 500 500 mA . . . . . . . . Peak Transient Supply Voltage, VCC Output Current (Source or Sink) 1.5 1.0 1.0 1.5 A . . . . . . . . Capacitive Discharge Energy 20 15 15 20 mJ Digital Inputs} 5.5 5.5 5.5 5.5 V Power Dissipation at TA = 25C 1 1 1 1 W Power Dissipation at TC = 25C 3 2 2 3 W Operating Junction Temperature Range (TJ) --55 to 125 --55 to 125 --55 to 125 --55 to 125 C Storage Temperature Range --65 to 150 --65 to 150 --65 to 150 --65 to 150 C 300 300 300 300 C Lead Temperature (Soldering, 10 Seconds) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All currents are positive into and negative out of the specified terminals. Digital drive can exceed 5.5V if input is limited to 10mA. Consult the Packaging Section of the Databook for thermal limitations and considerations of the package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004 -- 2008, Texas Instruments Incorporated www.ti.com 1 UC1709, UC2709, UC3709 DUAL HIGH- SPEED FET DRIVER SLUS196C -- NOVEMBER 1996 -- REVISED FEBRUARY 2008 THERMAL RESISTANCE TABLE PACKAGE jc(C/W) ja(C/W) SOIC--16 (DW) 20 (1) 35 to 58 (3) DIL--16 (J) 28 (2) 125 to 160 LCC--16 (L) 20 (2) 70 to 80 DIL--16 (N) 45 90 (3) NOTES: (1) Specified thermal resistance is jl (junction to lead)where noted. (2) jc data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states, "The baseline values shown are worst case (mean +2s) for a 60x60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 square mils. For device die sizes greater than 14400 square mils use the following values; dual-in-line, 11C/W; flat pack, .10C/W; pin grid array, 10C/W". (3) Specified ja (junction to ambient) is for devices mounted to 5-inch2 FR4 PC board with one ounce copper where noted. When resistance range is given, lower values are for 5 inch2 aluminum PC board. Test PWB was 0.062 inch thick and typically used 0.635-mm trace widths for power packages and 1.3-mm trace widths for non-power packages with a 100-mil x 100-mil probe land area at the end of each trace. 2 N/C N/C OUTPUT A 3 2 1 20 19 8 PIN DIL N OR J PACKAGE (TOP VIEW) N/C INPUT A LCC--20 (TOP VIEW) L PACKAGES N/C 1 8 N/C INPUT A 2 7 OUTPUT A GROUND 3 6 VCC INPUT B 4 5 OUTPUT B N/C -- No internal connection SOIC--16 (TOP VIEW) DW PACKAGE N/C 1 16 VCC N/C 2 15 N/C N/C 3 14 N/C OUTPUT A 4 13 OUTPUT B N/C 5 12 N/C INPUT A 6 11 INPUT B 18 N/C N/C 5 17 N/C GROUND 6 16 VCC N/C 7 15 N/C N/C 7 10 N/C N/C 8 14 N/C GROUND 8 9 N/C N/C OUTPUT B 10 11 12 13 N/C 9 N/C 4 INPUT B N/C www.ti.com UC1709, UC2709, UC3709 DUAL HIGH- SPEED FET DRIVER SLUS196C -- NOVEMBER 1996 -- REVISED FEBRUARY 2008 electrical characteristics over recommended operating free-air temperature range, TA = 55C to 125C for the UC1709, --40C to 85C for the UC2709, and 0C to 70C for the UC3709; VCC = 20 V, TA = TJ. PARAMETER Supply current TEST CONDITIONS MIN TYP MAX UNIT Both outputs low 10 12 mA Both outputs high 7 10 mA 0.8 V Logic 0 input voltage Logic 1 input voltage 2.2 V Input current VI = 0 --0.6 --1.0 mA Input leakage VI = 5 V Output high saturation VCC --V VO Output low saturation VO 0.05 0.1 mA IO = --50 mA 1.5 2.0 V IO = --500 mA 2.0 2.5 V IO = 50 mA 0.1 0.4 V IO = 500 mA 2.0 2.5 Thermal shutdown 155 V mA typical switching characteristics, VCC = 20 V, TA = 25C, delays measured to 10% output change PARAMETER TEST CONDITIONS OUTPUT CL = 0 nF 2.2 nF UNITS Rise time delay 80 80 ns 10% to 90% rise 20 40 ns Fall time delay 60 80 ns 20 40 ns 10% to 90% fall Output rise VCC cross--conduction curent spike duration Output fall NOTE: Refer to UC1705 specifications for further information. www.ti.com 25 ns 0 ns 3 UC1709, UC2709, UC3709 DUAL HIGH- SPEED FET DRIVER SLUS196C -- NOVEMBER 1996 -- REVISED FEBRUARY 2008 APPLICATION INFORMATION D1, D2: UC3611 Schottky Diodes Figure 1. Power bipolar drive circuit. D1, D2: UC3611 Schottky Diodes Figure 2. Power MOSFET drive circuit. Figure 3. Charge pump circuits. 4 www.ti.com UC1709, UC2709, UC3709 DUAL HIGH- SPEED FET DRIVER SLUS196C -- NOVEMBER 1996 -- REVISED FEBRUARY 2008 D1, D2: UC3611 Schottky Diodes Figure 4. Transformer coupled push--pull MOSFET drive circuit. D1, D2: UC3611 Schottky Diodes Figure 5. Power MOSFET drive circuit using negative bias voltage and level shifting to ground referenced PWM www.ti.com 5 UC1709, UC2709, UC3709 DUAL HIGH- SPEED FET DRIVER SLUS196C -- NOVEMBER 1996 -- REVISED FEBRUARY 2008 D1, D2: UC3611 Schottky Diodes Figure 6. Transformer coupled MOSFET drive circuit. 6 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-0151201VPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type UC1709J ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type UC1709J883B ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type UC1709L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type UC1709L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type UC2709DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2709DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2709N ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC2709NG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC3709DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3709DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3709N ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC3709NG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2009 to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MCER001A - JANUARY 1995 - REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. 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