LTC3833
1
3833f
TYPICAL APPLICATION
DESCRIPTION
Fast Accurate Step-Down
DC/DC Controller with
Differential Output Sensing
The LTC
®
3833 is a synchronous step-down DC/DC
switching regulator controller targeted for high power
applications. It drives all N-channel power MOSFETs. The
controlled on-time valley current mode architecture allows
for both fast transient response and constant frequency
switching in steady-state operation, independent of VIN,
VOUT and load current.
Differential output voltage sensing along with a precision
internal reference combine to offer ±0.67% output regula-
tion and the ability to correct for up to ±500mV variations
in the output terminals due to line losses. The operating
frequency can be programmed from 200kHz to 2MHz with
an external resistor and can be synchronized to an external
clock for noise and EMI sensitive applications.
Very low tON and tOFF times allow for near 0% and near
100% duty cycles, respectively. Programmable soft-start or
output voltage tracking is available. Safety features include
output overvoltage protection, programmable current limit
with foldback, and a power good output signal.
L, LT, LTC, LTM, OPTI-LOOP, PolyPhase, µModule, Linear Technology and the Linear logo
are registered trademarks and Hot Swap, No RSENSE and UltraFast are trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 5487554, 6580258, 6304066, 6476589,
6774611.
FEATURES
APPLICATIONS
n Wide VIN Range: 4.5V to 38V
n VOUT Range: 0.6V to 5.5V
n Output Accuracy: ±0.25% at 25°C and ±0.67%
over Temperature
n Differential Output Sensing Allowing Up to 500mV
Line Loss
n Fast Load Transient Response
n tON(MIN) = 20ns, tOFF(MIN) = 90ns
n Controlled On-Time Valley Current Mode
Architecture
n Frequency Programmable from 200kHz to 2MHz
and Synchronizable to External Clock
n RSENSE or Inductor DCR Current Sensing
n Overvoltage Protection and Current Limit Foldback
n Power Good Output Voltage Monitor
n Output Tracking or Adjustable Soft-Start
n External VCC Input for Bypassing Internal LDO
n 20-Pin QFN (3mm × 4mm) and TSSOP Packages
n Distributed Power Systems
n Point-of-Load Converters
n Computing Systems
n Datacomm Systems
1.5V, 20A, 300kHz High Current Step-Down Converter
Efficiency
VRNG VIN
MODE/PLLIN
VOUT
PGOOD
RUN
SENSE–
SENSE+
100k
INTVCC
10k
137k
300kHz
3.24k
LTC3833
15k
330µF
×2
10k
0.47µH
TG
0.1µF
0.1µF
470pF
180µF
VOUT
1.5V
20A
3833 TA01a
VIN
4.5V TO 14V
0.1µF
4.7µF
TRACK/SS
ITH
RT
EXTVCC
SGND
BOOST
SW
INTVCC INTVCC
BG
PGND
VOSNS+
VOSNS–LOAD CURRENT (A)
0.1
40
EFFICIENCY (%)
80
90
100
1 10 100
3833 TA01b
70
60
50 VIN = 12V
VOUT = 1.5V
PULSE-SKIPPING
MODE
FORCED
CONTINUOUS
MODE
LTC3833
2
3833f
VIN Voltage ................................................ –0.3V to 40V
BOOST Voltage .......................................... –0.3V to 46V
SW Voltage ................................................... –5V to 40V
INTVCC, EXTVCC, (BOOST-SW), PGOOD, RUN,
MODE/PLLIN, VRNG Voltages ....................... –0.3V to 6V
VOUT, SENSE+, SENSE– Voltages .................. –0.6V to 6V
VOSNS+, VOSNS– Voltages ........ –0.6V to (INTVCC + 0.3V)
RT, ITH Voltages ..................... –0.3V to (INTVCC + 0.3V)
TRACK/SS Voltages ..................................... –0.3V to 5V
(Note 1)
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3833EUDC#PBF LTC3833EUDC#TRPBF LFGT 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
LTC3833IUDC#PBF LTC3833IUDC#TRPBF LFGT 20-Lead (3mm × 4mm) Plastic QFN –40°C to 125°C
LTC3833EFE#PBF LTC3833EFE#TRPBF LTC3833FE 20-Lead Plastic TSSOP –40°C to 125°C
LTC3833IFE#PBF LTC3833IFE#TRPBF LTC3833FE 20-Lead Plastic TSSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ABSOLUTE MAXIMUM RATINGS
20 19 18 17
7 8
TOP VIEW
21
SGND
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
9 10
6
5
4
3
2
1
11
12
13
14
15
16
VOSNS–
VOSNS+
TRACK/SS
ITH
VRNG
RT
BOOST
TG
SW
BG
PGND
INTVCC
VOUT
SENSE–
SENSE+
PGOOD
RUN
EXTVCC
MODE/PLLIN
VIN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
FE PACKAGE
20-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
PGOOD
SENSE+
SENSE–
VOUT
VOSNS–
VOSNS+
TRACK/SS
ITH
VRNG
RT
BOOST
TG
SW
BG
PGND
INTVCC
VIN
MODE/PLLIN
EXTVCC
RUN
21
SGND
TJMAX = 125°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
Operating Junction Temperature Range
(Notes 2, 3, 4) ........................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
FE Package .......................................................300°C
LTC3833
3
3833f
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VFB = VOSNS+ – VOSNS–, unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
General
VIN Input Voltage Operating Range 4.5 38 V
VOUT Output Voltage Operating Range 0.6 5.5 V
IQInput DC Supply Current
Normal
Shutdown Supply Current
MODE/PLLIN = INTVCC
RUN = 0V
2
15
4
25
mA
µA
tON(MIN) Minimum On-Time VIN = 38V, VOUT = 0.6V 20 ns
tOFF(MIN) Minimum Off-Time 90 ns
Output Sensing
VREG Regulated Differential Feedback Voltage
(VOSNS+ – VOSNS–)
ITH = 1.2V (Note 5)
TA = 25°C
TA = 0°C to 85°C
TA = –40°C to 125°C
l
l
0.5985
0.596
0.594
0.6
0.6
0.6
0.6015
0.604
0.606
V
V
V
Regulated Differential Feedback Voltage
Over Line, Load and Common Mode
(VOSNS+ – VOSNS–)
VIN = 4.5V to 38V, ITH = 0.5V to 1.9V,
VOSNS– = ±500mV (Note 5)
TA = 0°C to 85°C
TA = –40°C to 125°C
l
l
0.594
0.591
0.6
0.6
0.606
0.609
V
V
gm(EA) Error Amplifier Transconductance ITH = 1.2V (Note 5) l1.4 1.7 2 mS
IVOSNS+VOSNS+ Input Bias Current VFB = 0.6V ±5 ±25 nA
IVOSNS–VOSNS– Input Bias Current VFB = 0.6V –35 –50 µA
Current Sensing
VSENSE(MAX) Valley Current Sense Threshold,
VSENSE+ – VSENSE–,
Peak Current = Valley + Ripple
VRNG = 2V, VFB = 0.57V
VRNG = 0V, VFB = 0.57V
VRNG = INTVCC, VFB = 0.57V
l
l
l
80
22
39
100
30
50
120
38
61
mV
mV
mV
VSENSE(MIN) Minimum Current Sense Threshold,
VSENSE+ – VSENSE–, Forced Continuous
Mode
VRNG = 2V, VFB = 0.63V
VRNG = 0V, VFB = 0.63V
VRNG = INTVCC, VFB = 0.63V
–50
–15
–25
mV
mV
mV
VSENSE(CM) SENSE+, SENSE– Voltage Range
(Common Mode)
Referenced to Signal Ground (SGND) l–0.5 5.5 V
ISENSE SENSE+, SENSE– Input Bias Current VSENSE(CM) = 0.6V
VSENSE(CM) = 5V
±5
1
±50
4
nA
µA
Start-Up and Shutdown
VRUN(TH) RUN Pin On Threshold VRUN Rising l1.1 1.2 1.3 V
VRUN(HYS) RUN Pin Hysteresis 70 mV
ISS Soft-Start Charging Current VTRACK/SS = 0V 1.0 µA
UVLOLOCK INTVCC Undervoltage Lockout INTVCC Falling l3.4 3.65 4.0 V
UVLORELEASE INTVCC Undervoltage Lockout Release INTVCC Rising l4.2 4.5 V
Switching Frequency and Clock Synchronization
f Free Running Switching Frequency RT = 205k
RT = 80.6k
RT = 18.2k
175
450
1800
200
500
2000
225
550
2200
kHz
kHz
kHz
VCLK(IH) Clock Input High Level into MODE/PLLIN 2 V
VCLK(IL) Clock Input Low Level into MODE/PLLIN 0.5 V
LTC3833
4
3833f
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VFB = VOSNS+ – VOSNS–, unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Drivers
RTG(HI) TG Driver Pull-Up On-Resistance TG High 2.5 Ω
RTG(LO) TG Driver Pull-Down On-Resistance TG Low 1.2 Ω
RBG(HI) BG Driver Pull-Up On-Resistance BG High 2.5 Ω
RBG(LO) BG Driver Pull-Down On-Resistance BG Low 0.8 Ω
tDLY(OFF) Top Gate Off to Bottom Gate On
Delay Time
(Note 6) 20 ns
tDLY(ON) Bottom Gate Off to Top Gate On
Delay Time
(Note 6) 15 ns
Internal VCC Regulator and External VCC
INTVCC Internal VCC Voltage 6V < VIN < 38V 5.1 5.3 5.55 V
INTVCC (%) Internal VCC Load Regulation ICC = 0mA to 50mA –1 –2 %
EXTVCC(TH) EXTVCC Switchover Voltage EXTVCC Rising 4.4 4.6 4.75 V
EXTVCC(HYS) EXTVCC Switchover Hysteresis 200 mV
∆EXTVCC EXTVCC Voltage Drop VEXTVCC = 5V, ICC = 50mA 200 mV
PGOOD Output
PGDOV PGOOD Upper Threshold VFB Rising (with Respect to Regulated
Feedback Voltage VREG)
5 7.5 10 %
PGDUV PGOOD Lower Threshold VFB Falling (with Respect to Regulated
Feedback Voltage VREG)
–10 –7.5 –5 %
PGDHYS PGOOD Hysteresis VFB Returning 2 %
VPGD(LO) PGOOD Low Voltage IPGOOD = 5mA 0.15 0.4 V
tPGD(FALL) Delay from OV/UV Fault to PGOOD Falling 20 µs
tPGD(RISE) Delay from OV/UV Recovery to PGOOD
Rising
10 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The junction temperature (TJ in °C) is calculated from the ambient
temperature (TA in °C) and power dissipation (PD in Watts) as follows:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance provided in the Pin
Configuration section for the corresponding package.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The LTC3833 is tested under pulsed loading conditions such
that TJ ≈ TA. The LTC3833E is guaranteed to meet specifications from
0°C to 85°C junction temperature; specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3833I is guaranteed to meet specifications over the full –40°C to 125°C
operating junction temperature range. Note that the maximum ambient
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal impedance and other environmental factors.
Note 5: The LTC3833 is tested in a feedback loop that adjusts
VFB = VOSNS+ – VOSNS– to achieve a specified error amplifier output voltage
(on ITH pin). The specification at 85°C is not tested in production. This
specification is assured by design, characterization and correlation to
production testing at 125°C.
Note 6: Delay times are measured using 50% levels.
LTC3833
5
3833f
TYPICAL PERFORMANCE CHARACTERISTICS
Transient Response: Pulse-
Skipping Mode Load Step: Pulse-Skipping Mode
Load Release: Pulse-Skipping
Mode
Normal Soft Start-Up
Soft Start-Up into
a Pre-Biased Output Output Tracking
Transient Response: Forced
Continuous Mode
Load Step: Forced Continuous
Mode
TA = 25°C unless otherwise noted
Load Release: Forced Continuous
Mode
ILOAD
20A/DIV
VOUT
50mV/DIV
50µs/DIV 3833 G01
LOAD TRANSIENT = 0A TO 20A
VIN = 12V, VOUT = 1.5V
FIGURE 10 CIRCUIT
IL
20A/DIV
ILOAD
20A/DIV
VOUT
50mV/DIV
5µs/DIV 3833 G02
LOAD STEP = 0A TO 20A
VIN = 12V, VOUT = 1.5V
FIGURE 10 CIRCUIT
IL
20A/DIV
ILOAD
20A/DIV
VOUT
50mV/DIV
5µs/DIV 3833 G03
LOAD RELEASE = 20A TO 0A
VIN = 12V, VOUT = 1.5V
FIGURE 10 CIRCUIT
IL
20A/DIV
ILOAD
20A/DIV
VOUT
50mV/DIV
50µs/DIV 3833 G04
LOAD TRANSIENT = 500mA TO 20A
VIN = 12V, VOUT = 1.5V
FIGURE 10 CIRCUIT
IL
20A/DIV
ILOAD
20A/DIV
VOUT
50mV/DIV
5µs/DIV 3833 G05
LOAD STEP = 500mA TO 20A
VIN = 12V, VOUT = 1.5V
FIGURE 10 CIRCUIT
IL
20A/DIV
ILOAD
20A/DIV
VOUT
50mV/DIV
5µs/DIV 3833 G06
LOAD RELEASE = 20A TO 500mA
VIN = 12V, VOUT = 1.5V
FIGURE 10 CIRCUIT
IL
20A/DIV
VIN
5V/DIV
TRACK/SS
200mV/DIV
10ms/DIV 3833 G07
VIN = 12V
VOUT = 1.5V
FIGURE 10 CIRCUIT
VOUT
500mV/DIV
RUN
2V/DIV
TRACK/SS
200mV/DIV
10ms/DIV 3833 G08
VIN = 12V
VOUT = 1.5V
FIGURE 10 CIRCUIT
VOUT
500mV/DIV
VOUT PRE-BIASED TO 0.75V TRACK/SS
200mV/DIV
10ms/DIV 3833 G09
VIN = 12V
VOUT = 1.5V
FIGURE 10 CIRCUIT
VOUT
500mV/DIV
LTC3833
6
3833f
Output Regulation
vs Input Voltage
Output Regulation
vs Load Current
Output Regulation
vs Temperature
Non-Synchronized Switching
Frequency vs Input Voltage Non-Synchronized Switching
Frequency vs Load Current
Non-Synchronized Switching
Frequency vs Temperature
Overcurrent Protection Short-Circuit Protection Overvoltage Protection
10ms/DIV
7.5A 7.5A
3833 G10
VIN = 12V
VOUT = 1.5V
FIGURE 10 CIRCUIT
VOUT
200mV/DIV
IL
10A/DIV
ILOAD
10A/DIV
CURRENT LIMIT (25A)
VOUT DROOPS DUE TO
REACHING CURRENT LIMIT
1ms/DIV 3833 G11
VIN = 12V
VOUT = 1.5V
FIGURE 10 CIRCUIT
VOUT
1V/DIV
IL
10A/DIV
SHORT-
CIRCUIT
TRIGGER
INDUCTOR CURRENT FOLDBACK
DURING SHORT-CIRCUIT
ILOAD
12A
ILOAD
12A
NOTE 7: INDUCTOR CURRENT REACHES
CURRENT LIMIT BEFORE FOLDBACK
AND DURING SHORT-CIRCUIT RECOVERY
SHORT-CIRCUIT
REGION
NOTE 7
20µs/DIV 3833 G12
VIN = 12V
VOUT = 1.5V
FIGURE 10 CIRCUIT
VOUT
200mV/DIV
IL
20A/DIV
BG
5V/DIV
OVERVOLTAGE
TRIGGER
OVERVOLTAGE REGION
NOTE 8: BG IS FORCED HIGH FOR EXTENDED
PERIODS TO REMOVE OVERVOLTAGE
NOTE 8
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted
VIN (V)
0
–0.2
NORMALIZED ∆VOUT (%)
–0.1
0
0.1
0.2
5 10 15 20
3833 G13
25 30 35 40
VOUT = 0.6V
ILOAD = 5A
VOUT NORMALIZED AT VIN = 15V
ILOAD (A)
0
NORMALIZED ∆VOUT (%)
0
0.1
8
3833 G14
–0.1
–0.2 24610
0.2 VIN = 15V
VOUT = 0.6V
VOUT NORMALIZED AT ILOAD = 4A
TEMPERATURE (°C)
–50
–0.2
NORMALIZED ∆VOUT (%)
–0.1
0
0.1
0.2
–25 0 25 50
3833 G15
55 100 125 150
VIN = 15V
VOUT = 0.6V
ILOAD = 0A
VOUT NORMALIZED AT TA = 25°C
VIN (V)
0
–1.0
NORMALIZED ∆f (%)
–0.5
0
0.5
1.0
10 20 30 40
3833 G16
1.5
2.0
5 15 25 35
VOUT = 0.6V
ILOAD = 5A
f = 500kHz
FREQUENCY NORMALIZED AT VIN = 15V
ILOAD (A)
0
NORMALIZED ∆f (%)
0
0.1
8
3833 G17
–0.1
–0.2 24610
0.2
VIN = 15V
VOUT = 0.6A
f = 500kHz
FREQUENCY NORMALIZED AT ILOAD = 4A
TEMPERATURE (°C)
–50
–2.0
NORMALIZED ∆f (%)
–1.5
–1.0
–0.5
0
0 50 100 150
3833 G18
0.5
1.0
–25 25 75 125
VIN = 15V, VOUT = 0.6V
ILOAD = 0A, f = 500kHz
FREQUENCY NORMALIZED AT TA = 25°C
LTC3833
7
3833f
Error Amplifier Transconductance
vs Temperature
Current Sense Voltage
vs ITH Voltage
Maximum Current Sense Voltage
vs Temperature
RUN Thresholds vs Temperature
Input Undervoltage Lockout
Thresholds vs Temperature
RUN and TRACK/SS Pull-Up
Currents vs Temperature
tON(MIN) and tOFF(MIN)
vs Voltage on VOUT Pin
tON(MIN) and tOFF(MIN)
vs Voltage on VIN Pin
tON(MIN) and tOFF(MIN)
vs Switching Frequency
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C unless otherwise noted
VOUT (V)
0
0
TIME (ns)
20
40
60
123 4
3833 G19
5
80
100
10
30
50
70
90
6
tOFF(MIN)
tON(MIN)
VIN = 38V
f ≈ 2000kHz
VIN (V)
0
0
TIME (ns)
10
30
40
50
100
70
10 20 25
3833 G20
20
80
90
60
5 15 30 35 40
VOUT = 0.6V
f ≈ 2000kHz
tOFF(MIN)
tON(MIN)
FREQUENCY (kHz)
200
0
TIME (ns)
20
40
60
500 800 1100 1400
3833 G21
1700
80
100
10
30
50
70
90
2000
tOFF(MIN)
tON(MIN)
VIN = 38V
VOUT = 0.6V
TEMPERATURE (°C)
–50
1.50
TRANSCONDUCTANCE (mS)
1.55
1.60
1.65
1.70
0 50 100 150
3833 G22
1.75
1.80
–25 25 75 125
ITH VOLTAGE (V)
0
–60
CURRENT SENSE VOLTAGE (mV)
–40
0
20
40
122.5
120
3833 G23
–20
0.5 1.5
60
80
100
VRNG = 0.6V
VRNG = 0.9V
VRNG = 1.3V
VRNG = 1.6V
VRNG = 2.0V
TEMPERATURE (°C)
–50
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
20
40
60
80
0 50 100 150
3833 G24
100
120
–25 25 75 125
VRNG = 2V
VRNG = 1V
VRNG = 0.6V
TEMPERATURE (°C)
–50
RUN PIN THRESHOLDS (V)
0.8
1.2
150
3833 G25
0.4
0050 100
–25 25 75 125
1.6
0.6
1.0
0.2
1.4 SWITCHING REGION
STANDBY REGION
SHUTDOWN REGION
TEMPERATURE (°C)
–50
3.3
UVLO THRESHOLDS (V)
3.5
3.7
3.9
4.1
0 50 100 150
3833 G26
4.3
4.5
–25 25 75 125
UVLO RELEASE
(INTVCC RISING)
UVLO LOCK
(INTVCC FALLING)
TEMPERATURE (°C)
–50
0.6
CURRENT (µA)
0.8
1.0
1.2
1.4
0 50 100 150
3833 G27
1.6
1.8
RUN
–25 25 75 125
TRACK/SS
LTC3833
8
3833f
PIN FUNCTIONS
PGOOD (Pin 1/Pin 17): Power Good Indicator Output.
This open-drain logic output is pulled to ground when
the output voltage is outside of a ±7.5% window around
the regulation point.
SENSE+ (Pin 2/Pin 18): Differential Current Sensing (+)
Input. For RSENSE current sensing, Kelvin (4-wire) connect
SENSE+ and SENSE– pins across the sense resistor. For
DCR sensing, Kelvin connect SENSE+ and SENSE– pins
across the sense filter capacitor.
SENSE– (Pin 3/Pin 19): Differential Current Sensing (–)
Input. For RSENSE current sensing, Kelvin (4-wire) connect
SENSE+ and SENSE– pins across the sense resistor. For
DCR sensing, Kelvin connect SENSE+ and SENSE– pins
across the sense filter capacitor.
VOUT (Pin 4/Pin 20): Output voltage sense for adjusting
the TG on-time for constant frequency operation. Tying
this pin to the local output (instead of remote output)
is recommended for most applications. This pin can be
programmed as needed for achieving the steady-state
on-time required for constant frequency operation.
VOSNS– (Pin 5/Pin 1): Differential Output Sensing (–)
Input. Connect this pin to the negative terminal of the
output capacitor. There is a bias current of 35µA (typical)
flowing out of this pin.
VOSNS+ (Pin 6/Pin 2): Differential Output Sensing (+) Input.
Connect this pin to the feedback resistor divider between
the positive and negative output capacitor terminals. In
nominal operation the LTC3833 will regulate the differen-
tial output voltage which is divided down to 0.6V by the
feedback resistor divider.
TRACK/SS (Pin 7/Pin 3): External Tracking and Soft-Start
Input. The LTC3833 regulates the differential feedback volt-
age (VOSNS+ − VOSNS–) to the smaller of 0.6V or the voltage
on the TRACK/SS pin. An internal 1.0μA pull-up current
source is connected to this pin. A capacitor to ground at
this pin sets the ramp time to the final regulated output
voltage. Alternatively, another voltage supply connected
through a resistor divider to this pin allows the output to
track the other supply during start-up.
ITH (Pin 8/Pin 4): Current Control Voltage and Switch-
ing Regulator Compensation Point. The current sense
threshold increases with this control voltage which ranges
from 0V to 2.4V.
VRNG (Pin 9/Pin 5): Current Sense Voltage Range Input.
The maximum allowed sense voltage between SENSE+ and
SENSE– is equal to 0.05 • VRNG. If VRNG is tied to SGND,
the device operates with a maximum sense voltage of
30mV. If VRNG is tied to INTVCC, the device operates with
a maximum sense voltage of 50mV.
RT (Pin 10/Pin 6): Switching Frequency Programming Pin.
Connect an external resistor from RT to signal ground to
program the switching frequency between 200kHz and
2MHz. An external clock applied to MODE/PLLIN must
be within ±30% of this free-running frequency to ensure
frequency lock.
RUN (Pin 11/Pin 7): Digital Run Control Input. RUN self
biases high with an internal 1.3µA pull-up. Forcing RUN
below 1.2V turns off TG and BG. Taking RUN below 0.75V
shuts down all bias and places the LTC3833 into micropower
shutdown mode of approximately 15μA.
EXTVCC (Pin 12/Pin 8): External VCC Input. When EXT-
VCC exceeds 4.6V, an internal switch connects this pin to
INTVCC and shuts down the internal regulator so that the
controller and gate drive power is drawn from EXTVCC.
EXTVCC should not exceed VIN.
MODE/PLLIN (Pin 13/Pin 9): External Clock Synchroniza-
tion Input and/or Forced Continuous Mode Input. When an
external clock is applied to this pin, the rising TG signal will
be synchronized with the rising edge of the external clock.
Additionally, this pin determines operation under light load
conditions. When either a clock input is detected or MODE/
PLLIN is tied to INTVCC, forced continuous mode operation
is selected. Tying this pin to SGND allows discontinuous
pulse-skipping mode operation at light loads.
(FE/UDC)
LTC3833
9
3833f
PIN FUNCTIONS
VIN (Pin 14/Pin 10): Main Supply Input. The supply voltage
can range from 4.5V to 38V. For increased noise immunity
decouple this pin to signal ground with an RC filter. The
voltage on this pin is also used to adjust the TG on-time
in order to maintain constant frequency operation.
INTVCC (Pin 15/Pin 11): Internal 5.3V Regulator Output.
The driver and control circuits are powered from this volt-
age. Decouple this pin to power ground with a minimum of
4.7μF ceramic capacitor (CVCC). The anode of the Schottky
diode, DB, connects to this pin.
PGND (Pin 16/Pin 12): Power Ground Connection. Connect
this pin as close as practical to the source of the bottom
N-channel power MOSFET, the (–) terminal of CVCC and
the (–) terminal of CIN.
BG (Pin 17/Pin 13): Bottom Gate Drive Output. This pin
drives the gate of the bottom N-channel power MOSFET
between INTVCC and power ground.
SW (Pin 18/Pin 14): Switch Node Connection. The (–)
terminal of the bootstrap capacitor, CB, connects to this
node. This pin swings from a diode voltage below ground
up to VIN.
TG (Pin 19/Pin 15): Top Gate Drive Output. This pin drives
the gate of the top N-Channel power MOSFET between
VSW and VBOOST
.
BOOST (Pin 20/Pin 16): Boosted Driver Supply Connec-
tion. The (+) terminal of the bootstrap capacitor, CB, as
well as the cathode of the Schottky diode, DB, connects
to this node. This node swings from INTVCC – VSCHOTTKY
to VIN + INTVCC – VSCHOTTKY.
SGND (Exposed Pad Pin 21/Exposed Pad Pin 21): Signal
Ground Connection. The SGND exposed pad must be
soldered to the circuit board for electrical contact and
rated thermal performance. All small-signal components
should be connected to the signal ground. Connect signal
ground to power ground only at one point using a single
PCB trace.
LTC3833
10
3833f
FUNCTIONAL DIAGRAM
Main Control Loop
The LTC3833 uses valley current mode control to regulate
the output voltage in an all N-channel MOSFET DC/DC step-
down converter. Current control is achieved by sensing
the inductor current across SENSE+ and SENSE–, either
by using an explicit resistor connected in series with the
inductor or by implicitly sensing the inductor’s resistive
(DCR) voltage drop through an RC filter connected across
the inductor.
In normal steady-state operation, the top MOSFET is turned
on for a fixed time interval proportional to the delay in the
–+–+
ICMP
EA
(gm(EA) = 1.7mS)
0.645V
0.555V
0.6V
1µA
IREV
LOGIC
CONTROL
PLL
SYSTEM
ONE-SHOT
TIMER
CLOCK
DETECT
OSCILLATOR
LDO
OUT EN
IN
VIN
4.2V
TIME
ADJUST
STOP
START
1.2V
0.75V
–
+
+
–
+
DA
(A = 1)
RPGD PGOOD
MODE/PLLIN
VRNG ITH
VOSNS–
VOSNS+
TRACK/SS
SENSE–
SENSE+
PGND
SW
EXTVCC
BO0ST
DBCB
MT
MB
L
COUT
RFB2
RFB1
RSENSE
INTVCC
INTVCC
BG
TG
SGND
RITH
CITH1
INTVCC
R1
INTVCC
R2
3.65V
UVLO
4.6V
VOUT
RT
RT
RUN 1.3µA
CVCC
VIN
CIN
VOUT
CSS
3833 FD
+
–
UV
+
–
+
–
–
+
–
–
OV
+
–
TG DRV
BG DRV
CLOCK
OPERATION
one-shot timer. The PLL system adjusts the delay in the
one-shot timer until the top MOSFET turn-on is synchro-
nized either to the internal oscillator or the external clock
input if provided. As the top MOSFET turns off, the bottom
MOSFET turns on with a small time delay (dead time) to
avoid shoot-through current. The next switching cycle is
initiated when the current comparator, ICMP
, senses that
inductor current has reached the valley threshold point
and turns the bottom MOSFET off immediately and the
top MOSFET on. Again in order to avoid shoot-through
current there is a small dead-time delay before the top
MOSFET turns on.
(Refer to Functional Diagram)
LTC3833
11
3833f
OPERATION
The voltage on the ITH pin sets the ICMP valley threshold
point. The error amplifier, EA, adjusts this ITH voltage
by comparing the differential feedback signal, VOSNS+ −
VOSNS–, to a 0.6V internal reference voltage. Consequently,
the LTC3833 regulates the output voltage by forcing the
differential feedback voltage to be equal to the 0.6V internal
reference. The difference amplifier, DA, converts the dif-
ferential feedback signal to a single-ended input for the
EA. If the load current increases, it causes a drop in the
differential feedback voltage relative to the reference. The
EA forces ITH voltage to rise until the average inductor
current again matches the load current.
Differential Output Sensing
The output voltage is resistively divided externally to create
a feedback voltage for the controller. The internal difference
amplifier, DA, senses this feedback voltage along with the
output’s remote ground reference to create a differential
feedback voltage. This scheme overcomes any ground
offsets between local ground and remote output ground,
resulting in a more accurate output voltage. The LTC3833
allows for remote output ground deviations as much as
±500mV with respect to local ground.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin. Power
on the INTVCC pin is derived in two ways: if the EXTVCC
pin is below 4.6V, then an internal 5.3V low dropout linear
regulator, LDO, supplies INTVCC power from VIN; if the
EXTVCC pin is tied to an external source larger than 4.6V,
then the LDO is shut down and an internal switch shorts
the EXTVCC pin to the INTVCC pin, thereby powering the
INTVCC pin with the external source and helping to increase
overall efficiency and decrease internal self heating through
power dissipated in the LDO. This external power source
could be the output of the step-down switching regulator
itself if the output is programmed to higher than 4.6V.
The top MOSFET driver is biased from the floating boot-
strap capacitor, CB, which normally recharges during
each off cycle through an external Schottky diode when
the top MOSFET turns off. If the VIN voltage is low and
INTVCC drops below 3.65V, undervoltage lockout circuitry
disables the external MOSFET driver and prevents the
power switches from turning on.
Shutdown and Start-Up
The LTC3833 can be shut down using the RUN pin. Pulling
this pin below 1.2V prevents the controller from switch-
ing, and less than 0.75V disables most of the internal bias
circuitry, including the INTVCC regulator. When RUN is less
than 0.75V, the shutdown IQ is about 15μA. Pulling the RUN
pin between 0.75V and 1.2V enables the controller into a
standby mode where all internal circuitry is powered-up
but the external MOSFET driver is disabled. The standby IQ
is about 2mA. Releasing the RUN pin from ground allows
an internal 1.3μA current to pull the pin above 1.2V and
fully enable the controller including the external MOSFET
driver. Alternatively, the RUN pin may be externally pulled
up or driven directly by logic. Be careful not to exceed the
absolute maximum rating of 6V on this pin. When pulled up
by a resistor to an external voltage, the RUN pin will sink
up to 35µA of current before reaching 6V. If the external
voltage is above 6V (e.g., VIN), select a large enough resis-
tor value so that the voltage on RUN will not exceed 6V.
The start-up of the controller’s output voltage, VOUT
, is
controlled by the voltage on the TRACK/SS pin. When
the voltage on the TRACK/SS pin is less than the 0.6V
internal reference, the LTC3833 regulates the differential
feedback voltage to the TRACK/SS voltage instead of the
0.6V reference. This allows the TRACK/SS pin to be used
for programming a ramp-up time for VOUT by connecting
an external capacitor from the TRACK/SS pin to SGND. An
internal 1μA pull-up current charges this capacitor, creating
a voltage ramp on the TRACK/SS pin. As the TRACK/SS
voltage rises from 0V to 0.6V (and beyond), the LTC3833
forces the output voltage, VOUT
, to ramp up smoothly to
its final value. Alternatively, the TRACK/SS pin can be used
to track the start-up of VOUT to another external supply
as in a master slave configuration. Typically, this requires
connecting a resistor divider from the master supply to
the TRACK/SS pin (see Soft-Start and Tracking).
(Refer to Functional Diagram)
LTC3833
12
3833f
OPERATION
When the RUN pin is pulled low to disable the controller or
when INTVCC drops below its undervoltage lockout thresh-
old of 3.65V, the TRACK/SS pin is pulled low internally.
Light Load Current Operation
When the DC load current is less than 1/2 of the peak-
to-peak inductor current ripple, the inductor current can
drop to zero or become negative. If the MODE/PLLIN pin
is connected to SGND, the LTC3833 will transition into
discontinuous mode operation (also called pulse-skipping
mode), where a current reversal comparator, IREV
, detects
and prevents negative inductor current by shutting off the
bottom MOSFET, MB. In this mode, both switches remain
off with the output capacitor supplying the load current.
As the output capacitor discharges and the output volt-
age droops lower, the EA will eventually move the ITH
voltage above the zero current level to initiate another
switching cycle.
If the MODE/PLLIN pin is tied to INTVCC or an external
clock is applied to MODE/PLLIN, the LTC3833 will be forced
to operate in continuous mode (called forced continuous
mode) and not transition into discontinuous mode. In this
case the current reversal comparator, IREV
, is disabled, al-
lowing the inductor current to become negative and thus
maintain constant frequency operation.
Frequency Selection and External Clock
Synchronization
The steady-state switching frequency of the LTC3833 is
set by an internal oscillator. The frequency of this internal
oscillator can be programmed from 200kHz to 2MHz by
connecting a resistor from the RT pin to SGND. The RT
pin is forced to 1.2V internally. A phase-locked loop (PLL)
system synchronizes the TG turn-on to this internal oscil-
lator when no external clock is provided.
For applications with stringent frequency or interference
requirements, an external clock source connected to
the MODE/PLLIN pin can be used to synchronize the TG
turn-on to the rising edge of the clock. The LTC3833 oper-
ates in forced continuous mode when it is synchronized to
the external clock. The external clock frequency has to be
within ±30% of the internal oscillator frequency for suc-
cessful synchronization and the clock input levels should
be greater than 2V for HI and less than 0.5V for LO. The
MODE/PLLIN pin has an internal 600k pull-down resistor.
Power Good and Fault Protection
The power good pin, PGOOD, is connected internally to
an open-drain N-channel MOSFET. An external pull-up
resistor to a voltage supply of up to 6V (or INTVCC) com-
pletes the power good detection scheme. Overvoltage
and undervoltage comparators OV and UV turn on the
MOSFET and pull the PGOOD pin low when the differen-
tial feedback voltage is outside a ±7.5% window of the
0.6V reference voltage. The PGOOD pin is also pulled low
when the LTC3833 is in the soft-start or tracking phase,
when in undervoltage lockout, or when the RUN pin is
low (shut down).
When the differential feedback voltage is within the ±7.5%
requirement, the open-drain NMOS is turned off and the
pin is pulled up by an external resistor. There is an internal
delay of 10µs before the PGOOD pin will indicate power
good once the differential feedback voltage is within the
±7.5% window. When the feedback voltage goes out of
the ±7.5% window, there is an internal 20μs delay before
PGOOD is pulled low. In an overvoltage condition, MT is
turned off and MB is turned on immediately without any
delay and held on until the overvoltage condition clears.
Foldback current limiting is provided if the output is shorted
to ground. As the differential feedback voltage drops, the
current threshold voltage on the ITH pin is pulled down
and clamped to 1.2V. This reduces the inductor valley
current level to 1/4th of its maximum value as the differ-
ential feedback approaches 0V. Foldback current limiting
is disabled at start-up.
(Refer to Functional Diagram)
LTC3833
13
3833f
APPLICATIONS INFORMATION
The Typical Application on the first page of this data sheet
is a basic LTC3833 application circuit. The LTC3833 can be
configured to sense the inductor current either through a
series sense resistor, RSENSE, or through an RC filter across
the inductor (DCR). The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Once the required output voltage and operat-
ing frequency have been determined, external component
selection is driven by load requirements, and begins with
the selection of inductor and current sensing components.
Next, the power MOSFETs are selected. Finally, input and
output capacitors are selected.
Output Voltage Programming and
Differential Output Sensing
The LTC3833 integrates differential output sensing with
output voltage programming, allowing for simple and
seamless design. As shown in Figure 1, the output voltage
is programmed by an external resistor divider from the
regulated output point to its ground reference. The resis-
tive divider is tapped by the VOSNS+ pin, and the ground
reference is sensed by VOSNS–. An optional feed-forward
capacitor, CFF
, can be used to improve the transient
performance of the regulator system as discussed under
OPTI-LOOP
®
Compensation. The resulting output voltage
is given according to the following equation:
VOUT =0.6V •1+RFB2
RFB1
More precisely, the VOUT value programmed in the previous
equation is with respect to the output’s ground reference,
and thus is a differential quantity. For example, if VOUT is
programmed to 5V and the output ground reference is at
–0.5V, then the output will be 4.5V with respect to signal
ground. The minimum differential output voltage is limited
to the internal reference, 0.6V, and the maximum differential
output voltage is 5.5V.
The VOSNS+ pin is high impedance with no input bias cur-
rent. The VOSNS– pin has about 35μA of current flowing
out of the pin.
Differential output sensing allows for more accurate output
regulation in high power distributed systems having large
line losses. Figure 2 illustrates the potential variations in
the power and ground lines due to parasitic elements.
These variations are exacerbated in multi-application
systems with shared ground planes. Without differential
output sensing, these variations directly reflect as an error
in the regulated output voltage. The LTC3833’s differential
output sensing can correct for up to ±500mV of variation
in the output’s power and ground lines.
The LTC3833’s differential output sensing scheme is
distinct from conventional schemes where the regulated
output and its ground reference are directly sensed with
a difference amplifier whose output is then divided down
with an external resistive divider and fed into the error
amplifier input. This conventional scheme is limited by
the common mode input range of the difference amplifier
and typically limits differential sensing to the lower range
of output voltages.
The LTC3833 allows for seamless differential output
sensing by sensing the resistively divided feedback volt-
age differentially. This allows for differential sensing in
the full output range from 0.6V to 5.5V. The difference
amplifier of the LTC3833 has a –3dB bandwidth of 8MHz,
high enough to not affect main loop compensation and
transient behavior.
To avoid noise coupling into VOSNS+, the resistor divider
should be placed near the VOSNS+ and VOSNS– pins and
physically close to the LTC3833. The remote output and
ground traces should be routed together as a differential
pair to the remote output. These traces should be termi-
nated as close as physically possible to the remote output
RFB2
VOSNS+
LTC3833
VOSNS–
COUT
CFF
(OPT)
3833 F01
VOUT
RFB1
Figure 1. Setting Output Voltage
LTC3833
14
3833f
APPLICATIONS INFORMATION
point that is to be accurately regulated through remote
differential sensing.
Switching Frequency Programming
The choice of operating frequency is a trade-off between
efficiency and component size. Lowering the operating fre-
quency improves efficiency by reducing MOSFET switching
losses but requires larger inductance and/or capacitance
to maintain low output ripple voltage. Conversely, raising
the operating frequency degrades efficiency but reduces
component size.
The switching frequency of the LTC3833 can be pro-
grammed from 200kHz to 2MHz by connecting a resistor
from the RT pin to signal ground. The value of this resistor
is given by the following empirical formula:
RTkΩ
[ ]
=41550
f kHz
[ ]
– 2.2
Not counting resistor tolerances, the switching fre-
quency could still have a ±10% deviation from the ideal
programmed value. The internal PLL has a synchroniza-
tion range of ±30% around this programmed frequency.
Therefore, during external clock synchronization be sure
that the external clock frequency is within this ±30% range
of the RT programmed frequency. It is advisable that the
RT programmed frequency be equal to the external clock
for maximum synchronization margin. Refer to Phase and
Frequency Synchronization for further details.
Inductor Selection
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use of
smaller inductor and capacitor values. A higher frequency
generally results in lower efficiency because of MOSFET
gate charge losses and top MOSFET transition losses.
In addition to this basic trade-off, the effect of inductor
value on ripple current and low current operation must
also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current, ∆IL, decreases with higher
inductance or frequency and increases with higher VIN:
∆IL=VOUT
f•L•1– VOUT
VIN
Accepting larger values of ∆IL allows the use of low induc-
tances, but results in higher output voltage ripple, higher
ESR losses in the output capacitor, and greater core losses.
A reasonable starting point for setting ripple current is
∆IL = 0.4 • IOUT(MAX) where IOUT(MAX) is the maximum
output current for the application. The maximum ∆IL
occurs at the maximum input voltage. To guarantee that
RFB1
MB
RFB2
MT L
CIN VIN
COUT1 COUT2
3833 F02
ILOAD
OTHER CURRENTS
FLOWING IN
SHARED GROUND
PLANE
POWER TRACE
PARASITICS
±VDROP(PWR)
+
–
GROUND TRACE
PARASITICS
±VDROP(GND)
ILOAD
LTC3833
VOSNS+VOSNS–
Figure 2: Differential Output Sensing Used to Correct Line Loss Variations in a
High Power Distributed System with a Shared Ground Plane
LTC3833
15
3833f
APPLICATIONS INFORMATION
ripple current does not exceed a specified maximum, the
inductance should be chosen according to:
L=VOUT
f•∆IL(MAX)
•1−VOUT
VIN(MAX)
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
tolerate the core loss of low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mμ cores. Ferrite core material saturates hard,
meaning that inductance collapses abruptly when the
peak design current is exceeded. This results in an abrupt
increase in inductor ripple current and consequent output
voltage ripple. Do not allow the core to saturate!
A variety of inductors designed for high current, low volt-
age applications are available from manufacturers such as
Sumida, Panasonic, Coiltronics, Coilcraft, Toko, Vishay,
Pulse and Wurth.
Current Sense Pins and Current Limit Programming
Inductor current is sensed through the SENSE+ and
SENSE– pins and fed into the internal current compara-
tors. The common mode input voltage range of the cur-
rent comparators is –0.5V to 5.5V. Both SENSE pins are
high impedance inputs. When the common mode range
is between –0.5V to 1.1V, there is no input bias current,
and when between 1.4V and 5.5V, there is less than 1μA
of current flowing into the pins. Between 1.1V and 1.4V,
the input bias current will be zero if the common mode
voltage is ramped up from 1.1V and less than 1μA if the
common mode voltage is ramped down from 1.4V. The
high impedance inputs to the current comparator allow
accurate DCR sensing. However, care must be taken not
to float these pins during normal operation.
The maximum allowed sense voltage VSENSE(MAX) between
SENSE+ and SENSE– is set by the voltage applied to the
VRNG pin and is given by:
VSENSE(MAX) = 0.05 • VRNG
The current mode control loop does not allow the induc-
tor current valleys to exceed 0.05 • VRNG. In practice, one
should allow sufficient margin to account for variations
in the LTC3833 and external component values. Note that
ITH is close to 2.4V when in current limit.
An external resistive divider from INTVCC can be used
to set the voltage on the VRNG pin between 0.6V and 2V,
resulting in maximum sense voltages between 30mV and
100mV. The wide voltage sense range allows for a variety
of applications. The VRNG pin can also be tied to either
SGND or INTVCC to force internal defaults. When VRNG is
tied to SGND, the device operates with a maximum sense
voltage of 30mV. When the VRNG pin is tied to INTVCC, the
device operates with a maximum sense voltage of 50mV.
RSENSE Inductor Current Sensing
A typical RSENSE inductor current sensing scheme is
shown in Figure 3. RSENSE is chosen based on the required
maximum output current. Given the maximum current,
IOUT(MAX), maximum sense voltage, VSENSE(MAX), set by the
VRNG pin, and maximum inductor ripple current, ∆IL(MAX),
the value of RSENSE can be chosen as:
RSENSE =VSENSE(MAX)
IOUT(MAX) –∆IL(MAX)
2
Conversely, given RSENSE and IOUT(MAX), VSENSE(MAX)
and thus the VRNG voltage could be determined from the
above equation. To assure that the maximum rated output
current can be supplied for different operating conditions
and component variations, sufficient design margin should
be built into these calculations.
Figure 3. RSENSE Current Sensing
RF
R ESL
RSENSE RESISTOR
AND
PARASITIC INDUCTANCE
FILTER COMPONENTS
PLACED NEAR SENSE PINS
RF
SENSE+
LTC3833
SENSE–
CF
3833 F03
VOUT
LTC3833
16
3833f
APPLICATIONS INFORMATION
Because of possible PCB noise in the current sensing loop,
the current ripple of ∆VSENSE = ∆IL • RSENSE also needs
to be checked in the design to get a good signal-to-noise
ratio. In general, for a reasonably good PCB layout, a
10mV ∆VSENSE voltage is recommended as a conservative
number to start with, either for RSENSE or DCR sensing
applications.
For today’s highest current density solutions the value of
the sense resistor can be less than 1mΩ and the maxi-
mum sense voltage can be as low as 30mV. In addition,
inductor ripple currents greater than 50% with operation
up to 2MHz are becoming more common. Under these
conditions, the voltage drop across the sense resistor’s
parasitic inductance becomes more relevant. A small RC
filter placed near the IC has been traditionally used to re-
duce the effects of capacitive and inductive noise coupled
in the sense traces on the PCB. A typical filter consists of
two series 10Ω resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 20ns.
The filter components need to be placed close to the IC.
The positive and negative sense traces need to be routed
as a differential pair and Kelvin (4-wire) connected to the
sense resistor.
DCR Inductor Current Sensing
For applications requiring higher efficiency at high load
currents, the LTC3833 is capable of sensing the voltage
drop across the inductor DCR, as shown in Figure 4.
The DCR of the inductor represents the small amount of
DC winding resistance, which can be less than 1mΩ for
today’s low value, high current inductors. In a high cur-
rent application requiring such an inductor, conduction
loss through a sense resistor would cost several points
of efficiency compared to DCR sensing.
The inductor DCR is sensed by connecting an RC filter
across the inductor. This filter typically consists of one
or two resistors (R1 and R2) and one capacitor (C1) as
shown in Figure 4. If the external R1||R2 • C1 time constant
is chosen to be exactly equal to the L/DCR time constant,
the voltage drop across the external capacitor is equal
to the voltage drop across the inductor DCR multiplied
by R2/(R1 + R2). Therefore, R2 may be used to scale
the voltage across the sense terminals when the DCR is
greater than the target sense resistance. With the ability
to program current limit through the VRNG pin, R2 may
be optional. C1 is usually selected to be in the range of
0.01μF to 0.47μF. This forces R1|| R2 to around 2k to 4k,
reducing error that might have been caused by the SENSE
pins’ input bias currents.
The first step in designing DCR current sensing is to
determine the DCR of the inductor. Where provided, use
the manufacturer’s maximum value, usually given at 25°C.
Increase this value to account for the temperature coef-
ficient of resistance, which is approximately 0.4%/°C. A
conservative value for inductor temperature TL is 100°C.
The DCR of the inductor can also be measured using a good
RLC meter, but the DCR tolerance is not always the same
and varies with temperature; consult the manufacturers’
datasheets for detailed information.
From the DCR value, VSENSE(MAX) is calculated as:
VSENSE(MAX) =DCRMAX at 25°C•1+0.4% TL(MAX) – 25°C
( )
•IOUT(MAX) –∆IL/2
If VSENSE(MAX) is within the maximum sense voltage of
the LTC3833 as programmed by the VRNG pin (30mV to
100mV), then the RC filter only needs R1. If VSENSE(MAX) is
higher, then R2 may be used to scale down the maximum
sense voltage so that it falls within range.
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
P
LOSS R1
( )
=VIN(MAX) – VOUT
( )
•VOUT
R1
R1
R2
(OPT)
DCRL
INDUCTOR
L/DCR = (R1||R2) C1
C1 NEAR SENSE PINS
SENSE+
LTC3833
SENSE–
C1
3833 F04
VOUT
COUT
Figure 4. DCR Current Sensing
LTC3833
17
3833f
APPLICATIONS INFORMATION
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
RSENSE sensing. Light load power loss can be modestly
higher with a DCR network than with a sense resistor due
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
To maintain a good signal-to-noise ratio for the current
sense signal, use a minimum ∆VSENSE of 10mV. For a
DCR sensing application, the actual ripple voltage will be
determined by:
∆VSENSE =VIN – VOUT
R1•C1 •VOUT
VIN •f
Power MOSFET Selection
Two external power MOSFETs must be selected for the
LTC3833 controller: one N-channel MOSFET for the top
(main) switch and one N-channel MOSFET for the bottom
(synchronous) switch. The peak-to-peak drive levels are
set by the INTVCC voltage. This voltage is typically 5.3V.
Consequently, logic-level threshold MOSFETs must be
used in most applications. Pay close attention to the
BVDSS specification for the MOSFETs as well; most of the
logic-level MOSFETs are limited to 30V or less. Selection
criteria for the power MOSFETs include the on-resistance,
RDS(ON), Miller capacitance, CMILLER, input voltage and
maximum output current. Miller capacitance, CMILLER,
can be approximated from the gate charge curve usu-
ally provided on the MOSFET manufacturers’ data sheet.
CMILLER is equal to the increase in gate charge along the
horizontal axis where the curve is approximately flat, di-
vided by the specified change in VDS. This result is then
multiplied by the ratio of the application VDS to the gate
charge curve specified VDS. When the IC is operating in
continuous mode, the duty cycles for the top and bottom
MOSFETs are given by:
Main Switch Duty Cycle DTOP
( )
=VOUT
VIN
Synchronous Switch Duty Cycle DBOT
( )
=1– VOUT
VIN
The MOSFET power dissipations at maximum output
current are given by:
P
TOP
=D
TOP
•I
OUT(MAX)2
•R
DS(ON)(MAX)
1+δ
( )
+V
IN2
•I
OUT(MAX)
2
•C
MILLER
R
TG(HI)
V
INTVCC
– V
MILLER
+R
TG(LO)
V
MILLER
•f
PBOT = DBOT • IOUT(MAX)2 • RDS(ON)(MAX) (1 + δ)
where DTOP and DBOT are the duty cycles of the top MOSFET
and bottom MOSFET respectively, δ is the temperature de-
pendency of RDS(ON), RTG(HI) is the TG pull-up resistance,
and RTG(LO) is the TG pull-down resistance. VMILLER is the
Miller effect VGS voltage and is taken graphically from the
MOSFET’s data sheet.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V, the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
short-circuit when the synchronous switch is on close to
100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
δ = 0.005/°C • (TJ – TA) can be used as an approximation
for low voltage MOSFETs (TJ is estimated junction tem-
perature of the MOSFET and TA is ambient temperature).
CIN and COUT Selection
In continuous mode, the source current of the top N-chan-
nel MOSFET is a square wave of duty cycle VOUT/VIN. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
IRMS ≅IOUT(MAX) •VOUT
VIN
•VIN
VOUT
– 1
This formula has a maximum at VIN = 2VOUT
, where IRMS
= IOUT(MAX)/2. This simple worst-case condition is com-
monly used for design because even significant deviations
LTC3833
18
3833f
APPLICATIONS INFORMATION
do not offer much relief. Note that capacitor manufactur-
ers’ ripple current ratings for electrolytic and conductive
polymer capacitors are often based on only 2000 hours of
life. This makes it advisable to further derate the capacitor
or to choose a capacitor rated at a higher temperature
than required.
The selection of COUT is primarily determined by the effec-
tive series resistance, ESR, to minimize voltage ripple. The
output ripple, ∆VOUT
, in continuous mode is determined by:
∆VOUT ≤ ∆ILRESR +1
8•f•COUT
The output ripple is highest at maximum input voltage
since ∆IL increases with input voltage. Typically, once the
ESR requirement for COUT has been met, the RMS current
rating generally far exceeds the peak-to-peak current ripple
requirement. The choice of using smaller output capaci-
tance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount pack-
ages. Special polymer capacitors offer very low ESR but
have lower capacitance density than other types. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
for use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
Ceramic capacitors have excellent low ESR characteris-
tics but can have a high voltage coefficient and audible
piezoelectric effects. The high Q of ceramic capacitors with
trace inductance can also lead to significant ringing. When
used as input capacitors, care must be taken to ensure
that ringing from inrush currents and switching does not
pose an overvoltage hazard to the power switches and
controller.
For high switching frequencies, reducing output ripple and
better EMI filtering may require small-value capacitors that
have low ESL (and correspondingly higher self resonant
frequencies) to be placed in parallel with larger value
capacitors that have higher ESL. This will ensure good
noise and EMI filtering in the entire frequency spectrum
of interest. Even though ceramic capacitors generally
have good high frequency performance, small ceramic
capacitors may still have to be parallel connected with
large ones to optimize performance.
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor, CB, connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises to
approximately VIN + INTVCC. The boost capacitor needs to
store approximately 100 times the gate charge required by
the top MOSFET. In most applications a 0.1μF to 0.47μF, X5R
or X7R dielectric capacitor is adequate. It is recommended
that the BOOST capacitor be no larger than 10% of the
INTVCC capacitor, CVCC, to ensure that the CVCC can supply
the upper MOSFET gate charge and BOOST capacitor under
all operating conditions. Variable frequency in response
to load steps offers superior transient performance but
requires higher instantaneous gate drive. Gate charge
demands are greatest in high frequency low duty factor
applications under high dI/dt load steps and at start-up.
In order to minimize SW node ringing and EMI, connect a
5Ω to 10Ω resistor in series with the BOOST pin. Make the
CB and DB connections on the other side of the resistor. This
series resistor helps to slow down the TG rise time, limiting
the high dI/dt current through the top MOSFET that causes
SW node ringing.
INTVCC Regulator and EXTVCC Power
The LTC3833 features a PMOS low dropout linear regu-
lator (LDO) that supplies power to INTVCC from the VIN
supply. INTVCC powers the gate drivers and much of the
LTC3833’s internal circuitry. The LDO regulates the voltage
at the INTVCC pin to 5.3V.
The LDO can supply a maximum current of 50mARMS and
must be bypassed to ground with a minimum of 4.7μF
ceramic capacitor. Good bypassing is needed to supply
LTC3833
19
3833f
APPLICATIONS INFORMATION
the high transient currents required by the MOSFET gate
drivers.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3833 to be
exceeded, especially if the LDO is active and provides
INTVCC. Power dissipation for the IC in this case is high-
est and is approximately equal to VIN • IINTVCC. The gate
charge current is dependent on operating frequency as
discussed in the Efficiency Considerations section. The
junction temperature can be estimated by using the equa-
tions given in Note 2 of the Electrical Characteristics. For
example, when using the LDO, LTC3833’s INTVCC current
is limited to less than 38mA from a 38V supply at TA =70°C
in the FE package:
TJ = 70°C + (38mA)(38V)(38°C/W) ≈ 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode at maximum
VIN.
When the voltage applied to EXTVCC pin rises above 4.6V,
the INTVCC LDO is turned off and the EXTVCC is connected
to INTVCC with an internal switch. This switch remains on
as long as the voltage applied to EXTVCC remains above
4.4V. Using the EXTVCC allows the MOSFET driver and
control power to be derived from the LTC3833’s switching
regulator output during normal operation and from the
LDO when the output is out of regulation (e.g., start-up,
short circuit). If more than 50mARMS current is required
through EXTVCC, then an external Schottky diode can be
added between the EXTVCC and INTVCC pins. Do not apply
more than 6V to the EXTVCC pin and make sure that this
external voltage source is less than VIN.
Significant efficiency and thermal gains can be realized
by powering INTVCC from the switching regulator output,
since the VIN current resulting from the driver and control
currents will be scaled by a factor of (Duty Cycle)/(Switcher
Efficiency).
Tying the EXTVCC pin to a 5V supply reduces the junction
temperature in the previous example from 125°C to:
TJ = 70°C + (38mA)(5V)(38°C/W) ≈ 77°C
However, for 3.3V and other low voltage outputs, addi-
tional circuitry is required to derive EXTVCC power from
the regulator output.
The following list summarizes the four possible connec-
tions for EXTVCC:
1. EXTVCC left open (or grounded). This will cause INTVCC
to be powered from the internal 5.3V LDO resulting
in an efficiency penalty of up to 10% at high input
voltages.
2. EXTVCC connected directly to switching regulator output
VOUT > 4.6V. This provides the highest efficiency.
3. EXTVCC connected to an external supply. If a 4.6V or
greater external supply is available, it may be used to
power EXTVCC providing that the external supply is
sufficient enough for MOSFET gate drive requirements.
4. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage converters, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.6V.
For applications where the main input power is less than
5.3V, tie the VIN and INTVCC pins together and tie the com-
bined pins to the VIN input with an optional 1Ω or 2.2Ω
resistor as shown in Figure 5 to minimize the voltage drop
caused by the gate charge current. This will override the
INTVCC LDO and will prevent INTVCC from dropping too low
due to the dropout voltage. Make sure the INTVCC voltage
exceeds the RDS(ON) test voltage for the external MOSFET
which is typically at 4.5V for logic-level devices.
INTVCC
LTC3833
VIN
CVCC
RVIN
3833 F05
VIN
CIN
Figure 5. Setup for VIN ≤ 5V
LTC3833
20
3833f
APPLICATIONS INFORMATION
VIN Undervoltage Lockout (UVLO)
The LTC3833 has two functions that help protect the con-
troller in case of input undervoltage conditions. A precision
UVLO comparator constantly monitors the INTVCC voltage
to ensure that an adequate gate-drive voltage is present.
The comparator enables UVLO and locks out the switch-
ing action until INTVCC rises above 4.2V. Once UVLO is
released, the comparator does not retrigger UVLO until
INTVCC falls below 3.65V. This hysteresis prevents oscil-
lations when there are disturbances on INTVCC.
Another way to detect an undervoltage condition is to
monitor the VIN supply. Because the RUN pin has a precision
turn-on voltage of 1.2V, one can use a resistor divider from
VIN to turn on the IC when VIN is high enough. The RUN pin
has bias currents that depend on the RUN voltage as well
as VIN voltage. These bias currents should be taken into ac-
count when designing the voltage divider and UVLO circuit
to prevent faulty conditions. Generally for RUN < 3V a bias
current of 1.3μA flows out of the RUN pin, and for RUN >
3V, correspondingly increasing current flows into the pin,
reaching a maximum of about 35μA for RUN = 6V.
Soft-Start and Tracking
The LTC3833 has the ability to either soft-start by itself
with a capacitor or track the output of an external supply.
Soft-start or tracking features are achieved not by limiting
the maximum output current of the switching regulator
but by controlling the regulator’s output voltage according
to the ramp rate on the TRACK/SS pin.
When configured to soft-start by itself, a capacitor should
be connected to the TRACK/SS pin. TRACK/SS is pulled
low until the RUN pin voltage exceeds 1.2V and UVLO is
released, at which point an internal current of 1μA charges
the soft-start capacitor, CSS, connected to TRACK/SS.
Current foldback is disabled during this phase to ensure
smooth soft-start or tracking. The soft-start or tracking
range is defined to be the voltage range from 0V to 0.6V
on the TRACK/SS pin. The total soft-start time can be
calculated as:
tSOFTSTART =0.6V •CSS
1µA
When the LTC3833 is configured to track another supply,
a voltage divider can be used from the tracking supply to
the TRACK/SS pin to scale the ramp rate appropriately.
Two common implementations of tracking as shown in
Figure 6a are coincident and ratiometric. For coincident
tracking, make the divider ratio from the external supply
the same as the divider ratio for the differential feedback
voltage. Ratiometric tracking could be achieved by using
a different ratio than the differential feedback (Figure 6b).
Note that the small soft-start capacitor charging current is
always flowing, producing a small offset error. To minimize
this error, select the tracking resistive divider values to be
small enough to make this offset error negligible.
Phase and Frequency Synchronization
For applications that require better control of EMI and
switching noise or have special synchronization needs, the
LTC3833 can phase and frequency synchronize the turn-on
of the top MOSFET to an external clock signal applied to
the MODE/PLLIN pin. The applied clock signal needs to
be within ±30% of the RT pin programmed free-running
frequency to assure proper frequency and phase lock.
The clock signal levels should generally comply to VIH >
2V and VIL < 0.5V. The MODE/PLLIN pin has an internal
600k pull-down resistor to ensure pulse-skipping mode
if the pin is left floating.
The LTC3833 uses the voltages on VIN and VOUT pins as
well as the RT programmed frequency to determine the
steady-state on-time as follows:
tON ≈VOUT
V
IN •f
An internal PLL system adjusts this on-time dynamically
in order to maintain phase and frequency lock with the
external clock. The LTC3833 will maintain phase and fre-
quency lock under steady-state conditions for VIN, VOUT
and load current.
As shown in the previous equation, the top MOSFET on-
time is a function of the switching regulator’s output. This
output is measured by the VOUT pin and is used to calculate
the required on-time. Therefore, simply connecting VOUT
to the regulator’s local output point is preferable for most
applications. However, there could be applications where
LTC3833
21
3833f
APPLICATIONS INFORMATION
the internally calculated on-time differs significantly from
the real on-time required by the application. For example,
if there are differences between the local output point and
the remotely regulated output point due to line losses, then
the internally calculated on-time will be inaccurate. Lower
efficiencies in the switching regulator can also cause the
real on-time to be significantly different from the internally
calculated on-time (see Efficiency Considerations). For
these circumstances, the voltage on the VOUT pin can
be programmed with a resistive divider from INTVCC or
from the regulator’s output itself. Note that there is a 500k
nominal resistance looking into the VOUT pin.
The PLL adjusted on-time achieved after phase locking is
the steady-state on-time required by the switching regula-
tor, and if the VOUT programmed on-time is substantially
equal to this steady-state on-time, then the PLL system
does not have to use its ±30% frequency lock range for
systematic corrections. Instead the lock range can be used
to correct for component variations or other operating point
conditions. If needed, the VOUT pin can be programmed
to achieve the steady-state on-time as required by the
application and therefore maintain constant frequency
operation.
If the application requires very low on-times approaching
minimum on-time, the PLL system may not be able to
maintain a ±30% synchronization range. In fact, there is
a possibility of losing phase/frequency lock at minimum
on-time, and definitely losing phase/frequency lock for
applications requiring less than minimum on-time. This
is discussed further under Minimum On-Time, Minimum
Off-Time and Dropout Operation.
During dynamic transient conditions either in the line or
load (e.g., load step or release), the LTC3833 may lose
phase and frequency lock in the process of achieving faster
transient response. For large slew rates (e.g., 10A/µs),
phase and frequency lock will be lost (see Figure 7) until
the system returns back to a steady-state condition at
which point the device will resume frequency lock and
eventually achieve phase lock to the external clock. For
relatively small slew rates (10A/s), phase and frequency
lock can still be maintained.
Figure 6b. Setup for Coincident and Ratiometric Tracking
Figure 6a. Two Different Modes of Output Tracking
TIME
Coincident Tracking
EXTERNAL
SUPPLY
EXTERNAL
SUPPLY
VOUT
VOLTAGE
VOUT
TIME 3833 F06
Ratiometric Tracking
VOLTAGE
RFB2
EXT. V
RFB1
Coincident Tracking Setup
TO
TRACK/SS
RFB2
VOUT
TO VOSNS+
RFB1
TO VOSNS–
R1
EXT. V
R2
R1+ R2 ≥
R2
TO
TRACK/SS
RFB2
VOUT
TO VOSNS+
RFB1
TO VOSNS–
3833 F06b
Ratiometric Tracking Setup
0.6V
EXT. V
LTC3833
22
3833f
APPLICATIONS INFORMATION
For light loading conditions, the phase and frequency
synchronization will be active if there is a clock input ap-
plied. If there is no clock input during light loading, then
the switching frequency is based on what the MODE/PLLIN
pin is tied to. When MODE/PLLIN is tied to INTVCC, the
LTC3833 will operate in forced continuous mode at the RT
programmed free-running frequency. When MODE/PLLIN
pin is tied to signal ground, the LTC3833 will operate in
pulse-skipping discontinuous conduction mode for light
loading and will switch to continuous conduction (at the
free-running frequency) for normal and heavy loads.
Minimum On-Time, Minimum Off-Time
and Dropout Operation
The minimum on-time is the smallest duration of time
in which the LTC3833 can keep the top power MOSFET ’s
gate (TG) in its on state. This minimum on-time is 20ns
for the LTC3833 and is achieved when the VOUT pin is
tied to its minimum value of 0.6V while the VIN is tied to
its maximum value of 38V. For larger values of VOUT or
smaller values of VIN, the minimum on-time achievable
will be longer than 20ns. The minimum on-time will have
a dependency on the operating conditions of the switching
regulator, but is intended to be smaller for high step-down
ratio applications that will require low on-times.
The effective minimum on-time of the switching regula-
tor, however, will depend also on external components
(especially the characteristics of the power MOSFETs) as
well as operating conditions of the switching regulator. The
effective on-time is defined as the time period that the SW
node stays high and this period can be different from the
time period that the top MOSFET ’s gate stays high. One
of the factors that contributes to this discrepancy is the
on/off switching characteristics of the power MOSFETs. If,
for example, the power MOSFET ’s turn-on delay is much
smaller than the turn-off delay, then the effective on-time
will be longer than the MOSFET ’s gate turn-on-time, thereby
limiting the minimum on-time to a longer value than that
forced by the LTC3833.
Light loading operation in forced continuous mode will
also elongate the effective minimum on-time, as shown
in Figure 8. At light loading, the dead times between the
top MOSFET switching on/off and the bottom MOSFET
switching on/off add to the intrinsic on-time of the top
MOSFET. In forced continuous light loading, when the
inductor current flows in the reverse direction, the SW
node is pre-biased high during the dead time from the
bottom FET turning off to the top FET turning on. On the
other edge, when the top MOSFET turns off and before
the bottom MOSFET turns on, the SW node lingers high
for a longer duration of time due to a smaller magnitude
of inductor current available in light loading to pull the
SW node low.
In continuous mode operation, the minimum on-time limit
imposes a minimum duty cycle of:
DMIN = f • tON(MIN)
LOSES PHASE
LOCK DUE
TO FAST
LOAD STEP
ESTABLISHES
FREQUENCY
LOCK SOON
ESTABLISHES
PHASE LOCK
AFTER ~600µs
ESTABLISHES
FREQUENCY
LOCK SOON
3833 F07
PHASE LOCKED
ILOAD
CLOCK
INPUT
SW
VOUT
LOSES PHASE
LOCK DUE TO
FAST LOAD
RELEASE
Figure 7. Phase and Frequency Locking Behavior During Transient Load Conditions
LTC3833
23
3833f
APPLICATIONS INFORMATION
where tON(MIN) is the effective minimum on-time for the
switching regulator. As the equation shows, reducing the
operating frequency will alleviate the minimum duty cycle
constraint.
If the application requires a smaller than minimum duty
cycle, the output voltage will still remain in regulation, but
the switching frequency will decrease from its programmed
value or lose frequency synchronization if using an external
clock. Depending on the application, this may not be of
critical importance.
For applications that require relatively low on-times,
proper caution has to be taken when choosing the top
power MOSFET. If a high Qg MOSFET is chosen such that
the on-time is not sufficient to fully turn the MOSFET on,
there will be significant losses in efficiency as a result
of larger RDS(ON) resistance and possibly failure of the
MOSFET due to significant heat dissipation.
The minimum off-time is the smallest duration of time
that the top power MOSFET ’s gate can be turned off and
then immediately turned back on. This minimum off-time
includes the time to turn on the bottom power MOSFET ’s
gate and turn it back off along with the dead time delays
from top MOSFET off to bottom MOSFET on and bottom
MOSFET off to top MOSFET on. The minimum off-time
that the LTC3833 can achieve is 90ns.
The effective minimum off-time of the switching regulator
is defined as the shortest period of time that the SW node
can stay low. This effective minimum off-time can vary
from the LTC3833’s 90ns of minimum off-time. The main
factor impacting the effective minimum off-time is the top
and bottom power MOSFETs’ gate charging characteristics,
including Qg and turn-on/off delays. These characteristics
can either extend or shorten the SW node’s minimum
off-time as compared to the LTC3833’s minimum off-time.
Large size (high Qg) power MOSFETs generally tend to
increase the effective minimum off-time due to longer
gate charging and discharging times. On the other hand,
imbalances in turn-on and turn-off delays could reduce
the effective minimum off-time.
The minimum off-time limit imposes a maximum duty
cycle of:
DMAX = 1 – f • tOFF(MIN)
where tOFF(MIN) is the effective minimum off-time of the
switching regulator. Reducing the operating frequency al-
leviates the maximum duty cycle constraint. If the maximum
duty cycle is reached, due to a drooping input voltage for
example, then the output will drop out of regulation. The
minimum input voltage to avoid dropout is:
V
IN(MIN) =VOUT
DMAX
At the onset of dropout, there is a region of VIN about
500mV that generates two discrete off-times, one being
the minimum off-time and the other being an off-time that
is about 40ns to 60ns larger than the minimum off-time.
This secondary off-time is due to the longer delay in trip-
ping the internal current comparator. The two off-times
average out to the required duty cycle to keep the output
in regulation with the output ripple remaining the same.
However, there is higher SW node jitter, especially appar-
ent when synchronized to an external clock. Depending
on the application, this may not be of critical importance.
DEAD-TIME
DELAYS
NEGATIVE
INDUCTOR
CURRENT
IN FCM
DURING BG-TG DEAD TIME,
NEGATIVE INDUCTOR CURRENT
WILL FLOW THROUGH TOP MOSFET’S
BODY DIODE TO PRECHARGE SW NODE
3833 F08
TG-SW
(VGS OF
TOP MOSFET)
BG
(VGS OF
BOTTOM MOSFET)
IL
SW
0
VIN
+
–
ILVIN
L
SW
DURING TG-BG DEAD TIME,
THE RATE OF SW NODE DISCHARGE
WILL DEPEND ON THE CAPACITANCE
ON THE SW NODE AND INDUCTOR
CURRENT MAGNITUDE
L
TOTAL CAPACITANCE
ON THE SW NODE
IL
Figure 8. Light Loading On-Time Extension with Forced
Continuous Mode Operation
LTC3833
24
3833f
APPLICATIONS INFORMATION
Fault Conditions: Current Limiting and Overvoltage
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3833, the maximum sense voltage is controlled
by the voltage on the VRNG pin. With valley current mode
control, the maximum sense voltage and the sense re-
sistance determine the maximum allowed inductor valley
current. The corresponding output current limit is:
ILIMIT =VSENSE(MAX)
RSENSE
+1
2•∆IL
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The current limit value should
be greater than the inductor current required to produce
maximum output power at the worst-case efficiency.
Worst-case efficiency typically occurs at the highest VIN
and highest ambient temperature. It is important to check
for consistency between the assumed MOSFET junction
temperatures and the resulting value of ILIMIT which heats
the MOSFET switches.
To further limit current in the event of a short circuit to
ground, the LTC3833 includes foldback current limiting.
If the output fails by more than 50%, then the maximum
sense voltage is progressively lowered to about one-fourth
of its full value.
If the output exceeds 7.5% of the programmed value,
then it is considered as an overvoltage (OV) condition.
In such a case, the top MOSFET is immediately turned
off and the bottom MOSFET is turned on indefinitely until
the OV condition is removed. Current limiting is not active
during an OV. If the output returns to a nominal level, then
normal operation resumes. If the OV persists a long time,
the current through the bottom MOSFET and inductor
could exceed their maximum ratings.
OPTI-LOOP Compensation
OPTI-LOOP compensation, through the availability of the
ITH pin, allows the transient response to be optimized for
a wide range of loads and output capacitors. The ITH pin
not only allows optimization of the control loop behavior
but also provides a test point for the step-down regulator ’s
DC-coupled and AC-filtered closed-loop response. The DC
step, rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at this pin.
The ITH series RITH-CITH1 filter sets the dominant pole-zero
loop compensation. Additionally, a small capacitor placed
from the ITH pin to SGND, CITH2, may be required to at-
tenuate high frequency noise. The values can be modified
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because their various types and values determine
the loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1μs to 10μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The general
goal of OPTI-LOOP compensation is to realize a fast but
stable ITH response with minimal output droop due to
the load step. For a detailed explanation of OPTI-LOOP
compensation, refer to Application Note 76.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT im-
mediately shifts by an amount equal to ∆ILOAD • ESR, where
ESR is the effective series resistance of COUT
. ∆ILOAD also
begins to charge or discharge COUT
, generating a feedback
error signal used by the regulator to return VOUT to its
steady-state value. During this recovery time, VOUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
Connecting a resistive load in series with a power MOSFET,
then placing the two directly across the output capacitor
and driving the gate with an appropriate signal generator is
a practical way to produce a realistic load-step condition.
The initial output voltage step resulting from the step change
in output current may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
phase margin. This is why it is better to look at the ITH
pin signal which is in the feedback loop and is the filtered
and compensated feedback loop response.
LTC3833
25
3833f
APPLICATIONS INFORMATION
The gain of the loop increases with RITH and the bandwidth
of the loop increases with decreasing CITH1. If RITH is
increased by the same factor that CITH1 is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor, CFF
, can
be added to improve the high frequency response, as shown
in Figure 1. Capacitor CFF provides phase lead by creating
a high frequency zero with RFB2 which improves the phase
margin. The output voltage settling behavior is related to
the stability of the closed-loop system and will demonstrate
overall performance of the step-down regulator.
In some applications, a more severe transient can be caused
by switching in loads with large (>10μF) input capacitors.
If the switch connecting the load has low resistance and
is driven quickly, then the discharged input capacitors are
effectively put in parallel with COUT
, causing a rapid drop in
VOUT
. No regulator can deliver enough current to prevent
this problem. The solution is to limit the turn-on speed of
the load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates cur-
rent limiting, short-circuit protection and soft starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power. Although all dissipative elements in
the circuit produce losses, four main sources account for
most of the losses:
1. I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause
the efficiency to drop at high output currents. In
continuous mode the average output current flows
though the inductor L, but is chopped between the
top and bottom MOSFETs. If the two MOSFETs have
approximately the same RDS(ON), then the resistance
of one MOSFET can simply by summed with the re-
sistances of L and the board traces to obtain the DC
I2R loss. For example, if RDS(ON) = 0.01Ω and RL =
0.005Ω, the loss will range from 15mW to 1.5W as
the output current varies from 1A to 10A.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the
input voltage, load current, driver strength and MOSFET
capacitance, among other factors. The loss is significant
at input voltages above 20V.
3. INTVCC current. This is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
controller IQ current. In continuous mode, IGATECHG =
f • (Qg(TOP) + Qg(BOT)), where Qg(TOP) and Qg(BOT) are the
gate charges of the topside and bottom side MOSFETs,
respectively.
Supplying INTVCC power through EXTVCC could save
several points of efficiency, especially for high VIN appli-
cations. Connecting EXTVCC to an output-derived source
will scale the VIN current required for the driver and
controller circuits by a factor of Duty Cycle/Efficiency.
For example, in a 20V to 5V application, 10mA of INTVCC
current results in approximately 2.5mA of VIN current.
This reduces the mid-current loss from 10% or more
(if the driver was powered directly from VIN) to only a
few percent.
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss
and sufficient capacitance to prevent the RMS current
from causing additional upstream losses in cabling,
fuses or batteries.
Other losses, which include the COUT ESR loss, bottom
MOSFET reverse-recovery loss and inductor core loss
generally account for less than 2% additional loss.
LTC3833
26
3833f
APPLICATIONS INFORMATION
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current there is no change in efficiency.
Power losses in the switching regulator will reflect as a
longer than ideal on-time. This efficiency accounted on-
time in continuous mode can be calculated as:
tON(REAL) ≈tON(IDEAL)
Efficiency
Design Example
Consider a step-down converter with VIN = 6V to 24V, VOUT
= 1.2V, IOUT(MAX) = 15A, and f = 350kHz (see Figure 9).
The regulated output voltage is determined by:
VOUT =0.6V •1+RFB2
RFB1
Using a 20k resistor from VOSNS+ to VOSNS–, the top
feedback resistor is also 20k.
The frequency is programmed by:
RTkΩ
[ ]
=41550
f kHz
[ ]
– 2.2 =41550
350 – 2.2 ≈116.5k
Select the nearest standard value of 115k.
The minimum on-time occurs for maximum VIN and should
be greater than 20ns which is the best that the LTC3833
can achieve. The minimum on-time for this application is:
tON(MIN) =VOUT
VIN(MAX) •f=1.2V
24V •350kHz ≈143ns
Set the inductor value to give 40% ripple current at maxi-
mum VIN:
L=1.2V
350kHz •40% •15A •1– 1.2V
24V
≈0.54µH
Select 0.56μH which is the nearest standard value.
VIN
VOUT
PGOOD
RUN
VRNG
SENSE–
SENSE+
RPGD
100k
INTVCC
RITH
47.5k
RT
115k
RDCR
3.09k
LTC3833
RFB2
20k
RFB1
20k
COUT1
330µF
2.5V
×2
MT
MB
COUT2
100µF
×2
L1
0.56µH
TG
SW
DB
CSS
0.1µF
RDIV1
52.3k
RDIV2
10k
CITH1
470pF
CITH2 47pF
3833 F09
VIN
6V TO 24V
VOUT
1.2V
15A
CDCR
0.1µF
CB 0.1µF
CVCC
4.7µF
CIN1: SANYO 25SVPD82M
COUT1: SANYO 2R5TPE330M9
DB: CENTRAL CMDSH-3
L1: VISHAY IHLP4040DZ-056µH
MB: RENESAS RJK0330DPB
MT: RENESAS RJK0305DPB
TRACK/SS
ITH
RT
MODE/PLLIN
EXTVCC
SGND
BOOST
INTVCC INTVCC
BG
PGND
VOSNS+
VOSNS–
CIN2
10µF
CIN1
82µF
25V
+
+
350kHz
Figure 9. 1.2V, 15A, 350kHz Step-Down Converter
Efficiency
LOAD CURRENT (A)
0.1
60
EFFICIENCY (%)
80
100
1 10 100
3833 F09b
40
50
70
90
30
20
VIN = 12V
VOUT = 1.2V
PULSE-SKIPPING
MODE
FORCED
CONTINUOUS
MODE
LTC3833
27
3833f
APPLICATIONS INFORMATION
The resulting maximum ripple current is:
∆IL=1.2V
350kHz •0.56µH •1– 1.2V
24V
≈5.8A
Often in high power applications, DCR current sensing is
preferred over RSENSE in order to maximize efficiency. In
order to determine the DCR filter values, first the induc-
tor manufacturer has to be chosen. For this design, the
Vishay IHLP-4040DZ-01 model is chosen with a value of
0.56μH and DCRMAX =1.8mΩ. This implies that:
VSENSE(MAX) = DRCMAX at 25°C • [1 + 0.4% (TL(MAX)
– 25°C)] • [IOUT(MAX) – ∆IL/2]
= 1.8mΩ • [1 + 0.4% (100°C – 25°C)] •
[15A – 5.8A/2]
≈ 28.3mV
The maximum sense voltage is within the range that
LTC3833 can handle without any additional scaling. There-
fore, the DCR filter consists of a simple RC filter across
the inductor. If the C is chosen to be 0.1µF, then the R can
be calculated as:
RDCR =L
DCRMAX •CDCR
=0.56µH
1.8mΩ•0.1µF ≈3.11k
The closest standard value is 3.09k.
The resulting value of VRNG with a 50% design margin
factor is:
VRNG = VSENSE(MAX)/0.05 • MF
= 28.3mV/0.05 • 1.5 ≈ 850mV
To generate the VRNG voltage, connect a resistive divider
from INTVCC to SGND with RDIV1 = 52.3k and RDIV2 =
10k.
For the external N-channel MOSFETs, Renesas RJK-
0305DBP (RDS(ON) = 13mΩ max, CMILLER = 150pF, VGS
= 4.5V, θJA = 40°C/W, TJ(MAX) = 150°C) is chosen for the
top MOSFET (main switch), and RJK0330DBP (RDS(ON)
= 3.9mΩ max, VGS = 4.5V, θJA = 40°C/W, TJ(MAX) =
150°C) is chosen for the bottom MOSFET (synchronous
switch). The power dissipation and the resulting junction
temperature for each MOSFET can be calculated for VIN
= 24V and TA = 75°C:
PTOP =1.2V
24V
•15A
( )
213mΩ
( )
1+0.4
( )
+24V
( )
2
•15A
2
150pF
( )
2.5Ω
5.3V – 3V +1.2Ω
3V
350kHz
≈0.54W
TJ(TOP) =75°C+0.54W
( )
40°C
W
≈97°C
P
BOT =24V – 1.2V
24V
15A
( )
23.9mΩ
( )
1+0.4
( )
≈1.2W
TJ(BOT) =75°C+1.2W
( )
40°C
W
=123°C
These numbers show that careful attention should be paid
to proper heat sinking when operating at higher ambient
temperatures.
Select CIN to give an RMS current rating greater than 7A
at 75°C. The output capacitor COUT is chosen for a low
ESR of 4.5mΩ to minimize output voltage changes due to
inductor ripple current and load steps. The output voltage
ripple is given as:
∆VOUT(RIPPLE) = ∆IL(MAX) • ESR = (5.8A)(4.5mΩ)
≈ 26mV
However, a 0A to 10A load step will cause an output
change of up to:
∆VOUT(STEP) = ∆ILOAD • ESR = (10A)(4.5mΩ) = 45mV
Optional 100μF ceramic output capacitors are included to
minimize the effect of ESR and ESL in the output ripple
and to improve load step response.
LTC3833
28
3833f
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3833.
• Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking
purposes. Use wide rails and/or entire planes for VIN,
VOUT and PGND nodes for good filtering and minimal
copper loss. If a ground layer is used, then it should
be immediately below (and/or above) the routing layer
for the power train components which consist of CIN,
power MOSFETs, inductor, sense resistor (if used) and
COUT
. Flood unused areas of all layers with copper for
better heat sinking.
• Keep signal and power grounds separate except at the
point where they are shorted together. Short signal and
power ground together only at a single point with a nar-
row PCB trace (or single via in a multilayer board). All
power train components should be referenced to power
ground and all small-signal components (e.g., CITH1,
RT
, CSS etc.) should be referenced to signal ground.
• Place CIN, power MOSFETs, inductor, sense resistor (if
used), and primary COUT capacitors close together in
one compact area. The SW node should be compact
but be large enough to handle the inductor currents
without large copper losses. Connect the drain of the
topside MOSFET as close as possible to the (+) plate of
CIN capacitor(s) that provides the bulk of the AC current
(these are normally the ceramic capacitors), and con-
nect the source of the bottom side MOSFET as close as
possible to the (–) terminal of the same CIN capacitor(s).
The high dI/dt loop formed by CIN, the top MOSFET,
and the bottom MOSFET should have short leads and
PCB trace lengths to minimize high frequency EMI and
voltage stress from inductive ringing. The (–) terminal
of the primary COUT capacitor(s) which filter the bulk
of the inductor ripple current (these are normally the
ceramic capacitors) should also be connected close to
the (–) terminal of CIN.
• Place BOOST, TG, SW, BG and PGND pins facing the
power train components. Keep high dV/dt signals on
BOOST, TG, SW and BG away from sensitive small-signal
traces and components.
•
For RSENSE current sensing, place the sense resistor
close to the inductor on the output side. Use a Kelvin
(4-wire) connection across the sense resistor and
route the traces together as a differential pair. RC filter
the differential sense signal close to SENSE+/SENSE–
pins, placing the filter capacitor as close as possible
to the pins. For DCR sensing, Kelvin connect across
the inductor and place the DCR sensing resistor closer
to the SW node and further away from the SENSE+/
SENSE– pins. Place the DCR capacitor close to the
SENSE+/SENSE– pins.
• Place the resistive feedback divider RFB1/2 as close as
possible to VOSNS+/VOSNS– pins and route the remote
output and ground traces together as a differential
pair and terminate as close to the regulation point as
possible (preferably Kelvin connect across the capacitor
at the remote output point).
• Place the ceramic CVCC capacitor as close as possible
to INTVCC and PGND pins. Likewise, the CB capacitor
should be as close as possible to BOOST and SW pins.
These capacitors provide the gate charging currents for
the power MOSFETs.
• Place small-signal components as close to their respec-
tive pins as possible. This minimizes the possibility of
PCB noise coupling into these pins. Give priority to
VOSNS+/VOSNS–,
SENSE+/SENSE–
, ITH, RT and VRNG
pins. Use sufficient isolation when routing a clock signal
into MODE/PLLIN pin so that the clock does not couple
into sensitive small-signal pins.
• Filter the VIN input to the LTC3833 with a simple RC
filter close to the pin. The RC filter should be referenced
to signal ground.
APPLICATIONS INFORMATION
LTC3833
29
3833f
APPLICATIONS INFORMATION
VRNG
VIN
MODE/PLLIN
VOUT
PGOOD
RUN
SENSE–
SENSE+
RPGD
100k
RF1
10Ω
RF2
10Ω
INTVCC RVIN
2.2Ω
LTC3833
RFB2
15k
RFB1
10k
CIN1: SANYO 16SVP180M
COUT1: SANYO 2R5TPE330M9
DB: CENTRAL CMDSH-3
L1: PULSE PA0515.471NLT
MB: RENESAS RJK0330DPB
MT: RENESAS RJK0305DPB
DB
MT
INTVCC
MB
COUT1
330µF
2.5V
×2
COUT2
100µF
×2
L1
0.47µH
RSENSE
1.5mΩ
TG
CB
0.1µF
CIN2
22µF
×2
CIN1
180µF
16V
VOUT
1.5V
20A
3833 F10a
VIN
4.5V TO 14V
CVIN
0.1µF
CF
1000pF
CVCC
4.7µF
TRACK/SS
ITH
RT
RT 137k
CITH1 220pF
CITH2 47pF
CSS 0.1µF
RITH 84.5k
EXTVCC
SGND
BOOST
SW
INTVCC
BG
PGND
VOSNS+
VOSNS–
+
+
Efficiency
LOAD CURRENT (A)
0.1
40
EFFICIENCY (%)
80
90
100
1 10 100
3833 F10b
70
60
50
VIN = 12V
VOUT = 1.5V
PULSE-SKIPPING
MODE
FORCED
CONTINUOUS
MODE
Figure 10. 1.5V, 20A, 300kHz High Current Step-Down Converter
LTC3833
30
3833f
TYPICAL APPLICATIONS
5V, 8A, 200kHz High Efficient Step-Down Converter
VIN
VOUT
PGOOD
RUN
VRNG
SENSE–
SENSE+
RPGD
100k
INTVCC
RITH
86.6k
RT
205k
RVIN
2.2Ω
RDCR
5.9k
RB
10Ω
LTC3833
COUT1
330µF
6.3V
×2
MT
MB
CIN1: NICHICON UCJ1H101MCL1GS
COUT1: SANYO 6TPE330MIL
DB: DIODES INC. SDM10K45
L1: COOPER HC2LP-6R0
MB: INFINEON BSC035N04LS
MT: INFINEON BSC035N04LS
COUT2
100µF
×2
RFB2
147k
RFB1
20k
L1
6µH
TG
DB
CSS
0.1µF
CITH1
220pF
CVIN
0.1µF
3833 TA02
VIN
7V TO 38V
VOUT
5V
8A
CDCR
0.22µF
CB
0.1µF
CVCC
4.7µF
TRACK/SS
ITH
RT
MODE/PLLIN
EXTVCC
SGND
BOOST
SW
INTVCC INTVCC
BG
PGND
VOSNS+
VOSNS–
CIN2
10µF
×3
CIN1
100µF
50V
+
+
Efficiency
LOAD CURRENT (A)
0.1
70
EFFICIENCY (%)
90
95
100
1 10
3833 TA02b
85
80
75 VIN = 12V
VOUT = 5V
PULSE-SKIPPING
MODE
FORCED
CONTINUOUS
MODE
LTC3833
31
3833f
TYPICAL APPLICATIONS
0.6V, 10A, 200kHz Low Output Step-Down Converter
VIN
VOUT
PGOOD
MODE/PLLIN
VRNG
RUN
SENSE–
SENSE+
RPGD
100k
INTVCC
RITH
51k
RT
205k
CSS
2200pF
CITH1
220pF
LTC3833
COUT2
100µF
×2
COUT1
330µF
2.5V
×2
L1
1µH
RSENSE
3mΩ
TG
CB 0.1µF
CIN2
10µF
×3
VOUT
0.6V
10A
3833 TA03
VIN
4.5V TO 14V
CF
1000pF
CVCC
4.7µF
DB
TRACK/SS
ITH
RT
EXTVCC
SGND
BOOST
SW
INTVCC INTVCC
BG
PGND
VOSNS+
VOSNS–
RVIN
2.2Ω
RF2
10Ω
RF1
10Ω
CVIN
0.1µF
MT
MB
CIN1: NICHICON UCJ1H101MCL1GS
COUT: SANYO 2R5TPE330M9
DB: DIODES INC. SDM10K45
L1: WURTH 7443320100
MT: INFINEON BSC093N04LS
MB: INFINEON BSC035N04LS
+
CIN1
100µF
50V
+
Efficiency
LOAD CURRENT (A)
20
50
40
30
90
80
70
60
3833 TA03b
EFFICIENCY (%)
0.1 10
1
VIN = 12V
VOUT = 0.6V
PULSE-SKIPPING
MODE
FORCED
CONTINUOUS
MODE
LTC3833
32
3833f
TYPICAL APPLICATIONS
Area Compact 2.5V, 5A, 1.2MHz Step-Down Converter
VIN
VOUT
EXTVCC
PGOOD
RUN SENSE–
SENSE+
RPGD
100k
INTVCC
RITH
20k
RT
33.2k
CSS
0.01µF
CITH1
220pF
RDCR
1.1k
LTC3833
COUT1
100µF
L1
1µH
RFB2
31.6k
RFB1
10k
TG
CB 0.1µF VOUT
2.5V
5A
3833 TA04
VIN
6V TO 28V
CIN2
10µF
CIN1
47µF
35V
CDCR
0.1µF
CVCC
4.7µF
DB
TRACK/SS
ITH
RT
MODE/PLLIN
VRNG
SGND
BOOST
SW
INTVCC INTVCC
BG
PGND
VOSNS+
VOSNS–
RVIN
2.2Ω
CVIN
0.1µF
MT
MB
CIN1: KEMET T521X476M035ATE070
DB: DIODES INC. SDM10K45
L1: VISHAY IHLP2525CZ-1µH
MT, MB: VISHAY/SILICONIX Si4816BDY
+
Efficiency
LOAD CURRENT (A)
20
50
40
30
90
80
70
60
3833 TA04b
EFFICIENCY (%)
0.1 10
1
VIN = 12V
VOUT = 2.5V
PULSE-
SKIPPING
MODE
FORCED
CONTINUOUS
MODE
LTC3833
33
3833f
TYPICAL APPLICATIONS
3.3V, 15A, 200kHz High Power Step-Down Converter
Efficiency
VIN
VOUT
PGOOD
VRNG
RUN
SENSE–
SENSE+
RPGD
100k
INTVCC
RITH
18.2k
RT
205k
RDCR1
3.92k
RVIN
2.2Ω
LTC3833
RFB2
90.9k
RFB1
20k
COUT1
220µF
4V
×2
MT
MB
COUT2
100µF
×2
L1
2µH
TG
SW
DB
CSS
0.1µF
CITH1
680pF
CITH2 47pF
3833 TA06
VIN
4.5V TO 24V
VOUT
3.3V
15A
CDCR
0.22µF
RDCR2
17.4k
CB
0.1µF
CVCC
4.7µF
CIN1: SUNCON 35HVP100M
COUT1: SANYO 4TPE220MFC2
DB: CENTRAL CMDSH-3
L1: WURTH 7443551200
MB: RENESAS RJK0330DPB
MT: RENESAS RJK0305DPB
TRACK/SS
ITH
RT
MODE/PLLIN
EXTVCC
SGND
BOOST
INTVCC INTVCC
BG
PGND
VOSNS+
VOSNS–
CIN2
10µF
×5
CVIN
0.1µF
CIN1
100µF
35V
+
+
LOAD CURRENT (A)
0.1
40
EFFICIENCY (%)
80
90
100
1 10 100
3833 F10b
70
60
50
VIN = 12V
VOUT = 3.3V
FORCED
CONTINUOUS
MODE
PULSE-SKIPPING
MODE
LTC3833
34
3833f
PACKAGE DESCRIPTION
UDC Package
20-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1742 Rev Ø)
3.00 ± 0.10 1.50 REF
4.00 ± 0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
19 20
1
2
BOTTOM VIEW—EXPOSED PAD
2.50 REF
0.75 ± 0.05
R = 0.115
TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UDC20) QFN 1106 REV Ø
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
2.50 REF
3.10 ± 0.05
4.50 ± 0.05
1.50 REF
2.10 ± 0.05
3.50 ± 0.05
PACKAGE OUTLINE
R = 0.05 TYP
1.65 ± 0.10
2.65 ± 0.10
1.65 ± 0.05
2.65 ± 0.05
0.50 BSC
LTC3833
35
3833f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev H)
Exposed Pad Variation CB
FE20 (CB) TSSOP REV H 0910
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10
111214 13
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
3.86
(.152)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
LTC3833
36
3833f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010
LT 1010 • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
High Frequency 5.5V, 4A, 2MHz Step-Down Converter
RDIV1
100k
RDIV2
26.1k
VIN
VOUT
EXTVCC
VRNG
RUN
SENSE–
SENSE+
RPGD
100k
INTVCC
RITH
20k
RT
18.2k
CSS
0.1µF
CITH1
220pF
LTC3833
RFB2
165k
CFF
22pF
RFB1
20k
COUT1
22µF
×2
L1
1.2µH
RSENSE
10mΩ
TG
CB 0.1µF
CIN1
47µF
35V
3833 TA05
VIN
7V TO 14V
VOUT
5.5V
4A
CIN2
4.7µF
×2
CVCC
4.7µF
DB
TRACK/SS
ITH
RT
MODE/PLLIN
PGOOD
SGND
BOOST
SW
INTVCC INTVCC
BG
PGND
VOSNS+
VOSNS–
RVIN
2.2Ω
RF1
10Ω
RF2
10Ω
CVIN
0.1µF
MT
MB
CF
1000pF
CIN1: KEMET T521X476M035ATE070
DB: DIODES, INC. SDM10K45
L1: WURTH 744313120
MT, MB: INFINEON BSC093N04LS
+
PART NUMBER DESCRIPTION COMMENTS
LTC3878/LTC3879 No RSENSE™ Constant On-Time Synchronous Step-Down
DC/DC Controller
Very Fast Transient Response, tON(MIN) = 43ns, 4V ≤ VIN ≤ 38V,
0.6V ≤ VOUT ≤ 0.9VIN, SSOP-16, MSOP-16E, 3mm × 3mm QFN-16
LTC3775 High Frequency Synchronous Voltage Mode Step-Down
DC/DC Controller
Very Fast Transient Response, tON(MIN) = 30ns, 4V ≤ VIN ≤ 38V,
0.6V ≤ VOUT ≤ 0.8VIN, MSOP-16E, 3mm × 3mm QFN-16
LTC3854 Small Footprint Synchronous Step-Down DC/DC Controller Fixed 400kHz Operating Frequency 4.5V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 5.25V, 2mm × 3mm QFN-12
LTC3851A/LTC3851A-1 No RSENSE Wide VIN Range Synchronous Step-Down
DC/DC Controller
Phase-Lockable Fixed Frequency 250kHz to 750kHz, 4V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 5.25V, MSOP-16E, 3mm × 3mm QFN-16, SSOP-16
LTC3891 60V, Low IQ Synchronous Step-Down DC/DC Controller PLL Capable Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V,
0.8V ≤ VOUT ≤ 24V, IQ = 50µA
LTC3856 2-Phase, Single Output Synchronous Step-Down
DC/DC Controller with Diff Amp and DCR Temperature
Compensation
Phase-Lockable Fixed 250kHz to 770kHz Frequency,
4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 5.25V
LTC3829 3-Phase, Single Output Synchronous Step-Down
DC/DC Controller with Diff Amp and DCR Temperature
Compensation
Phase-Lockable Fixed 250kHz to 770kHz Frequency,
4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 5.25V
LTC3855 2-Phase, Dual Output Synchronous Step-Down DC/DC
Controller with Differential Remote Sense
Phase-Lockable Fixed Frequency 250kHz to 770kHz,
4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 12.5V
LTC3850/LTC3850-1 2-Phase, Dual Output Synchronous Step-Down DC/DC
Controllers, RSENSE or DCR Current Sensing
Phase-Lockable Fixed Frequency 250kHz to 780kHz, 4V ≤ VIN ≤ 30V,
0.8V ≤ VOUT ≤ 5.25V, 4mm × 4mm QFN-28, 4mm × 5mm QFN-28,
SSOP-28
LTC3853 Triple Output, Multiphase Synchronous Step-Down DC/DC
Controller, RSENSE or DCR Current Sensing
Phase-Lockable Fixed Frequency 250kHz to 750kHz, 4V ≤ VIN ≤ 24V,
VOUT Up to 13.5V
Efficiency
LOAD CURRENT (A)
20
50
40
30
90
80
70
60
3833 TA05b
EFFICIENCY (%)
0.1 10
1
VIN = 12V
VOUT = 5.5V
FORCED
CONTINUOUS
MODE
PULSE-
SKIPPING
MODE
