LTC2387-18 18-Bit, 15Msps SAR ADC Features Description 15Msps Throughput Rate nn No Pipeline Delay, No Cycle Latency nn 95.7dB SNR (Typ) at f = 1MHz IN nn 102dB SFDR (Typ) at f = 1MHz IN nn Nyquist Sampling Up to 7.5MHz Input nn Guaranteed 18-Bit, No Missing Codes nn 3LSB INL (Max) nn 8.192V P-P Differential Inputs nn 5V and 2.5V Supplies nn Internal 20ppm/C (Max) Reference nn Serial LVDS Interface nn 125mW Power Dissipation nn 32-Pin (5mm x 5mm) QFN Package The LTC(R)2387-18 is a low noise, high speed, 18-bit 15Msps successive approximation register (SAR) ADC ideally suited for a wide range of applications. The combination of excellent linearity and wide dynamic range makes the LTC2387-18 ideal for high speed imaging and instrumentation applications. No latency operation provides a unique solution for high speed control loop applications. The very low distortion at high input frequencies enables communications applications requiring wide dynamic range and significant signal bandwidth. nn To support high speed operation while minimizing the number of data lines, the LTC2387-18 features a serial LVDS digital interface. The LVDS interface has one-lane and two-lane output modes, allowing the user to optimize the interface data rate for each application. Applications L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7705765, 8232905, 8810443. Other patents are pending. High Speed Data Acquisition nn Imaging nn Communications nn Control Loops nn Instrumentation nn ATE nn Typical Application FFT, fSMPL = 15Msps, fIN = 2kHz 5V 2.5V 0.1F 0 2.5V 0.1F fIN = 2kHz SNR = 96.0dB THD = -117dB SINAD = 95.7dB SFDR = 119dB -20 0.1F 24.9 4.096V 0V 4.096V 0V OVDD CLK DCO DA DB IN+ + - VDDL 82pF LTC2387-18 82pF 24.9 TWOLANES TESTPAT PD IN- VCM 0.1F REFBUF REFGND LVDS INTERFACE REFIN GND CNV -60 -80 -100 -120 SAMPLE CLOCK -140 -160 0.1F 10F AMPLITUDE (dBFS) -40 VDD 238718 TA01a 0 2.5 5 FREQUENCY (MHz) 7.5 238718 TA01b 238718fa For more information www.linear.com/LTC2387-18 1 LTC2387-18 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) TWOLANES GND CNV- CNV+ GND VDDL VCM VDDL TOP VIEW Supply Voltage (VDD)...................................................6V Supply Voltage (VDDL, OVDD)....................................2.8V Analog Input Voltage (Note 3) IN+, IN-..........................(GND - 0.3V) to (VDD + 0.3V) REFBUF..........................(GND - 0.3V) to (VDD + 0.3V) REFIN (Note 4)............................(GND - 0.3V) to 2.8V Digital Input Voltage (Note 3) PD, TESTPAT.............. (GND - 0.3V) to (OVDD + 0.3V) CLK+, CLK-................. (GND - 0.3V) to (OVDD + 0.3V) TWOLANES, CNV+, CNV-............................(GND - 0.3V) to (VDDL + 0.3V) Power Dissipation............................................... 500mW Operating Temperature Range LTC2387C................................................. 0C to 70C LTC2387I..............................................-40C to 85C Storage Temperature Range................... -65C to 150C 32 31 30 29 28 27 26 25 GND 1 24 CLK+ + 2 23 CLK- IN- 3 IN 22 OVDD GND 4 21 GND 33 GND REFGND 5 20 DCO+ REFGND 6 19 DCO- REFBUF 7 18 DA+ REFBUF 8 17 DA- DB+ DB - TESTPAT PD VDD VDD GND REFIN 9 10 11 12 13 14 15 16 UH PACKAGE 32-LEAD (5mm x 5mm) PLASTIC QFN TJMAX = 125C, JA = 34C/W EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2387CUH-18#PBF LTC2387CUH-18#TRPBF 238718 32-Lead (5mm x 5mm) Plastic QFN 0C to 70C LTC2387IUH-18#PBF LTC2387IUH-18#TRPBF 238718 32-Lead (5mm x 5mm) Plastic QFN -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS VIN + Absolute Input Range (IN+) VIN- Absolute Input Range (IN-) VIN+ - VIN- Input Differential Voltage Range VINCM Common Mode Input Range IIN Analog Input DC Leakage Current CIN Analog Input Capacitance Sample Mode Hold Mode 20 2 pF pF CMRR Input Common Mode Rejection Ratio fIN = 1MHz 75 dB 2 MIN TYP MAX UNITS (Note 6) l -0.1 VREFBUF + 0.1 V (Note 6) l -0.1 VREFBUF + 0.1 V VIN+ - VIN- (VIN+ + VIN-)/2 l -VREFBUF l VREFBUF/2 - 0.1 l -1 VREFBUF/2 VREFBUF V VREFBUF/2 + 0.1 V 1 A 238718fa For more information www.linear.com/LTC2387-18 LTC2387-18 Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN MAX UNITS l 18 Bits No Missing Codes l 18 Bits l -3 l l Transition Noise INL Integral Linearity Error DNL Differential Linearity Error ZSE Zero-Scale Error 1.4 REFBUF = 4.096V (Notes 7, 9) (Note 8) LSBRMS 0.6 3 -0.9 0.2 0.9 LSB -16 1.5 16 LSB Zero-Scale Error Drift FSE TYP Resolution 0.02 Full-Scale Error REFBUF = 4.096V (REFBUF Overdriven) (Notes 8, 9) REFIN = 2.048V (REFIN Overdriven) (Note 8) Full-Scale Error Drift REFBUF = 4.096V (REFBUF Overdriven) (Note 9) REFIN = 2.048V (REFIN Overdriven) l l -25 -160 5 25 LSB LSB/C 25 160 0.1 1.5 LSB LSB ppm/C ppm/C Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and AIN = -1dBFS. (Notes 5, 10) SYMBOL PARAMETER CONDITIONS MIN TYP SINAD Signal-to-(Noise + Distortion) Ratio fIN = 2kHz fIN = 1MHz fIN = 5MHz SNR Signal-to-Noise Ratio THD l l 93 92.6 95.7 94.5 83 dB dB dB fIN = 2kHz fIN = 1MHz fIN = 5MHz l l 93.2 93 96 95.7 94.6 dB dB dB Total Harmonic Distortion (First Five Harmonics) fIN = 2kHz fIN = 1MHz fIN = 5MHz l l SFDR Spurious Free Dynamic Range fIN = 2kHz fIN = 1MHz fIN = 5MHz l l -117 -101 -83 103 97 -3dB Input Bandwidth MAX UNITS -103 -96 dB dB dB 119 102 84 dB dB dB 200 MHz Internal Reference Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VREFIN Internal Reference Output Voltage IOUT = 0A 2.043 2.048 2.053 V VREFIN Temperature Coefficient (Note 11) 5 20 l REFIN Output Impedance VREFIN Line Regulation VDD = 4.75V to 5.25V REFIN Input Voltage Range (REFIN Overdriven) (Note 6) l 2.008 ppm/C 15 k 0.3 mV/V 2.048 2.088 V 238718fa For more information www.linear.com/LTC2387-18 3 LTC2387-18 Reference Buffer Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Buffer Output Voltage VREFIN = 2.048V l 4.090 4.096 4.102 V REFBUF Input Voltage Range (REFBUF Overdriven) (Notes 6, 9) l 4.016 4.096 4.176 V IREFBUF REFBUF Load Current VREFBUF = 4.096V (REFBUF Overdriven) (Notes 9, 12) VREFBUF = 4.096V, Sleep Mode (REFBUF Overdriven) (Note 9) l 1.6 0.5 1.8 VCM Common Mode Output VREFBUF = 4.096V, IOUT = 0A l 2.048 2.068 VCM Output Impedance -1mA < IOUT < 1mA VREFBUF 2.028 mA mA V 15 Digital Inputs and Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PD, TESTPAT, TWOLANES VIH High Level Input Voltage VDDL = OVDD = 2.5V l VIL Low Level Input Voltage VDDL = OVDD = 2.5V l IIN Digital Input Current VIN = 0V to 2.5V l CIN Digital Input Capacitance 1.7 V -10 0.6 V 10 A 3 pF CNV+, Single-Ended Convert Start Mode (CNV- Tied to GND) VIH High Level Input Voltage VDDL = 2.5V l VIL Low Level Input Voltage VDDL = 2.5V l CIN Digital Input Capacitance 1.7 V 0.6 V 2 pF CNV+/CNV-, Differential Convert Start Mode VID Differential Input Voltage VICM Common Mode Input Voltage (Note 13) l 175 350 650 mV l 0.8 1.25 1.7 V l 175 350 650 mV l 0.8 1.25 1.7 V mV CLK+/CLK- (LVDS Clock Input) VID Differential Input Voltage VICM Common Mode Input Voltage (Note 13) DCO+/DCO-, DA+/DA-, DB+/DB- (LVDS Outputs) VOD Differential Output Voltage 100 Differential Load l 247 350 454 VOS Common Mode Output Voltage 100 Differential Load l 1.125 1.25 1.375 V Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Supply Voltage (Note 6) l 4.75 5 5.25 V VDDL Supply Voltage (Note 6) l 2.375 2.5 2.625 V OVDD Supply Voltage (Note 6) l 2.375 2.5 2.625 V IVDD IVDDL IOVDD IPOWERDOWN IPOWERDOWN Supply Current Supply Current Supply Current Power-Down Mode Current Power-Down Mode Current 15Msps Sample Rate 15Msps Sample Rate 15Msps Sample Rate Power-Down Mode (IVDD) Power-Down Mode (IVDDL + IOVDD) l l l l l 5 31.4 8.8 1 2 6 35 10.3 20 250 mA mA mA A A PD Power Dissipation Power-Down Mode 15Msps Sample Rate Power-Down Mode (IVDD + IVDDL + IOVDD) l l 125 10 144 725 mW W IDIFFCNV Increase in IVDDL with Differential CNV Mode Enabled (No Increase During Power-Down) 2.1 ITWOLANE Increase in IOVDD with Two-Lane Mode Enabled (No Increase During Power-Down) 3.6 4 mA mA 238718fa For more information www.linear.com/LTC2387-18 LTC2387-18 ADC Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN fSMPL Sampling Frequency l 0.02 tCONV CNV to Output Data Ready l 54 tACQ Acquisition Time tCYC Time Between Conversions tCNVH CNV High Time tCNVL CNV Low Time TYP 58 MAX UNITS 15 Msps 63 tCYC - 39 ns ns l 66.6 (Note 13) l 50,000 ns 5 ns (Note 13) l 8 ns 65 tFIRSTCLK CNV to First CLK from the Same Conversion (Note 13) l tLASTCLK CNV to Last CLK from the Previous Conversion (Note 13) l tCLKH CLK High Time l 1.25 ns tCLKL CLK Low Time l 1.25 ns tCLKDCO CLK to DCO Delay (Note 13) l 0.7 1.3 2.3 ns tCLKD CLK to DA/DB Delay (Note 13) l 0.7 1.3 2.3 ns tSKEW DCO to DA/DB skew tCLKD - tCLKDCO (Note 13) l -200 0 200 ps tAP Sampling Delay Time (Note 13) 0 tJITTER Sampling Delay Jitter (Note 13) 0.25 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground or above VDD, VDDL or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above VDD, VDDL or OVDD without latchup. Note 4: When this pin voltage is taken below ground, it will be clamped by an internal diode. When this pin voltage is taken above VDDL, it is clamped by a diode in series with a 2k resistor. This product can handle input currents up to 100mA below ground without latchup. Note 5: VDD = 5V, VDDL = 2.5V, OVDD = 2.5V, fSMPL = 15MHz, REFIN = 2.048V, single-ended CNV, one-lane output mode unless otherwise noted. Note 6: Recommended operating conditions. ns 49 ns ns psRMS Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Zero-scale error is the offset voltage measured from -0.5LSB when the output code flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Full-scale error is the worst-case deviation of the first and last code transitions from ideal and includes the effect of offset error. Note 9: When REFBUF is overdriven, the internal reference buffer must be turned off by setting REFIN = 0V. Note 10: All specifications in dB are referred to a full-scale VREFBUF differential input. Note 11: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 12: fSMPL = 15MHz, IREFBUF varies linearly with sample rate. Note 13: Guaranteed by design, not subject to test. 238718fa For more information www.linear.com/LTC2387-18 5 LTC2387-18 Typical Performance Characteristics TA = 25C, VDD = 5V, VDDL = 2.5V, OVDD = 2.5V, REFIN = 2.048V, fSMPL = 15Msps, unless otherwise noted. 2.0 6.0 1.0 1.5 4.5 0.8 1.0 3.0 0.5 0 -0.5 1.5 0 -1.5 -1.0 -3.0 -1.5 -4.5 -2.0 -6.0 0 65536 131072 196608 OUTPUT CODE 262144 0.6 0.2 0.0 -0.2 -0.4 -0.6 -0.8 0 65536 131072 196608 OUTPUT CODE 238718 G01a -1.0 262144 60000 -40 20000 0 SNR = 96.0dB THD = -117dB SINAD = 95.7dB SFDR = 119dB -40 -60 -80 -100 N+6 N+5 N+4 N+3 N+2 N N+1 N-1 N-2 N-3 N-4 N-5 N-6 OUTPUT CODE -160 -80 -100 -140 -140 0 -60 -120 -120 10000 262144 SNR = 95.8dB THD = -109dB SINAD = 95.6dB SFDR = 109dB -20 AMPLITUDE (dBFS) -20 AMPLITUDE (dBFS) 70000 30000 131072 196608 OUTPUT CODE 32k Point FFT fSMPL = 15Msps, fIN = 200kHz 0 80000 40000 65536 238718 G02 32k Point FFT fSMPL = 15Msps, 2kHz fINfIN= =2kHz 50000 0 238718 G01b DC Histogram COUNTS 0.4 DNL ERROR (LSB) INL ERROR (ppm) INL ERROR (LSB) Differential Nonlinearity vs Output Code Integral Nonlinearity vs Output Code (ppm) Integral Nonlinearity vs Output Code (LSB) -160 0 238718 G03 2.5 5 FREQUENCY (MHz) 7.5 0 2.5 5.0 FREQUENCY (MHz) 7.5 238718 G05 238718 G04 SNR = 95.6dB THD = -103dB SINAD = 94.6dB SFDR = 104dB -20 -60 -80 -100 -40 -100 -140 -140 0 2.5 5 FREQUENCY (MHz) 7.5 238718 G06 6 94.0 -80 -120 -160 SNR 96.0 -60 -120 -160 SNR, SINAD vs Input Frequency 98.0 SNR = 94.6dB THD = -83dB SINAD = 83dB SFDR = 84dB -20 AMPLITUDE (dBFS) -40 AMPLITUDE (dBFS) 0 32k Point FFT fSMPL = 15Msps, fIN IN = 5MHz SNR, SINAD (dBFS) 0 32k Point FFT fSMPL = 15Msps, fIN = 1MHz 92.0 SINAD 90.0 88.0 86.0 84.0 82.0 80.0 0 2.5 5 FREQUENCY (MHz) 7.5 238718 G07 78.0 0.01 0.1 1 FREQUENCY (MHz) 10 238718 G08 238718fa For more information www.linear.com/LTC2387-18 LTC2387-18 Typical Performance Characteristics TA = 25C, VDD = 5V, VDDL = 2.5V, OVDD = 2.5V, REFIN = 2.048V, fSMPL = 15Msps, unless otherwise noted. THD vs Input Frequency and Amplitude -1dBFS -3dBFS -6dBFS -10dBFS -80 SFDR vs Input Level, fIN = 2kHz IN 150 dBFS 130 -100 -110 -120 110 dBc 100 120 90 80 110 90 80 70 60 60 0.1 1 FREQUENCY (MHz) 50 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 10 238718 G09 dBc 100 70 -140 0.01 dBFS 130 120 -130 vs Input Level, fIN = 1MHz fSFDR IN = 1MHz 140 140 SFDR (dBFS, dBc) -90 THD (dBFS) 150 SFDR (dBFS, dBc) -70 50 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 0 238718 G11 238718 G10 SNR SINAD THD, HARMONICS (dBFS) 97 SNR, SINAD (dBFS) -110 96 95 94 2kHz, -1dBFS -1dBFS ffIN IN == 2kHz, THD 2ND 3RD MAX INL MAX DNL MIN DNL MIN INL 0.75 -115 -120 -125 93 0.50 0.25 0 -0.25 -0.50 -0.75 92 -40 -20 0 20 40 TEMPERATURE (C) 60 80 -130 -40 -20 238718 G12 0 20 40 TEMPERATURE (C) 60 80 -1.00 -40 Full-Scale Error vs Temperature, Zero-Scale Error Error vs vs Temperature Temperature Zero-Scale 4 30 -2 - FS 2 0 -2 -4 -4 -6 -40 SUPPLY CURRENT (mA) 4 ZERO-SCALE ERROR (LSB) 35 0 -20 0 20 40 TEMPERATURE (C) 60 80 238718 G15 60 -6 -40 80 Supply Current vs Temperature 6 + FS 0 20 40 TEMPERATURE (C) 238718 G14 6 2 -20 238718 G13 REFBUF = 4.096V FULL-SCALE ERROR (LSB) INL/DNL vs Temperature 1.00 INL/DNL ERROR (LSB) 98 THD, Harmonics vs Temperature, SNR, SINAD vs Temperature, fIN IN = 2kHz, -1dBFS 0 25 20 IVDDL IVDD IOVDD 15 10 5 -20 0 20 40 TEMPERATURE (C) 60 80 238718 G16 0 -40 -20 0 20 40 TEMPERATURE (C) 60 80 238718 G17 238718fa For more information www.linear.com/LTC2387-18 7 LTC2387-18 Typical Performance Characteristics REFIN = 2.048V, fSMPL = 15Msps, unless otherwise noted. Analog Input Current Differential Input Voltage vs Differential Input Voltage 35 1.00 30 0.75 25 IVDDL IVDD IOVDD 15 10 5 0 5 10 SAMPLE RATE (Msps) 15 THREE TYPICAL UNITS IN- 0.25 0 -0.25 -0.50 2.050 fSMPL = 15Msps 0.50 -0.75 0 Internal Reference Output vs Temperature REFERENCE OUTPUT (V) ANALOG INPUT CURRENT (mA) SUPPLY CURRENT (mA) Supply Current vs Sample Rate 20 TA = 25C, VDD = 5V, VDDL = 2.5V, OVDD = 2.5V, 2.049 2.048 IN+ -1.00 -4.096 -2.048 0 2.048 DIFFERENTIAL INPUT (V) 4.096 238718 G19 238718 G18 2.047 -40 -20 0 20 40 TEMPERATURE (C) 60 80 238718 G20 Pin Functions GND (Pins 1, 4, 10, 21, 26, 29 ): Ground. Connect to a solid ground plane in the PCB underneath the ADC. IN+, IN- (Pins 2, 3): Positive and Negative Differential Analog Inputs. The inputs must be driven differentially and 180 out of phase, with a common mode voltage of 2.048V. The differential input range is 4.096V (each input pin swings from 0V to 4.096V.) REFGND (Pins 5, 6): Reference Ground. The two pins should be shorted together and connected to the reference bypass capacitor with a short, wide trace. In addition, connect the pins to the exposed pad (Pin 33). A suggested layout is shown in the ADC Reference section of the data sheet. 8 REFBUF (Pins 7, 8): Internal Reference Buffer Output. The output voltage of the internal 2x gain reference buffer, nominally 4.096V, is provided on this pin. The two pins should be shorted together and bypassed to REFGND with a 10F (X7R, 0805 size) ceramic capacitor. If the internal buffer is not required, tie REFIN to GND to power down the buffer and connect an external 4.096V reference to REFBUF. REFIN (Pin 9): Internal Reference Output/Reference Buffer Input. The output voltage of the internal reference, nominally 2.048V, is output on this pin. An external reference can be applied to REFIN if a more accurate reference is required. For increased filtering of reference noise, bypass this pin to GND using a 0.1F or larger ceramic capacitor. If the internal reference buffer is not used, tie REFIN to GND to power down the buffer and connect an external buffered reference to REFBUF. 238718fa For more information www.linear.com/LTC2387-18 LTC2387-18 Pin Functions VDD (Pins 11, 12): 5V Analog Power Supply. The range of VDD is 4.75V to 5.25V. The two pins should be shorted together and bypassed to GND with 0.1F and 10F ceramic capacitors. PD (Pin 13): Digital input that enables power-down mode. When PD is low, the LTC2387 enters power-down mode, and all circuitry (including the LVDS interface) is shut down. When PD is high, the part operates normally. Logic levels are determined by OVDD. TESTPAT (Pin 14): Digital input that forces the LVDS data outputs to be a test pattern. When TESTPAT is high, the digital outputs are a test pattern. When TESTPAT is low, the digital outputs are the ADC conversion result. Logic levels are determined by OVDD. DB-/DB+, DA-/DA+ (Pins 15/16, 17/18): Serial LVDS Data Outputs. In one-lane output mode, DB-/DB+ are not used and their LVDS driver is disabled to reduce power consumption. DCO-/DCO+ (Pins 19/20): LVDS Data Clock Output. This is an echoed version of CLK-/CLK+ that can be used to latch the data outputs. OVDD (Pin 22): 2.5V Output Power Supply. The range of OVDD is 2.375V to 2.625V. Bypass to GND with a 0.1F ceramic capacitor. TWOLANES (Pin 25): Digital input that enables two-lane output mode. When TWOLANES is high (two-lane output mode), the ADC outputs two bits at a time on DA-/DA+ and DB-/DB+. When TWOLANES is low (one-lane output mode), the ADC outputs one bit at a time on DA-/DA+, and DB-/DB+ are disabled. Logic levels are determined by VDDL. CNV-/CNV+ (Pins 27/28): Conversion Start LVDS Input. A rising edge on CNV+ puts the internal sample-and-hold into the hold mode and starts a conversion cycle. CNV+ can also be driven with a 2.5V CMOS signal if CNV- is tied to GND. VDDL (Pins 30, 31): 2.5V Analog Power Supply. The range of VDDL is 2.375V to 2.625V. The two pins should be shorted together and bypassed to GND with 0.1F and 10F ceramic capacitors. VCM (Pin 32): Common Mode Output. VCM, nominally 2.048V, can be used to set the common mode of the analog inputs. Bypass to GND with a 0.1F ceramic capacitor close to the pin. If VCM is not used, the bypass capacitor is not necessary as long as the parasitic capacitance on the VCM pin is under 10pF. Exposed Pad (Pin 33): The exposed pad on the bottom of the package. Connect to the ground plane of the PCB using multiple vias. CLK-/CLK+ (Pins 23/24): LVDS Clock Input. This is an externally applied clock that serially shifts out the conversion result. 238718fa For more information www.linear.com/LTC2387-18 9 LTC2387-18 Functional Block Diagram VDD VDDL OVDD CNV CONTROL LOGIC TWOLANES TESTPAT PD CLK IN+ + IN- VCM SERIAL LVDS INTERFACE 18-BIT, 15Msps ADC - 0.5 2 GND REFGND REFBUF 15k DCO DA DB 2.048V REFERENCE REFIN 238718 BD 10 238718fa For more information www.linear.com/LTC2387-18 For more information www.linear.com/LTC2387-18 DA- DA+ DCO- DCO+ CLK- CLK+ CNV+ CNV- ANALOG INPUT tAP OUTPUT DATA FROM SAMPLE N-1 LOGIC 0 tFIRSTCLK tCONV D8 D7 D6 D5 D4 D3 D2 D1 D0 tCNVH SAMPLE N D17 tCYC 1 3 4 5 6 7 8 tLASTCLK 9 OUTPUT DATA FROM SAMPLE N 16 15 14 13 12 11 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 2 INPUT ACQUISITION tACQ SAMPLE N+1 One-Lane Output Mode LOGIC 0 D17 OUTPUT DATA FROM SAMPLE N+1 238718 TD01 16 15 14 13 12 11 10 D9 D8 D7 INPUT ACQUISITION LTC2387-18 Timing Diagram 238718fa 11 12 For more information www.linear.com/LTC2387-18 DB- DB+ DA- DA+ DCO- DCO+ CLK- CLK+ CNV+ CNV- ANALOG INPUT tAP OUTPUT DATA FROM SAMPLE N-1 14 12 10 D8 D6 D4 D2 D0 LOGIC 0 LOGIC 0 tFIRSTCLK tCONV 15 13 11 D9 D7 D5 D3 D1 tCNVH SAMPLE N D16 D17 tCYC 1 3 4 tLASTCLK 5 14 12 10 D8 D6 D4 D2 D0 15 13 11 D9 D7 D5 D3 D1 2 OUTPUT DATA FROM SAMPLE N INPUT ACQUISITION tACQ SAMPLE N+1 Two-Lane Output Mode LOGIC 0 LOGIC 0 D16 D17 238718 TD02 14 12 10 D8 15 13 11 D9 OUTPUT DATA FROM SAMPLE N+1 INPUT ACQUISITION LTC2387-18 Timing Diagram 238718fa LTC2387-18 Timing Diagram Data Output Timing tCLKH CLK- tCLKL CLK+ DCO- tCLKDCO tCLKDCO tCLKD tCLKD DCO+ DA- DA+ DB- DB+ 238718 TD03 Applications Information Overview Converter Operation The LTC2387-18 is a low noise, high speed, 18-bit successive approximation register (SAR) ADC. Operating from 5V and 2.5V supplies, the LTC2387-18 has a fully differential 4.096V input range, making it ideal for applications that require a wide dynamic range. The LTC2387-18 achieves 3LSB INL (maximum), no missing codes at 18-bits and 96dB SNR (typical). The LTC2387-18 operates in two phases. During the acquisition phase, the sample capacitors are connected to the analog input pins IN+ and IN- to sample the differential analog input voltage. A rising edge on the CNV pin initiates a conversion. During the conversion phase, the ADC is sequenced through a successive approximation algorithm, comparing the sampled input with binary-weighted fractions of the reference voltage (e.g. VREFBUF/2, VREFBUF/4 ... VREFBUF/262144) using a differential comparator. At the end of conversion, control logic prepares the 18-bit digital output code for serial transfer. The LTC2387-18 includes a precision internal 2.048V reference, with a guaranteed 0.25% initial accuracy and a 20ppm/C (maximum) temperature coefficient, as well as an internal reference buffer. The LTC2387-18 also has a high speed serial LVDS interface that can output one or two bits at a time. The fast 15Msps throughput with no pipeline latency makes the LTC2387-18 ideally suited for a wide variety of high speed applications. The LTC2387-18 dissipates only 125mW at 15Msps and has a power-down mode to reduce the power consumption to 10W during inactive periods. Transfer Function The LTC2387-18 digitizes the full-scale voltage of 2x REFBUF into 218 levels, resulting in an LSB size of 31.25V with REFBUF = 4.096V. The output data is in two's complement format. The ideal transfer function is shown in Figure 1. The ideal offset binary transfer function can be obtained from the two's complement transfer function by inverting the most significant bit (MSB) of each output code. 238718fa For more information www.linear.com/LTC2387-18 13 LTC2387-18 OUTPUT CODE (TWO'S COMPLEMENT) Applications Information The inputs draw a small current spike while charging the CSAMPLE capacitors during acquisition. This current spike is consistent and does not depend on the previously sampled input voltage. During conversion and power-down, the analog inputs draw only a small leakage current. 011...111 BIPOLAR ZERO 011...110 000...001 000...000 111...111 Input Drive Circuits 111...110 100...001 A low impedance source can directly drive the high impedance inputs of the LTC2387-18 without gain error. A high impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time is important even for DC signals because the ADC inputs draw a current spike when entering acquisition. FSR = +FS - -FS 1LSB = FSR/262144 100...000 -FSR/2 -1 0V 1 FSR/2 - 1LSB LSB LSB INPUT VOLTAGE (V) 238718 F01 Figure 1. LTC2387-18 Transfer Function Analog Inputs The LTC2387-18 has a fully differential 4.096V input range. The IN+ and IN- pins should be driven 180 degrees out-of-phase with respect to each other, centered around a common mode voltage (IN+ + IN-)/2 that is restricted to (VREFBUF/2 0.1V). The ADC samples and digitizes the voltage difference between the two analog input pins (IN+ - IN-), and any unwanted signal that is common to both inputs is reduced by the common mode rejection ratio (CMRR) of the ADC. The analog inputs can be modeled by the equivalent circuit shown in Figure 2. The diodes and 10 resistors at the input provide ESD and overdrive protection. In the acquisition phase, each input sees approximately 18pF (CSAMPLE) from the sampling capacitor in series with 28 (RON) from the on-resistance of the sampling switch. CPAR is a lumped capacitance on the order of 2pF formed primarily of diode junctions. VDD IN+ 10 28 CSAMPLE 18pF CPAR 2pF BIAS VOLTAGE VDD IN- 10 28 CSAMPLE 18pF CPAR 2pF 238718 F02 Figure 2. Equivalent Circuit for the Differential Analog Inputs of the LTC2387-18 14 For best performance, a buffer amplifier should be used to drive the analog inputs of the LTC2387-18. The amplifier provides low output impedance enabling fast settling of the analog signal during the acquisition phase. It also provides isolation between the signal source and the current spike drawn by the ADC inputs when entering acquisition. The LTC2387-18 is optimized for pulsed inputs that are fully settled when sampled, or dynamic signals up to the Nyquist frequency (7.5MHz). Input signals that change faster than 300mV/ns when they are sampled are not recommended. This is equivalent to an 8VP-P sine wave at 12MHz. Input Filtering The noise and distortion of the buffer amplifier and other supporting circuitry must be considered since they add to the ADC noise and distortion. A buffer amplifier with low noise density must be selected to minimize SNR degradation. A filter network should be placed between the buffer output and ADC input to both minimize the noise contribution of the buffer and reduce disturbances reflected into the buffer from ADC sampling transients. A simple one-pole lowpass RC filter is sufficient for many applications. It is important that the RC time constant of this filter be small enough to allow the analog inputs to settle within the ADC acquisition time (tACQ), as insufficient settling can limit INL and THD performance. High quality capacitors and resistors should be used in the RC filters since these components can add distortion. 238718fa For more information www.linear.com/LTC2387-18 LTC2387-18 Applications Information NPO type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self-heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Figure 3 shows a typical input drive circuit with an RC filter. The optimal values for R and C are application-specific and may require experimentation. Setting R = 24.9 gives good performance over a wide range of conditions. 4.096V 24.9 0V CFILT IN+ LTC2387-18 4.096V CFILT 0V IN - 238718 F03 24.9 Figure 3. Typical Input Drive Circuit The value for CFILT involves a trade off: larger values give better noise, and smaller values give better full-scale error. Figure 4 shows a range of capacitor values to consider as a starting point based on the sample rate. 400 350 MAX VALUE (LOWER NOISE) CFILT (pF) 300 250 200 150 100 50 MIN VALUE (LOWER FULL-SCALE ERROR) 9 10 11 12 13 SAMPLE RATE (Msps) 14 15 238718 F04 Figure 4. Suggested Range of CFILT Values vs Sample Rate Input Currents One of the biggest challenges in coupling an amplifier to the LTC2387-18 is in dealing with current spikes drawn by analog inputs at the start of each acquisition phase. The analog inputs may be modeled as a switched capacitor load on the drive circuit. A drive circuit may rely partially on attenuating switched-capacitor current spikes with small filter capacitors placed directly at the ADC inputs and partially on the driver amplifier having sufficient bandwidth to recover from the residual disturbance. Amplifiers optimized for DC performance may not have sufficient bandwidth to fully recover at the ADC's maximum conversion rate, which can produce nonlinearity and other errors. Coupling filter circuits may be classified in two broad categories: Fully Settled - This case is characterized by filter time constants and an overall settling time that are considerably shorter than the sample period. When acquisition begins, the coupling filter is disturbed. For a typical first order RC filter, the disturbance will look like an initial step with an exponential decay. The amplifier will have its own response to the disturbance, which may include ringing. If the input settles completely (to within the accuracy of the LTC2387-18), the disturbance will not contribute any error. Partially Settled - In this case, the beginning of acquisition causes a disturbance of the coupling filter, which then begins to settle out towards the nominal input voltage. However, acquisition ends (and the conversion begins) before the input settles to its final value. This generally produces a gain error, but as long as the settling is linear, no distortion is produced. The coupling filter's response is affected by the amplifier's output impedance and other parameters. A linear settling response to fast switchedcapacitor current spikes can NOT always be assumed for precision, low bandwidth amplifiers. The coupling filter serves to attenuate the current spikes' high-frequency energy before it reaches the amplifier. 238718fa For more information www.linear.com/LTC2387-18 15 LTC2387-18 Applications Information ADC Reference REFIN The internal reference circuitry of the LTC2387-18 is shown in Figure 5. There is a low noise, low drift (20ppm/C), bandgap reference connected to REFIN (Pin 9). An internal reference buffer gains the REFIN voltage by 2x to 4.096V at REFBUF (Pins 7, 8). The voltage difference between REFBUF and REFGND determines the full-scale input range of the ADC. The reference and reference buffer can also be externally driven if desired. LTC2387-18 9 8 15k REFIN REFBUF 2.048V REFERENCE 2x 0.1F REFBUF REFBUF 10F REFGND REFGND 238718 F06 Figure 6. Configuration for Using the Internal Reference Figure 7 shows a suggested layout for the REFBUF capacitor. The capacitor should be connected to REFBUF and REFGND through short, wide traces. REFGND should also be connected with a wide trace to the grounded exposed pad (Pin 33). 7 8k LTC2387-18 1 ADC CORE 2 6 3 4 5 5 REFGND 6 7 238718 F05 Figure 5. LTC2387-18 Internal Reference Circuitry 8 9 10 11 12 Internal Reference with Internal Reference Buffer To use the internal reference and internal reference buffer, bypass REFIN to GND with a 0.1F ceramic capacitor (Figure 6). Bypass REFBUF to REFGND with a single 10F (X7R, 0805 size) ceramic capacitor. The REFBUF capacitor should be as close as possible to the LTC2387-18 package to minimize wiring inductance. Do not place this capacitor on the opposite side of the board. Adding a second, smaller capacitor in parallel with the 10F may degrade performance and is not recommended. 16 238718 F07 Figure 7. Suggested REFBUF Bypass Capacitor Layout 238718fa For more information www.linear.com/LTC2387-18 LTC2387-18 Applications Information External Reference with Internal Reference Buffer REFIN If more accuracy and/or lower drift is desired, REFIN can be directly overdriven by an external 2.048V reference as shown in Figure 8. Linear Technology offers a portfolio of high performance references designed to meet the needs of many applications. With its small size, low power, and high accuracy, the LTC6655-2.048 is well suited for use with the LTC2387-18 when overdriving the internal reference. The LTC6655-2.048 offers 0.025% (max) initial accuracy and 2ppm/C (max) temperature coefficient for high precision applications. Bypassing the LTC6655-2.048 with a 2.7F to 10F ceramic capacitor close to the REFIN pin is recommended. LTC6655-2.048 5V 0.1F VIN VOUT_F SHDN VOUT_S GND REFIN 2.7F LTC2387-18 REFBUF REFBUF 10F REFGND REFGND 238718 F08 Figure 8. Using the LTC6655-2.048 as an External Reference External Reference Buffer The internal reference buffer can also be overdriven with an external 4.096V reference at REFBUF as shown in Figure 9. To do so, REFIN must be grounded to disable the reference buffer. The external reference must have a fast transient response and be able to drive the 0.5mA to 1.6mA load at the REFBUF pin. The LTC6655-4.096 is recommended when overdriving REFBUF. LTC2387-18 LTC6655-4.096 5V VIN VOUT_F SHDN VOUT_S 0.1F GND REFBUF REFBUF 10F REFGND REFGND 238718 F09 Figure 9. Overdriving REFBUF Using the LTC6655-4.096 Common Mode Output The VCM pin is an output that provides one-half the voltage present on the REFBUF pin. This voltage can be used to set the common mode of a differential amplifier driving the analog inputs. Bypass VCM to GND with a 0.1F ceramic capacitor. If VCM is not used it can be left floating, but the parasitic capacitance on the pin needs to be under 10pF. The VCM output has 1/f noise which for most driver circuits will be removed by the ADC common mode rejection ratio. VCM is not recommended for single-ended to differential circuits that pass the VCM noise to only one ADC input. Dynamic Performance Fast Fourier Transform (FFT) techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. The LTC2387-18 provides guaranteed tested limits for both AC distortion and noise measurements. 238718fa For more information www.linear.com/LTC2387-18 17 LTC2387-18 Applications Information 0 Signal-to-Noise and Distortion Ratio (SINAD) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as: V22 + V32 + V42 +...+ Vn 2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. Figure 10 shows that the LTC2387-18 achieves a typical THD of -117dB at a 15MHz sampling rate with a 2kHz input. 18 -40 -60 -80 -100 -120 -140 -160 0 2.5 5 FREQUENCY (MHz) 7.5 238718 F10 The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 10 shows that the LTC2387-18 achieves a typical SNR of 96dB at a 15MHz sampling rate with a 2kHz input. THD=20log SNR = 96.0dB THD = -117dB SINAD = 95.7dB SFDR = 119dB -20 AMPLITUDE (dBFS) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies from above DC and below half the sampling frequency. Figure 10 shows that the LTC2387-18 achieves a typical SINAD of 95.7dB at a 15MHz sampling rate with a 2kHz input. fIN = 2kHz Figure 10. 32k Point FFT of the LTC238718, fSMPL = 15Msps, fIN = 2kHz Power Considerations The LTC2387-18 requires three power supplies: VDD (5V), VDDL (2.5V), and OVDD (2.5V). Bypass VDD to GND with a 0.1F ceramic capacitor close to the pair of pins and a 10F ceramic capacitor in parallel. Bypass VDDL to GND with a 0.1F ceramic capacitor close to the pair of pins and a 10F ceramic capacitor in parallel. OVDD can come from the same source as VDDL but it should be isolated by a ferrite bead and have its own 0.1F bypass capacitor. Power Supply Sequencing The LTC2387-18 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the Absolute Maximum Ratings section. The LTC2387-18 has a power-on-reset (POR) circuit that will reset the LTC2387-18 at initial power-up or whenever VDD or VDDL drops well below their minimum values. Once the supply voltage re-enters the nominal supply voltage range, the POR will reinitialize the ADC. 238718fa For more information www.linear.com/LTC2387-18 LTC2387-18 Applications Information When PD is pulled low, LTC2387-18 enters power-down mode. In this state, all internal functions, including the reference and LVDS outputs, are turned off and subsequent conversion requests are ignored. The power consumption drops to a typical value of 10W. This mode can be used if the LTC2387-18 is inactive for a long period of time and the user wants to minimize power dissipation. The amount of time required to recover from power-down mode depends on how REFBUF is configured. When using the internal reference buffer with a 10F bypass capacitor, the ADC will stabilize after 20ms. If REFBUF is externally driven, the recovery time can be significantly less. Timing and Control CNV Timing The LTC2387-18 conversion is controlled by the CNV+ and CNV- inputs. CNV+/CNV- can be driven directly with an LVDS signal. Alternatively, CNV+ can be driven with a 0V to 2.5V CMOS signal when CNV- is tied to GND. A rising edge on CNV+ will sample the analog inputs and start a conversion. The pulse width of CNV+ should meet the tCNVH and tCNVL specifications in the timing table. After the LTC2387-18 is powered on, or exits power-down mode, conversion data is invalid for the first two conversion cycles. Subsequent results are accurate as long as the time between conversions meets the tCYC specification. If the analog input signal has not completely settled when it is sampled, the ADC noise performance will be affected by jitter on the rising edge of CNV+. In this case the rising edge of CNV+ should be driven by a clean low jitter signal. Note that the ADC is less sensitive to jitter on the falling edge of CNV+. In applications that are insensitive to jitter, CNV can be driven directly from an FPGA. Internal Conversion Clock The LTC2387-18 has an internal clock that is trimmed to achieve a maximum conversion time of 63ns. With a typical acquisition time of 27.7ns, throughput performance of 15Msps is guaranteed. Digital Interface The LTC2387-18 has a serial LVDS digital interface that is easy to connect to an FPGA. Three LVDS pairs are required: CLK, DCO, and DA. A fourth LVDS pair, DB, is optional (Figure 11). LTC2387-18 CLK+ FPGA - + Power-Down Mode 100 CLK- DCO+ 100 + - 100 + - 100 + - DCO- DA+ DA- DB+ OPTIONAL DB- 238718 F11 Figure 11. Digital Output Interface to an FPGA 238718fa For more information www.linear.com/LTC2387-18 19 LTC2387-18 Applications Information The LVDS signals should be routed on the PC board as 100 differential transmission lines and terminated at the receiver with 100 resistors. Data must be clocked out after the current conversion is complete, and before the next conversion finishes. The valid time window for clocking out data is shown in Figure 13. Note that it is allowed to be still clocking out data when the next conversion begins. A conversion is started by the rising edge of CNV+. When the conversion is complete, the most-significant data bit is output on DA. Data is then ready to be shifted out by applying a burst of nine clock pulses to the CLK input. The data on DA is updated by every edge of CLK. An echoed version of CLK is output on DCO. The edges of DA and DCO are aligned, so DCO can be used to latch DA in the FPGA. The timing of a single conversion is shown in Figure 12. Two-Lane Output Mode At high sample rates the required LVDS interface data rate can reach >400Mbps. Most FPGAs can support this, but if a lower data rate is desired, the two-lane output mode can be used. When the TWOLANES input pin is tied high, CNV 1 2 3 4 5 6 7 8 9 CLK DCO tCONV DA D17 16 15 14 13 12 11 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB 238718 F12 Figure 12. Timing Diagram for a Single Conversion in One-Lane Mode CONVERSION N CONVERSION N+1 CNV tFIRSTCLK tLASTCLK 1 2 3 4 5 6 7 8 9 CLK TIME WINDOW FOR CLOCKING OUT CONVERSION N 238718 F13 Figure 13. Valid Time Window for Clocking Out Data 20 238718fa For more information www.linear.com/LTC2387-18 LTC2387-18 Applications Information the optional LVDS output DB is enabled, and data is output two bits at a time on DA and DB. Enabling the DB output increases the supply current from OVDD by about 3.6mA. In two-lane mode, five clock pulses are required for CLK (see Timing Diagrams). Output Test Patterns To allow in-circuit testing of the digital interface to the ADC, there is a test mode that forces the ADC data outputs to known values: One-Lane Mode: 10 1000 0001 1111 1100 Two-Lane Mode: 11 0011 0000 1111 1100 The test pattern is enabled when the TESTPAT pin is brought high. (except for REFBUF). The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. Of particular importance is the capacitor between REFBUF and REFGND, which should be a 10F (X7R, 0805 size) ceramic capacitor. This capacitor should be on the same side of the circuit board as the ADC, and as close to the device as possible. Adding a second, smaller capacitor in parallel with the 10F may degrade performance and is not recommended. The analog inputs, convert start, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. Exposed Package Pad Board Layout The LTC2387-18 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane in the first layer beneath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VDDL, OVDD, VCM, REFIN, and REFBUF pins. Bypass capacitors must be located as close to the pins as possible. Size 0402 ceramic capacitors are recommended For good electrical and thermal performance, the exposed pad on the bottom of the package must be soldered to a large grounded pad on the PC board. This pad should be connected to the internal ground planes by an array of vias. Mechanical Stress Shift The mechanical stress of mounting a part to a board can cause subtle changes to the SNR and internal voltage reference. The best soldering method is to use IR reflow or convection soldering with a controlled temperature profile. Hand soldering with a heat gun or a soldering iron is not recommended. 238718fa For more information www.linear.com/LTC2387-18 21 LTC2387-18 Package Description Please refer to http://www.linear.com/product/LTC2387-18#packaging for the most recent package drawings. UH Package 32-Lead Plastic QFN (5mm x 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 0.70 0.05 5.50 0.05 4.10 0.05 3.50 REF (4 SIDES) 3.45 0.05 3.45 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 0.10 (4 SIDES) BOTTOM VIEW--EXPOSED PAD 0.75 0.05 R = 0.05 TYP 0.00 - 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER 31 32 0.40 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.50 REF (4-SIDES) 3.45 0.10 3.45 0.10 (UH32) QFN 0406 REV D 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 22 0.25 0.05 0.50 BSC 238718fa For more information www.linear.com/LTC2387-18 LTC2387-18 Revision History REV DATE DESCRIPTION A 10/15 Updated Typical Application, Graph 4 and Figure 10 FFT plots. PAGE NUMBER 1, 6, 18 238718fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. For more www.linear.com/LTC2387-18 23 LTC2387-18 Typical Application Input Drive Circuit with Low Distortion up to 1MHz 5V +7.5V 82pF VDDL OVDD IN+ LTC2387-18 1/2 LT6201 4.096V 0V SNR = 94.6dB THD = -115dB SINAD = 94.5dB SFDR = 115dB -20 0.1F -40 VDD 1/2 LT6201 fIN < 1MHz 0 0.1F 24.9 0V 2.5V 82pF LVDS INTERFACE TWOLANES TESTPAT PD IN- REFBUF REFGND 24.9 CLK DCO DA DB REFIN -60 -80 -100 -120 CNV 15MHz SAMPLE CLOCK 238718 TA02 0.1F -2.5V AMPLITUDE (dBFS) 4.096V 0.1F 2.5V -140 -160 10F 0 2.5 5 FREQUENCY (MHz) 7.5 238718 TA02b 128k Point FFT, fSMPL = 15Msps, fIN = 50kHz Low Power, Low Noise Input Drive Circuit for Signals up to 8kHz +7.5V 0 1/2 LT6237 5.1 0V 10nF fIN < 8kHz 4.096V 20 1/2 LT6237 5.1 0V 10nF -2.5V 20 SNR = 96.0dB THD = -114dB SINAD = 95.9dB SFDR = 116dB -20 24.9 -40 C1 27nF 68pF IN+ LTC2387-18 C2 27nF 24.9 68pF IN- 238718 TA03 C1, C2: GRM3195C1H273JA01D OR OTHER NP0 CAPACITOR AMPLITUDE (dBFS) 4.096V -60 -80 -100 -120 -140 -160 0 50 100 150 FREQUENCY (kHz) 200 238718 TA03b 128k Point FFT, fSMPL = 15Msps, fIN = 8kHz (Zoomed View) Related Parts PART NUMBER DESCRIPTION COMMENTS LTC2378-20 20-Bit, 1Msps, Low Power SAR ADC 104dB SNR, -125dB THD, 21mW at 1Msps LTC2389-18 18-Bit, 2.5Msps SAR ADC 99.8dB SNR, -116dB THD, 3LSB INL (Max) LTC2271 16-Bit, 20Msps Serial Dual ADC 84.1dB SNR, 99dB SFDR, 92mW per Channel LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.2V, 2ppm/C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package LTC6652 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.2V, 5ppm/C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package Low Noise Op-Amp 0.95nV/Hz, Up to 1.6GHz GBW ADCs References Amplifiers LT6200 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2387-18 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC2387-18 238718fa LT 1015 REV A * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2015