LTC2387-18
1
238718fa
For more information www.linear.com/LTC2387-18
Typical applicaTion
FeaTures DescripTion
18-Bit, 15Msps SAR ADC
The LTC
®
2387-18 is a low noise, high speed, 18-bit 15Msps
successive approximation register (SAR) ADC ideally
suited for a wide range of applications. The combination
of excellent linearity and wide dynamic range makes the
LTC2387-18 ideal for high speed imaging and instru-
mentation applications. No latency operation provides a
unique solution for high speed control loop applications.
The very low distortion at high input frequencies enables
communications applications requiring wide dynamic
range and significant signal bandwidth.
To support high speed operation while minimizing the
number of data lines, the LTC2387-18 features a serial
LVDS digital interface. The LVDS interface has one-lane
and two-lane output modes, allowing the user to optimize
the interface data rate for each application.
FFT, fSMPL = 15Msps, fIN = 2kHz
applicaTions
n 15Msps Throughput Rate
n No Pipeline Delay, No Cycle Latency
n 95.7dB SNR (Typ) at fIN = 1MHz
n 102dB SFDR (Typ) at fIN = 1MHz
n Nyquist Sampling Up to 7.5MHz Input
n Guaranteed 18-Bit, No Missing Codes
n ±3LSB INL (Max)
n 8.192VP-P Differential Inputs
n 5V and 2.5V Supplies
n Internal 20ppm/°C (Max) Reference
n Serial LVDS Interface
n 125mW Power Dissipation
n 32-Pin (5mm × 5mm) QFN Package
n High Speed Data Acquisition
n Imaging
n Communications
n Control Loops
n Instrumentation
n ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 7705765, 8232905, 8810443. Other patents are pending.
SAMPLE
CLOCK
10µF
0.1µF
0.1µF
2.5V5V
0.1µF0.1µF
CLK
DCO
DA
DB
LVDS
INTERFACE
238718 TA01a
IN–
IN+
82pF
24.9Ω
24.9Ω
GNDREFINREFBUF REFGND
LTC2387-18
VCM
82pF TWOLANES
TESTPAT
PD
CNV
VDD
2.5V
0.1µF
VDDL OVDD
+
–
4.096V
0V
4.096V
0V
SNR = 96.0dB
THD = –117dB
SINAD = 95.7dB
SFDR = 119dB
FREQUENCY (MHz)
0
2.5
5
7.5
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
f
IN
= 2kHz
238718 TA01b
LTC2387-18
2
238718fa
For more information www.linear.com/LTC2387-18
pin conFiguraTionabsoluTe MaxiMuM raTings
Supply Voltage (VDD) ..................................................6V
Supply Voltage (VDDL, OVDD) ................................... 2.8V
Analog Input Voltage (Note 3)
IN+, IN– .........................(GND – 0.3V) to (VDD + 0.3V)
REFBUF .........................(GND – 0.3V) to (VDD + 0.3V)
REFIN (Note 4) ...........................(GND – 0.3V) to 2.8V
Digital Input Voltage (Note 3)
PD, TESTPAT ............. (GND – 0.3V) to (OVDD + 0.3V)
CLK+, CLK– ................ (GND – 0.3V) to (OVDD + 0.3V)
TWOLANES, CNV+,
CNV– ...........................(GND – 0.3V) to (VDDL + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2387C ................................................ 0°C to 70°C
LTC2387I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
32
33
GND
31 30 29 28 27 26 25
9 10 11 12
TOP VIEW
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1GND
IN+
IN–
GND
REFGND
REFGND
REFBUF
REFBUF
CLK+
CLK–
OV
DD
GND
DCO
+
DCO
–
DA+
DA–
VCM
VDDL
VDDL
GND
CNV+
CNV–
GND
TWOLANES
REFIN
GND
VDD
VDD
PD
TESTPAT
DB–
DB+
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2387CUH-18#PBF LTC2387CUH-18#TRPBF 238718 32-Lead (5mm × 5mm) Plastic QFN 0°C to 70°C
LTC2387IUH-18#PBF LTC2387IUH-18#TRPBF 238718 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+Absolute Input Range (IN+) (Note 6) l–0.1 VREFBUF + 0.1 V
VIN–Absolute Input Range (IN–) (Note 6) l–0.1 VREFBUF + 0.1 V
VIN+ – VIN–Input Differential Voltage Range VIN+ – VIN–l–VREFBUF VREFBUF V
VINCM Common Mode Input Range (VIN+ + VIN–)/2 lVREFBUF/2 – 0.1 VREFBUF/2 VREFBUF/2 + 0.1 V
IIN Analog Input DC Leakage Current l–1 1 μA
CIN Analog Input Capacitance Sample Mode
Hold Mode
20
2
pF
pF
CMRR Input Common Mode Rejection Ratio fIN = 1MHz 75 dB
LTC2387-18
3
238718fa
For more information www.linear.com/LTC2387-18
converTer characTerisTics
DynaMic accuracy
inTernal reFerence characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
The
l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 5, 10)
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution l18 Bits
No Missing Codes l18 Bits
Transition Noise 1.4 LSBRMS
INL Integral Linearity Error REFBUF = 4.096V (Notes 7, 9) l–3 ±0.6 3 LSB
DNL Differential Linearity Error l–0.9 ±0.2 0.9 LSB
ZSE Zero-Scale Error (Note 8) l–16 ±1.5 16 LSB
Zero-Scale Error Drift 0.02 LSB/°C
FSE Full-Scale Error REFBUF = 4.096V (REFBUF Overdriven) (Notes 8, 9)
REFIN = 2.048V (REFIN Overdriven) (Note 8)
l
l
–25
–160
±5
±25
25
160
LSB
LSB
Full-Scale Error Drift REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
REFIN = 2.048V (REFIN Overdriven)
±0.1
±1.5
ppm/°C
ppm/°C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 2kHz
fIN = 1MHz
fIN = 5MHz
l
l
93
92.6
95.7
94.5
83
dB
dB
dB
SNR Signal-to-Noise Ratio fIN = 2kHz
fIN = 1MHz
fIN = 5MHz
l
l
93.2
93
96
95.7
94.6
dB
dB
dB
THD Total Harmonic Distortion
(First Five Harmonics)
fIN = 2kHz
fIN = 1MHz
fIN = 5MHz
l
l
–117
–101
–83
–103
–96
dB
dB
dB
SFDR Spurious Free Dynamic Range fIN = 2kHz
fIN = 1MHz
fIN = 5MHz
l
l
103
97
119
102
84
dB
dB
dB
–3dB Input Bandwidth 200 MHz
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREFIN Internal Reference Output Voltage IOUT = 0μA 2.043 2.048 2.053 V
VREFIN Temperature Coefficient (Note 11) l±5 ±20 ppm/°C
REFIN Output Impedance 15 kΩ
VREFIN Line Regulation VDD = 4.75V to 5.25V 0.3 mV/V
REFIN Input Voltage Range (REFIN Overdriven) (Note 6) l2.008 2.048 2.088 V
LTC2387-18
4
238718fa
For more information www.linear.com/LTC2387-18
reFerence buFFer characTerisTics
DigiTal inpuTs anD DigiTal ouTpuTs
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
power requireMenTs
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREFBUF Reference Buffer Output Voltage VREFIN = 2.048V l4.090 4.096 4.102 V
REFBUF Input Voltage Range (REFBUF Overdriven) (Notes 6, 9) l4.016 4.096 4.176 V
IREFBUF REFBUF Load Current VREFBUF = 4.096V (REFBUF Overdriven) (Notes 9, 12)
VREFBUF = 4.096V, Sleep Mode (REFBUF Overdriven) (Note 9)
l1.6
0.5
1.8 mA
mA
VCM Common Mode Output VREFBUF = 4.096V, IOUT = 0μA l2.028 2.048 2.068 V
VCM Output Impedance –1mA < IOUT < 1mA 15 Ω
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PD, TESTPAT, TWOLANES
VIH High Level Input Voltage VDDL = OVDD = 2.5V l1.7 V
VIL Low Level Input Voltage VDDL = OVDD = 2.5V l0.6 V
IIN Digital Input Current VIN = 0V to 2.5V l–10 10 μA
CIN Digital Input Capacitance 3 pF
CNV+, Single-Ended Convert Start Mode (CNV– Tied to GND)
VIH High Level Input Voltage VDDL = 2.5V l1.7 V
VIL Low Level Input Voltage VDDL = 2.5V l0.6 V
CIN Digital Input Capacitance 2 pF
CNV+/CNV–, Differential Convert Start Mode
VID Differential Input Voltage (Note 13) l175 350 650 mV
VICM Common Mode Input Voltage l0.8 1.25 1.7 V
CLK+/CLK– (LVDS Clock Input)
VID Differential Input Voltage (Note 13) l175 350 650 mV
VICM Common Mode Input Voltage l0.8 1.25 1.7 V
DCO+/DCO–, DA+/DA–, DB+/DB– (LVDS Outputs)
VOD Differential Output Voltage 100Ω Differential Load l247 350 454 mV
VOS Common Mode Output Voltage 100Ω Differential Load l1.125 1.25 1.375 V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage (Note 6) l4.75 5 5.25 V
VDDL Supply Voltage (Note 6) l2.375 2.5 2.625 V
OVDD Supply Voltage (Note 6) l2.375 2.5 2.625 V
IVDD
IVDDL
IOVDD
IPOWERDOWN
IPOWERDOWN
Supply Current
Supply Current
Supply Current
Power-Down Mode Current
Power-Down Mode Current
15Msps Sample Rate
15Msps Sample Rate
15Msps Sample Rate
Power-Down Mode (IVDD)
Power-Down Mode (IVDDL + IOVDD)
l
l
l
l
l
5
31.4
8.8
1
2
6
35
10.3
20
250
mA
mA
mA
μA
μA
PDPower Dissipation
Power-Down Mode
15Msps Sample Rate
Power-Down Mode (IVDD + IVDDL + IOVDD)
l
l
125
10
144
725
mW
μW
IDIFFCNV Increase in IVDDL with Differential CNV Mode Enabled (No Increase During Power-Down) 2.1 mA
ITWOLANE Increase in IOVDD with Two-Lane Mode Enabled (No Increase During Power-Down) 3.6 mA
LTC2387-18
5
238718fa
For more information www.linear.com/LTC2387-18
aDc TiMing characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above VDD,
VDDL or OVDD, they will be clamped by internal diodes. This product can
handle input currents up to 100mA below ground or above VDD, VDDL or
OVDD without latchup.
Note 4: When this pin voltage is taken below ground, it will be clamped by
an internal diode. When this pin voltage is taken above VDDL, it is clamped
by a diode in series with a 2k resistor. This product can handle input
currents up to 100mA below ground without latchup.
Note 5: VDD = 5V, VDDL = 2.5V, OVDD = 2.5V, fSMPL = 15MHz,
REFIN=2.048V, single-ended CNV, one-lane output mode unless
otherwise noted.
Note 6: Recommended operating conditions.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Sampling Frequency l0.02 15 Msps
tCONV CNV↑ to Output Data Ready l54 58 63 ns
tACQ Acquisition Time tCYC – 39 ns
tCYC Time Between Conversions l66.6 50,000 ns
tCNVH CNV High Time (Note 13) l5 ns
tCNVL CNV Low Time (Note 13) l8 ns
tFIRSTCLK CNV↑ to First CLK↑ from the Same Conversion (Note 13) l65 ns
tLASTCLK CNV↑ to Last CLK↓ from the Previous
Conversion
(Note 13) l49 ns
tCLKH CLK High Time l1.25 ns
tCLKL CLK Low Time l1.25 ns
tCLKDCO CLK to DCO Delay (Note 13) l0.7 1.3 2.3 ns
tCLKD CLK to DA/DB Delay (Note 13) l0.7 1.3 2.3 ns
tSKEW DCO to DA/DB skew tCLKD – tCLKDCO (Note 13) l–200 0 200 ps
tAP Sampling Delay Time (Note 13) 0 ns
tJITTER Sampling Delay Jitter (Note 13) 0.25 psRMS
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Zero-scale error is the offset voltage measured from –0.5LSB
when the output code flickers between 00 0000 0000 0000 0000 and
111111 1111 1111 1111. Full-scale error is the worst-case deviation of
the first and last code transitions from ideal and includes the effect of
offset error.
Note 9: When REFBUF is overdriven, the internal reference buffer must be
turned off by setting REFIN = 0V.
Note 10: All specifications in dB are referred to a full-scale ±VREFBUF
differential input.
Note 11: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 12: fSMPL = 15MHz, IREFBUF varies linearly with sample rate.
Note 13: Guaranteed by design, not subject to test.
LTC2387-18
6
238718fa
For more information www.linear.com/LTC2387-18
Typical perForMance characTerisTics
32k Point FFT fSMPL = 15Msps,
fIN = 2kHz
32k Point FFT fSMPL = 15Msps,
fIN = 200kHz
32k Point FFT fSMPL = 15Msps,
fIN = 1MHz
32k Point FFT fSMPL = 15Msps,
fIN = 5MHz SNR, SINAD vs Input Frequency
Integral Nonlinearity vs
Output Code (LSB)
Differential Nonlinearity vs
Output Code
DC Histogram
TA = 25°C, VDD = 5V, VDDL = 2.5V, OVDD = 2.5V,
REFIN = 2.048V, fSMPL = 15Msps, unless otherwise noted.
Integral Nonlinearity
vs Output Code (ppm)
OUTPUT CODE
0
65536
131072
196608
262144
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
INL ERROR (LSB)
238718 G01a
OUTPUT CODE
0
65536
131072
196608
262144
–6.0
–4.5
–3.0
–1.5
0
1.5
3.0
4.5
6.0
INL ERROR (ppm)
238718 G01b
OUTPUT CODE
–1.0
DNL ERROR (LSB)
0.8
0.6
0.4
0.2
0.0
–0.8
–0.6
–0.4
–0.2
1.0
238718 G02
0 65536 131072 196608 262144
OUTPUT CODE
0
COUNTS
30000
10000
70000
40000
20000
50000
60000
80000
238718 G03
N-6
N-4
N-5
N-1
N-3
N-2
N
N+2
N+1
N+4
N+3
N+6
N+5
SNR = 96.0dB
THD = –117dB
SINAD = 95.7dB
SFDR = 119dB
FREQUENCY (MHz)
0
2.5
5
7.5
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
f
IN
= 2kHz
238718 G04
FREQUENCY (MHz)
0 2.5 5.0 7.5
–160
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
0
238718 G05
SNR = 95.8dB
THD = –109dB
SINAD = 95.6dB
SFDR = 109dB
SNR = 95.6dB
THD = –103dB
SINAD = 94.6dB
SFDR = 104dB
FREQUENCY (MHz)
0
2.5
5
7.5
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
238718 G06
SNR = 94.6dB
THD = –83dB
SINAD = 83dB
SFDR = 84dB
FREQUENCY (MHz)
0
2.5
5
7.5
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
IN
238718 G07
SNR
SINAD
FREQUENCY (MHz)
0.01
0.1
1
10
78.0
80.0
82.0
84.0
86.0
88.0
90.0
92.0
94.0
96.0
98.0
SNR, SINAD (dBFS)
238718 G08
LTC2387-18
7
238718fa
For more information www.linear.com/LTC2387-18
Typical perForMance characTerisTics
SNR, SINAD vs Temperature,
fIN = 2kHz, –1dBFS
THD, Harmonics vs Temperature,
fIN = 2kHz, –1dBFS INL/DNL vs Temperature
Full-Scale Error vs Temperature,
REFBUF = 4.096V Zero-Scale Error vs Temperature Supply Current vs Temperature
SFDR vs Input Level, fIN = 2kHz SFDR vs Input Level, fIN = 1MHz
THD vs Input Frequency
and Amplitude
TA = 25°C, VDD = 5V, VDDL = 2.5V, OVDD = 2.5V,
REFIN = 2.048V, fSMPL = 15Msps, unless otherwise noted.
–1dBFS
–3dBFS
–6dBFS
–10dBFS
FREQUENCY (MHz)
0.01
0.1
1
10
–140
–130
–120
–110
–100
–90
–80
–70
THD (dBFS)
and Amplitude
238718 G09
INPUT LEVEL (dBFS)
–80
–70
–60
–50
–40
–30
–20
–10
0
50
60
70
80
90
100
110
120
130
140
150
SFDR (dBFS, dBc)
IN
238718 G10
dBc
dBFS
INPUT LEVEL (dBFS)
–80
–70
–60
–50
–40
–30
–20
–10
0
50
60
70
80
90
100
110
120
130
140
150
SFDR (dBFS, dBc)
f
IN
= 1MHz
238718 G11
dBc
dBFS
SNR
SINAD
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
92
93
94
95
96
97
98
SNR, SINAD (dBFS)
IN
238718 G12
THD
2ND
3RD
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
–130
–125
–120
–115
–110
THD, HARMONICS (dBFS)
f
IN
= 2kHz, -1dBFS
238718 G13
MAX INL
MAX DNL
MIN DNL
MIN INL
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
1.00
INL/DNL ERROR (LSB)
238718 G14
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
–6
–4
–2
0
2
4
6
FULL-SCALE ERROR (LSB)
REFBUF = 4.096V
238718 G15
+ FS
– FS
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
–6
–4
–2
0
2
4
6
ZERO-SCALE ERROR (LSB)
Zero-Scale Error vs Temperature
238718 G16
I
VDDL
I
VDD
I
OVDD
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
0
5
10
15
20
25
30
35
SUPPLY CURRENT (mA)
Supply Current vs Temperature
238718 G17
LTC2387-18
8
238718fa
For more information www.linear.com/LTC2387-18
Typical perForMance characTerisTics
Supply Current vs Sample Rate
Analog Input Current
vs Differential Input Voltage
Internal Reference Output
vs Temperature
TA = 25°C, VDD = 5V, VDDL = 2.5V, OVDD = 2.5V,
REFIN = 2.048V, fSMPL = 15Msps, unless otherwise noted.
pin FuncTions
GND (Pins 1, 4, 10, 21, 26, 29 ): Ground. Connect to a
solid ground plane in the PCB underneath the ADC.
IN+, IN– (Pins 2, 3): Positive and Negative Differential
Analog Inputs. The inputs must be driven differentially
and 180° out of phase, with a common mode voltage of
2.048V. The differential input range is ±4.096V (each input
pin swings from 0V to 4.096V.)
REFGND (Pins 5, 6): Reference Ground. The two pins
should be shorted together and connected to the refer-
ence bypass capacitor with a short, wide trace. In ad-
dition, connect the pins to the exposed pad (Pin 33). A
suggested layout is shown in the ADC Reference section
of the data sheet.
REFBUF (Pins 7, 8): Internal Reference Buffer Output.
The output voltage of the internal 2× gain reference buffer,
nominally 4.096V, is provided on this pin. The two pins
should be shorted together and bypassed to REFGND with
a 10µF (X7R, 0805 size) ceramic capacitor. If the internal
buffer is not required, tie REFIN to GND to power down the
buffer and connect an external 4.096V reference to REFBUF.
REFIN (Pin 9): Internal Reference Output/Reference Buffer
Input. The output voltage of the internal reference, nomi-
nally 2.048V, is output on this pin. An external reference
can be applied to REFIN if a more accurate reference is
required. For increased filtering of reference noise, bypass
this pin to GND using a 0.1µF or larger ceramic capacitor.
If the internal reference buffer is not used, tie REFIN to
GND to power down the buffer and connect an external
buffered reference to REFBUF.
I
VDDL
I
VDD
I
OVDD
SAMPLE RATE (Msps)
0
5
10
15
0
5
10
15
20
25
30
35
SUPPLY CURRENT (mA)
238718 G18
IN–
IN+
f
SMPL
= 15Msps
DIFFERENTIAL INPUT (V)
–4.096
–2.048
0
2.048
4.096
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
1.00
ANALOG INPUT CURRENT (mA)
Differential Input Voltage
238718 G19
THREE TYPICAL UNITS
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
2.047
2.048
2.049
2.050
REFERENCE OUTPUT (V)
238718 G20
LTC2387-18
9
238718fa
For more information www.linear.com/LTC2387-18
pin FuncTions
VDD (Pins 11, 12): 5V Analog Power Supply. The range
of VDD is 4.75V to 5.25V. The two pins should be shorted
together and bypassed to GND with 0.1μF and 10μF ce-
ramic capacitors.
PD (Pin 13): Digital input that enables power-down mode.
When PD is low, the LTC2387 enters power-down mode,
and all circuitry (including the LVDS interface) is shut
down. When PD is high, the part operates normally. Logic
levels are determined by OVDD.
TESTPAT (Pin 14): Digital input that forces the LVDS data
outputs to be a test pattern. When TESTPAT is high, the
digital outputs are a test pattern. When TESTPAT is low,
the digital outputs are the ADC conversion result. Logic
levels are determined by OVDD.
DB–/DB+, DA–/DA+ (Pins 15/16, 17/18): Serial LVDS
Data Outputs. In one-lane output mode, DB–/DB+ are not
used and their LVDS driver is disabled to reduce power
consumption.
DCO–/DCO+ (Pins 19/20): LVDS Data Clock Output. This
is an echoed version of CLK–/CLK+ that can be used to
latch the data outputs.
OVDD (Pin 22): 2.5V Output Power Supply. The range of
OVDD is 2.375V to 2.625V. Bypass to GND with a 0.1μF
ceramic capacitor.
CLK–/CLK+ (Pins 23/24): LVDS Clock Input. This is an
externally applied clock that serially shifts out the conver-
sion result.
TWOLANES (Pin 25): Digital input that enables two-lane
output mode. When TWOLANES is high (two-lane output
mode), the ADC outputs two bits at a time on DA–/DA+
and DB–/DB+. When TWOLANES is low (one-lane output
mode), the ADC outputs one bit at a time on DA–/DA+, and
DB–/DB+ are disabled. Logic levels are determined by VDDL.
CNV–/CNV+ (Pins 27/28): Conversion Start LVDS Input.
A rising edge on CNV+ puts the internal sample-and-hold
into the hold mode and starts a conversion cycle. CNV+
can also be driven with a 2.5V CMOS signal if CNV– is
tied to GND.
VDDL (Pins 30, 31): 2.5V Analog Power Supply. The
range of VDDL is 2.375V to 2.625V. The two pins should
be shorted together and bypassed to GND with 0.1μF and
10μF ceramic capacitors.
VCM (Pin 32): Common Mode Output. VCM, nominally
2.048V, can be used to set the common mode of the ana-
log inputs. Bypass to GND with a 0.1μF ceramic capacitor
close to the pin. If VCM is not used, the bypass capacitor
is not necessary as long as the parasitic capacitance on
the VCM pin is under 10pF.
Exposed Pad (Pin 33): The exposed pad on the bottom
of the package. Connect to the ground plane of the PCB
using multiple vias.
LTC2387-18
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TiMing DiagraM
tAP
tCNVH
ANALOG
INPUT
CNV–
CNV+
D17 16 15 14 13 12 11 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
OUTPUT DATA FROM SAMPLE N
LOGIC 0 D17 16 15 14 13 12 11 10 D9 D8 D7 LOGIC 0 D8 D7 D6 D5 D4 D3 D2 D1 D0
OUTPUT DATA FROM SAMPLE N+1 OUTPUT DATA FROM SAMPLE N–1
SAMPLE N
SAMPLE N+1
CLK+
CLK–
DCO+
DCO–
DA+
DA–
INPUT ACQUISITION INPUT ACQUISITION
tACQ
tCYC
123456789
tLASTCLK
tFIRSTCLK
tCONV
238718 TD01
One-Lane Output Mode
LTC2387-18
12
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TiMing DiagraM
t
AP
t
CNVH
ANALOG
INPUT
CNV
–
CNV
+
D17 15 13 11 D9 D7 D5 D3 D1LOGIC 0 D17 15 13 11 D9LOGIC 0 15 13 11 D9 D7 D5 D3 D1
SAMPLE N
SAMPLE N+1
CLK
+
CLK
–
DCO
+
DCO
–
DA
+
DA
–
INPUT ACQUISITION INPUT ACQUISITION
t
ACQ
t
CYC
12345
t
LASTCLK
t
FIRSTCLK
t
CONV
D16 14 12 10 D8 D6 D4 D2 D0LOGIC 0 D16 14 12 10 D8LOGIC 0 14 12 10 D8 D6 D4 D2 D0
OUTPUT DATA FROM SAMPLE N OUTPUT DATA FROM SAMPLE N+1 238718 TD02OUTPUT DATA FROM SAMPLE N–1
DB
+
DB
–
Two-Lane Output Mode
LTC2387-18
13
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TiMing DiagraM
applicaTions inForMaTion
Data Output Timing
t
CLKH
tCLKDCO
CLK+
CLK–
DCO
+
DCO
–
DA+
DA–
tCLKDCO
tCLKD tCLKD
t
CLKL
238718 TD03
DB+
DB–
OVERVIEW
The LTC2387-18 is a low noise, high speed, 18-bit succes-
sive approximation register (SAR) ADC. Operating from 5V
and 2.5V supplies, the LTC2387-18 has a fully differential
±4.096V input range, making it ideal for applications that
require a wide dynamic range. The LTC2387-18 achieves
±3LSB INL (maximum), no missing codes at 18-bits and
96dB SNR (typical).
The LTC2387-18 includes a precision internal 2.048V
reference, with a guaranteed 0.25% initial accuracy and
a ±20ppm/°C (maximum) temperature coefficient, as well
as an internal reference buffer. The LTC2387-18 also has
a high speed serial LVDS interface that can output one or
two bits at a time. The fast 15Msps throughput with no
pipeline latency makes the LTC2387-18 ideally suited for
a wide variety of high speed applications. The LTC2387-18
dissipates only 125mW at 15Msps and has a power-down
mode to reduce the power consumption to 10μW during
inactive periods.
CONVERTER OPERATION
The LTC2387-18 operates in two phases. During the ac-
quisition phase, the sample capacitors are connected to
the analog input pins IN+ and IN– to sample the differential
analog input voltage. A rising edge on the CNV pin initiates
a conversion. During the conversion phase, the ADC is
sequenced through a successive approximation algorithm,
comparing the sampled input with binary-weighted frac-
tions of the reference voltage (e.g. VREFBUF/2, VREFBUF/4
… VREFBUF/262144) using a differential comparator. At
the end of conversion, control logic prepares the 18-bit
digital output code for serial transfer.
TRANSFER FUNCTION
The LTC2387-18 digitizes the full-scale voltage of 2×
REFBUF into 218 levels, resulting in an LSB size of
31.25μV with REFBUF = 4.096V. The output data is in
two’s complement format. The ideal transfer function is
shown in Figure1. The ideal offset binary transfer func-
tion can be obtained from the two’s complement transfer
function by inverting the most significant bit (MSB) of
each output code.
LTC2387-18
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For more information www.linear.com/LTC2387-18
applicaTions inForMaTion
ANALOG INPUTS
The LTC2387-18 has a fully differential ±4.096V input
range. The IN+ and IN– pins should be driven 180 degrees
out-of-phase with respect to each other, centered around
a common mode voltage (IN+ + IN–)/2 that is restricted
to (VREFBUF/2 ± 0.1V). The ADC samples and digitizes the
voltage difference between the two analog input pins (IN+
− IN–), and any unwanted signal that is common to both
inputs is reduced by the common mode rejection ratio
(CMRR) of the ADC. The analog inputs can be modeled
by the equivalent circuit shown in Figure 2. The diodes
and 10Ω resistors at the input provide ESD and overdrive
protection. In the acquisition phase, each input sees ap-
proximately 18pF (CSAMPLE) from the sampling capacitor
in series with 28Ω (RON) from the on-resistance of the
sampling switch. CPAR is a lumped capacitance on the
order of 2pF formed primarily of diode junctions.
The inputs draw a small current spike while charging the
CSAMPLE capacitors during acquisition. This current spike is
consistent and does not depend on the previously sampled
input voltage. During conversion and power-down, the
analog inputs draw only a small leakage current.
Input Drive Circuits
A low impedance source can directly drive the high im-
pedance inputs of the LTC2387-18 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the dis-
tortion performance of the ADC. Minimizing settling time
is important even for DC signals because the ADC inputs
draw a current spike when entering acquisition.
For best performance, a buffer amplifier should be used
to drive the analog inputs of the LTC2387-18. The ampli-
fier provides low output impedance enabling fast settling
of the analog signal during the acquisition phase. It also
provides isolation between the signal source and the current
spike drawn by the ADC inputs when entering acquisition.
The LTC2387-18 is optimized for pulsed inputs that are
fully settled when sampled, or dynamic signals up to the
Nyquist frequency (7.5MHz). Input signals that change
faster than 300mV/ns when they are sampled are not
recommended. This is equivalent to an 8VP-P sine wave
at 12MHz.
Input Filtering
The noise and distortion of the buffer amplifier and other
supporting circuitry must be considered since they add
to the ADC noise and distortion. A buffer amplifier with
low noise density must be selected to minimize SNR
degradation. A filter network should be placed between
the buffer output and ADC input to both minimize the
noise contribution of the buffer and reduce disturbances
reflected into the buffer from ADC sampling transients. A
simple one-pole lowpass RC filter is sufficient for many
applications. It is important that the RC time constant of
this filter be small enough to allow the analog inputs to
settle within the ADC acquisition time (tACQ), as insufficient
settling can limit INL and THD performance.
High quality capacitors and resistors should be used in
the RC filters since these components can add distortion.
Figure 1. LTC2387-18 Transfer Function
Figure 2. Equivalent Circuit for the Differential Analog
Inputs of the LTC2387-18
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO’S COMPLEMENT)
–1
LSB
238718 F01
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FSR/2 – 1LSB–FSR/2
FSR = +FS – –FS
1LSB = FSR/262144
IN
+10Ω
CPAR
2pF
CSAMPLE
18pF
V
DD
238718 F02
IN
–
BIAS
VOLTAGE
10Ω
CPAR
2pF
CSAMPLE
18pF
VDD
28Ω
28Ω
LTC2387-18
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For more information www.linear.com/LTC2387-18
applicaTions inForMaTion
NPO type dielectric capacitors have excellent linearity.
Carbon surface mount resistors can generate distortion
from self-heating and from damage that may occur during
soldering. Metal film surface mount resistors are much
less susceptible to both problems.
Figure 3 shows a typical input drive circuit with an RC filter.
The optimal values for R and C are application-specific and
may require experimentation. Setting R = 24.9Ω gives good
performance over a wide range of conditions.
Input Currents
One of the biggest challenges in coupling an amplifier to
the LTC2387-18 is in dealing with current spikes drawn
by analog inputs at the start of each acquisition phase.
The analog inputs may be modeled as a switched capacitor
load on the drive circuit. A drive circuit may rely partially on
attenuating switched-capacitor current spikes with small
filter capacitors placed directly at the ADC inputs and par-
tially on the driver amplifier having sufficient bandwidth to
recover from the residual disturbance. Amplifiers optimized
for DC performance may not have sufficient bandwidth
to fully recover at the ADC’s maximum conversion rate,
which can produce nonlinearity and other errors. Coupling
filter circuits may be classified in two broad categories:
Fully Settled – This case is characterized by filter time
constants and an overall settling time that are consider-
ably shorter than the sample period. When acquisition
begins, the coupling filter is disturbed. For a typical first
order RC filter
, the disturbance will look like an initial step
with an exponential decay. The amplifier will have its own
response to the disturbance, which may include ringing. If
the input settles completely (to within the accuracy of the
LTC2387-18), the disturbance will not contribute any error.
Partially Settled – In this case, the beginning of acquisi-
tion causes a disturbance of the coupling filter, which then
begins to settle out towards the nominal input voltage.
However
, acquisition ends (and the conversion begins)
before the input settles to its final value. This generally
produces a gain error
, but as long as the settling is linear,
no distortion is produced. The coupling filter’s response
is affected by the amplifier’s output impedance and other
parameters. A linear settling response to fast switched-
capacitor current spikes can NOT always be assumed for
precision, low bandwidth amplifiers. The coupling filter
serves to attenuate the current spikes’ high-frequency
energy before it reaches the amplifier.
Figure 3. Typical Input Drive Circuit
Figure 4. Suggested Range of CFILT Values vs Sample Rate
24.9Ω
24.9Ω
C
FILT
C
FILT
4.096V
0V
4.096V
0V
IN+
IN–
LTC2387-18
238718 F03
MAX VALUE (LOWER NOISE)
MIN VALUE
(LOWER FULL–SCALE ERROR)
SAMPLE RATE (Msps)
9
10
11
12
13
14
15
50
100
150
200
250
300
350
400
C
FILT
(pF)
238718 F04
The value for CFILT involves a trade off: larger values give
better noise, and smaller values give better full-scale error.
Figure 4 shows a range of capacitor values to consider as
a starting point based on the sample rate.
LTC2387-18
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Figure 6. Configuration for Using the Internal Reference
Figure 5. LTC2387-18 Internal Reference Circuitry
ADC REFERENCE
The internal reference circuitry of the LTC2387-18 is shown
in Figure 5. There is a low noise, low drift (20ppm/°C),
bandgap reference connected to REFIN (Pin 9). An internal
reference buffer gains the REFIN voltage by 2× to 4.096V
at REFBUF (Pins 7, 8). The voltage difference between
REFBUF and REFGND determines the full-scale input range
of the ADC. The reference and reference buffer can also
be externally driven if desired.
Internal Reference with Internal Reference Buffer
To use the internal reference and internal reference buf-
fer, bypass REFIN to GND with a 0.1μF ceramic capacitor
(Figure 6). Bypass REFBUF to REFGND with a single 10μF
(X7R, 0805 size) ceramic capacitor
. The REFBUF capacitor
should be as close as possible to the LTC2387-18 package
to minimize wiring inductance. Do not place this capaci-
tor on the opposite side of the board. Adding a second,
smaller capacitor in parallel with the 10μF may degrade
performance and is not recommended.
Figure 7 shows a suggested layout for the REFBUF capaci-
tor. The capacitor should be connected to REFBUF and
REFGND through short, wide traces. REFGND should also
be connected with a wide trace to the grounded exposed
pad (Pin 33).
238718 F07
9 10 11 12
8
7
6
5
4
3
2
1
applicaTions inForMaTion
Figure 7. Suggested REFBUF Bypass Capacitor Layout
238718 F05
2.048V
REFERENCE
ADC
CORE
REFGND
REFBUF
REFIN
8k
15k
9
8
7
6
5
LTC2387-18
2×
238718 F06
REFGND
REFBUF
REFIN
0.1µF LTC2387-18
REFGND
REFBUF
10µF
LTC2387-18
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applicaTions inForMaTion
Figure 9. Overdriving REFBUF Using the LTC6655-4.096
External Reference with Internal Reference Buffer
If more accuracy and/or lower drift is desired, REFIN can
be directly overdriven by an external 2.048V reference as
shown in Figure 8. Linear Technology offers a portfolio of
high performance references designed to meet the needs
of many applications. With its small size, low power, and
high accuracy, the LTC6655-2.048 is well suited for use
with the LTC2387-18 when overdriving the internal ref-
erence. The LTC6655-2.048 offers 0.025% (max) initial
accuracy and 2ppm/°C (max) temperature coefficient for
high precision applications. Bypassing the LTC6655-2.048
with a 2.7μF to 10μF ceramic capacitor close to the REFIN
pin is recommended.
External Reference Buffer
The internal reference buffer can also be overdriven with
an external 4.096V reference at REFBUF as shown in
Figure 9. To do so, REFIN must be grounded to disable
the reference buffer. The external reference must have a
fast transient response and be able to drive the 0.5mA
to 1.6mA load at the REFBUF pin. The LTC6655-4.096 is
recommended when overdriving REFBUF.
Common Mode Output
The VCM pin is an output that provides one-half the voltage
present on the REFBUF pin. This voltage can be used to
set the common mode of a differential amplifier driving the
analog inputs. Bypass VCM to GND with a 0.1μF ceramic
capacitor. If VCM is not used it can be left floating, but the
parasitic capacitance on the pin needs to be under 10pF.
The VCM output has 1/f noise which for most driver circuits
will be removed by the ADC common mode rejection ratio.
VCM is not recommended for single-ended to differential
circuits that pass the VCM noise to only one ADC input.
DYNAMIC PERFORMANCE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2387-18 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Figure 8. Using the LTC6655-2.048 as an External Reference
238718 F09
REFGND
REFBUF
REFIN
LTC2387-18
REFGND
REFBUF
10µF
VIN
5V
LTC6655-4.096
GND
SHDN
VOUT_F
VOUT_S
0.1µF
238718 F08
REFGND
REFBUF
REFIN
2.7µF LTC2387-18
REFGND
REFBUF
10µF
VIN
5V
LTC6655-2.048
GND
SHDN
VOUT_F
VOUT_S
0.1µF
LTC2387-18
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Figure 10. 32k Point FFT of the
LTC2387-18, fSMPL = 15Msps, fIN = 2kHz
applicaTions inForMaTion
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 10 shows that the LTC2387-18 achieves
a typical SINAD of 95.7dB at a 15MHz sampling rate with
a 2kHz input.
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 10 shows
that the LTC2387-18 achieves a typical SNR of 96dB at a
15MHz sampling rate with a 2kHz input.
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD=20log V22+V32+V42+…+ Vn2
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. Figure 10 shows that the
LTC2387-18 achieves a typical THD of –117dB at a 15MHz
sampling rate with a 2kHz input.
POWER CONSIDERATIONS
The LTC2387-18 requires three power supplies: VDD (5V),
VDDL (2.5V), and OVDD (2.5V). Bypass VDD to GND with
a 0.1μF ceramic capacitor close to the pair of pins and a
10μF ceramic capacitor in parallel. Bypass VDDL to GND
with a 0.1μF ceramic capacitor close to the pair of pins
and a 10μF ceramic capacitor in parallel. OVDD can come
from the same source as VDDL but it should be isolated
by a ferrite bead and have its own 0.1μF bypass capacitor.
Power Supply Sequencing
The LTC2387-18 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2387-18
has a power-on-reset (POR) circuit that will reset the
LTC2387-18 at initial power-up or whenever VDD or VDDL
drops well below their minimum values. Once the supply
voltage re-enters the nominal supply voltage range, the
POR will reinitialize the ADC.
SNR = 96.0dB
THD = –117dB
SINAD = 95.7dB
SFDR = 119dB
FREQUENCY (MHz)
0
2.5
5
7.5
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
f
IN
= 2kHz
238718 F10
LTC2387-18
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applicaTions inForMaTion
Power-Down Mode
When PD is pulled low, LTC2387-18 enters power-down
mode. In this state, all internal functions, including the
reference and LVDS outputs, are turned off and subsequent
conversion requests are ignored. The power consumption
drops to a typical value of 10µW. This mode can be used
if the LTC2387-18 is inactive for a long period of time and
the user wants to minimize power dissipation.
The amount of time required to recover from power-down
mode depends on how REFBUF is configured. When using
the internal reference buffer with a 10µF bypass capacitor,
the ADC will stabilize after 20ms. If REFBUF is externally
driven, the recovery time can be significantly less.
TIMING AND CONTROL
CNV Timing
The LTC2387-18 conversion is controlled by the CNV+ and
CNV– inputs. CNV+/CNV– can be driven directly with an
LVDS signal. Alternatively, CNV+ can be driven with a 0V
to 2.5V CMOS signal when CNV– is tied to GND. A rising
edge on CNV+ will sample the analog inputs and start a
conversion. The pulse width of CNV+ should meet the
tCNVH and tCNVL specifications in the timing table.
After the LTC2387-18 is powered on, or exits power-down
mode, conversion data is invalid for the first two conver-
sion cycles. Subsequent results are accurate as long as
the time between conversions meets the tCYC specification.
If the analog input signal has not completely settled when
it is sampled, the ADC noise performance will be affected
by jitter on the rising edge of CNV+. In this case the rising Figure 11. Digital Output Interface to an FPGA
edge of CNV+ should be driven by a clean low jitter signal.
Note that the ADC is less sensitive to jitter on the falling
edge of CNV+.
In applications that are insensitive to jitter, CNV can be
driven directly from an FPGA.
Internal Conversion Clock
The LTC2387-18 has an internal clock that is trimmed
to achieve a maximum conversion time of 63ns. With a
typical acquisition time of 27.7ns, throughput perfor-
mance of 15Msps is guaranteed.
DIGITAL INTERFACE
The LTC2387-18 has a serial LVDS digital interface that
is easy to connect to an FPGA. Three LVDS pairs are re-
quired: CLK±, DCO±, and DA±. A fourth LVDS pair, DB±, is
optional (Figure 11).
238718 F11
LTC2387-18
OPTIONAL
FPGA
100Ω
CLK+
CLK–
–
+
100Ω
DCO+
DCO–
+
–
100Ω
DA+
DA–
100Ω
DB+
DB–
+
–
+
–
LTC2387-18
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Figure 12. Timing Diagram for a Single Conversion in One-Lane Mode
tCONV
238718 F12
CNV
D17 16 15 14 13 12 11 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CLK
DCO
DA
1 2 3 4 5 6 7 8 9
MSB LSB
applicaTions inForMaTion
Figure 13. Valid Time Window for Clocking Out Data
tFIRSTCLK tLASTCLK
238718 F13
CNV
CLK
1 2 3 4 5 6 7 8 9
TIME WINDOW FOR CLOCKING OUT CONVERSION N
CONVERSION N CONVERSION N+1
The LVDS signals should be routed on the PC board as
100Ω differential transmission lines and terminated at the
receiver with 100Ω resistors.
A conversion is started by the rising edge of CNV+. When
the conversion is complete, the most-significant data bit
is output on DA±. Data is then ready to be shifted out by
applying a burst of nine clock pulses to the CLK± input.
The data on DA± is updated by every edge of CLK±. An
echoed version of CLK± is output on DCO±. The edges of
DA± and DCO± are aligned, so DCO± can be used to latch
DA± in the FPGA. The timing of a single conversion is
shown in Figure 12.
Data must be clocked out after the current conversion is
complete, and before the next conversion finishes. The valid
time window for clocking out data is shown in Figure 13.
Note that it is allowed to be still clocking out data when
the next conversion begins.
Two-Lane Output Mode
At high sample rates the required LVDS interface data rate
can reach >400Mbps. Most FPGAs can support this, but
if a lower data rate is desired, the two-lane output mode
can be used. When the TWOLANES input pin is tied high,
LTC2387-18
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the optional LVDS output DB± is enabled, and data is out-
put two bits at a time on DA± and DB±. Enabling the DB±
output increases the supply current from OVDD by about
3.6mA. In two-lane mode, five clock pulses are required
for CLK± (see Timing Diagrams).
Output Test Patterns
To allow in-circuit testing of the digital interface to the
ADC, there is a test mode that forces the ADC data outputs
to known values:
One-Lane Mode: 10 1000 0001 1111 1100
Two-Lane Mode: 11 0011 0000 1111 1100
The test pattern is enabled when the TESTPAT pin is
brought high.
BOARD LAYOUT
The LTC2387-18 requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with an
internal ground plane in the first layer beneath the ADC is
recommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
High quality ceramic bypass capacitors should be used
at the VDD, VDDL, OVDD, VCM, REFIN, and REFBUF pins.
Bypass capacitors must be located as close to the pins as
possible. Size 0402 ceramic capacitors are recommended
(except for REFBUF). The traces connecting the pins and
bypass capacitors must be kept short and should be made
as wide as possible.
Of particular importance is the capacitor between REFBUF
and REFGND, which should be a 10μF (X7R, 0805 size)
ceramic capacitor. This capacitor should be on the same
side of the circuit board as the ADC, and as close to the
device as possible. Adding a second, smaller capacitor in
parallel with the 10μF may degrade performance and is
not recommended.
The analog inputs, convert start, and digital outputs should
not be routed next to each other. Ground fill and grounded
vias should be used as barriers to isolate these signals
from each other.
Exposed Package Pad
For good electrical and thermal performance, the exposed
pad on the bottom of the package must be soldered to a
large grounded pad on the PC board. This pad should be
connected to the internal ground planes by an array of vias.
Mechanical Stress Shift
The mechanical stress of mounting a part to a board can
cause subtle changes to the SNR and internal voltage
reference. The best soldering method is to use IR reflow
or convection soldering with a controlled temperature
profile. Hand soldering with a heat gun or a soldering iron
is not recommended.
applicaTions inForMaTion
LTC2387-18
22
238718fa
For more information www.linear.com/LTC2387-18
package DescripTion
Please refer to http://www.linear.com/product/LTC2387-18#packaging for the most recent package drawings.
5.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.50 REF
(4-SIDES)
3.45 ±0.10
3.45 ±0.10
0.75 ±0.05 R = 0.115
TYP
0.25 ±0.05
(UH32) QFN 0406 REV D
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 ±0.05
3.50 REF
(4 SIDES)
4.10 ±0.05
5.50
±0.05
0.25 ±0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
3.45 ±0.05
3.45 ±0.05
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
LTC2387-18
23
238718fa
For more information www.linear.com/LTC2387-18
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 10/15 Updated Typical Application, Graph 4 and Figure 10 FFT plots. 1, 6, 18
LTC2387-18
24
238718fa
For more information www.linear.com/LTC2387-18
LINEAR TECHNOLOGY CORPORATION 2015
LT 1015 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2387-18
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC2378-20 20-Bit, 1Msps, Low Power SAR ADC 104dB SNR, –125dB THD, 21mW at 1Msps
LTC2389-18 18-Bit, 2.5Msps SAR ADC 99.8dB SNR, –116dB THD, ±3LSB INL (Max)
LTC2271 16-Bit, 20Msps Serial Dual ADC 84.1dB SNR, 99dB SFDR, 92mW per Channel
References
LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.2V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6652 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.2V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
Amplifiers
LT6200 Low Noise Op-Amp 0.95nV/√Hz, Up to 1.6GHz GBW
Low Power, Low Noise Input Drive Circuit for Signals up to 8kHz
Input Drive Circuit with Low Distortion up to 1MHz
128k Point FFT, fSMPL = 15Msps,
fIN = 50kHz
128k Point FFT, fSMPL = 15Msps,
fIN = 8kHz (Zoomed View)
24.9Ω
24.9Ω
82pF
82pF
0.1µF
0.1µF
0.1µF
10µF
0.1µF
4.096V
0V
4.096V
0V
IN+
IN–
LTC2387-18
1/2 LT6201
1/2 LT6201
f
IN
< 1MHz
V
DD
V
DDL
5V
2.5V
2.5V
OV
DD
CLK
DCO
DA
DB
TWOLANES
TESTPAT
PD
CNV
REFBUF
REFGND
REFIN
LVDS
INTERFACE
15MHz
SAMPLE
CLOCK
+7.5V
-2.5V
238718 TA02
SNR = 94.6dB
THD = –115dB
SINAD = 94.5dB
SFDR = 115dB
FREQUENCY (MHz)
0
2.5
5
7.5
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
238718 TA02b
5.1Ω
20Ω
5.1Ω
20Ω
C1
27nF
C2
27nF
10nF
10nF
24.9Ω
24.9Ω
68pF
68pF
4.096V
0V
4.096V
0V
IN+
IN–
LTC2387-18
1/2 LT6237
f
IN
< 8kHz
1/2 LT6237
C1, C2: GRM3195C1H273JA01D OR OTHER NP0 CAPACITOR
+7.5V
-2.5V
238718 TA03
SNR = 96.0dB
THD = –114dB
SINAD = 95.9dB
SFDR = 116dB
FREQUENCY (kHz)
0
50
100
150
200
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
238718 TA03b
