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LM26480-Q1
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SNVSA58C –JANUARY 2015–REVISED NOVEMBER 2017
Product Folder Links: LM26480-Q1
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10 Power Supply Recommendations
All power inputs should be tied to the main VDD source (that is, a battery), unless the user wishes to power it
from another source. (that is, powering LDO from Buck output).
The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The
analog VDD inputs must have an input voltage between 2.8 V and 5.5 V, as specified in the Recommended
Operating Conditions: Bucks section of this datasheet.
The other VIN pins (VINLDO1, VINLDO2, VIN1, VIN2) can actually have inputs lower than 2.8 V, as long as they
are higher than the programmed output (0.3 V). The analog and digital grounds should be tied together outside
of the chip to reduce noise coupling.
11 Layout
11.1 Layout Guidelines
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
ii the traces. These can send erroneous signals to the DC-DC converter device, resulting in poor regulation or
instability. Poor layout can also result in re-flow problems leading to poor solder joints, which can result in erratic
or degraded performance.
Good layout for the LM26480-Q1 bucks can be implemented by following a few simple design rules, as shown in
Figure 34.
1. Place the buck inductor and filter capacitors close together and make the trace short. The traces between
these components carry relatively high switching currents and act as antennas. Following this rule reduces
radiated noise. Place the capacitors and inductor close to the buck.
2. Arrange the components so that the switching current loops curl in the same direction. During the first halt of
each cycle, current flows from the input filter capacitor, through the buck and inductor to the output filter
capacitor and back through ground, forming a current loop. In the second half of each cycle, current is pulled
up from ground, through the buck by the inductor, to the output filter capacitor and then back through ground,
forming a second current loop. Routing these loops so the current curls in the same direction prevents
magnetic field reversal between the two half-cycles and reduces radiated noise.
3. Connect the ground pins of the buck, and filter capacitors together using generous component-side copper
fill as a pseudo-ground plane. Then connect this to the ground-plane (if one is used) with several vias. This
reduces ground–plane noise by preventing the switching currents from circulating through the ground plane.
It also reduces ground bounce at the buck by giving it a low-impedance ground connection.
4. Use wide traces between the power components and for power connections to the DC-DC converter circuit.
This reduces voltage errors caused by resistive losses across the traces
5. ROUT noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power
components. The voltage feedback trace must remain close to the buck circuit and should be routed directly
from FB to VOUT at the output capacitor and must be routed opposite to noise components. This reduces
EMI radiated onto the DC-DC converter’s own voltage feedback trace.
In mobile phones, for example, a common practice is to place the DC-DC converter on one corner of the board,
arrange the CMOS digital circuitry around it (because this also generates noise), and then place sensitive
preamplifiers and IF stages on the diagonally opposing corner. Often, the sensitive circuitry is shielded with a
metal pan and power to it is post-regulated to reduce conducted noise, using low-dropout linear regulators.
For more information on board layout techniques, refer to AN-1187 Leadless Leadframe Package (LLP) on TI's
website. This application note also discusses package handling, solder stencil, and the assembly process.