SCC2681T
Dual asynchronous receiver/transmitter
(DUART)
Product data 2004 Apr 06
INTEGRATED CIRCUITS
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2
2004 Apr 06
DESCRIPTION
The Philips Semiconductors SCC2681 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip
MOS-LSI communications device that provides two independent
full-duplex asynchronous receiver/transmitter channels in a single
package. The SCC2681T features a faster bus cycle time than the
standard SCC2681. The quick bus cycle eliminates or reduces the
need for wait states with fast CPUs and permits high throughput in
I/O intensive systems. Higher external clock rates may be used with
the transmitter, receiver and counter timer which in turn provide
greater versatility in baud rate generation. The SCC2681T interfaces
directly with microprocessors and may be used in a polled or
interrupt driven system. It is manufactured in CMOS technology.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16× clock derived from a programmable counter/timer,
or an external 1× or 16× clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver is quadruple buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the receiver buf fer is full.
Also provided on the SCC2681T are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
For a complete functional description and programming information
for the SCC2681T, refer to the SCC2681 product specification.
FEATURES
•Fast bus cycle times reduce or eliminate CPU wait states
•Dual full-duplex asynchronous receiver/transmitters
•Quadruple buf fered receiver data registers
•Programmable data format
–5 to 8 data bits plus parity
–Odd, even, no parity or force parity
–1, 1.5 or 2 stop bits programmable in 1/16-bit increments
•16-bit programmable Counter/T imer
•Programmable baud rate for each receiver and transmitter
selectable from:
–22 fixed rates: 50 to 115.2 k baud
–Non-standard rates to 115.2
–Non-standard user-defined rate derived from programmable
counter/timer
–External 1× or 16× clock
•Parity, framing, and overrun error detection
•False start bit detection
•Line break detection and generation
•Programmable channel mode
–Normal (full-duplex)
–Automatic echo
–Local loopback
–Remote loopback
•Multi-function programmable 16-bit counter/timer
•Multi-function 7-bit input port
–Can serve as clock or control inputs
–Change of state detection on four inputs
–100 kΩ typical pull-up resistors
•Multi-function 8-bit output port
–Individual bit set/reset capability
–Outputs can be programmed to be status/interrupt/DMA signals
–Auto 485 turn-around
•Versatile interrupt system
–Single interrupt output with eight maskable interrupting
conditions
–Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
•Maximum data transfer rates:
–1× – 1 MB/sec transmitter and receiver
–16× – 500 kB/sec receiver and 250 kB/sec transmitter
•Automatic wake-up mode for multidrop applications
•Start-end break interrupt/status
•Detects break which originates in the middle of a character
•On-chip crystal oscillator
•Single +5 V power supply
•Commercial temperature range
ORDERING INFORMATION
DESCRIPTION VCC = +5 V ± 10%, Tamb = 0 °C to +70 °CDWG #
44-Pin Plastic Lead Chip Carrier (PLCC) SCC2681TC1A44 SOT187-2
NOTE: For a full register description and programming information see the SCC2681.
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 3
BLOCK DIAGRAM
8
D0–D7
RDN
WRN
CEN
A0–A3
RESET
INTRN
X1/CLK
X2
4
BUS BUFFER
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
INTERRUPT CONTROL
IMR
ISR
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL OSC
CSRA
CSRB
ACR
CTLR
CHANNEL A
TRANSMIT
HOLDING REG
TRANSMIT
SHIFT REGISTER
RECEIVE
HOLDING REG (3)
RECEIVE
SHIFT REGISTER
MRA1, 2
CRA
SRA
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
OUTPUT PORT
FUNCTION
SELECT LOGIC
OPCR
TxDA
RxDA
IP0-IP6
OP0-OP7
VCC
GND
CONTROL
TIMING
INTERNAL DATABUS
CHANNEL B
(AS ABOVE)
IPCR
ACR
OPR
CTLR
U
RxDB
TxDB
8
7
SD00099
Figure 1. Block Diagram
NOTE:
Refer to SCC2681 for functional description.
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 4
PIN CONFIGURATION
6
40
41
42
43
44
1
2
IP2
IP6
IP5
IP4
VCC
A0
n.c.
3
4
5
IP3
A1
A2
IP1
A3
IP0
WRN
RDN
RxDB
n.c.
TxDB
OP1
OP3
OP5
OP7
7
8
9
10
11
12
13
14
15
16
17
18
28
27
26
25
24
23
22
21
20
19
D0
D2
D4
D6
INTRN
GND
n.c.
D7
D5
D1
D3
39
38
37
36
35
34
33
32
31
30
29
CEN
RESET
X2
X1/CLK
RxDA
n.c.
TxDA
OP0
OP2
OP4
OP6
SCC2681TC1A44
SD00737
Figure 2. Pin configuration
PIN DESCRIPTION
MNEMONIC PIN TYPE NAME AND FUNCTION
D0–D7 21, 25, 20,
26, 19, 27,
18, 28
I/O Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the
DUART and the CPU. D0 is the least significant bit.
CEN 39 IChip Enable: Active LOW input signal. When LOW, data transfers between the CPU and the DUART
are enabled on D0–D7 as controlled by the WRN, RDN, and A0–A3 inputs. When CEN is HIGH, the
DUART places the D0–D7 lines in the three-state condition.
WRN 9 I Write Strobe: When LOW and CEN is also LOW, the contents of the data bus is loaded into the
addressed register. The transfer occurs on the rising edge of the signal.
RDN 10 IRead Strobe: When low and CEN is also LOW, causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on the falling edge of RDN.
A0–A3 2, 4, 6, 7 IAddress Inputs: Select the DUART internal registers and ports for read/write operations.
RESET 38 IReset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the
HIGH state, stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and
TxDB outputs in the mark (HIGH) state. Clears Test modes, sets MR pointer to MR1.
INTRN 24 OInterrupt Request: Active-LOW , open-drain output which signals the CPU that one or more of the eight
maskable interrupting conditions are true.
X1/CLK 36 ICrystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock
Timing.
X2 37 ICrystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not
connected.
It must not be grounded.
RxDA 35 IChannel A Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is HIGH, ‘space’
is LOW.
RxDB 11 IChannel B Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is HIGH, ‘space’
is LOW.
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 5
MNEMONIC NAME AND FUNCTIONTYPEPIN
TxDA 33 OChannel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held
in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode.
‘Mark’ is HIGH, ‘space’ is LOW.
TxDB 13 OChannel B T ransmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback
mode. ‘Mark’ is HIGH, ‘space’ is LOW.
OP0 32 OOutput 0: General purpose output, or channel A request to send (RTSAN, active-LOW). Can be
deactivated automatically on receive or transmit.
OP1 14 OOutput 1: General purpose output, or channel B request to send (RTSBN, active-LOW). Can be
deactivated automatically on receive or transmit.
OP2 31 OOutput 2: General purpose output, or channel A transmitter 1× or 16× clock output, or channel A
receiver 1× clock output.
OP3 15 OOutput 3: General purpose output, or open-drain, active-LOW counter/timer interrupt output, or channel
B transmitter 1× clock output, or channel B receiver 1× clock output.
OP4 30 OOutput 4: General purpose output, or channel A open-drain, active-LOW, RxRDY A/FFULLA interrupt
output.
OP5 16 OOutput 5: General purpose output, or channel B open-drain, active-LOW, RxRDYB/FFULLB interrupt
output.
OP6 29 OOutput 6: General purpose output, or channel A open-drain, active-LOW, TxRDY A interrupt output.
OP7 17 OOutput 7: General purpose output, or channel B open-drain, active-LOW TxRDYB interrupt output.
IP0 8 I Input 0: General purpose input, or channel A clear to send active-LOW input (CTSAN). Pin has an
internal VCC pull-up device supplying 1 to 4 µA of current.
IP1 5 I Input 1: General purpose input, or channel B clear to send active-LOW input (CTSBN). Pin has an
internal VCC pull-up device supplying 1 to 4 µA of current.
IP2 40 IInput 2: General purpose input, or counter/timer external clock input. Pin has an internal VCC pull-up
device supplying 1 to 4 µA of current.
IP3 3 I Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has
an internal VCC pull-up device supplying 1 to 4 µA of current.
IP4 43 IInput 4: General purpose input, or channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 µA of current.
IP5 42 IInput 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has
an internal VCC pull-up device supplying 1 to 4 µA of current.
IP6 41 IInput 6: General purpose input, or channel B receiver external clock input (RxCB). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal VCC pull-up device supplying 1 to 4 µA of current.
VCC 44 I Power Supply: +5 V supply input.
GND 22 IGround
n.c. 1, 12, 23,
34 not connected
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 6
ABSOLUTE MAXIMUM RATINGS1
SYMBOL PARAMETER RATING UNIT
Tamb Operating ambient temperature range20 to +70 °C
Tstg Storage temperature range –65 to +150 °C
All voltages with respect to GND3–0.5 to +6.0 V
Pin voltage range VSS – 0.5 to VCC + 0.5 V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150 °C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 7
DC ELECTRICAL CHARACTERISTICS1, 2, 3
Tamb = 0 °C to +70 °C; VCC = +5.0 V ± 10%
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITIONS
Min Typ Max
UNIT
VIL LOW-level input voltage – – 0.8 V
VIH HIGH-level input voltage (except X1/CLK) Tamb ≥ 0 °C 2.0 – – V
VIH HIGH-level input voltage (except X1/CLK) Tamb < 0 °C 2.5 – – V
VIH HIGH-level input voltage (X1/CLK) 0.8 VCC – – V
VOL LOW-level output voltage IOL = 2.4 mA – – 0.4 V
VOH HIGH-level output voltage (except open-drain outputs)4IOH = –400 µAVCC – 0.5 – – V
IIX1 X1/CLK input current VIN = 0 V to VCC –10 – +10 µA
IILX1 X1/CLK input LOW current – operating VIN = 0 V –75 – 0 µA
IIHX1 X1/CLK input HIGH current – operating VIN = VCC 0 – 75 µA
IOHX2 X2 output HIGH current – operating VOUT = VCC; X1 = 0 0 – +75 µA
IOHX2S X2 output HIGH short circuit current – operating VOUT = 0 V ; X1 = 0 –10 – –1 mA
IOLX2 X2 output LOW current – operating VOUT = 0 V ; X1 = VCC –75 – 0 µA
IOLX2S X2 output LOW short circuit current – operating VOUT = VCC; X1 = VCC 1 – 10 mA
Input leakage current:
IIAll except input port pins VIN = 0 V to VCC –10 – +10 µA
Input port pins VIN = 0 V to VCC –20 – +10 µA
IOZH Output of f current HIGH, 3-state data bus VIN = VCC – – 10 µA
IOZL Output of f current LOW, 3-state data bus VIN = 0 V –10 – – µA
IODL Open-drain output LOW current in off-state VIN = 0 V –10 – – µA
IODH Open-drain output HIGH current in off-state VIN = VCC – – 10 µA
ICC
Power supply current5
I
CC Operating mode CMOS input levels ––10 mA
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 2.4 V with a transition time of
5 ns maximum. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of 0.8 V and
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.
3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50 pF, RL = 2.7 kΩ to VCC.
5. All outputs are disconnected. Inputs are switching between CMOS levels of VCC – 0.2 V and VSS + 0.2 V.
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 8
AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
Min Typ Max
UNIT
Reset timing (see Figure 3)
tRES Reset pulse width 1.0 – – µs
Bus timing (see Figure 4) (Note 5)
tAVEL A0–A3 set-up to RDN and CEN, or WRN and CEN LOW 0 – – ns
tELAX RDN and CEN, or WRN and CEN LOW to A0–A3 invalid 100 – – ns
tRLRH RDN and CEN LOW to RDN or CEN HIGH 120 – – ns
tEHEL CEN HIGH to CEN LOW6, 7110 – – ns
tRLDA CEN and RDN LOW to data outputs active 15 – – ns
tRLDV CEN and RDN LOW to data valid – – 100 ns
tRHDI CEN or RDN HIGH to data invalid 10 – – ns
tRHDF CEN or RDN HIGH to data outputs floating – – 65 ns
tWLWH WRN and CEN LOW to WRN or CEN HIGH 75 – – ns
tDVWH Data input valid to WRN or CEN HIGH 35 – – ns
tWHDI WRN or CEN HIGH to data invalid 15 – – ns
Port timing (see Figure 5)
tPS Port input set-up time before RDN LOW 0 – – ns
tPH Port input hold time after RDN HIGH 0 – – ns
tPD Port output valid after WRN HIGH – – 200 ns
Interrupt timing (see Figure 6)
INTRN (or OP3–OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt) – – 200 ns
Write THR (TxRDY interrupt) – – 200 ns
tIR Reset command (delta break interrupt) – – 200 ns
Stop C/T command (counter interrupt) – – 200 ns
Read IPCR (input port change interrupt) – – 200 ns
Write IMR (clear of interrupt mask bit) – – 200 ns
Clock timing (see Figure 7)
tCLK X1/CLK HIGH or LOW time 90 ns
fCLK X1/CLK frequency 2 4 MHz
tCTC CTCLK (IP2) HIGH or LOW time 55 ns
fCTC CTCLK (IP2) frequency80 8 MHz
tRX RxC HIGH or LOW time 55 ns
f
RxC frequency (16×)803.6864 8 MHz
f
RX (1×)80 1 MHz
tTX TxC HIGH or LOW time 110 ns
fTX TxC frequency (16×)80 4 MHz
(1×)80 1 MHz
Transmit timing (see Figure 8)
tTXD TxD output delay from TxC external clock input on IP pin – – 300 ns
tTCS Output delay from TxC LOW at OP pin to TxD data output 0 – 100 ns
Receive timing (see Figure )
tRXS RxD data set-up time before RxC HIGH at external clock input on IP pin 200 – – ns
tRXH RxD data hold time after RxC HIGH at external clock input on IP pin 25 – – ns
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with a
transition time of 20 ns maximum. For X1/CLK this swing is between 0.4 V and 4.0 V. All time measurements are referenced at inp ut
voltages of 0.8 V and 2.0 V and output voltages of 0.8 V and 2.0 V as appropriate.
3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 9
4. Test conditions for outputs: CL = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50 pF, RL = 2.7 kΩ to VCC.
5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must
be negated for tEHEL to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the
RDN input even if the CEN is used as the strobing signal for bus operations.
7. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
8. Minimum frequencies are not tested but are guaranteed by design.
SD00028
RESET
tRES
Figure 3. Reset Timing
A0–A3
CEN
(READ)
tAVEL
RDN
D0–D7
(READ) FLOAT FLOATVALIDINVALID
CEN
(WRITE)
VALID
D0–D7
(WRITE)
tELAX
tEHEL
tRLRH
tRHDF
tRHDI
tRLDV
tRLDA
tEHEL
tWLWH
WRN
tDVWH tWHDI
SD00100
Figure 4. Bus Timing
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 10
RDN
IP0–IP6
WRN
OP0–OP7
tPS tPH
OLD DATA
NEW DATA
(a) INPUT PINS
tPD
(b) OUTPUT PINS
SD00101
Figure 5. Port Timing
NOTES:
1. INTRN or OP3-OP7 when used as interrupt outputs.
2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
signal, VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and
test environment are pronounced and can greatly affect the resultant measurement.
VM
VOL +0.5V
VOL
WRN
INTERRUPT1
OUTPUT
tIR
SD00102
Figure 6. Interrupt Timing
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 11
X1/CLK
CTCLK
RxC
TxC
tCLK
tCTC
tRx
tTx
tCLK
tCTC
tRx
tTx
+5 V
R1
1 kΩ
X1
X2
C1 = C2 = 24 pF FOR CL = 20 pF X1
X2
3.6864 MHz
3 pF
4 pF
50 TO
150 kΩ
TO INTERNAL CLOCK DRIVERS
SCC2681T
NOTE:
C1 AND C2 SHOULD BE BASED ON MANUFACTURER’S SPECIFICATION. PARASITIC CAPACITANCE SHOULD BE
INCLUDED WITH C1 AND C2. R1 IS ONLY REQUIRED IF U1 WILL NOT DRIVE TO X1 INPUT LEVELS
TYPICAL CRYSTAL SPECIFICATION
FREQUENCY : 2 – 4 MHz
LOAD CAPACITANCE (CL): 12 – 32 pF
TYPE OF OPERATION: PARALLEL RESONANT, FUNDAMENTAL MODE
NC
SD00726
RESISTOR REQUIRED
WHEN U1 IS A TTL DEVICE
U1
Figure 7. Clock Timing
SD00103
TxD
TxC
(INPUT)
TxC
(1X OUTPUT)
tTXD
tTCS
1 BIT TIME
(1 OR 16 CLOCKS)
Figure 8. Transmit
tRXS
RxC
(1X INPUT)
RxD
tRXH
SD00104
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 12
Figure 9. Receive
TRANSMITTER
ENABLED
TxD D1 D2 D3 D4 D6BREAK
TxRDY
(SR2)
WRN
D1 D2 D3 D4 D6START
BREAK STOP
BREAK D5 WILL
NOT BE
TRANSMITTED
CTSN1
(IP0)
RTSN2
(OP0)
OPR(0) = 1 OPR(0) = 1
NOTES:
1. Timing shown for MR2(4) = 1.
2. Timing shown for MR2(5) = 1.
SD00094
Figure 10. Transmitter Timing
D1 D2 D3 D4 D5 D6 D7 D8
RxD
D6, D7, D8 WILL BE LOST
RECEIVER
ENABLED
RxRDY
(SR0)
FFULL
(SR1)
RxRDY/
FFULL
(OP5)2
RDN
D1 D2 D3 D4
D5 WILL
BE LOST
OVERRUN
(SR4) RESET BY
COMMAND
RTS1
(OP0)
OPR(0) = 1
NOTES:
1. Timing shown for MR1(7) = 1.
2. Shown for OPCR(4) = 1 and MR1(6) = 0.
SD SD SD SD
S = STATUS
D = DATA
SD00105
Figure 11. Receiver Timing
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 13
TRANSMITTER
ENABLED
TxD ADD#1
TxRDY
(SR2)
WRN
MR1(4–3) = 11
MR1(2) = 1
1
BIT 9
D0 0
BIT 9
ADD#2 1
BIT 9
MASTER STATION
ADD#1MR1(2) = 0D0 MR1(2) = 1 ADD#2
RxD ADD#1 1
BIT 9
D0 0
BIT 9
ADD#2 1
BIT 9
PERIPHERAL STATION
0
BIT 9
0
BIT 9
RECEIVER
ENABLED
RxRDY
(SR0)
RDN/WRN
MR1(4–3) = 11 ADD#1 D0 ADD#2
SD S = STATUS
D = DATA SD
SD00106
Figure 12. Wake-Up Mode
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 14
PLCC44: plastic leaded chip carrier; 44 leads SOT187-2
Philips Semiconductors Product data
SCC2681TDual asynchronous receiver/transmitter (DUART)
2004 Apr 06 15
REVISION HISTORY
Rev Date Description
_1 20040406 Product data (9397 750 12073). ECN 853-2446 01-A15014 of 15 December 2003.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2004
All rights reserved. Printed in U.S.A.
Date of release: 04-04
Document order number: 9397 750 12073
Data sheet status[1]
Objective data
Preliminary data
Product data
Product
status[2] [3]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Level
I
II
III
