MOTOROLA Order this document by MC33493/D SEMICONDUCTOR TECHNICAL DATA TANGO3 MC33493 PLL Tuned UHF Transmitter for Data Transfer Applications * * * * * * * * * * * Selectable frequency bands: 315-434MHz and 868MHz OOK and FSK modulation Adjustable output power range Fully integrated VCO Supply voltage range: 1.9-3.6V Very low standby current: 0.1nA @ TA =25C Low supply voltage shutdown Data clock output for microcontroller Extended temperature range: -40C to 125C Low external component count Typical application compliant with ETSI standard PIN CONNECTIONS DATACLK 1 14 MODE DATA 2 13 ENABLE BAND 3 12 VCC GND 4 11 GNDRF XTAL1 5 10 RFOUT XTAL0 6 9 VCC REXT 7 8 CFSK Ordering Information Device Ambiant Temperature Range Package MC33493 DTB -40C to 125C TSSOP14 Figure 1: Simplified block diagram This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 1.5 (c) Motorola, Inc., 2001. MC33493 PIN FUNCTION DESCRIPTION Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DATACLK DATA BAND GND XTAL1 XTAL0 REXT CFSK VCC RFOUT GNDRF VCC ENABLE MODE Description Clock output to the microcontroller Data input Frequency band selection Ground Reference oscillator input Reference oscillator output Power amplifier output current setting input FSK switch output Power supply Power amplifier output Power amplifier ground Power supply Enable input Modulation type selection input ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VCC VGND - 0.3 to 3.7 V VGND - 0.3 to VCC + 0.3 V ESD HBM Voltage Capability on Each Pin (note 1) 2000 V ESD MM Voltage Capability on Each Pin (note 2) 150 V Supply Voltage Voltage Allowed on Each Pin Storage Temperature Ts -65 to +150 C Junction Temperature Tj +150 C Notes: 1 Human Body model, AEC-Q100-002 Rev. C. 2 Machine Model, AEC-Q100-003 Rev. E. MOTOROLA SEMICONDUCTORS PRODUCTS 2 MC33493 TRANSMITTER FUNCTIONAL DESCRIPTION MC33493 is a PLL tuned low power UHF transmitter. The different modes of operation are controlled by the microcontroller through several digital input pins. The power supply voltage ranges from 1.9V to 3.6V allowing operation with a single lithium cell. PHASE LOCKED LOOP AND LOCAL OSCILLATOR The VCO is a completely integrated relaxation oscillator. The Phase Frequency Detector (PFD) and the loop filter are fully integrated.The exact output frequency is equal to: fRFOUT = fXTAL x PLL divider ratio. The frequency band of operation is selected through the BAND pin. Table 1 provides details for each frequency band selection. Table 1: Frequency band selection and associated divider ratios BAND input Frequency PLL divider Crystal oscillator level band (MHz) ratio frequency (MHz) 315 9.84 High 32 434 13.56 Low 868 64 An out-of-lock function is performed by monitoring the PFD output voltage. When it exceeds defined limits, the RF output stage is disabled. RF OUTPUT STAGE The output stage is a single ended square wave switched current source. Harmonics are present in the output current drive. Their radiated absolute level depends on the antenna characteristics and output power. Typical application demonstrates compliance to ETSI standard. A resistor Rext connected to the REXT pin controls the output power allowing a trade-off between radiated power and current consumption. The output voltage is internally clamped to Vcc 2Vbe (typ. Vcc 1.5V @ TA=25C). MODULATION A low logic level has to be applied on pin MODE to select the On Off Keying (OOK) modulation. This modulation is performed by switching on/off the RF output stage. The logic level applied on pin DATA controls the output stage state: DATA=0 -> output stage off, DATA=1 -> output stage on. If a high logic level is applied on pin MODE, then Frequency Shift Keying (FSK) modulation is selected. This modulation is achieved by crystal pulling. An internal switch connected to CFSK pin enables to switch the external crystal load capacitors. Figure 2 shows the possible configurations: serial and parallel. The logic level applied on pin DATA controls the state of this internal switch: DATA=0 -> switch off, DATA=1 -> switch on. DATA input is internally re-synchronized by the crystal reference signal. The corresponding jitter on the data duty cycle cannot exceed 1 reference period (75ns for a 13.56MHz crystal). This crystal pulling solution implies that the RF output frequency deviation equals the crystal frequency deviation multiplied by the PLL divider ratio (see table 1). MOTOROLA SEMICONDUCTORS PRODUCTS 3 MC33493 Figure 2: Crystal pulling configurations MICROCONTROLLER INTERFACE Four digital input pins (ENABLE, DATA, BAND and MODE) enable the circuit to be controlled by a microcontroller. It is recommended to configure the band frequency and the modulation type before enabling the circuit. One digital output (DATACLK) provides to the microcontroller a reference frequency for data clocking.This frequency is equal to the crystal oscillator frequency divided by 64 (see table 2). Table 2: DATACLK frequency versus crystal oscillator frequency Crystal oscillator DATACLK frequency (MHz) frequency (kHz) 9.84 154 13.56 212 MOTOROLA SEMICONDUCTORS PRODUCTS 4 MC33493 STATE MACHINE Figure 3 details the state machine. Figure 3: State machine Power ON AND ENABLE=0 State 1 Standby mode ENABLE=0 ENABLE=1 State 2 PLL out of lock-in range No RF output PLL in lock-in range PLL out of lock-in range ENABLE=0 State 4 Shutdown mode VBattery < VShutdown State 3 Transmission mode State 1: The circuit is in standby mode and draws only a leakage current from the power supply. State 2: In this state, the PLL is out of the lock-in range. Therefore the RF output stage is switched off preventing RF transmission. Data clock is available on pin DATACLK. Each time the device is enabled, the state machine passes through this state. State 3: In this state, the PLL is within the lock-in range. If t