Intel® Pentium® 4 Processor on
90 nm Process
Datasheet
2.80 GHz – 3.40 GHz Frequencies Supporting Hyper-Threading
Technology1 for All Frequencies with 800 MHz Front Side Bus
February 2005
Document Number: 300561-003
2Datasheet
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ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATE NT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no resp onsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Pentium® 4 processor on 90 nm process may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Curr ent characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
1Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading
Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use.
See http://www.intel.com/info/hyperthreading/ for more information including details on which processors suppor t HT Technology.
Intel, Pentium, Intel NetBurst, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United Stat es
and other countries.
*Other names and brands may be claimed as the property of othe rs.
Copyright © 2004–2005, Int el Corporation. All rights reserved.
Datasheet 3
Contents
1 Introduction..................................................................................................................9
1.1 Terminology.........................................................................................................10
1.1.1 Processor Packaging Terminology.........................................................10
1.2 References..........................................................................................................11
2 Electrical Specifications........................................................................................13
2.1 Power and Ground Pins......................................................................................13
2.2 Decoupling Guidelines ........................................................................................13
2.2.1 VCC Decoupling......................................................................................13
2.2.2 FSB GTL+ Decoupling ...........................................................................13
2.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking....................................14
2.3 Voltage Identification.................... ... .... ... ... ... .................................... ...................14
2.3.1 Phase Lock Loop (PLL) Power and Filter...............................................16
2.4 Reserved, Unused, and TESTHI Pins.............. ... ................... .............................17
2.5 FSB Signal Groups..............................................................................................18
2.6 Asynchronous GTL+ Signals...............................................................................19
2.7 Test Access Port (TAP) Connection....................................................................19
2.8 FSB Frequency Select Signals (BSEL[1:0])........................................................20
2.9 Absolute Maximum and Minimum Ratings..........................................................21
2.10 Processor DC Specifications............... ... ... ... .................... ... ... ... .... ... ...................21
2.11 VCC Overshoot Specification...............................................................................29
2.11.1 Die Voltage Validation.. ................... .... ... ... ................... .... ... ... ... .............30
3 Package Mechanical Specifications.................................................................31
3.1 Package Mechanical Specifications....................................................................31
3.1.1 Package Mechanical Drawing................................................................32
3.1.2 Processor Component Keep-out Zones.................................................35
3.1.3 Package Loading Specifications ............................................................35
3.1.4 Package Handling Guidelines ................................................................35
3.1.5 Package Insertion Specifications ...........................................................36
3.1.6 Processor Mass Specification ................................................................36
3.1.7 Processor Materials................................................................................36
3.1.8 Processor Markings......... ... .... ... ... ... .... ... ... ................... .... ... ...................36
3.1.9 Processor Pinout Coordinates................................................................37
4 Pin List and Signal Description..........................................................................39
4.1 Processor Pin Assignments ................................... ... ... .................... ... ... ... ..........39
4.2 Alphabetical Signals Reference ..........................................................................54
5 Thermal Specifications and Design Considerations.................................63
5.1 Processor Thermal Specifications.......................................................................63
5.1.1 Thermal Specifications........................ ... ... ... .................... ... ... ... ... .... ......63
5.1.2 Thermal Metrology ............. .... ... ... ... .... ... ... ... ... .................... ... ... ... .... ... ...66
5.2 Processor Thermal Features..................... ................... .... ... ... ... .... ................... ...67
5.2.1 Thermal Monitor........... ... ... .... ... ... ... .... ................... ... ... .... ... ...................67
4Datasheet
5.2.2 On-Demand Mode. ... .... ... ... .................... ... ... ... ... .... ................... ... ... .... ...68
5.2.3 PROCHOT# Signal Pin..........................................................................68
5.2.4 THERMTRIP# Signal Pin.......................................................................69
5.2.5 Tcontrol and Fan Speed Reduction..........................................................69
5.2.6 Thermal Diode........................................................................................69
6Features.......................................................................................................................71
6.1 Power-On Configuration Options ........................................................................71
6.2 Clock Control and Low Power States..................................................................72
6.2.1 Normal State—State 1 ...........................................................................72
6.2.2 AutoHALT Powerdown State—State 2 ..................................................72
6.2.3 Stop-Grant State—State 3 .....................................................................73
6.2.4 HALT/Grant Snoop State—State 4 ........................................................73
6.2.5 Sleep State—State 5..............................................................................74
7 Boxed Processor Specifications.......................................................................75
7.1 Mechanical Specifications...................................................................................76
7.1.1 Boxed Processor Cooling Solution Dimensions.....................................76
7.1.2 Boxed Processor Fan Heatsink Weight..................................................77
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach
Clip Assembly ........................................................................................78
7.2 Electrical Requirements ......................................................................................78
7.2.1 Fan Heatsink Power Supply...................................................................78
7.3 Thermal Specifications........................................................................................79
7.3.1 Boxed Processor Cooling Requirements ...............................................79
7.3.2 Variable Speed Fan ........ ................... .... ... ... ... ... .................... ... ... ... .... ...81
Datasheet 5
Figures
1 Phase Lock Loop (PLL) Filter Requirements ......................................................16
2V
CC Static and Transient Tolerance for Loadline A............. ................... .............24
3V
CC Static and Transient Tolerance for Loadline B............. ................... .............26
4V
CC Overshoot Example Waveform....................................................................30
5 Processor Package Assembly............. ... ... ... .... ... ... ... ... .................... ... ... ... ..........31
6 Processor Package Drawing (Sheet 1 of 2)........................................................33
7 Processor Package Drawing (Sheet 2 of 2)........................................................34
8 Processor Top-Side Markings... ... .................... ... ... ... ... .... ................... ... ... .... ... ...36
9 Processor Pinout Coordinates (Top View)..........................................................37
10 Pinout Diagram (Top View—Left Side) ............... ... ... ... .... ... ... ... .... ... ... ... ... ..........40
11 Pinout Diagram (Top View—Right Side)...... .... ................... ... ... .... ... ... ... ... .... ... ...41
12 Thermal Profile... .... ... ... ... ... .... ... ... ... .................... ... ................... .... ................... ...66
13 Case Temperature (TC) Measurement Location.................................................66
14 Stop Clock State Machine...................... ... ... .... ... ... ................................... ..........72
15 Mechanical Representation of the Boxed Processor ..........................................75
16 Space Requirements for the Boxed Processor (Side View)................................76
17 Space Requirements for the Boxed Processor (Top View).................................77
18 Boxed Processor Fan Heatsink Power Cable Connector Description.... ... .... ... ...78
19 Baseboard Power Header Placement Relative to Processor Socket..................79
20 Boxed Processor Fan Heatsink Airspace Keep-out Requirements
(side 1 view)........................................................................................................80
21 Boxed Processor Fan Heatsink Airspace Keep-out Requirements
(side 2 view)........................................................................................................80
22 Boxed Processor Fan Heatsink Set Points .........................................................81
6Datasheet
Tables
1 References..........................................................................................................11
2 Core Frequency to FSB Multiplier Configuration.................................................14
3 Voltage Identification Definition...........................................................................15
4 FSB Pin Groups .............. ... ... .... ... ... ... .... ................... ................................... .......18
5 Signal Characteristics .........................................................................................19
6 Signal Reference Voltages..................................................................................19
7 BSEL[1:0] Frequency Table for BCLK[1:0] ......................... ... ... ... .... ... ... ... ... .... ...20
8 Processor DC Absolute Maximum Ratings.........................................................21
9 Voltage and Current Specifications.....................................................................22
10 VCC Static and Transient Tolerance for Loadline A.............................................23
11 VCC Static and Transient Tolerance for Loadline B.............................................25
12 GTL+ Signal Group DC Specifications................................................................27
13 Asynchronous GTL+ Signal Group DC Specifications........................................27
14 PWRGOOD and TAP Signal Group DC Specifications ......................................28
15 VCCVID DC Specifications .................................................................................28
16 VIDPWRGD DC Specifications....... ... .... ... ... ... .... ... ... ... ... .................... ... ... ... .... ...28
17 BSEL [1:0] and VID[5:0] DC Specifications.........................................................29
18 BOOTSELECT DC Specificat ions............................. ... ... .... ... ... ................... .... ...29
19 VCC Overshoot Specifications.............................................................................29
20 Processor Loading Specifications.......................................................................35
21 Package Handling Guidelines.............................................................................35
22 Processor Materials ............................................................................................36
23 Alphabetical Pin Assignment...............................................................................42
24 Numerical Pin Assignment..................................................................................48
25 Signal Description ...............................................................................................54
26 Processor Thermal Specifications.......................................................................64
27 Thermal Profile....................................................................................................65
28 Thermal Diode Parameters.................................................................................70
29 Thermal Diode Interface......................................................................................70
30 Power-On Configuration Option Pins..................................................................71
31 Fan Heatsink Power and Signal Specifications...................................................79
32 Boxed Processor Fan Heatsink Set Points .........................................................81
.
Datasheet 7
Revision History
§
Revision Description Date
-001 • Initial release February 2004
-002 • Added specifications for 3.20 GHz processors with PRB = 1
• Added ISGNT/ISLP specifications
• Updated thermal diode specifications
• Other changes marked with change bars
April 2004
-003 • Added specifications for 3.40 GHz processors with PRB = 0 February 2005
8Datasheet
Intel® Pentium® 4 Processor on 90 nm
Process 2.80A/E GHz, 3E GHz, 3.20E
GHz, and 3.40E GHz
§
•Available at 2.80A/E GHz, 3E GHz,
3.20E GHz, and 3.40E GHz
•Supports Hyper-Threading Technology1
(HT Technology) for all frequencies wit h
800 MHz front side bus (FSB)
•Binary compatible with applications
running on previous members of th e Intel
microprocessor line
•Intel NetBurst® microarchitecture
•FSB frequencies at 533 MHz, and
800 MHz
•Hyper-Pipelined Technology
—Advance Dynamic Execution
—Very deep out-of-order execution
•Enhanced branch prediction
•Optimized for 32-bit applications running
on advanced 32-bit operating systems
•478-Pin Package
•16-KB Level 1 data cache
•1-MB Advanced Transfer Cache (on-die,
full-speed Level 2 (L2) cache) with 8-way
associativity and Error Correcting Code
(ECC)
•144 Streaming SIMD Extensions 2
(SSE2) instructions
•13 Streaming SIMD Extensions 3 (SSE3)
instructions
•Enhanced floating point and multimedia
unit for enhanced video, audio,
encryption, and 3D performance
•Power Management capab ilities
—System Management mode
—Multiple low-power states
•8-way cache associativity provides
improved cache hit rate on load/store
operations
Datasheet 9
Introduction
1Introduction
The Intel® Pentium® 4 processor on 90 nm process is a follow on to the Int e l® Pentiu m® 4
processor in the 478-pin package with enhancements to the Intel NetBurst® microarchitecture. The
Pentium 4 processor on 90 nm process uses Flip-Chip Pin Grid Array (FC-m P GA4) package
technology, and plugs in to a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to
as the mPGA478B so cket. The Penti um 4 processor on 90 nm process, like its predecessor, the
Pentium 4 processor in the 478-pin package, is based on the same Intel 32-bit microarchitecture
and maintains the traditio n of com patibility with IA-32 software.
Note: In this document the Pentium 4 processor on 90 nm process is also referred to as the processor.
The Pentium 4 processor on 90 nm process supports Hyper-Threading Technology1. Hyper-
Threading Technolog y allows a single, physical processor to function as two logical processors.
While some execution resources (such as caches, execution units, and buses) are shared, each
logical processor has its own architecture state with its own set of general-purpose registers,
control registers to provide increased system responsiveness in multitasking environments, and
headroom for next generation multithreaded appli cations. Intel recommends enabling Hy per-
Threading Technolog y with Microsoft Windows* XP Professional or Windows* XP Home, and
disabling Hyper-Threading Technology via the BIOS for all previous versions of Windows
operating systems. For more information on Hyper-Threading Technology, see www.intel.com/
info/hyperthreading. Refer to Section 6.1, for Hyper-Threading Technology configuration details.
In addition to supporting all the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new
instructions that further extend the capabilities of Intel processor technology. These new
instructions are called Streaming SIMD Extensions 3 (SSE3).These new instructions enhance the
performance of optimized applications for the di git a l hom e such as vide o, image processing and
media compression technology . 3D graphics and other entertainment applications (such as gaming)
will have the opportunity to take advantage of these new instructions as platforms with the Pentium
4 processor on 90 nm process and SSE3 become av ailable in the market place.
The processor’s Intel NetBurst microarchitecture front side bus (FSB) uses a split-transaction,
deferred reply protocol like the Pentium 4 processor. The Intel NetBurst microarchitecture FSB
uses Source-Synchronous Transfer (SST) of address and data to improve performance by
transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X
data bus, the address bus can deliver addresses two times per bus clock and is referred to as a
"double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to 6.4 GB/s.
Intel will enable support compo nents for the processor including heatsink, heatsink retention
mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be
completed from the top of the basebo ard and sho uld not require any special tooling .
The processor includes an address bus powerdown capability that removes power from the address
and data pins when the FSB is not in use. This feature is always enabled on the processor.
10 Datasheet
Introduction
1.1 Terminology
A ‘#’ symbol after a signal name ref e rs to an active low signal, indicating a signal is in the active
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“FSB” refers to the interface between the processor and system core logic (i.e., the chipset
components). The FSB is a multiprocessing interface to processors, memory, and I/O.
1.1.1 Processor Packaging Terminology
Commonly used terms are explained here for clarificatio n:
•Intel® Pentium® 4 processor on 90 nm process — Processor in the FC-mPGA4 package
with a 1-MB L2 cache.
•Processor — For this document, the term processor is the generic form of the Pentium 4
processor on 90 nm process.
•Keep-out zone — The area on or near the processor that system design cannot use.
•Intel® 865G/865GV/865PE/865P chipset — Chipset that supports DDR memory technology
for the Pentium 4 processor on 90 nm process.
•Intel® 875P chipset — Chipset that supports DDR memory technology for the Pentium 4
processor on 90 nm process
•Processor core — Processor core die with integrated L2 cache.
•FC-mPGA4 package — The Pentium 4 processor on 90 nm process is availab le in a Flip-
Chip Micro Pin Grid Array 4 package, consis ti ng of a processor core mounted on a pinned
substrate with an integrated heat spreader (IHS). This packaging technology employs a
1.27 mm [0.05 in] pitch for the substrate pins.
•mPGA478B socket — The Pentium 4 processor on 90 nm process mates with the system
board through a surface mount, 478-pin , zero insertion force (ZIF) socket.
•Integrated heat spreader (IHS) —A component of the processor package used to enhance
the thermal performance of the package. Component thermal solutions interface with the
processor at the IHS surface.
•Retention mechanism (RM)—Since the mPGA478B socket does not include any mechanical
features for heatsink attach, a retention mechanism is required. Component thermal solutions
should attach to the processor via a retention mechanism that is independent of the socket.
•Storage conditions — Refers to a non-operation al state. The processor may be installed in a
platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air.
Under these conditions, pro cessor pins should not be connected to any supply volt a ges, have
any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e. unsealed packaging or
a device removed from packaging material) the processor must handled in accordance with
moisture sensitivity labeling (MSL) as indi cated on the packaging material.
•Functional operation — Refers to normal operating conditions in which all processor
specifications, including DC, AC, FSB, signal qua lity, mechanical and thermal, are satisfied.
Datasheet 11
Introduction
1.2 References
Material and concepts available in the following documents may be beneficial when reading this
document.
§
Table 1. References
Document Location
Intel® Pentium® 4 Processor Specification Update http://developer.intel.com/design/
pentium4/specupdt/249199.htm
Intel® 865G/865GV/865PE/865P Chipset Platform Design Guide http://developer.intel.com/design/
chipsets/designex/252518.htm
Intel® 875P Chipset Platform Design Guide http://developer.intel.com/design/
chipsets/designex/252527.htm
Intel® Pentium® 4 Processor on 90 nm Process Thermal Design
Guidelines http://developer.intel.com/design/
Pentium4/guides/300564.htm
Voltage Regulator-Down (VRD) 10.0: for Desktop Socket 478 Design
Guide http://developer.intel.com/design/
Pentium4/guides/252885.htm
Intel® Pentium®4 Processor 478-Pin Socket (mPGA478B) Socket
Design Guidelines http://developer.intel.com/design/
pentium4/guides/249890.htm
Intel® Architecture Software Developer's Manual
IA-32 Intel® Architecture Software Developer’s Manual
Volume 1: Basic Architecture
http://www.intel.com/design/
pentium4/manuals/index_new.htm
IA-32 Intel® Architecture Software Developer’s Manual,
Volume 2A: Instruction Set Reference, A-M
IA-32 Intel® Architecture Software Developer’s Manual,
Volume 2A: Instruction Set Reference, N-Z
IA-32 Intel® Architecture Software Developer’s Manual,
Volume 3: System Programming Guide
AP-485 Intel® Processor Identification and the CPUID Instruction http://developer.intel.com/design/
xeon/applnots/241618.htm
ITP700 Debug Port Design Guide http://developer.intel.com/design/
Xeon/guides/249679.htm
12 Datasheet
Introduction
Datasheet 13
Electrical Specifications
2Electrical Specifications
2.1 Power and Ground Pins
For clean on-chip power distribution, the processor has 85 VCC (power) and 179 VSS (ground)
pins. All power pins must be connected to VCC, while all VSS pins must be connected to a system
ground plane.The processor VCC pins must be supplied by the voltage determined by the VID
(Voltage identification) pins.
2.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large current swings between low and full power states. This may cause voltages on
power planes to sag below their minimum values if bulk decoupling is not adequ a te. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in Table 9. Failure to do so can result in tim ing violations or reduced lifetime
of the component. For further information and design guidelines, refer to the appropriate platform
design guide, and the Voltage Regulator-Down (VRD) 10.0 Design Guidelines for Desktop Socket
478.
2.2.1 VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the
large current sw ings when the part is poweri ng on, or entering/exiting low power states, must be
provided by the voltage regulato r solution (VR). For more details on this topic, refer to the
appropriate platform design guide, and the Voltage Regulator-Down (VRD) 10.0 Design Guidelines
for Desktop Socket 478.
2.2.2 FSB GTL+ Decoupling
The processor integrates signal termination on the die as well as incorporating high frequency
decoupling capacitance on the processor package. Decoupling must also be provided by the system
baseboard for proper GTL+ bus operation. For more information, refer to the appropriate platform
design guide.
14 Datasheet
Electrical Specifications
2.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.
As in previous generation processors, the processor core frequency is a multiple of the BCLK[1:0]
frequency. No user intervention is necessary, and the processor will automatically run at the speed
indicated on the package. The processor uses a differential clocking implementation .
2.3 Voltage Identification
The VID specification for the processor is supported by the Voltage Regulator-Down (VRD) 10.0
Design Guidelines for Desktop Socket 478. The voltage set by the VID pins is the maximum
voltage allowed by the processor. A mini mum voltage is provided in Table 9 and changes with
frequency. This allow s processors running at a higher frequency to have a relaxed minimum
voltage specification. The specifications have been set such that one voltage regulat or can work
with all supported frequencies.
Individual processor VID va lues may be calib rated during manufacturing such that two devices at
the same speed may have different VID settings.
The processor uses six voltage identification pins, VID[5:0], to support automatic selection of
power supply voltages. Table 3 specifies the voltage level corresponding to the state of VID [5: 0].
A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to low voltage level. If the processor
socket is empty (VID[5:0] = x1 1111), or the voltage regulation circuit cannot supply the voltage
that is requested, it must disable itself. See the Voltage Regulator-Down (VRD) 10.0 Design
Guidelines for Desktop Socket 478 for more details.
Power source characteristics must be guaranteed to be stable when the supply to the voltage
regulator is stable.
The processor’ s Voltage Identification circuit requires an independent 1.2 V supply and some other
power sequencing considerations.
Table 2. Core Frequency to FSB Multiplier Configuration
Multiplication of System
Core Frequency to FSB
Frequency
Core Frequency
(133 MHz BCLK/533 MHz FSB) Core Frequency
(200 MHz BCLK/800 MHz FSB) Notes
1/14 RESERVED 2.80E GHz
1/15 RESERVED 3E GHz
1/16 RESERVED 3.20E GHz 1
NOTES:
1. Individual processors operate only at or below the rated frequency.
1/17 RESERVED 3.40E GHz 1
1/18 RESERVED RESERVED 1
1/19 RESERVED RESERVED 1
1/20 RESERVED RESERVED 1
1/21 2.80A GHz RESERVED 1
Datasheet 15
Electrical Specifications
Table 3. Voltage Identificatio n Definition
VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID
001010 0.8375 0110101.2125
101001 0.8500 1110011.2250
001001 0.8625 0110011.2375
101000 0.8750 1110001.2500
001000 0.8875 0110001.2625
100111 0.9000 1101111.2750
000111 0.9125 0101111.2875
100110 0.9250 1101101.3000
000110 0.9375 0101101.3125
100101 0.9500 1101011.3250
000101 0.9625 0101011.3375
100100 0.9750 1101001.3500
000100 0.9875 0101001.3625
100011 1.0000 1100111.3750
000011 1.0125 0100111.3875
100010 1.0250 1100101.4000
000010 1.0375 0100101.4125
100001 1.0500 1100011.4250
000001 1.0625 0100011.4375
100000 1.0750 1100001.4500
000000 1.0875 0100001.4625
111111VR output off 1011111.4750
011111VR output off 0011111.4875
111110 1.1000 1011101.5000
011110 1.1125 0011101.5125
111101 1.1250 1011011.5250
011101 1.1375 0011011.5375
111100 1.1500 1011001.5500
011100 1.1625 0011001.5625
111011 1.1750 1010111.5750
011011 1.1875 0010111.5875
111010 1.2000 1010101.6000
16 Datasheet
Electrical Specifications
2.3.1 Phase Lock Loop (PLL) Power and Filter
VCCA and VCCIOPLL are power sources required by the PLL clock generators on the processor
silicon. Since these PLLs are analog, they require low noise power supplies for minimum jitter.
Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings
(i.e., maximum frequency). To prev ent this degradation, these supplies must be low pass filtered
from VCC.
The AC low-pass requirements, with input at VCC are as follows:
•< 0.2 dB gain in pass band
•< 0.5 dB attenuation in pass band < 1 Hz
•> 34 dB attenuation from 1 MHz to 66 MHz
•> 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 1. For recommendations on implementing the filter,
refer to the appropriate platform design guide.
.
NOTES:
1. Diagram not to scale.
2. No specification exists for frequencies beyond fcore (core frequency).
3. fpeak, if existent, should be less than 0.05 MHz.
Figure 1. Phase Lock Loop (PLL) Filte r Requirements
0 dB
–28 dB
–34 dB
0.2 dB
–0.5 dB
1 MHz 66 MH z fcorefpeak1 HzDC
Passband High
Frequency
Band
Forbidden
Zone
Forbidden
Zone
Datasheet 17
Electrical Specifications
2.4 Reserved, Unused, and TESTHI Pins
All RESERVED pins must remain unconnected. Connection of these pin s to VCC, VSS, or to any
other signal (including each other) can result in component mal fun ction or incompatibility with
future processors. See Chapter 4 for a pin listing of the processor and the location of all
RESERVED pins.
For reliable operation, always connect unused inputs or bi directional signals to an appropriate
signal level. In a system level design, on-die termination has been included on the processor to
allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be
left as no connects since GTL+ termination is provided on the processor silicon. However, see
Table 5 for details on GTL+ signals that do not include on-die terminat ion. Unused active high
inputs should be connected through a resisto r to ground (VSS). Unused outputs can be left
unconnected; however, this may interfere with some test access port (TAP) functions, complicate
debug probing, and prevent boundary scan testing. A resistor must be used when tying
bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. For unused GTL+ input or I/O signals, use pull-up resistors of the
same value as the on-die termination resistors (RTT).
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ out puts do no t include on-die
termination. Inputs and used outputs must be terminated on the system board. Unused outputs may
be terminated on the system board or left unconnected. Note that leaving unused outputs
unterminated may interfere with some TAP functio ns, complicate debug probing, and prevent
boundary scan testing. Signal terminati on for these signal types is discussed in the appropriate
platform design guide.
The TESTHI pins must be tied to the processor VCC using a matched resistor, where a matched
resistor has a resistance value within ±20% of the impedance of the board transmission line traces.
For example, if the trace impedance is 60 Ω, then a value between 48 Ω and 72 Ω is required.
The TESTHI pins may use individual pull-up resistors or be grouped together as detailed below. A
matched resistor must be used for each group:
•TESTHI[1:0]
•TESTHI[7:2]
•TESTHI8 – cannot be grouped with other TESTHI signals
•TESTHI9 – cannot be grouped with other TESTHI signals
•TESTHI10 – cannot be grouped with other TESTHI signals
•TESTHI11 – cannot be grouped with other TESTHI signals
•TESTHI12 – cannot be grouped with other TESTHI signals
18 Datasheet
Electrical Specifications
2.5 FSB Signal Groups
The FSB signals have been combined into groups by buffer type. GTL+ input signals have
differential input buffers that use GTLREF as a reference level. In this document, the term "GTL+
Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly,
"GTL+ Output" refers to the GTL+ output grou p as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock si gnal s th at are dependent on the rising edge of
BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals that
are relative to their respective strobe lines (data and address) as well as the rising edge of BC LK0.
Asychronous signals are still present (A20M#, IGN NE#, etc.) and can become active at an y tim e
during the clock cycle. Table 4 identifies which signals are common clock, source synchrono us,
and asynchronous.
Table 4. FSB Pin Groups
Signal Group Type Signals1
NOTES:
1. Refer to Section 4.2 for signal descriptions.
GTL+ Common Clock
Input Synchronous to
BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
GTL+ Common Clock I/O Synchronous to
BCLK[1:0] AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#,
DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#
GTL+ Source
Synchronous I/O Synchronous to
associated strobe
SignalsAssociated Strobe
REQ[4:0]#, A[16:3]#2ADSTB0#
A[35:17]#2ADSTB1#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#
2. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration
options. See Section 6.1 for details.
GTL+ Strobes Synchronous to
BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Asynchronous GTL+
Input A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,
SLP#, STPCLK#
Asynchronous GTL+
Output FERR#/PBE#, IERR#, THERMTRIP#
Asynchronous GTL+
Input/Output PROCHOT#
TAP Input Synchronous to TCK TCK, TDI, TMS, TRST#
TAP Output Synchronous to TCK TDO
FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]3
3. In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
Power/Other
VCC, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA,
GTLREF[3:0], COMP[1:0], RESERVED, TESTHI[12:0],
THERMDA, THERMDC, VCC_SENSE, VSS_SENSE,
VCCVID, VCCVIDLB, BSEL[1:0], SKTOCC#, DBR#3,
VIDPWRGD, BOOTSELECT, OPTIMIZED/COMPAT#,
PWRGOOD
Datasheet 19
Electrical Specifications
2.6 Asynchronous GTL+ Signals
Legacy input signals (such as A20M#, IGNNE#, INIT#, SMI#, SLP#, and STPCLK#) use CMOS
input buffers. All of these signals follow the same DC requirements as GTL+ signals; however , the
outputs are not actively driven hig h (durin g a logical 0-to-1 transition) by the processor. These
signals do not have setup or hold time specificat ions in relatio n to BCLK[1:0].
2.7 Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the processor be first in the TA P chain and followed by any oth e r components
within the system. A translation buffer should be used to connect to the rest of the chain unless one
of the other components is capable of accepting an input of the appropriate voltage level. Similar
considerations must be made for TCK, TMS, TRST#, TDI, and TDO. Two copies of each signal
may be required, with each driving a different voltage level.
Table 5. Signal Characteristics
Signals with RTT Signals with No RTT
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BOOTSELECT1, BPRI#, D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
OPTIMIZED/COMPAT#1, PROCHOT#, REQ[4:0]#,
RS[2:0]#, RSP#, TRDY#
NOTES:
1. The OPTIMIZED/COMPAT# and BOOTSELECT pins have a 500–5000 Ω pull-up to VCCVID rather than RTT.
A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[1:0],
COMP[1:0], FERR#/PBE#, IERR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#,
SKTOCC#, SLP#, SMI#, STPCLK#, TDO,
TESTHI[12:0], THERMDA, THERMDC,
THERMTRIP#, VID[5:0], VIDPWRGD,
GTLREF[3:0], TCK, TDI, TRST#, TMS
Open Drain Signals2
2. Signals that do not have RTT, nor are actively driven to their high-voltage level.
BSEL[1:0], VID[5:0], THERMTRIP#, FERR#/PBE#,
IERR#, BPM[5:0]#, BR0#, TDO
Table 6. Signal Reference Voltages
GTLREF VCC/2 VCCVID/2
BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#, BNR#,
HIT#, HITM#, MCERR#, PROCHOT#, BR0#, A[35:0]#, ADS#,
ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#,
DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,
LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
A20M#, IGNNE#, INIT#,
PWRGOOD1, SLP#,
SMI#, STPCLK#, TCK1,
TDI1, TMS1, TRST#1
NOTES:
1. These signals also have hysteresis added to the reference voltage. See Table 14 for more information.
VIDPWRGD,
BOOTSELECT,
OPTIMIZED/
COMPAT#
20 Datasheet
Electrical Specifications
2.8 FSB Frequency Select Signals (BSEL[1:0])
The BSEL[1:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).
Table 7 defines the possible combinations of the signals and the frequency associated with each
combination. The required frequency is determined by the processor, chipset, and clock
synthesizer. All agents must operate at the same frequency.
The processor operates at a 533 MHz or 800 MHz FSB frequency (selected by a 133 MHz or
200 MHz BCLK[1:0] frequency). Individual processors will only operate at their specified FSB
frequency.
For more information about these pins, refer to Section 4.2 and the appropriate platform design
guide.
Table 7. BSEL[1:0] Frequency Table for BCLK[1:0]
BSEL1 BSEL0 Function
L L RESERVED
L H 133 MHz
H L 200 MHz
H H RESERVED
Datasheet 21
Electrical Specifications
2.9 Absolute Maximum and Minimum Ratings
Table 8 specifies abso lute maximum and minimum ratings. Within functional operation limits,
functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute maximum and
minimum ratings, neither functi onality nor long-term reliability can be expected. If a device is
returned to conditions withi n functional operation limits after having been subjected to conditions
outside these li mi ts, but within the absolute maximum and mini mum ratings, the device may be
functional, but with its lifetime degraded depending on exposure to conditions exceeding the
functional operation condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-
term reliability can be expected. Moreover, if a device is subjected to these conditions for any
length of time then, when returned to conditions within the functional operating condition limits, it
will either not function, or its reliability will be severely degraded.
Although the processor contains protective circuitry to resist damage from static electric discharg e,
precautions should always be taken to avoid high static voltages or electric fields.
NOTES:
1. For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must
be satisfied.
2. Storage temperature is applicable to storage conditions only . In this scenario, the processor must not receive
a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-
term reliability of the device. F or functional operation, refer to the processor case temperature specifications.
3. This rating applies to the processor and does not include any tray or packaging.
2.10 Processor DC Specifications
The pr oces sor DC spec ifica tions i n this se ction are defined at the processor cor e silico n and not
at the package pins unless noted otherwise. See Chapter 4 for the pin signal defini tions and signal
pin assignments. Most of the signals on the processor FSB are in the GTL+ signal group. The DC
specifications for these signals are listed in Table 12.
Previously, legacy signals and Test Access Port (TAP) signal s to the processor used low-voltage
CMOS buffer types. However, these interfaces now follow DC specifications similar to GTL+. The
DC specifications for these signal groups are listed in Table 13 and Table 14.
Table 9 through Table 17 list the DC specifications for the processor and are valid only while
meeting specifications for case temperature, clock frequency, and input voltages. Care should be
taken to read all notes associated with each parameter.
MSR_PLATFORM_BRV bit 18 is a Platform Requirement Bit (PRB) that indicates that the
processor has specific platform requirements.
Table 8. Processor DC Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
VCC Any processor supply voltage with
respect to VSS - 0.3 1.55 V 1
TCProcessor case temperature See Section 5 See Section 5 °C 2, 3
TSTORAGE Processor storage temperature –40 +85 °C 2, 3
22 Datasheet
Electrical Specifications
Table 9. Voltage and Current Specifications
Symbol Parameter Min Typ Max Unit Notes1
VID range VID 1.250 1.400 V 2
VCC
VCC Loadline A processors
3.20E GHz (PRB = 1)
3.40E GHz (PRB = 1)
See Table 10 and
Figure 2 VID – ICC(max) * 1.45 mΩV3,4,5
VCC
VCC Loadline B processors
2.80A/E GHz (PRB = 0)
3E GHz (PRB = 0)
3.20E GHz (PRB = 0)
3.40E GHz (PRB = 0)
See Table 11 and
Figure 3 VID – ICC(max) * 1.45 mΩV3,4,5
ICC
ICC for processor with multiple VID:
2.80A/E GHz (PRB = 0)
3E GHz (PRB = 0)
3.20E GHz (PRB = 0)
3.40E GHz (PRB = 0)
3.20E GHz (PRB = 1)
3.40E GHz (PRB = 1)
78
78
78
78
91
91
A6
ISGNT
ISLP
ICC Stop-Grant:
2.80A/E GHz (PRB = 0)
3E GHz (PRB = 0)
3.20E GHz (PRB = 0)
3.40E GHz (PRB = 0)
3.20E GHz (PRB = 1)
3.40E GHz (PRB = 1)
40
40
40
40
50
50
A7,8,10
ITCC ICC TCC active ICC A9
ICC_VCCA ICC for PLL pins 60 mA 10
ICC_VCCIOPLL ICC for I/O PLL pin 60 mA 10
ICC_GTLREF ICC for GTLREF pins (all pins) 200 µA
ICC_VCCVID/
VCCVIDLB ICC for VCCVID/VCCVIDLB 150 mA 10
NOTES:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.
2. Individual processor VID values may be calibrated during manu facturin g such that two devices at the same speed may ha ve
different VID settings.
3. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is re-
quired. See Section 2.3 and Table 3 for more information.
4. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the socket with a
100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length
of ground wire on the probe should be less than 5 mm. Ensur e external noise from the system is not coupled into the oscillo-
scope probe.
5. Refer to Table 10/Figure 2 or Table 11/Figure 3 for the minimum, typical, and maximum VCC allowed for a g iven current. The
processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current. Moreover ,
VCC should never exceed the VID voltage. Failure to adhere to this specification can shorten the processor lifetime.
6. ICC_MAX is specified at VCC_MAX
7. The current specified is also for the AutoHALT State.
8. ICC Stop-Grant and ICC Sleep are specified at VCC_MAX.
9. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the as-
sertion of PROCHOT# is the same as the maximum ICC for the processor.
Datasheet 23
Electrical Specifications
10. These parameters are based on design characterization and are not tested.
Table 10. VCC Static and Transient Tolerance for Loadline A
Icc (A) Voltage Deviation from VID Setting (V)1,2,3
NOTES:
1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in
Section 2.11.
2. This table is intended to aid in reading discrete points on Figure 2.
3. The loadlines specify voltage limit s at the die measured at the VCC_SENSE and VSS_SENSE pins. V oltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer
to the Voltage Regulator-Down (VRD) 10.0 Design Guide for socket loadline guidelines and VR implemen-
tation details for 478_VR_CONFIG_A.
Maximum Voltage Typical Voltage Minimum Voltage
0 0.000 -0.019 -0.038
5 -0.007 -0.027 -0.047
10 -0.015 -0.035 -0.055
15 -0.022 -0.043 -0.064
20 -0.029 -0.051 -0.072
25 -0.036 -0.058 -0.081
30 -0.044 -0.066 -0.089
35 -0.051 -0.074 -0.098
40 -0.058 -0.082 -0.106
45 -0.065 -0.090 -0.115
50 -0.073 -0.098 -0.123
55 -0.080 -0.106 -0.132
60 -0.087 -0.114 -0.140
65 -0.094 -0.121 -0.149
70 -0.102 -0.129 -0.157
75 -0.109 -0.137 -0.166
80 -0.116 -0.145 -0.174
85 -0.123 -0.153 -0.183
90 -0.131 -0.161 -0.191
91 -0.132 -0.162 -0.193
24 Datasheet
Electrical Specifications
NOTES:
1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in
Section 2.11.
2. This loadline specification shows the deviation from the VID set point.
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to
the Voltage Regulator-Down (VRD) 10.0 Design Guide for socket loadline guidelines and VR implementation
details for 478_VR_CONFIG_A.
Figure 2. VCC Static and Transient Tolerance for Loadline A
VID - 0.000
VID - 0.038
VID - 0.076
VID - 0.114
VID - 0.152
VID - 0.190
VID - 0.228
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 9
0
Icc [A]
Vcc [V]
Vcc
Typical
Vcc
Maximum
Vcc
Minimum
Datasheet 25
Electrical Specifications
Table 11. VCC Static and Transient Tolerance for Loadline B
Icc (A) Voltage Deviation from VID Setting (V)1,2,3
NOTES:
1. The loadline specification includes both static and transient limits except for overshoot allowed
as shown in Section 2.11.
2. This table is intended to aid in reading discrete points on Figure 3.
3. The loadlines specify volt age limit s at the die measured at the VCC_SENSE and VSS_SENSE
pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor
VCC and VSS pins. Refer to the Voltage Regulator-Down (VRD) 10.0 Design Guide for socket
loadline guidelines and VR implementation details for 478_VR_CONFIG_B.
Maximum Voltage Typical Voltage Minimum Voltage
0 0.000 -0.025 -0.050
5 -0.007 -0.033 -0.059
10 -0.015 -0.041 -0.068
15 -0.022 -0.049 -0.077
20 -0.029 -0.058 -0.086
25 -0.036 -0.066 -0.095
30 -0.044 -0.074 -0.104
35 -0.051 -0.082 -0.113
40 -0.058 -0.090 -0.122
45 -0.065 -0.098 -0.131
50 -0.073 -0.106 -0.140
55 -0.080 -0.114 -0.149
60 -0.087 -0.123 -0.158
65 -0.094 -0.131 -0.167
70 -0.102 -0.139 -0.176
75 -0.109 -0.147 -0.185
78 -0.113 -0.152 -0.190
26 Datasheet
Electrical Specifications
NOTES:
1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in
Section 2.11.
2. This loadline specification shows the deviation from the VID set point.
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to
the Voltage Regulator-Down (VRD) 10.0 Design Guide for socket loadline guidelines and VR implementation
details for 478_VR_CONFIG_B.
Figure 3. VCC Static and Transient Tolerance for Loadline B
VID - 0.000
VID - 0.025
VID - 0.050
VID - 0.075
VID - 0.100
VID - 0.125
VID - 0.150
VID - 0.175
VID - 0.200
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75
Icc [A]
Vcc [V]
Vcc
Typical
Vcc
Maximum
Vcc
Minimum
Datasheet 27
Electrical Specifications
Table 12. GTL+ Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes1
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
VIL Input Low Voltage 0.0 GTLREF – (0.10 * VCC)V
2, 3
2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. The VCC referred to in these specifications is the instantaneous VCC.
VIH Input High Voltage GTLREF + (0.10 * VCC)V
CC V3, 4
4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
VOH Output High Voltage 0.90*VCC VCC V3
IOL Output Low Current N/A VCC/[(0.50*RTT_MIN)+(RON_MIN)] A
ILI Input Leakage Current N/A ± 200 µA 5
5. Leakage to VSS with pin held at VCC.
ILO Output Leakage Current N/A ± 200 µA 6
6. Leakage to VCC with pin held at 300 mV.
RON Buffer On Resistance 8 12 Ω
Table 13. Asynchronous GTL+ Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes1
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
VIL Input Low Voltage 0.0 VCC/2 – (0.10 * VCC)V
2, 3
2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals,
VIH = GTLREF + (0.10 * VCC) and VIL= GTLREF - (0.10 * Vcc).
VIH Input High Voltage VCC/2 + (0.10 * VCC)V
CC V3, 4, 5
4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. The VCC referred to in these specifications refers to instantaneous VCC.
VOH Output High Voltage 0.90*VCC VCC V 5, 6
6. All outputs are open drain.
IOL Output Low Current VCC/[(0.50*RTT_MIN)+(RON_MIN)] A 7
7. The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.
ILI Input Leakage Current N/A ± 200 µA 8
8. Leakage to Vss with pin held at VCC.
ILO Output Leakage Current N/A ± 200 µA 10
RON Buffer On Resistance 8 12 Ω
28 Datasheet
Electrical Specifications
.
Table 14. PWRGOOD and TAP Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes1, 2
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open drain.
VHYS Input Hysteresis 200 350 mV 3
3. VHYS represents the amount of hysteresis, nominally centered about 0.5 * VCC for all TAP inputs.
VT+ Input low to high threshold
voltage 0.5 * (VCC + VHYS_MIN) 0.5 * (VCC + VHYS_MAX)V 4
4. The VCC referred to in these specifications refers to instantaneous VCC.
VT- Input high to low threshold
voltage 0.5 * (VCC – VHYS_MAX) 0.5 * (VCC – VHYS_MIN)V 4
VOH Output High Voltage N/A VCC V4
IOL Output Low Current 45 mA 5
5. The maximum output current is based on maximum current handling capability of the buffer and is not specified
into the test load.
ILI Input Leakage Current ± 200 µA 6
6. Leakage to VCC with pin held at 300 mV.
ILO Output Leakage Current ± 200 µA 6
RON Buffer On Resistance 7 12 Ω
Table 15. VCCVID DC Specifications
Symbol Parameter Min Typ Max Unit Notes
VCCVID Voltage 1.14 1.2 1.26 V
VCCVIDLB Voltage 1.14 1.2 1.26 V
Table 16. VIDPWR GD DC Specifications
Symbol Parameter Min Typ Max Unit Notes
VIL Input Low Voltage 0.3 V
VIH Input High Voltage 0.9 V
Datasheet 29
Electrical Specifications
.
2.11 VCC Overshoot Specification
The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage
when transitioning from a high-to-low current load condition. This overshoot cannot exceed
VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). The time duration of the
overshoot event must not exceed T OS_MAX (TOS_MAX is the maxi mum allowable time duration above
VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE
and VSS_SENSE pins.
Table 17. BSEL [1:0] and VID[5:0] DC Specifications
Symbol Parameter Max Unit Notes1
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
RON (BSEL) Buffer On Resistance 60 Ω2
2. These parameters are not tested and are based on design simulations.
RON (VID) Buffer On Resistance 60 Ω2
IOL Max Pin Current 8 mA
ILO Output Leakage Current 200 µA 3
3. Leakage to VSS with pin held at 2.5 V.
VTOL Voltage Tolerance 3.3 + 5% V
Table 18. BOOTSELECT DC Specifications
Symbol Parameter Min Typ Max Unit Notes
VIL Input Low Voltage 0.2 * VCCVID V1
NOTES:
1. These parameters are not tested and are based on design simulations.
VIH Input High Voltage 0.8 * VCCVID V1
Table 19. VCC Overshoot Specifications
Symbol Parameter Min Typ Max Unit Figure Notes
VOS_MAX Magnitude of VCC overshoot above
VID 0.050 V 4
TOS_MAX Time duration of VCC overshoot
above VID 25 µs4
30 Datasheet
Electrical Specifications
NOTES:
1. VOS is measured overshoot voltage.
2. TOS is measured time duration above VID.
2.11.1 Die Voltage Validation
Overshoot events from application testing on real processors must meet the specifications in
Table 19 when measured across the VCC_SENSE and VSS_SENSE pins. Overshoot events that
are < 10 ns in duration may be ignored. These measurements of processor die level overshoot
should be taken with a 100 MHz bandwidth limited oscilloscope.
§
Figure 4. VCC Overshoot Example Waveform
Time
Example Overshoot Waveform
Voltage (V)
VID
VID + 0.050
TOS
VOS
TOS: Overshoot time above VID
VOS: Overshoot above VID
Datasheet 31
Package Mechanical Specifications
3Package Mechanical
Specifications
3.1 Package Mechanical Specifications
The Pentium 4 processor on 90 nm process is in a Flip-Chip Pin Grid Array (FC-mPGA4) package
that interfaces with the motherboard via a mPGA478B socket. The package consists of a processor
core mounted on a substrate pin-carrier. An integrated heat spreader (IHS) is attached to the
package substrate and core and serves as the mating surface for processor component thermal
solutions (such as a heatsink). Figure 5 shows a sketch of the processor package componen ts and
how they are assembled together. Refer to the mPGA479, mPGA478A, mPGA478B, mPGA478C,
and mPGA476 Socket Design Guidelines for complete details on the mP GA478B socket.
The package components shown in Figure 5 include the following:
•Integrated Heat Spreader (IHS)
•Thermal Interface Material (TIM)
•Processor core (die)
•Package substrate
•Capacitors
NOTE:
1. Socket and motherboard are included for reference and are not part of processor package.
Figure 5. Processor Package Assembly
SOCKET
SUBSTRATE
IHS
CAPACITORS
CORE (DIE)
MOTHERBOARD
TIM
SOCKET
SUBSTRATE
IHS
CAPACITORS
CORE (DIE)
MOTHERBOARD
TIM
32 Datasheet
Package Mechanical Specifications
3.1.1 Package Mechanical Drawing
The package mechanical drawings are shown in Figure 6 and Figure 7. The drawings include
dimensions necessary to design a thermal solution for the processor. These dimension s include:
•Package reference with tolerances (total height, length, width, etc.)
•IHS parallelism and tilt
•Pin dimensions
•Top-side and back-side component keep-out dimensions
•Reference datums
All drawing dimensions are in mm [in].
Datasheet 33
Package Mechanical Specifications
Figure 6. Processor Package Drawing (Sheet 1 of 2)
34 Datasheet
Package Mechanical Specifications
Figure 7. Processor Package Drawing (Sheet 2 of 2)
Datasheet 35
Package Mechanical Specifications
3.1.2 Processor Component Keep-out Zones
The processor may contain components on the substrate that define component keep-out zone
requirements. A thermal and mechanical solution design must not intrude into the required keep-
out zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the
package substrate. See Figure 6 and Figure 7 for keep-out zones.
The location and quantity of package capacitors may change due to manufacturing efficiencies but
will remain within the component keep-in.
3.1.3 Package Loading Specifications
Table 20 provides dynamic and static load specifications for the processor package. These
mechanical maximum load limits should not be exceeded during heatsink assembly, shipping
conditions, or standard use condit ion. Also, any mechanical system or component testing should
not exceed the maximum limits. The processor package substrate should not be used as a
mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum
loading specification must be maintained by any thermal and mechanical solutions.
.
3.1.4 Package Handling Guidelines
Table 21 includes a list of guidelines on package ha ndli ng in terms of recommended maximum
loading on the processor IHS relative to a fixed substrate. These package hand ling loads may be
experienced during heatsink removal.
Table 20. Processor Loading Specifications
Parameter Minimum Maximum Notes
Static 44 N [10 lbf] 445 N [100 lbf] 1, 2, 3
NOTES:
1. These specifications apply to uniform compressive loading in a direction normal to the processor IHS.
2. This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the
minimum specified load on the processor package.
3. These specifications are based on limited testing for design characterization. Loading limits are for the pack-
age only and does not include the limits of the processor socket.
Dynamic 890 N [200 lbf] 1, 3, 4
4. Dynamic loading is defined as an 1 1 ms duration average load superimposed on the static load requirement.
Transient 667 N [150 lbf] 1, 3, 5
5. T ransient loading is defined as a 2 second duration peak load superimposed on the static load requirement,
representative of loads experienced by the package during heatsink installation.
Table 21. Package Handling Guidelines
Parameter Maxim um Recom mended Notes
Shear 356 N [80 lbf] 1, 2
NOTES:
1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
2. These guidelines are based on limited testing for design characterization.
Tensile 156 N [35 lbf] 2, 3
3. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.
Torque 8 N-m [70 lbf-in] 2, 4
4. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top sur-
face.
36 Datasheet
Package Mechanical Specifications
3.1.5 Package Insertion Specifications
The processor can be inserted into and removed from a mPGA478B so cket 15 times. The socket
should meet the mPGA478B requireme nts detail ed in the mPGA479, mPGA478A, mPGA478B,
mPGA478C, and mPGA476 Socket Design Guidelines.
3.1.6 Processor Mass Specification
The typical mass of the processor is 19 g [0.67 oz]. This mass [weight] includes all the components
that are included in the package.
3.1.7 Processor Materials
Table 22 lists some of the package components and associated materials.
3.1.8 Processor Markings
Figure 8 shows the topside markings on the processor. This diagram is intended to aid in the
identification of the processor.
Table 22. Processor Materials
Component Material
Integrated Heat Spreader (IHS) Nickel Plated Copper
Substrate Fiber Reinforced Resin
Substrate Pins Gold Plated Copper
Figure 8. Processor Top-Side Markings
2-D Matrix Mark
m c `03
SSPEC/Country of Assy
FPO
Product Code
AAAAAAAA
NNNN ATPO
Serial #
INTEL
PENTIUM® 4
X.XXGHZ / 1M / 800
SLXXX MALAY
BBBBBBBB
Brand Copyright Info
Datasheet 37
Package Mechanical Specifications
3.1.9 Processor Pinout Coordinates
Figure 9 shows the top view of the processor pin coordinates. The coordinate s are referred to
throughout the document to identify processor pins.
.
§
Figure 9. Processor Pinout Coordinates (Top View)
Processor
Top View
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
K
J
H
G
F
E
D
C
B
A
L
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
K
J
H
G
F
E
D
C
B
A
L
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Common
Clock
VCC/VSS
Data Address
Clocks VCC/VSS Async/TAP
= VCC
= VSS = Sign al /O t h er
= GTLREF
38 Datasheet
Package Mechanical Specifications
Datasheet 39
Pin List and Signal Description
4Pin List and Signal Description
This chapter provides the processor pinout and signal description.
4.1 Processor Pin Assignments
The pinout footprint is shown in Figure 10 and Figure 11. These figures represent the pinout
arranged by pin number. Table 23 provides the pinout arranged alphabetically by sign al name and
Table 24 provides the pinout arranged num erical ly by pin number.
40 Datasheet
Pin List and Signal Description
Figure 10. Pinout Diagram (Top View—Left Side)
26 25 24 23 22 21 20 19 18 17 16 15 14
AF SKTOCC# Reserved Reserved BCLK1 BCLK0 VCC VSS VCC VSS VCC VSS VCC VSS AF
AE OPTIMIZED/
COMPAT# DBR# VSS VCCA VSS Reserved VCC VSS VCC VSS VCC VSS VCC AE
AD ITP_CLK1 TESTHI12 TESTHI0 VSS VSSA VSS VCCIOPLL VCC VSS VCC VSS VCC VSS AD
AC ITP_CLK0 VSS TESTHI4 TESTHI5 VSS TESTHI2 TESTHI3 VSS VCC VSS VCC VSS VCC AC
AB SLP# RESET# VSS PWR
GOOD TESTHI7 VSS VSS VCC VSS VCC VSS VCC VSS AB
AA VSS D61# D63# VSS D62# GTLREF TESTHI6 VSS VCC VSS VCC VSS VCC AA
YD56# VSS D59# D58# VSS D60# Y
WD55# D57# VSS DSTBP3# DSTBN3# VSS W
VVSS D51# D54# VSS D53# DBI3# V
UD48# VSS D49# D50# VSS D52# U
TD44# D45# VSS D47# D46# VSS T
RVSS D42# D43# VSS DSTBN2# D40# R
PDBI2# VSS D41# DSTBP2# VSS D34# P
ND38# D39# VSS D36# D33# VSS N
MD37# VSS D35# D32# VSS D27# M
LVSS DP3# COMP0 VSS D28# D24# L
KDP2# DP1# VSS D30# DSTBN1# VSS K
JDP0# VSS D29# DSTBP1# VSS D14# J
HVSS D31# D26# VSS D16# D11# H
GD25# DBI1# VSS D18# D10# VSS G
FD22# VSS D20# D19# VSS DSTBP0# GTLREF VCC VSS VCC VSS VCC VSS F
EVSS D21# D17# VSS DSTBN0# DBI0# VCC VSS VCC VSS VCC VSS VCC E
DD23# D15# VSS D13# D5# VSS VSS VCC VSS VCC VSS VCC VSS D
CD12# VSS D8# D7# VSS D4# VCC VSS VCC VSS VCC VSS VCC C
BVSS D9# D6# VSS D1# D0# VSS VCC VSS VCC VSS VCC VSS B
AVSS D3# VSS D2# Reserved VSS VCC VSS VCC VSS VCC VSS VCC A
26 25 24 23 22 21 20 19 18 17 16 15 14
Datasheet 41
Pin List and Signal Description
Figure 11. Pinout Diagram (Top View—Right Side)
13 12 11 10 9 8 7 6 5 4 3 2 1
AF VCC VSS VCC VSS VCC VSS VCC VSS VCC VCCVID VCCVIDLB VCC VSS AF
AE VSS VCC VSS VCC VSS VCC VSS VCC VID0 VID1 VID2 VID3 VID4 AE
AD VCC VSS VCC VSS VCC VSS VCC BSEL0 BSEL1 VSS VID5 VIDPWRGD BOOT
SELECT AD
AC VSS VCC VSS VCC VSS VCC VSS BPM0# VSS BPM2# IERR# VSS AP0# AC
AB VCC VSS VCC VSS VCC VSS VCC VSS BPM1# BPM5# VSS RSP# A35# AB
AA VSS VCC VSS VCC VSS VCC VSS GTLREF BPM4# VSS BINIT# TESTHI1 VSS AA
YBPM3# VSS STPCLK# TESTHI10 VSS A34# Y
WVSS INIT# TESTHI9 VSS A33# A29# W
VMCERR# AP1# VSS A32# A27# VSS V
UTESTHI8 VSS A31# A25# VSS A23# U
TVSS A30# A26# VSS A22# A17# T
RA28# ADSTB1# VSS A21# A18# VSS R
PA24# VSS A20# A19# VSS COMP1 P
NVSS A16# A15# VSS A14# A12# N
MA8# VSS A11# A10# VSS A13# M
LA5# ADSTB0# VSS A7# A9# VSS L
KVSS REQ1# A4# VSS A3# A6# K
JTRDY# VSS REQ2# REQ3# VSS REQ0# J
HBR0# DBSY# VSS REQ4# DRDY# VSS H
GVSS RS1# LOCK# VSS BNR# ADS# G
FVCC VSS VCC VSS VCC VSS TMS GTLREF VSS RS2# HIT# VSS RS0# F
EVSS VCC VSS VCC VSS VCC VSS TRST# LINT1 VSS HITM# DEFER# VSS E
DVCC VSS VCC VSS VCC VSS VCC VSS TDO TCK VSS BPRI# LINT0 D
CVSS VCC VSS VCC VSS VCC VSS A20M# VSS THERMDC PROCHOT# VSS TDI C
BVCC VSS VCC VSS VCC VSS VCC FERR#/
PBE# SMI# VSS THERMDA IGNNE# B
AVSS VCC VSS VCC VSS VCC Reserved TESTHI11 VCC_SENSE VSS_SENSE VSS THERMTRIP# A
13 12 11 10 9 8 7 6 5 4 3 2 1
Pin List and Signal Description
42 Datasheet
Table 23. Alphabetical Pin Assignment
Pin Name Pin # Signal Buffer
Type Direction
A3# K2 Source Synch Input/Output
A4# K4 Source Synch Input/Output
A5# L6 Source Synch Input/Output
A6# K1 Source Synch Input/Output
A7# L3 Source Synch Input/Output
A8# M6 Source Synch Input/Output
A9# L2 Source Synch Input/Output
A10# M3 Source Synch Inpu t/Output
A11# M4 Source Synch Input/Output
A12# N1 Source Synch Input/Output
A13# M1 Source Synch Inpu t/Output
A14# N2 Source Synch Input/Output
A15# N4 Source Synch Input/Output
A16# N5 Source Synch Input/Output
A17# T1 Source Synch Input/Output
A18# R2 Source Synch Input/Output
A19# P3 Source Synch Input/Output
A20# P4 Source Synch Input/Output
A21# R3 Source Synch Input/Output
A22# T2 Source Synch Input/Output
A23# U1 Source Synch Input/Output
A24# P6 Source Synch Input/Output
A25# U3 Source Synch Input/Output
A26# T4 Source Synch Input/Output
A27# V2 Source Synch Input/Output
A28# R6 Source Synch Input/Output
A29# W1 Source Synch Input/Output
A30# T5 Source Synch Input/Output
A31# U4 Source Synch Input/Output
A32# V3 Source Synch Input/Output
A33# W2 Source Synch Input/Output
A34# Y1 Source Synch Input/Output
A35# AB1 Source Synch Input/Output
A20M# C6 Asynch GTL+ Input
ADS# G1 Common Clock Input/Output
ADSTB0# L5 Source Synch Input/Output
ADSTB1# R5 Source Synch Input/ Output
AP0# AC1 Common Clock Input/Output
AP1# V5 Common Clock Input/Output
BCLK0 AF22 Bus Clock Input
BCLK1 AF23 Bus Clock Input
BINIT# AA3 Common Clock Input/Output
BNR# G2 Common Clock Input/Output
BOOTSELECT AD1 Power/Other Input
BPM0# AC6 Common Clock Input/Output
BPM1# AB5 Common Clock Input/Output
BPM2# AC4 Common Clock Input/Output
BPM3# Y6 Common Clock Input/Output
BPM4# AA5 Common Clock Input/Output
BPM5# AB4 Common Clock Input/Output
BPRI# D2 Common Clock Input
BR0# H6 Common Clock Input/Output
BSEL0 AD6 Power/Other Output
BSEL1 AD5 Power/Other Output
COMP0 L24 Power/Other Input
COMP1 P1 Power/Other Input
D0# B21 Source Synch Input/Output
D1# B22 Source Synch Input/Output
D2# A23 Source Synch Input/Output
D3# A25 Source Synch Input/Output
D4# C21 Source Synch Input/Output
D5# D22 Source Synch Input/Output
D6# B24 Source Synch Input/Output
D7# C23 Source Synch Input/Output
D8# C24 Source Synch Input/Output
D9# B25 Source Synch Input/Output
D10# G22 Source Synch Input/O utput
D11# H21 Source Synch Input/Output
D12# C26 Source Synch Input/Output
D13# D23 Source Synch Input/Output
D14# J21 Source Synch Input/Output
D15# D25 Source Synch Input/Output
D16# H22 Source Synch Input/Output
D17# E24 Source Synch Input/Output
D18# G23 Source Synch Input/O utput
D19# F23 Source Synch Input/Output
D20# F24 Source Synch Input/Output
D21# E25 Source Synch Input/Output
D22# F26 Source Synch Input/Output
D23# D26 Source Synch Input/Output
D24# L21 Source Synch Input/Output
D25# G26 Source Synch Input/O utput
Table 23. Alphabetical Pin Assignment
Pin Name Pin # Signal Buffer
Type Direction
Pin List and Signal Description
Datasheet 43
D26# H24 Source Synch Input/Output
D27# M21 Source Synch Input/Output
D28# L22 Source Synch Input/Output
D29# J24 Source Synch Input/Output
D30# K23 Source Synch Input/Output
D31# H25 Source Synch Input/Output
D32# M23 Source Synch Input/Output
D33# N22 Source Synch Input/Output
D34# P21 Source Synch Input/Output
D35# M24 Source Synch Input/Output
D36# N23 Source Synch Input/Output
D37# M26 Source Synch Input/Output
D38# N26 Source Synch Input/Output
D39# N25 Source Synch Input/Output
D40# R21 Source Synch Input/Output
D41# P24 Source Synch Input/Output
D42# R25 Source Synch Input/Output
D43# R24 Source Synch Input/Output
D44# T26 Source Synch Input/Output
D45# T25 Source Synch Input/Output
D46# T22 Source Synch Input/Output
D47# T23 Source Synch Input/Output
D48# U26 Source Synch Input/Output
D49# U24 Source Synch Input/Output
D50# U23 Source Synch Input/Output
D51# V25 Source Synch Input/Output
D52# U21 Source Synch Input/Output
D53# V22 Source Synch Input/Output
D54# V24 Source Synch Input/Output
D55# W26 Source Synch Input/Output
D56# Y26 Source Synch Input/Output
D57# W25 Source Synch Input/Output
D58# Y23 Source Synch Input/Output
D59# Y24 Source Synch Input/Output
D60# Y21 Source Synch Input/Output
D61# AA25 Source Synch Input/Output
D62# AA22 Source Synch Input/Output
D63# AA24 Source Synch Input/Output
DBI0# E21 Source Synch Input/Outpu t
DBI1# G25 Source Synch Input/Output
DBI2# P26 Source Synch Input/Outpu t
Table 23. Alphabetical Pin Assignment
Pin Name Pin # Signal Buffer
Type Direction
DBI3# V21 Source Synch Input/Output
DBR# AE25 Power/Other Output
DBSY# H5 Common Clock Input/Output
DEFER# E2 Common Clock Input
DP0# J26 Common Clock Input/Output
DP1# K25 Common Clock Input/Output
DP2# K26 Common Clock Input/Output
DP3# L25 Common Clock Input/Output
DRDY# H2 Common Clock Input/Output
DSTBN0# E22 Source Synch Input/Output
DSTBN1# K22 Source Synch Input/Output
DSTBN2# R22 Source Synch Input/Output
DSTBN3# W22 Source Synch Input/Output
DSTBP0# F21 Source Synch Input/Output
DSTBP1# J23 Source Synch Input/Output
DSTBP2# P23 Source Synch Input/Output
DSTBP3# W23 Source Synch Input/Output
FERR#/PBE# B6 Asynch AGL+ Output
GTLREF AA21 Power/Other Input
GTLREF AA6 Power/Other Input
GTLREF F20 Power/Other Input
GTLREF F6 Power/Other Input
HIT# F3 Common Clock Input/Output
HITM# E3 Common Clock Input/Output
IERR# AC3 Asynch GTL+ Output
IGNNE# B2 Asynch GTL+ Input
INIT# W5 Asynch GTL+ Input
ITP_CLK0 AC26 TAP Input
ITP_CLK1 AD26 TAP Input
LINT0 D1 Asynch GTL+ Input
LINT1 E5 Asynch GTL+ Input
LOCK# G4 Common Clock Input/Output
MCERR# V6 Common Clock Input/Output
OPTIMIZED/
COMPAT# AE26 Power/Other Input
PROCHOT# C3 Asynch GTL+ Input/Output
PWRGOOD AB23 Power/Other Input
REQ0# J1 Source Synch Input/Output
REQ1# K5 Source Synch Input/Output
REQ2# J4 Source Synch Input/Output
REQ3# J3 Source Synch Input/Output
REQ4# H3 Source Synch Input/Output
Table 23. Alphabetical Pin Assignment
Pin Name Pin # Signal Buffer
Type Direction
Pin List and Signal Description
44 Datasheet
RESERVED A22
RESERVED A7
RESERVED AE21
RESERVED AF24
RESERVED AF25
RESET# AB25 Common Clock Input
RS0# F1 Common Clock Input
RS1# G5 Common Clock Input
RS2# F4 Common Clock Input
RSP# AB2 Common Clock Input
SKTOCC# AF26 Power/Other Output
SLP# AB26 Asynch GTL+ Input
SMI# B5 Asynch GTL+ Input
STPCLK# Y4 Asynch GTL+ Input
TCK D4 TAP Input
TDI C1 TAP Input
TDO D5 TAP Output
TESTHI0 AD24 Power/Other Input
TESTHI1 AA2 Power/Other Input
TESTHI2 AC21 Power/Other Input
TESTHI3 AC20 Power/Other Input
TESTHI4 AC24 Power/Other Input
TESTHI5 AC23 Power/Other Input
TESTHI6 AA20 Power/Other Input
TESTHI7 AB22 Power/Other Input
TESTHI8 U6 Power/Other Input
TESTHI9 W4 Power/Other Input
TESTHI10 Y3 Power/Other Input
TESTHI11 A6 Power/Other Input
TESTHI12 AD25 Power/Other Input
THERMDA B3 Power/Other
THERMDC C4 Power/Other
THERMTRIP# A2 Asynch GTL+ Output
TMS F7 TAP Input
TRDY# J6 Common Clock Input
TRST# E6 TAP Input
VCC A10 Power/Other
VCC A12 Power/Other
VCC A14 Power/Other
VCC A16 Power/Other
VCC A18 Power/Other
Table 23. Alphabetical Pin Assignment
Pin Name Pin # Signal Buffer
Type Direction
VCC A20 Power/Other
VCC A8 Power/Other
VCC AA10 Power/Other
VCC AA12 Power/Other
VCC AA14 Power/Other
VCC AA16 Power/Other
VCC AA18 Power/Other
VCC AA8 Power/Other
VCC AB11 Power/Other
VCC AB13 Power/Other
VCC AB15 Power/Other
VCC AB17 Power/Other
VCC AB19 Power/Other
VCC AB7 Power/Other
VCC AB9 Power/Other
VCC AC10 Power/Other
VCC AC12 Power/Other
VCC AC14 Power/Other
VCC AC16 Power/Other
VCC AC18 Power/Other
VCC AC8 Power/Other
VCC AD11 Power/Other
VCC AD13 Power/Other
VCC AD15 Power/Other
VCC AD17 Power/Other
VCC AD19 Power/Other
VCC AD7 Power/Other
VCC AD9 Power/Other
VCC AE10 Power/Other
VCC AE12 Power/Other
VCC AE14 Power/Other
VCC AE16 Power/Other
VCC AE18 Power/Other
VCC AE20 Power/Other
VCC AE6 Power/Other
VCC AE8 Power/Other
VCC AF11 Power/Other
VCC AF13 Power/Other
VCC AF15 Power/Other
VCC AF17 Power/Other
VCC AF19 Power/Other
Table 23. Alphabetical Pin Assignment
Pin Name Pin # Signal Buffer
Type Direction
Pin List and Signal Description
Datasheet 45
VCC AF2 Power/Other
VCC AF21 Power/Other
VCC AF5 Power/Other
VCC AF7 Power/Other
VCC AF9 Power/Other
VCC B11 Power/Other
VCC B13 Power/Other
VCC B15 Power/Other
VCC B17 Power/Other
VCC B19 Power/Other
VCC B7 Power/Other
VCC B9 Power/Other
VCC C10 Power/Other
VCC C12 Power/Other
VCC C14 Power/Other
VCC C16 Power/Other
VCC C18 Power/Other
VCC C20 Power/Other
VCC C8 Power/Other
VCC D11 Power/Other
VCC D13 Power/Other
VCC D15 Power/Other
VCC D17 Power/Other
VCC D19 Power/Other
VCC D7 Power/Other
VCC D9 Power/Other
VCC E10 Power/Other
VCC E12 Power/Other
VCC E14 Power/Other
VCC E16 Power/Other
VCC E18 Power/Other
VCC E20 Power/Other
VCC E8 Power/Other
VCC F11 Power/Other
VCC F13 Power/Other
VCC F15 Power/Other
VCC F17 Power/Other
VCC F19 Power/Other
VCC F9 Power/Other
VCCA AE23 Power/Other
VCCIOPLL AD20 Power/Other
Table 23. Alphabetical Pin Assignment
Pin Name Pin # Signal Buffer
Type Direction
VCC_SENSE A5 Power/Other Output
VCCVID AF4 Power/Other Input
VCCVIDLB AF3 Power/Other Input
VID0 AE5 Power/Other Output
VID1 AE4 Power/Other Output
VID2 AE3 Power/Other Output
VID3 AE2 Power/Other Output
VID4 AE1 Power/Other Output
VID5 AD3 Power/Other Output
VIDPWRGD AD2 Power/Other Input
VSS A11 Power/Other
VSS A13 Power/Other
VSS A15 Power/Other
VSS A17 Power/Other
VSS A19 Power/Other
VSS A21 Power/Other
VSS A24 Power/Other
VSS A26 Power/Other
VSS A3 Power/Other
VSS A9 Power/Other
VSS AA1 Power/Other
VSS AA11 Power/Other
VSS AA13 Power/Other
VSS AA15 Power/Other
VSS AA17 Power/Other
VSS AA19 Power/Other
VSS AA23 Power/Other
VSS AA26 Power/Other
VSS AA4 Power/Other
VSS AA7 Power/Other
VSS AA9 Power/Other
VSS AB10 Power/Other
VSS AB12 Power/Other
VSS AB14 Power/Other
VSS AB16 Power/Other
VSS AB18 Power/Other
VSS AB20 Power/Other
VSS AB21 Power/Other
VSS AB24 Power/Other
VSS AB3 Power/Other
VSS AB6 Power/Other
Table 23. Alphabetical Pin Assignment
Pin Name Pin # Signal Buffer
Type Direction
Pin List and Signal Description
46 Datasheet
VSS AB8 Power/Other
VSS AC11 Power/Other
VSS AC13 Power/Other
VSS AC15 Power/Other
VSS AC17 Power/Other
VSS AC19 Power/Other
VSS AC2 Power/Other
VSS AC22 Power/Other
VSS AC25 Power/Other
VSS AC5 Power/Other
VSS AC7 Power/Other
VSS AC9 Power/Other
VSS AD10 Power/Other
VSS AD12 Power/Other
VSS AD14 Power/Other
VSS AD16 Power/Other
VSS AD18 Power/Other
VSS AD21 Power/Other
VSS AD23 Power/Other
VSS AD4 Power/Other
VSS AD8 Power/Other
VSS AE11 Power/Other
VSS AE13 Power/Other
VSS AE15 Power/Other
VSS AE17 Power/Other
VSS AE19 Power/Other
VSS AE22 Power/Other
VSS AE24 Power/Other
VSS AE7 Power/Other
VSS AE9 Power/Other
VSS AF1 Power/Other
VSS AF10 Power/Other
VSS AF12 Power/Other
VSS AF14 Power/Other
VSS AF16 Power/Other
VSS AF18 Power/Other
VSS AF20 Power/Other
VSS AF6 Power/Other
VSS AF8 Power/Other
VSS B10 Power/Other
VSS B12 Power/Other
Table 23. Alphabetical Pin Assignment
Pin Name Pin # Signal Buffer
Type Direction
VSS B14 Power/Other
VSS B16 Power/Other
VSS B18 Power/Other
VSS B20 Power/Other
VSS B23 Power/Other
VSS B26 Power/Other
VSS B4 Power/Other
VSS B8 Power/Other
VSS C11 Power/Other
VSS C13 Power/Other
VSS C15 Power/Other
VSS C17 Power/Other
VSS C19 Power/Other
VSS C2 Power/Other
VSS C22 Power/Other
VSS C25 Power/Other
VSS C5 Power/Other
VSS C7 Power/Other
VSS C9 Power/Other
VSS D10 Power/Other
VSS D12 Power/Other
VSS D14 Power/Other
VSS D16 Power/Other
VSS D18 Power/Other
VSS D20 Power/Other
VSS D21 Power/Other
VSS D24 Power/Other
VSS D3 Power/Other
VSS D6 Power/Other
VSS D8 Power/Other
VSS E1 Power/Other
VSS E11 Power/Other
VSS E13 Power/Other
VSS E15 Power/Other
VSS E17 Power/Other
VSS E19 Power/Other
VSS E23 Power/Other
VSS E26 Power/Other
VSS E4 Power/Other
VSS E7 Power/Other
VSS E9 Power/Other
Table 23. Alphabetical Pin Assignment
Pin Name Pin # Signal Buffer
Type Direction
Pin List and Signal Description
Datasheet 47
VSS F10 Power/Other
VSS F12 Power/Other
VSS F14 Power/Other
VSS F16 Power/Other
VSS F18 Power/Other
VSS F2 Power/Other
VSS F22 Power/Other
VSS F25 Power/Other
VSS F5 Power/Other
VSS F8 Power/Other
VSS G21 Power/Other
VSS G24 Power/Other
VSS G3 Power/Other
VSS G6 Power/Other
VSS H1 Power/Other
VSS H23 Power/Other
VSS H26 Power/Other
VSS H4 Power/Other
VSS J2 Power/Other
VSS J22 Power/Other
VSS J25 Power/Other
VSS J5 Power/Other
VSS K21 Power/Other
VSS K24 Power/Other
VSS K3 Power/Other
VSS K6 Power/Other
VSS L1 Power/Other
VSS L23 Power/Other
VSS L26 Power/Other
VSS L4 Power/Other
VSS M2 Power/Other
VSS M22 Power/Other
VSS M25 Power/Other
VSS M5 Power/Other
Table 23. Alphabetical Pin Assignment
Pin Name Pin # Signal Buffer
Type Direction
VSS N21 Power/Other
VSS N24 Power/Other
VSS N3 Power/Other
VSS N6 Power/Other
VSS P2 Power/Other
VSS P22 Power/Other
VSS P25 Power/Other
VSS P5 Power/Other
VSS R1 Power/Other
VSS R23 Power/Other
VSS R26 Power/Other
VSS R4 Power/Other
VSS T21 Power/Other
VSS T24 Power/Other
VSS T3 Power/Other
VSS T6 Power/Other
VSS U2 Power/Other
VSS U22 Power/Other
VSS U25 Power/Other
VSS U5 Power/Other
VSS V1 Power/Other
VSS V23 Power/Other
VSS V26 Power/Other
VSS V4 Power/Other
VSS W21 Power/Other
VSS W24 Power/Other
VSS W3 Power/Other
VSS W6 Power/Other
VSS Y2 Power/Other
VSS Y22 Power/Other
VSS Y25 Power/Other
VSS Y5 Power/Other
VSSA AD22 Power/Other
VSS_SENSE A4 Power/Other Output
Table 23. Alphabetical Pin Assignment
Pin Name Pin # Signal Buffer
Type Direction
Pin List and Signal Description
48 Datasheet
Table 24. Numerical Pin Assignment
Pin # Pin Name Signal Buffer
Type Direction
A2 THER MTRIP# Asynch GTL+ Output
A3 VSS Power/Other
A4 VSS_SENSE Power/Other Output
A5 VCC_SENSE Power/Other Output
A6 TESTHI11 Power/Other Input
A7 RESERVED
A8 VCC Power/Other
A9 VSS Power/Other
A10 VCC Power/Other
A11 VSS Power/Other
A12 VCC Power/Other
A13 VSS Power/Other
A14 VCC Power/Other
A15 VSS Power/Other
A16 VCC Power/Other
A17 VSS Power/Other
A18 VCC Power/Other
A19 VSS Power/Other
A20 VCC Power/Other
A21 VSS Power/Other
A22 RESERVED
A23 D2# Source Synch Input/Out p ut
A24 VSS Power/Other
A25 D3# Source Synch Input/Out p ut
A26 VSS Power/Other
B2 IGNNE# Asynch GTL+ Input
B3 THERMDA Power/Other
B4 VSS Power/Other
B5 SMI# A synch GTL+ Input
B6 FERR #/PBE# Asynch AGL+ Output
B7 VCC Power/Other
B8 VSS Power/Other
B9 VCC Power/Other
B10 VSS Power/Other
B11 VCC Power/Other
B12 VSS Power/Other
B13 VCC Power/Other
B14 VSS Power/Other
B15 VCC Power/Other
B16 VSS Power/Other
B17 VCC Power/Other
B18 VSS Power/Other
B19 VCC Power/Other
B20 VSS Power/Other
B21 D0# Source Synch Input/Output
B22 D1# Source Synch Input/Output
B23 VSS Power/Other
B24 D6# Source Synch Input/Output
B25 D9# Source Synch Input/Output
B26 VSS Power/Other
C1 TDI TAP Input
C2 VSS Power/Other
C3 PROCHOT# Asynch GTL+ Input/Output
C4 THERMDC Power/Other
C5 VSS Power/Other
C6 A20M# Asynch GTL+ Input
C7 VSS Power/Other
C8 VCC Power/Other
C9 VSS Power/Other
C10 VCC Power/Other
C11 VSS Power/Other
C12 VCC Power/Other
C13 VSS Power/Other
C14 VCC Power/Other
C15 VSS Power/Other
C16 VCC Power/Other
C17 VSS Power/Other
C18 VCC Power/Other
C19 VSS Power/Other
C20 VCC Power/Other
C21 D4# Source Synch Input/Output
C22 VSS Power/Other
C23 D7# Source Synch Input/Output
C24 D8# Source Synch Input/Output
C25 VSS Power/Other
C26 D12# Source Synch Input/Output
D1 LINT0 Asynch GTL+ Input
D2 BPRI# Common Clock Input
D3 VSS Power/Other
D4 TCK TAP Input
D5 TDO TAP Output
D6 VSS Power/Other
Table 24. Numerical Pin Assignment
Pin # Pin Name Signal Buffer
Type Direction
Pin List and Signal Description
Datasheet 49
D7 VCC Power/Other
D8 VSS Power/Other
D9 VCC Power/Other
D10 VSS Power/Other
D11 VCC Power/Other
D12 VSS Power/Other
D13 VCC Power/Other
D14 VSS Power/Other
D15 VCC Power/Other
D16 VSS Power/Other
D17 VCC Power/Other
D18 VSS Power/Other
D19 VCC Power/Other
D20 VSS Power/Other
D21 VSS Power/Other
D22 D5# Source Sync h Input/Out p ut
D23 D13# Source Synch Input/Output
D24 VSS Power/Other
D25 D15# Source Synch Input/Output
D26 D23# Source Synch Input/Output
E1 VSS Power/Other
E2 DEFER# Common Clock Input
E3 HITM# Common Clock Input/Output
E4 VSS Power/Other
E5 LINT1 Asynch GTL+ Input
E6 TRST# TAP Input
E7 VSS Power/Other
E8 VCC Power/Other
E9 VSS Power/Other
E10 VCC Power/Other
E11 VSS Power/Other
E12 VCC Power/Other
E13 VSS Power/Other
E14 VCC Power/Other
E15 VSS Power/Other
E16 VCC Power/Other
E17 VSS Power/Other
E18 VCC Power/Other
E19 VSS Power/Other
E20 VCC Power/Other
E21 DBI0# Source Sync h Input/Out p ut
Table 24. Numerical Pin Assignment
Pin # Pin Name Signal Buffer
Type Direction
E22 DSTBN0# Source Synch Input/Output
E23 VSS Power/Other
E24 D17# Source Synch Input/Output
E25 D21# Source Synch Input/Output
E26 VSS Power/Other
F1 RS0# Common Clock Input
F2 VSS Power/Other
F3 HIT# Common Clock Input/Output
F4 RS2# Common Clock Input
F5 VSS Power/Other
F6 GTLREF Power/Other Input
F7 TMS TAP Input
F8 VSS Power/Other
F9 VCC Power/Other
F10 VSS Power/Other
F11 VCC Power/Other
F12 VSS Power/Other
F13 VCC Power/Other
F14 VSS Power/Other
F15 VCC Power/Other
F16 VSS Power/Other
F17 VCC Power/Other
F18 VSS Power/Other
F19 VCC Power/Other
F20 GTLREF Power/Other Input
F21 DSTBP0# Source Synch Input/Output
F22 VSS Power/Other
F23 D19# Source Synch Input/Output
F24 D20# Source Synch Input/Output
F25 VSS Power/Other
F26 D22# Source Synch Input/Output
G1 ADS# Common Clock Input/Output
G2 BNR# Common Clock Input/Output
G3 VSS Power/Other
G4 LOCK# Common Clock Input/Output
G5 RS1# Common Clock Input
G6 VSS Power/Other
G21 VSS Power/Other
G22 D10# Source Synch Input/Output
G23 D18# Source Synch Input/Output
G24 VSS Power/Other
Table 24. Numerical Pin Assignment
Pin # Pin Name Signal Buffer
Type Direction
Pin List and Signal Description
50 Datasheet
G25 DBI1# Source Sync h In p ut/Output
G26 D25# Source Synch Input/Output
H1 VSS Power/Other
H2 DRDY# Common Clock Input/Output
H3 REQ4# Source Synch Input/Output
H4 VSS Power/Other
H5 DBSY# Common Clock Input/Output
H6 BR0# Common Clock Input/Outpu t
H21 D11# Source Synch Input/Output
H22 D16# Source Synch Input/Output
H23 VSS Power/Other
H24 D26# Source Synch Input/Output
H25 D31# Source Synch Input/Output
H26 VSS Power/Other
J1 REQ0# Source Synch Input/Output
J2 VSS Power/Other
J3 REQ3# Source Synch Input/Output
J4 REQ2# Source Synch Input/Output
J5 VSS Power/Other
J6 TRDY# Common Clock Input
J21 D14# Source Synch Input/Output
J22 VSS Power/Other
J23 DSTBP1# Source Synch Input/Output
J24 D29# Source Synch Input/Output
J25 VSS Power/Other
J26 DP0# Common Clock Input/Output
K1 A6# Source Synch Input/Output
K2 A3# Source Synch Input/Output
K3 VSS Power/Other
K4 A4# Source Synch Input/Output
K5 REQ1# Source Synch Input/Output
K6 VSS Power/Other
K21 VSS Power/Other
K22 DSTBN1# Source Synch Input/Output
K23 D30# Source Synch Input/Output
K24 VSS Power/Other
K25 DP1# Common Clock Input/Output
K26 DP2# Common Clock Input/Output
L1 VSS Power/Other
L2 A9# Source Synch Input/Output
L3 A7# Source Synch Input/Output
Table 24. Numerical Pin Assignment
Pin # Pin Name Signal Buffer
Type Direction
L4 VSS Power/Other
L5 ADSTB0# Source Synch Input/Output
L6 A5# Source Synch Input/Output
L21 D24# Source Synch Input/Output
L22 D28# Source Synch Input/Output
L23 VSS Power/Other
L24 COMP0 Power/Other Input
L25 DP3# Co m m o n C lo ck I n pu t/Output
L26 VSS Power/Other
M1 A13# Source Synch Input/Outp ut
M2 VSS Power/Other
M3 A10# Source Synch Input/Outp ut
M4 A11# Source Synch Input/Output
M5 VSS Power/Other
M6 A8# Source Synch Input/Output
M21 D27# Source Synch Input/Output
M22 VSS Power/Other
M23 D32# Source Synch Input/Output
M24 D35# Source Synch Input/Output
M25 VSS Power/Other
M26 D37# Source Synch Input/Output
N1 A12# Source Synch Input/Output
N2 A14# Source Synch Input/Output
N3 VSS Power/Other
N4 A15# Source Synch Input/Output
N5 A16# Source Synch Input/Output
N6 VSS Power/Other
N21 VSS Power/Other
N22 D33# Source Synch Input/Output
N23 D36# Source Synch Input/Output
N24 VSS Power/Other
N25 D39# Source Synch Input/Output
N26 D38# Source Synch Input/Output
P1 COMP1 Power/Other Input
P2 VSS Power/Other
P3 A19# Source Synch Input/Output
P4 A20# Source Synch Input/Output
P5 VSS Power/Other
P6 A24# Source Synch Input/Output
P21 D34# Source Synch Input/Output
P22 VSS Power/Other
Table 24. Numerical Pin Assignment
Pin # Pin Name Signal Buffer
Type Direction
Pin List and Signal Description
Datasheet 51
P23 DSTBP#2 Source Synch Input/Output
P24 D41# Source Synch Input/Output
P25 VSS Power/Other
P26 DBI2# Source Sync h Input/Out p ut
R1 VSS Power/Other
R2 A18# Source Synch Input/Output
R3 A21# Source Synch Input/Output
R4 VSS Power/Other
R5 ADSTB1# Source Synch Input/Output
R6 A28# Source Synch Input/Output
R21 D40# Source Synch Input/Output
R22 DSTBN#2 Source Synch Input/O ut put
R23 VSS Power/Other
R24 D43# Source Synch Input/Output
R25 D42# Source Synch Input/Output
R26 VSS Power/Other
T1 A17# Source Synch Input/Output
T2 A22# Source Synch Input/Output
T3 VSS Power/Other
T4 A26# Source Synch Input/Output
T5 A30# Source Synch Input/Output
T6 VSS Power/Other
T21 VSS Power/Other
T22 D46# Source Synch Input/Output
T23 D47# Source Synch Input/Output
T24 VSS Power/Other
T25 D45# Source Synch Input/Output
T26 D44# Source Synch Input/Output
U1 A23# Source Synch Input/Output
U2 VSS Power/Other
U3 A25# Source Synch Input/Output
U4 A31# Source Synch Input/Output
U5 VSS Power/Other
U6 TESTHI8 Power/Other Input
U21 D52# Source Synch Input/Output
U22 VSS Power/Other
U23 D50# Source Synch Input/Output
U24 D49# Source Synch Input/Output
U25 VSS Power/Other
U26 D48# Source Synch Input/Output
V1 VSS Power/Other
Table 24. Numerical Pin Assignment
Pin # Pin Name Signal Buffer
Type Direction
V2 A27# Source Synch Input/Output
V3 A32# Source Synch Input/Output
V4 VSS Power/Other
V5 AP1# Common Clock Input/Output
V6 MCERR# Common Clock Input/Output
V21 DBI3# Source Synch Input/Output
V22 D53# Source Synch Input/Output
V23 VSS Power/Other
V24 D54# Source Synch Input/Output
V25 D51# Source Synch Input/Output
V26 VSS Power/Other
W1 A29# Source Synch Input/Output
W2 A33# Source Synch Input/Output
W3 VSS Power/Other
W4 TESTHI9 Power/Other Input
W5 INIT# Asynch GTL+ Input
W6 VSS Power/Other
W21 VSS Power/Other
W22 DSTBN3# Source Synch Input/Out put
W23 DSTBP3# Source Synch Input/Output
W24 VSS Power/Other
W25 D57# Source Synch Input/Output
W26 D55# Source Synch Input/Output
Y1 A34# Source Synch Input/Output
Y2 VSS Power/Other
Y3 TESTHI10 Power/Other Input
Y4 STPCLK# Asynch GTL+ Input
Y5 VSS Power/Other
Y6 BPM3# Common Clock Input/Output
Y21 D60# Source Synch Input/Output
Y22 VSS Power/Other
Y23 D58# Source Synch Input/Output
Y24 D59# Source Synch Input/Output
Y25 VSS Power/Other
Y26 D56# Source Synch Input/Output
AA1 VSS Power/Other
AA2 TESTHI1 Power/Other Input
AA3 BINIT# Common Clock Input/Output
AA4 VSS Power/Other
AA5 BPM4# Common Clock Input/Output
AA6 GTLREF Power/Other Input
Table 24. Numerical Pin Assignment
Pin # Pin Name Signal Buffer
Type Direction
Pin List and Signal Description
52 Datasheet
AA7 VSS Power/Other
AA8 VCC Power/Other
AA9 VSS Power/Other
AA10 VCC Power/Other
AA11 VSS Power/Other
AA12 VCC Power/Other
AA13 VSS Power/Other
AA14 VCC Power/Other
AA15 VSS Power/Other
AA16 VCC Power/Other
AA17 VSS Power/Other
AA18 VCC Power/Other
AA19 VSS Power/Other
AA20 TESTHI6 Power/Other Input
AA21 GTLREF Power/Other Input
AA22 D62# Source Synch Input/Output
AA23 VSS Power/Other
AA24 D63# Source Synch Input/Output
AA25 D61# Source Synch Input/Output
AA26 VSS Power/Other
AB1 A35# Source Synch Input/Output
AB2 RSP# Common Clock Input
AB3 VSS Power/Other
AB4 BPM5# Common Clock Input/Output
AB5 BPM1# Common Clock Input/Output
AB6 VSS Power/Other
AB7 VCC Power/Other
AB8 VSS Power/Other
AB9 VCC Power/Other
AB10 VSS Power/Other
AB11 VCC Power/Other
AB12 VSS Power/Other
AB13 VCC Power/Other
AB14 VSS Power/Other
AB15 VCC Power/Other
AB16 VSS Power/Other
AB17 VCC Power/Other
AB18 VSS Power/Other
AB19 VCC Power/Other
AB20 VSS Power/Other
AB21 VSS Power/Other
Table 24. Numerical Pin Assignment
Pin # Pin Name Signal Buffer
Type Direction
AB22 TESTHI7 Power/Other Input
AB23 PWRGOOD Power/Other Input
AB24 VSS Power/Other
AB25 RESET# Common Clock Input
AB26 SLP# Asynch GTL+ Input
AC1 AP0# Common Clock In pu t/ Ou tput
AC2 VSS Power/Other
AC3 IERR# Asynch GTL+ Output
AC4 BPM2# Common Clock Input/Output
AC5 VSS Power/Other
AC6 BPM0# Common Clock Input/Output
AC7 VSS Power/Other
AC8 VCC Power/Other
AC9 VSS Power/Other
AC10 VCC Power/Other
AC11 VSS Power/Other
AC12 VCC Power/Other
AC13 VSS Power/Other
AC14 VCC Power/Other
AC15 VSS Power/Other
AC16 VCC Power/Other
AC17 VSS Power/Other
AC18 VCC Power/Other
AC19 VSS Power/Other
AC20 TESTHI3 Power/Other Input
AC21 TESTHI2 Power/Other Input
AC22 VSS Power/Other
AC23 TESTHI5 Power/Other Input
AC24 TESTHI4 Power/Other Input
AC25 VSS Power/Other
AC26 ITP_CLK0 TAP Input
AD1 BOOTSELECT Power/Other Input
AD2 VIDPWRGD Power/Other Input
AD3 VID5 Power/Other Output
AD4 VSS Power/Other
AD5 BSEL1 Power/Other Output
AD6 BSEL0 Power/Other Output
AD7 VCC Power/Other
AD8 VSS Power/Other
AD9 VCC Power/Other
AD10 VSS Power/Other
Table 24. Numerical Pin Assignment
Pin # Pin Name Signal Buffer
Type Direction
Pin List and Signal Description
Datasheet 53
AD11 VCC Power/Other
AD12 VSS Power/Other
AD13 VCC Power/Other
AD14 VSS Power/Other
AD15 VCC Power/Other
AD16 VSS Power/Other
AD17 VCC Power/Other
AD18 VSS Power/Other
AD19 VCC Power/Other
AD20 VCCIOPLL Power/Other
AD21 VSS Power/Other
AD22 VSSA Power/Other
AD23 VSS Power/Other
AD24 TESTHI0 Power/Other Input
AD25 TESTHI12 Power/Other Input
AD26 ITP_CLK1 TAP Input
AE1 VID4 Power/Other Output
AE2 VID3 Power/Other Output
AE3 VID2 Power/Other Output
AE4 VID1 Power/Other Output
AE5 VID0 Power/Other Output
AE6 VCC Power/Other
AE7 VSS Power/Other
AE8 VCC Power/Other
AE9 VSS Power/Other
AE10 VCC Power/Other
AE11 VSS Power/Other
AE12 VCC Power/Other
AE13 VSS Power/Other
AE14 VCC Power/Other
AE15 VSS Power/Other
AE16 VCC Power/Other
AE17 VSS Power/Other
AE18 VCC Power/Other
Table 24. Numerical Pin Assignment
Pin # Pin Name Signal Buffer
Type Direction
AE19 VSS Power/Other
AE20 VCC Power/Other
AE21 RESERVED
AE22 VSS Power/Other
AE23 VCCA Power/Other
AE24 VSS Power/Other
AE25 DBR# Power/Other Output
AE26 OPTIMIZED/
COMPAT# Power/Other Input
AF1 VSS Power/Other
AF2 VCC Power/Other
AF3 VCCVIDLB Power/Other Input
AF4 VCCVID Power/Other Input
AF5 VCC Power/Other
AF6 VSS Power/Other
AF7 VCC Power/Other
AF8 VSS Power/Other
AF9 VCC Power/Other
AF10 VSS Power/Other
AF11 VCC Power/Other
AF12 VSS Power/Other
AF13 VCC Power/Other
AF14 VSS Power/Other
AF15 VCC Power/Other
AF16 VSS Power/Other
AF17 VCC Power/Other
AF18 VSS Power/Other
AF19 VCC Power/Other
AF20 VSS Power/Other
AF21 VCC Power/Other
AF22 BCLK0 Bus Clock Input
AF23 BCLK1 Bus Clock Input
AF24 RESERVED
AF25 RESERVED
AF26 SKTOCC# Power/Other Output
Table 24. Numerical Pin Assignment
Pin # Pin Name Signal Buffer
Type Direction
54 Datasheet
Pin List and Signal Description
4.2 Alphabetical Signals Reference
Table 25. Signal Description (Page 1 of 8)
Name Type Description
A[35:3]# Input/
Output
A[35:3]# (Address) define a 236-byte physical memory address space. In
subphase 1 of the address phase, these pins transmit the address of a
transaction. In subphase 2, these pin s tr ansmit transaction type information.
These signals must connect the appropriate pins of all agents on the processor
FSB. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source
synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor samples a subset
of the A[35:3]# pins to determine power-on configuration. See Section 6.1 for
more details.
A20M# Input
If A20M# (Address-20 Mask) is asserted, the processor masks physical address
bit 20 (A20#) before looking up a line in any internal cach e and before driving a
read/write transaction on the bus. Asserting A20M# emulates the 8086
processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is
only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an input/output write instruction, it must be valid along with the TRDY#
assertion of the corresponding input/output write bus transaction.
ADS# Input/
Output
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new
transaction.
ADSTB[1:0]# Input/
Output
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and
falling edges. Strobes are associated with signals as shown below.
AP[1:0]# Input/
Output
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,
A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is
high if an even number of covered signals are low and low if an odd number of
covered signals are low. This allows parity to be high when all the covered
signals are high. AP[1:0]# should connect t he appropriate pins of all processor
FSB agents. The following table defines the coverage model of these signals.
BCLK[1:0] Input
The differential pair BCLK (Bus Clock) determines the FSB frequency. All
processor FSB agents must receive these signals to drive their outputs and latch
their inputs.
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing VCROSS.
Signals Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB0#
A[35:17]# ADSTB1#
Request Signals Subphase 1 Subphase 2
A[35:24]# AP0# AP1#
A[23:3]# AP1# AP0#
REQ[4:0]# AP1# AP0#
Datasheet 55
Pin List and Signal Description
BINIT# Input/
Output
BINIT# (Bus Initialization) may be observed and driven by all processor FSB
agents and, if used, must connect the appropriate pins of all such agents. If the
BINIT# driver is enabled during power-on configuration, BINIT# is asserted to
signal any bus condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration, and BINIT# is
sampled asserted, symmetric agents reset their bus LOCK# activity and bus
request arbitration state machines. The bus agents do not reset their IOQ and
transaction tracking state machines upon observation of BINIT# activation. Once
the BINIT# assertion has been observed, the bus agents will re-arbitrate for the
FSB and attempt completion of their bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling
architecture of the system.
BNR# Input/
Output BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
BOOTSELECT Input This input is required to determine whether the processor is installed in a
platform that supports the processor. The processor will not operate if this pin is
low. This input has a weak internal pullup.
BPM[5:0]# Input/
Output
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor
signals. They are outputs from the processor that indicate the status of
breakpoints and programmable counters used for monitoring processor
performance. BPM[5:0]# should connect the appropriate pins of all processor
FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is
a processor output used by debug tools to determine processor debug
readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ#
is used by debug tools to request debug operation of the processor.
Refer to the Intel® 865G/865GV/865PE/865P Chipset Platform Design Guide for
more detailed information.
These signals do not have on-die termination. Refer to Section 2.4, and the
Intel® 865G/865GV/865PE/865P Chipset Platform Design Guide for termination
requirements.
BPRI# Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor
FSB. It must connect the appropriate pins of all processor FSB agents.
Observing BPRI# active (as asserted by the priority agent) causes all other
agents to stop issuing new requests, unless such requests are part of an
ongoing locked operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by de-asserting BPRI#.
BR0# Input/
Output
BR0# (Bus Request) drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration, this pin is sampled
to determine the agent ID = 0.
This signal does not have on-die termination and must be terminated.
BSEL[1:0] Output
The BCLK[1:0] frequency select signals BSEL[1:0] (Bus Select) are used to
select the processor input clock frequency. Table 7 defines the possible
combinations of the signals and the frequency associated with each
combination. The required frequency is determined by the processor, chipset,
and clock synthesizer. All agents must operate at the same frequency. For more
information about these pins, including termination re commendations, refer to
Section 2.8 and the appropriate platform design guidelines.
COMP[1:0] Analog COMP[1:0] must be terminated on the system board using precision resistors.
Refer to the Intel® 865G/865GV/865PE/865P Chipset Platform Design Guide for
details on implementation.
Table 25. Signal Description (Page 2 of 8)
Name Type Description
56 Datasheet
Pin List and Signal Description
D[63:0]# Input/
Output
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the processor FSB agents, and must connect the appropriate pins on
all such agents. The data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times in a
common clock period. D[63:0]# are latched from the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a
pair of one DSTBP# and one DSTBN#. The following table shows the grouping
of data signals to data strobes and DBI#.
Furthermore, the DBI# pins determine the polarity of the data signals. Each
group of 16 data signals corresponds to one DBI# signal. When the DBI# signal
is active, the corresponding data group is inverted and therefore sampled active
high.
DBI[3:0]# Input/
Output
DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity
of the D[63:0]# signals.The DBI[3:0]# signals are activated when the data on the
data bus is inverted. If more than half the data bits, within a 16-bit group, would
have been asserted electrically low, the bus agent may invert the data bus
signals for that particular sub-phase for that 16-bit group.
DBR# Output DBR# (Debug Reset) is used only in processor systems where no debug port is
implemented on the system board. DBR# is used by a debug port interposer so
that an in-target probe can drive system reset. If a debug port is implemented in
the system, DBR# is a no connect in the system. DBR# is not a processor signal.
DBSY# Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on
the processor FSB to indicate that the data bus is in use. The data bus is
released after DBSY# is de-asserted. This signal must connect the appropr iate
pins on all processor FSB agents.
DEFER# Input DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or input/output agent. This signal must
connect the appropriate pins of all processor FSB agents.
DP[3:0]# Input/
Output DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They
are driven by the agent responsible for driving D[63:0]#, and must connect the
appropriate pins of all processor FSB agents.
Table 25. Signal Description (Page 3 of 8)
Name Type Description
Quad-Pumped Signal Groups
Data Group DSTBN#/
DSTBP# DBI#
D[15:0]# 0 0
D[31:16]# 1 1
D[47:32]# 2 2
D[63:48]# 3 3
DBI[3:0] Assignment To Data Bus
Bus Signal Data Bus Signals
DBI3# D[63:48]#
DBI2# D[47:32]#
DBI1# D[31:16]#
DBI0# D[15:0]#
Datasheet 57
Pin List and Signal Description
DRDY# Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be de-asserted to insert idle clocks. This signal must connect the
appropriate pins of all processor FSB agents.
DSTBN[3:0]# Input/
Output
Data strobe used to latch in D[63:0]#.
DSTBP[3:0]# Input/
Output
Data strobe used to latch in D[63:0]#.
FERR#/PBE# Output
FERR#/PBE# (Floating Point Error/Pending Break Event) is a multiplexed signal
and its meaning is qualified by STPCLK#. When STPCLK# is not asserted,
FERR#/PBE# indicates a floating-point error and will be asserted when the
processor detects an unmasked floating-point error. When STPCLK# is not
asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387
coprocessor, and is included for compatibility with systems using MS-DOS*-type
floating-point error reporting.
When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the
processor has a pending break event waiting for service. The assertion of
FERR#/PBE# indicates that the processor should be returned to the Normal
state. For additional information on the pending break event functionality,
including the identification of support of the feature and enable/disable
information, refer to volume 3 of the Intel Architecture Software Developer's
Manual and the Intel Processor Identification and the CPUID Instruction
application note.
GTLREF Input GTLREF determines the signal reference level for GTL+ input pins. GTLREF is
used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1.
Refer to the Intel® 865G/865GV/865PE/865P Chipset Platform Design Guide for
more information.
HIT#
HITM#
Input/
Output
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Any FSB agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
HITM# together.
IERR# Output
IERR# (Internal Error) is asserted by a processor as the result of an internal
error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction
on the processor FSB. This transaction may optionally be converted to an
external error signal (e.g., NMI) by system core logic. The processor will keep
IERR# asserted until the assertion of RESET#.
This signal does not have on-die termination. Refer to Section 2.4 for
termination requirements.
Table 25. Signal Description (Page 4 of 8)
Name Type Description
Signals Associated Strobe
D[15:0]#, DBI0# DSTBN0#
D[31:16]#, DBI1# DSTBN1#
D[47:32]#, DBI2# DSTBN2#
D[63:48]#, DBI3# DSTBN3#
Signals Associated Strobe
D[15:0]#, DBI0# DSTBP0#
D[31:16]#, DBI1# DSTBP1#
D[47:32]#, DBI2# DSTBP2#
D[63:48]#, DBI3# DSTBP3#
58 Datasheet
Pin List and Signal Description
IGNNE# Input
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is de-asserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in Control Register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However , to ensure recognition of this signal
following an input/output write instruction, it must be valid along with the TRDY#
assertion of the corresponding input/output write bus transaction.
INIT# Input
INIT# (Initialization), when asserted, resets integer registers inside the processor
without affecting its internal caches or floating-point registers. The processor
then begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop r equests during INIT#
assertion. INIT# is an asynchronous signal and must connect the appropriate
pins of all processor FSB agents.
If INIT# is sampled active on the active-to-inactive transition of RESET#, then
the processor executes its Built-in Self-Test (BIST).
ITP_CLK[1:0] Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems
where no debug port is implemented on the system board. ITP_CLK[1:0] are
used as BCLK[1:0] references for a debug port implemented on an interposer. If
a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the
system. These are not processor signals.
LINT[1:0] Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC
Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR (a
maskable interrupt request signal) and LINT1 becomes NMI (a nonmaskable
interrupt). INTR and NMI are backward compatible with the signals of those
names on the Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the
APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is
the default configuration.
LOCK# Input/
Output
LOCK# indicates to the system that a transaction must occur atomically. This
signal must connect the appropriate pins of all processor FSB agents. For a
locked sequence of transactions, LOCK# is asserted from the beginning of the
first transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
FSB, it will wait until it observes LOCK# de-asserted. This enables symmetric
agents to retain ownership of the processor FSB throughout the bus locked
operation and ensures the atomicity of lock.
MCERR# Input/
Output
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor FSB agents.
MCERR# assertion conditions are configurable at a system level. Assertion
options are defined by the following options:
• Enabled or disabled.
• Asserted, if configured, for internal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus transaction after it
observes an error.
• Asserted by any bus agent when it observes an error in a bus transaction .
For more details regarding machine check architecture, refer to the IA-32
Software Developer’s Manual, Volume 3: System Programming Guide.
OPTIMIZED/
COMPAT# Input This signal should be left as a no connect on the baseboard to indicate that the
baseboard supports the Intel® Pentium® 4 processor on 90 nm process. This
input has a weak internal pull-up.
Table 25. Signal Description (Page 5 of 8)
Name Type Description
Datasheet 59
Pin List and Signal Description
PROCHOT# Input/
Output
As an output, PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system activates the TCC, if en abled. The TCC remains
active until the system de-asserts PROCHOT#.
PWRGOOD Input
PWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that the clocks and power supplies are stable and
within their specifications. The term ‘Clean’ implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]# Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins of all
processor FSB agents. They are asserted by the current bus owner to define the
currently active transaction type. These signals are source synchronous to
ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity
checking of these signals.
RESET# Input
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least 1 ms after VCC and BCLK
have reached their proper specifications. On observing active RESET#, all FSB
agents will de-assert their outputs within two clocks. RESET# must not be kept
asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are described
in the Section 6.1.
This signal does not have on-die termination and must be terminated on
the system board.
RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of all processor FSB agents.
RSP# Input
RSP# (Response Parity) is driven by the response agent (the agent responsible
for completion of the current transaction) during assertion of RS[2:0]#, the
signals for which RSP# provides parity protection. It must connect to the
appropriate pins of all processor FSB agents.
A correct parity signal is high if an even number of covered signals are low and
low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is
also high, since this indicates it is not being driven by any agent guaranteeing
correct parity.
SKTOCC# Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System
board designers may use this pin to determine if the processor is present.
SLP# Input
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing internal clock
signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor
will recognize only assertion of the RESET# signal, and de-assertion of SLP#. If
SLP# is de-asserted, the processor exits the Sleep state and returns to Stop-
Grant state, restarting its internal clock signals to the bus and processor core
units.
Table 25. Signal Description (Page 6 of 8)
Name Type Description
60 Datasheet
Pin List and Signal Description
SMI# Input
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, the processor saves the
current state and enters System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program execution
from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the processor will tristate
its outputs.
STPCLK# Input
STPCLK# (Stop Clock), when a sserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the FSB and APIC units. The processor continues to snoop bus
transactions and service interrupts while in Stop-Grant state. When STPCLK# is
de-asserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#
is an asynchronous input.
TCK Input TCK (Test Clock) provides the clock input for the processor Test Bus (also known
as the Test Access Port).
TDI Input TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO Output TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TESTHI[12:0] Input TESTHI[12:0] must be connected to a VCC power source through a resistor for
proper processor operation. See Section 2.4 for more details.
THERMDA Other Thermal Diode Anode. See Section 5.2.6.
THERMDC Other Thermal Diode Cathode. See Section 5.2.6.
THERMTRIP# Output
In the event of a catastrophic cooling failure, the processor will automatically
shut down when the silicon has reached a temperature approximately 20 °C
above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the
processor junction temperature has reached a level beyond which permanent
silicon damage may occur. Upon assertion of THERMTRIP#, the processor will
shut off its internal clocks (thus, halting program execution) in an attempt to
reduce the processor junction temperature. To protect the processor, its core
voltage (VCC) must be removed following the assertion of THERMTRIP#. Driving
of the THERMTRIP# signal is enabled within 10 µs of the assertion of
PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,
THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-
assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the
processor’s junction temperature remains at or above the trip level,
THERMTRIP# will again be asserted within 10 µs of the assertion of
PWRGOOD.
TMS Input TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all FSB agents.
TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
driven low during power on Reset.
VCC Input VCC are the power pins for the processor. The voltage supplied to these pins is
determined by the VID[5:0] pins.
VCCA Input VCCA provides isolated power for the internal processor core PLLs. Refer to the
Intel® 865G/865GV/865PE/865P Chipset Platform Design Guide for complete
implementation details.
Table 25. Signal Description (Page 7 of 8)
Name Type Description
Datasheet 61
Pin List and Signal Description
§
VCCIOPLL Input VCCIOPLL provides isolated power for internal processor FSB PLLs. Follow the
guidelines for VCCA, and refer to the Intel® 865G/865GV/865PE/865P Chipset
Platform Design Guide for complete implementation details.
VCC_SENSE Output VCC_SENSE is an isolated low impedance connection to processor core power
(VCC). It can be used to sense or measure voltage near the silicon with little
noise.
VCCVID Input 1.2 V is required to be supplied to the VCCVID pin if the platform is going to
support the processor. Refer to the Intel® 865G/865GV/865PE/865P Chipset
Platform Design Guide for more information.
VCCVIDLB Input 1.2 V is required to be supplied to the VCCVIDLB pin if the platform is going to
support the processor. Refer to the Intel® 865G/865GV/865PE/865P Chipset
Platform Design Guide for more information.
VID[5:0] Output
VID[5:0] (Voltage ID) pins are used to support automatic selection of power
supply voltages (VCC). These are open drain signals that are driven by the
processor and must be pulled up to 3.3 V with 1 kΩ 5% resistors. The voltage
supply for these pins must be valid before the voltage regulator (VR) can supply
VCC to the processor. Conversely, the VR output must be disabled until the
voltage supply for the VID pins becomes valid. The VID pins are needed to
support the processor voltage specification variations. See Table 3 for definitions
of these pins. The VR must supply the voltage that is requested by the pins, or
disable itself.
VIDPWRGD Input The processor requires this input to determine that the V CCVID and VCCVIDLB
voltages are stable and within specification.
VSS Input VSS are the ground pins for the processor and should be connected to the
system ground plane.
VSSA Input VSSA is the isolated ground for internal PLLs.
VSS_SENSE Output VSS_SENSE is an isolated low impedance connection to processor core VSS. It
can be used to sense or measure ground near the silicon with little noise.
Table 25. Signal Description (Page 8 of 8)
Name Type Description
62 Datasheet
Pin List and Signal Description
Datasheet 63
Thermal Specifications and Design Considerations
5Thermal Specifications and Design
Considerations
5.1 Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures withi n operat ing limits as set
forth in Section 5.1.1. Any attempt to operate the processo r outside these operating limits may
result in permanent damage to the processor and potentially other components within th e system .
As processor technology changes, thermal management becomes increasingly crucial when
building computer systems. Maintaining the proper thermal environment is key to reliable, long-
term system operation.
A complete thermal solution includes both comp onen t and system level thermal management
features. Component level thermal solutions can include active or passive heatsinks attached to the
processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of
system fans combined with ducting and venting.
For more information on designing a component lev el thermal solution, refer to the Intel®
Pentium® 4 Processor on 90 nm Process Thermal De sign Guidelines.
Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on
the boxed processor.
5.1.1 Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor -based systems, the
system/processor thermal sol ution should be designed such that the processor remains within the
minimum and maximum case temperature (TC) specifications when operating at or below the
Thermal Design Power (TDP) value listed per frequency in Table 26. Thermal solutions not
designed to provide this level of thermal capability may affect the long-term reliability of the
processor and system. For more details on thermal solution design, refer to th e Intel® Pentium® 4
Processor on 90 nm Process Thermal Design Guidelines.
The Pentium 4 processor on 90 nm process introduces a new methodology for managing processor
temperatures that is intended to support acoustic noise reduction through fan speed control.
Selection of the appropriate fan speed is based on the temperature reported by the processor’s
Thermal Diode. If the diode temperature is greater than or equal to Tcontrol, then the processor case
temperature must remain at or below the temperature as specified by the thermal profile. If the
diode temperature is less than Tcontrol, then the case temperature is permitted to exceed the thermal
profile, but the diode temperature must remain at or below Tcontrol. Systems that implement fan
speed control must be designed to take these conditions into account. Systems that do not alter the
fan speed only need to guarantee the case temperature meets the thermal profile specifications.
64 Datasheet
Thermal Specifications and Design Considerations
To determine a processor's case temperature specification based on the thermal profile, it is
necessary to accurately measure processor power dissipation. Intel has developed a methodology
for accurate power measurement that correlates to Intel test temperature and voltage conditions.
Refer to the Intel® Pentium® 4 Processor on 90 nm Process Thermal Design Guidelines for the
details of this methodology.
The case temperature is defined at the geometric top center of the processor IHS. Analysis
indicates that real applications are unlikely to cause the processor t o consum e maxi mum power
dissipation for sustained periods of time. Intel recommends that complete thermal solution designs
target the Thermal Design Power (TDP) indicated in Table 26 instead of the maximum processor
power consumption. The Thermal Monitor feature is intended to help protect the processor in the
unlikely event that an application exceeds the TDP recommendation for a sustained period of time.
For more details on the usage of this feature, refer to Section 5.2. In all cases, the Thermal
Monitor feature must be enabled for the processor to remain within specification.
Table 26. Processor Thermal Specifications
Core Frequency
(GHz) Thermal Design
Power (W) Minimum TC (°C) Maximum TC (°C) Notes
2.80A/E (PRB = 0) 89 5 See Table 27 and Figure 12 1, 2
3E (PRB = 0) 89 5 See Table 27 and Figure 12 1, 2
3.20E (PRB = 0) 89 5 See Table 27 and Figure 12 1, 2
3.40E (PRB = 0) 89 5 See Table 27 and Figure 12 1, 2
3.20E (PRB = 1) 103 5 See Table 27 and Figure 12 1, 2
NOTES:
1. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is
not the maximum power that the processor can dissipate.
2. This table shows the maximum TDP for a given frequency range. Individual processors may have a lower
TDP. Therefore, the maximum TC will vary depending on the TDP of the individual processor. Refer to
Figure 12 and Table 27 for the allowed combinations of power and TC.
3.40E (PRB = 1) 103 5 See Table 27 and Figure 12 1, 2
Datasheet 65
Thermal Specifications and Design Considerations
Table 27. Thermal Profile
Power (W) Maximum Tc (°C) Power Maximum Tc (°C)
0 43.3 54 59.0
2 43.9 56 59.5
4 44.5 58 60.1
6 45.0 60 60.7
8 45.6 62 61.3
10 46.2 64 61.9
12 46.8 66 62.4
14 47.4 68 63.0
16 47.9 70 63.6
18 48.5 72 64.2
20 49.1 74 64.8
22 49.7 76 65.3
24 50.3 78 65.9
26 50.8 80 66.5
28 51.4 82 67.1
30 52.0 84 67.7
32 52.6 86 68.2
34 53.2 88 68.8
36 53.7 90 69.4
38 54.3 92 70.0
40 54.9 94 70.6
42 55.5 96 71.1
44 56.1 98 71.7
46 56.6 100 72.3
48 57.2 102 72.9
50 57.8 104 73.5
52 58.4
66 Datasheet
Thermal Specifications and Design Considerations
5.1.2 Thermal Metrology
The maximum and minimum case temperatures (TC) are specified in Table 27. These temperature
specifications are meant to help ensure proper operation of the processor. Figure 13 illustrates
where Intel recommends TC thermal measurements should be made. For deta iled guidelines on
temperature measurement methodology, refer to the Intel® Pentium® 4 Processor on 90 nm
Process Thermal Design Guidelines.
Figure 12. Thermal Profile
y = 0.29x + 43.3
35.0
40.0
45.0
50.0
55.0
60.0
65.0
70.0
75.0
80.0
0 102030405060708090100
Power (W)
Tcase (C)
Figure 13. Case Temperature (TC) Measurement Location
31 mm x 31 mm IHS [1.22 x 1.22 in]
35 mm x 35 mm substrate [1.378 in x 1.378 in]
M easure TC at t his po int
(geometric center of IHS)
Measure from edge of processor IHS
15.5 mm
[0.61 in]
15.5 mm
[0.61 in]
Datasheet 67
Thermal Specifications and Design Considerations
5.2 Processor Thermal Features
5.2.1 Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the TCC when
the processor silicon reaches its maximum operating temperature. The TCC reduces processor
power consumption as needed by modulating (starting and stopping) the internal processor core
clocks. The Thermal Monitor feature must be enabled for the processor to be operating
within specifications. The temperature at which Thermal Monitor activates the thermal control
circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal
manner, and interrupt requests are latched (and serv iced during the time that the clocks are on)
while the TCC is active.
When the Thermal Monitor feature is enabled and a high temperature situation exists (i.e., TCC is
active), the clocks are modulated by alternately turnin g the clocks off and on at a duty cycle
specific to the processor (typically 30–50%). Clocks often will not be off for more than
3.0 microseconds when the TCC is active. Cycle times are processor speed dependent and decrease
as processor core frequencies increase. A small amount of hysteresis has been included to prevent
rapid active/inactive transitions of the TCC when the processor temperature is near its maximum
operating temperature. Once the temperature has dropped below the maximum operating
temperature and the hysteresis timer has expired, the TCC goes inactive and clock modulation
ceases.
With a properly designed and characterized thermal solution, it is anticipated that the TCC would
only be activated for very short periods of time when running the most power intensive
applications. The processor performance im pact du e to these brief periods of TCC activation is
expected to be so minor that it would be immeasurable. An under-designed thermal solution that is
not able to prevent excessive activation of the TCC in the anticipated ambient environmen t may
cause a noticeable performance loss, and in some cases may result in a TC that exceeds the
specified maximum temperature and may affect the long-term reliability of the processor. In
addition, a thermal solution that is significantly under-designed may not be capable of cooling the
processor, even when the TCC is active continuously. Refer to the Intel® Pentium® 4 Processor on
90 nm Process Thermal Design Guidelines for information on designing a thermal solution.
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and
cannot be modified. The Thermal Monitor does not require any additional hardware, software
drivers, or interrupt handling routines.
68 Datasheet
Thermal Specifications and Design Considerations
5.2.2 On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force the processor
to reduce its power consumption . This mechanism is referred to as "On-Demand" mode and is
distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to reduce
system level power consumption . Systems using the processor must not rely on software usage of
this mechanism to limit the processo r temperature.
If bit 4 of the ACPI P_CNT Control Register (located in the processor IA32_THERM_CONTROL
MSR) is written to a 1, the processor will immediately reduce its power consu mp tion via
modulation (starting and stop ping) of the internal core clock, independent of the processor
temperature. When using On-Demand mode, the duty cycle of the clock modulatio n is
programmable via bits 3:1 of the same ACPI P_CNT Control Register. In On-Demand mode, the
duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5%
increments. On-Demand mode may be used in conjun ction with the Thermal Monitor . If the system
tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty
cycle of the TCC will override the duty cycle selected by the On-Demand mode.
5.2.3 PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature
has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the
Thermal Monitor must be enabled for the processor to be operating within specification), the TCC
will be active when PROCHOT# is asserted. The processor can be configured to generate an
interrupt upon the assertion or de-assertion of PROCHOT# . Refer to the Intel Architecture
Software Developer's Manuals for specific register and programming details.
The processor implements a bi-directional PRO CHOT# capability to allow system designs to
protect various components from over-temperature situations. The PROCHOT# signal is bi-
directional in that it can either signal when the processor has reached its maximum operating
temperature or be driven from an external source to activate the TCC. The ability to activate the
TCC via PROCHOT# can provide a means for thermal protection of sy stem components.
One application is the thermal protection of voltage regulators (VR). System designers can create a
circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR
is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, th e VR can cool down
as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR
thermal designs to target maximum sus tained current instead of maximum current. Systems should
still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in
case of system cooling failure. The system thermal design should allow the power delivery
circuitry to operate within its temperature specification even while the processor is operating at its
Thermal Design Power. With a properly de si gne d and characterized thermal solution, it is
anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time
when running the most power intensi ve appli cations. An under-designed thermal solution that is
not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may
cause a noticeable performance loss. Refer to the Intel® 865G/865GV/865PE/865P Chipset
Platform Design Guide and the Voltage Regulator-Down (VRD) 10.0 Design Guidelines for
Desktop Socket 478 for details on implementing the bi-directio nal PROCHOT# feature.
Datasheet 69
Thermal Specifications and Design Considerations
5.2.4 THERMTRIP# Signal Pin
Regardless of whether or not the Thermal Monitor feature is enabled, in the event of a catastrophic
cooling failure, the processor will automatically shut down when the silicon has reached an
elevated temperature (refer to the THERMTRIP# definition in Table 25). At this point , the FSB
signal THERMTRIP# will go active and stay active as described in Table 25. THERMTRIP#
activation is independent of processor activity and does not generate any bus cycles. If
THERMTRIP# is asserted, processor core voltage (VCC) must be removed.
5.2.5 Tcontrol and Fan Speed Reduction
Tcontrol is a temperature specification based on a temperature reading from the thermal diode. The
value for Tcontrol will be calibrated in manufacturing and configured for each processor. The
Tcontrol temperature for a given processor can be obtained by reading the
IA32_TEMPERATURE_TARGET MSR in the processor. The Tcontrol value that is read from the
IA32_TEMPERATURE_TARGET MSR needs to be converted from Hexadecimal to Decimal and
added to a base value of 50 °C.
The value of Tcontrol may vary from 00h to 1Eh (0 to 30 °C).
When Tdiode is above Tcontrol, then Tc must be at or below Tc(max) as defined by the thermal profile
in Table 27 and Figure 12; otherwise, the processor temperature can be maintained at Tcontrol (or
lower) as measured by the thermal diode.
The purpose of this feature is to support acoustic optim ization through fan speed control.
5.2.6 Thermal Diode
The processor incorporates an on-die thermal diode. A thermal sensor located on the system board
may monitor the di e temp erature of the processor for thermal ma nag ement/long term die
temperature change purposes. Table 28 and Table 29 provide the diode parameter and interface
specifications. This thermal diode is separate from the Therm al Monitor’s thermal sensor and
cannot be used to predict the behavior of the Thermal Monitor.
70 Datasheet
Thermal Specifications and Design Considerations
§
Table 28. Thermal Diode Parameters
Symbol Parameter Min Typ Max Unit Notes
IFW Forward Bias Current 11 187 uA 1
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
n Diode Ideality Factor 1.0083 1.011 1.023 2, 3, 4, 5
2. Characterized at 75 °C.
3. Not 100% tested. Specified by design characterization.
4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equa-
tion:
IFW = IS * (e qVD/nkT –1)
where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann
Constant, and T = absolute temperature (Kelvin).
5. Devices found to have an ideality factor of 1.0183 to 1.023 will cr eate a temp eratur e error of ap proximate ly
2 C higher than the actual temperature. In order to minimize any potential acoustic impact of this temperature
error, Tcontrol will be increased by 2 C on these parts.
RTSeries Resistance 3.242 3.33 3.594 Ω2, 3, 6
6. The series resistance, RT, is provided to allow for a more accurate measurement of the thermal diode tem-
perature. RT, as defined, includes the pins of the processor but does not include any socket resistance or
board trace resistance between the socket and the externa l remote diode thermal sensor. RT can be used
by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term.
Another application is that a temperature offset can be manually calculated and progra mmed into an offset
register in the remote diode thermal sen sors as exemplified by the equation:
Terror = [RT * (N-1) * IFWmin] / [nk/q * ln N]
where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic
charge.
Table 29. Thermal Diode Interface
Pin Name Pin Number Pin Description
THERMDA B3 diode anode
THERMDC C4 diode cathode
Datasheet 71
Features
6Features
This chapter contains power-on configuration options and clock control/lo w power state
descriptions.
6.1 Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples the hardware
configuration at reset, on the active-to-i nactive transition of RESET# . For specifications on these
options, refer to Table 30.
The sampled information configures the processor for subsequent operation. These configuration
options cannot be changed except by another reset. All resets reconfigure the processor; for reset
purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.
Table 30. Power-On Configuration Option Pins
Configuration Option Pin1,2
NOTES:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address pins not identified in this table as configuration options should not be asserted during RESET#.
Output tristate SMI#
Execute BIST INIT#
In Order Queue pipelining (set IOQ depth to 1) A7#
Disable MCERR# observation A9#
Disable BINIT# observation A10#
APIC Cluster ID (0-3) A[12:11]#
Disable bus parking A15#
Disable Hyper-Threading Technology A31#
Symmetric agent arbitration ID BR0#
RESERVED A[6:3]#, A8#, A[14:13]#, A[16:30]#, A[32:35]#
72 Datasheet
Features
6.2 Clock Control and Low Power States
The processor allows the use of AutoHALT, Stop-Grant, and Sleep states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on each
particular state. See Figure 14 for a visual representation of the processor low power states.
6.2.1 Normal State—State 1
This is the normal operating state for the processor.
6.2.2 AutoHALT Powerdown State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor transitions to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or
LINT[1:0] (NMI, INTR). RESET# causes the processor to immediately initiali ze itself.
The return from a System Management In terrupt (SMI) handler can be to either Normal Mode or
the AutoHALT powerdown state. See the Intel Architecture Software Developer's Manual, Volume
III: System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the AutoHALT powerdown st ate.
When the system de-asserts the STPCLK# interrupt, the processor will return executi on to th e
HALT state.
While in AutoHALT powerdown state, the processor wil l pro cess FSB snoops and interrupts.
Figure 14. Stop Clock State Machine
STPCLK#
De-asserted
SLP#
De-asserted
1. Norm al State
Normal executio n.
3. Stop Grant State
BCLK running.
Snoops and interr up ts allowed.
5. Sleep State
BCLK running.
No snoops or interrupts allowed.
2. Auto HALT Power Down State
BCLK running.
Snoops and interrupts allow ed.
4. HALT/Grant Snoop State
BCLK running.
Service snoops to caches.
STPCLK#
Asserted
SLP#
Asserted
Snoop
Event
Occurs
Snoop
Event
Serviced
HALT Instruction and
HALT Bus Cycle Generated
INIT#, BINIT#, INTR, NMI,
SMI#, RESET#
Snoop Event Serviced
Snoop Event Occurs
STPCLK# Asserted
STPCLK# De-asserted
Datasheet 73
Features
6.2.3 Stop-Grant State—State 3
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.
Since the GTL+ signal pins receive power from the FSB, these pins should not be driven (allowing
the level to return to VCC) for minimum power drawn by the termination resistors in this state. In
addition, all other in put pins on the FSB should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched
and can be serviced by software upon exit from the Stop Grant state.
RESET# will cause the processor to immediately initi alize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state occurs with the de-assertion of the
STPCLK# signal. When re-entering the Stop Grant state from the Sleep state, STPCLK# should
only be de-asse rted one or more bus clocks after the de-assertion of SLP#.
A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the FSB
(see Section 6.2.4). A transition to the Sleep state (see Section 6.2.5) occurs with the assertion of
the SLP# signal.
While in the Stop-Grant State, SMI#, INIT#, BINIT#, and LINT[1:0] are latched by the processor,
and only serviced when the processor returns to the Normal State. Only one occurrence of each
event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process snoops on the FSB and it will latch interrupts
delivered on the FSB.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if
there is any pending interrupt latched within the processor. Pending interrup ts that are bl ocked by
the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to
system logic that it sh ould return the processor to the Normal state.
6.2.4 HALT/Grant Snoop State—State 4
The processor responds to snoop or interrupt transactions on the FSB while in Stop-Grant state or
in AutoHALT powerdown state. During a snoop or interrupt transaction, the processor enters the
HALT/Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been
serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched.
After the snoop is serviced or the interrupt is latched, th e processor will return to the Stop-Grant
state or AutoHALT powerdown state, as appropriate.
74 Datasheet
Features
6.2.5 Sleep State—State 5
The Sleep state is a very low power state in which the processor maintains its cont ext, maintains
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be
entered from Stop-Grant state. Once in the S top-Gra nt state, the processor will enter the Sleep state
upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is
in the Stop Grant state. SLP# assertions while the processor is not in the Stop Grant state is out of
specification and may result in errone ou s processor operation.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the FSB while the processor is in Sleep state. Any transition on an inp ut signal
before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep St ate, the SLP#
and STPCLK# signals should be de-asserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.
Once in the Sleep state, the SLP# pin must be de-asserted if another asynchronous FSB event needs
to occur. The SLP# pin has a minimum assertion of one BCLK period.
When the processor is in the Sleep state, it will not respond to interrupts or snoo p transactions.
§
Datasheet 75
Boxed Processor Specifications
7Boxed Processor Specifications
The processor will also be of fered as an Intel boxed processor. Intel boxed processors are intended
for system integrators who build sy stems from baseboards and standard components. The boxed
processor will be supplied with a cooling solution. This chapter documents baseboard and system
requirements for the cooling solution that will be supplied with the boxed processor . This chapter is
particularly important for OEMs that manufacture baseboards for system integrators. Unless
otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets].
Figure 15 shows a mechanical representation of a boxed processor.
Note: •Drawings in this section reflect only the specifications on the Intel boxed processor produ ct.
These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is
the system designer's responsibility to consid er their proprietary cooling solution when
designing to the required keep-out zone on their system platform and chassis. Refer to the
Intel® Pentium® 4 Pro cessor on 90 nm Process Thermal Design Guidelines for further
guidance. Contact your local Intel Sales Represen tative for this document.
NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
Figure 15. Mechanical Representation of the Boxed Processor
76 Datasheet
Boxed Processor Specifications
7.1 Mechanical Specifications
7.1.1 Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor . The boxed processor
will be shipped with an unattached fan heatsink. Figure 15 shows a mechanical representation of
the boxed processor.
Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The
physical space requirements and dimensions for the boxed processor with assembled fan heatsink
are shown in Figure 16 (side views), and Figure 17 (top view). The airspace requirements for the
boxed processor fan heatsink must also be incorporated into new baseboard and system designs.
Airspace requirements are shown in Figure 20 and Figure 21. Note that some figures hav e
centerlines shown (marked with alphabetic designations) to clarify relat ive dim e nsioning.
Figure 16. Space Requirements for the Boxed Processor (Side View)
Datasheet 77
Boxed Processor Specifications
7.1.2 Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the
Intel® Pentium® 4 Pro cessor on 90 nm Process Thermal Design Guidelines for details on the
processor weight and heatsink requirements.
Note: The processor retention mechanism, based on the Intel reference design, should be used to ensure
compatibility with the heatsink attach clip assembly and the boxed processor thermal solution. The
heatsink attach clip assembly is latched to the retention tab features at each corner of the retention
mechanism.
The target load applied by the clips to the processor heat spreader for Intel's reference design is
75 ±15 lbf (maximum load is constrained by the package load capability). It is normal to observe a
bow or bend in the board due to this compressive load on the processor package and the socket.
The level of bow or bend depends on the motherboard material properties and component layout.
Any additional board stiffening devices (such as plates) are not necessary and should not be used
along with the reference mechanical componen ts an d boxed processor. Using such devices
increases the compressive load on the processor package and socket, likely beyond the maximum
load that is specified for those components. See the Intel® Pentium® 4 Processor on 90 nm Pr ocess
Thermal Design Guidelines for details on the Int el reference design.
Chassis that have adequate clearance between the motherboard and chassis wall (minimum
0.250 inch) should be selected to ensure the board's underside bend does not contact the chassis.
Figure 17. Space Requirements for the Boxed Processor (Top View)
78 Datasheet
Boxed Processor Specifications
7.1.3 Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly
The boxed processor thermal solution requires a processor retention mechanism and a heatsink
attach clip assembly to secure the processor and fan heatsink in the baseboard socket. The boxed
processor will not ship with retention mechanisms but will ship with the heatsink attach clip
assembly. Baseboards designed for use by system integrators should inclu de the reten tio n
mechanism that supports the boxed processor. Baseboard documentation should includ e
appropriate retention mechanism installation instructions.
7.2 Electrical Requirements
7.2.1 Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be
shipped with the boxed processor to draw power from a power header on the baseboard. The power
cable connector and pinout are shown in Figure 18. Baseboards must provide a m a tched power
header to support the boxed processor. Table 31 contains specifications for the input and output
signals at the fan heatsink connector. The fan h eatsi nk outputs a SENSE signal that is an open-
collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor
provides VOH to match the system board-mounted fan speed monitor requ irements, if applicable.
Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should
be tied to GND.
Note: The motherboard must supply a constant +12 V to the processor's power header to ensure proper
operation of the variable speed fan for the boxed processor.
The power header on the baseboard must be positioned to allow the fan heatsink power cable to
reach it. The power header identification and location should be documented in the platform
documentation, or on the system board itsel f. Figure 19 shows the location of the fan power
connector relative to the processor socket. The baseboard power header should be posi t io n ed
within 4.33 inches from the center of the processor socket.
Figure 18. Boxed Processor Fan Heatsink Power Cable Connector Description
Pin Signal
Straight squa re pin, 3-pin term inal hous ing with
polarizing ribs and friction locking ramp.
0.100" pin pitch, 0.025" square pin width.
Waldom*/Molex* P/N 22-01-3037 or equivalen t.
Match with straight pin, friction lock header on m otherboard
Waldom/Molex P/N 22-23-2031, AMP* P/N 640456-3,
or equivalent.
1
2
3
GND
+12V
SENSE
123
Datasheet 79
Boxed Processor Specifications
7.3 Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution used by the boxed
processor.
7.3.1 Boxed Processor Cooling Requirements
The boxed proc essor may be direct ly cool ed wit h a fan heatsink. However, meeting the processor's
temperature specification is also a function of the thermal design of the entire system, and
ultimately the responsibilit y of the system integrator. The processor temperature specification is
presented in Chapter 5. The boxed processor fan heatsink is able to keep the processor temperature
within the specifications (see Table 26) in chassis that provide good thermal management. For the
Table 31. Fan Heatsink Power and Signal Specifications
Description Min Typ Max Unit Notes
+12 V: 12 volt fan power supply 10.2 12 13.8 V
IC: Fan current draw 740 mA
SENSE: SENSE frequency 2 pulses per fan
revolution 1
NOTES:
1. Baseboard should pull this pin up to 5 V with a resistor.
Figure 19. Baseboard Power Header Placement Relative to Processor Socket
80 Datasheet
Boxed Processor Specifications
boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan
heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan
heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is
not blocked. Blocking the airflow to the fan heatsink reduces the coo ling efficiency and decreases
fan life. Figure 20 and Figure 21 illustrate an acceptable airspace clearance for the fan heatsink.
The air temperature entering the fan is required to be at or below 38 °C. Again, meet ing the
processor's temperature specification is the responsibility of th e system integrator.
Figure 20. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (side 1 view)
Figure 21. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (side 2 view)
Datasheet 81
Boxed Processor Specifications
7.3.2 Variable Speed Fan
The boxed processor fan operates at different speeds over a short range of internal chassis
temperatures. This allows the processor fan to operate at a lower speed and noise level, while
internal chassis temperatures are low. If the internal chassis temperature increases beyond a lower
set point, the fan speed will rise linearly with the internal temperat ure until the higher set point is
reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan noise
levels. Systems should be designed to provide adequate air around the boxed processor fan
heatsink that remains below the lower set point. These set points, represente d in Figure 22 and
Table 32, can vary by a few degrees from fan heatsink to fan heatsink. The internal chassis
temperature should be kept below 38 ºC. Meeting the processor's temperature specification
(see Chapter 5) is the responsibility of the system integrator.
Note: The motherboard must supply a constant +12 V to the processor's power header to ensure proper
operation of the variable speed fan for the boxed processor (refer to Table 31 for the specific
requirements).
§
Figure 22. Boxed Processor Fan Heatsink Set Points
Table 32. Boxed Processor Fan Heatsink Set Points
Boxed Processor Fan
Heatsink Set Point (ºC) Boxed Processor Fan Speed Notes
X ≤ 30 °C When the internal chassis temperature is below or equal to this set point,
the fan operates at its lowest speed. Recommended maximum internal
chassis temperature for nominal operating environment. 1
NOTES:
1. Set point variance is approximately ±1 °C from fan heatsink to fan heatsink.
Y = 34 °C When the internal chassis temperature is at this point, the fan operates
between its lowest and highest speeds. Recommended maximum
internal chassis temperature for worst-case operating environment.
Z ≥ 38 °C When the internal chassis temperature is above or equal to this set point,
the fan operates at its highest speed. 1
Lower Set Point
Lowest Noise Level
Intern al Chassis Temperature (De grees C)
XYZ
Inc reasi ng Fan
Speed & Noise
Higher Set P oint
Highest Noise Lev el
