5-1
FAST AND LS TTL DATA
HEX D FLIP-FLOP
The LSTTL /MSI SN54 /74LS174 is a high speed Hex D Flip-Flop. The
device is used primarily as a 6-bit edge-triggered storage register. The
information on the D inputs is transferred to storage during the LOW to HIGH
clock transition. The device has a Master Reset to simultaneously clear all
flip-flops. The LS174 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all Motorola TTL families.
•Edge-Triggered D-Type Inputs
•Buffered-Positive Edge-Triggered Clock
•Asynchronous Common Reset
•Input Clamp Diodes Limit High Speed Termination Effects
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
CONNECTION DIAGRAM DIP (TOP VIEW)
14 13 12 11 10 9
1 2 3 4 5 6 7
16 15
8
VCC
MR
Q5D5D4Q4Q3
D3CP
Q0D0D1Q1D2Q2GND
PIN NAMES LOADING (Note a)
HIGH LOW
D0–D5
CP
MR
Q0–Q5
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
LOGIC DIAGRAM
D Q
CP
CD
Q5Q4Q3Q2Q1Q0
CP D5D4D3D2D1D0
MR 14
2
6
7
3
4
5
9 11
12 10
13
15
D Q
CP
CD
D Q
CP
CD
D Q
CP
CD
D Q
CP
CD
D Q
CP
CD
1
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
SN54/74LS174
HEX D FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16 1
16
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
16 1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
D5
D4
D3
D2
D1
D0
9
1
3 4 6 11 13 14
CP
MR Q2
Q1
Q0Q3Q4Q5
2 5 7 10 12 15
5-2
FAST AND LS TTL DATA
SN54/74LS174
FUNCTIONAL DESCRIPTION
The LS174 consists of six edge-triggered D flip-flops with
individual D inputs and Q outputs. The Clock (CP) and Master
Reset (MR) are common to all flip-flops.
Each D input’s state is transferred to the corresponding flip-
flop’s output following the LOW to HIGH Clock (CP) transition.
A LOW input to the Master Reset (MR) will force all outputs
LOW independent of Clock or Data inputs. The LS174 is
useful for applications where the true output only is required
and the Clock and Master Reset are common to all storage
elements.
TRUTH TABLE
Inputs (t = n, MR = H) Outputs (t = n+1) Note 1
D Q
H H
L L
Note 1: t = n + 1 indicates conditions after next clock.
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V
TAOperating Ambient Temperature Range 54
74 –55
025
25 125
70 °C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 54
74 4.0
8.0 mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74 0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54 2.5 3.5 V
V
CC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74 0.25 0.4 V IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74 0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 26 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
5-3
FAST AND LS TTL DATA
SN54/74LS174
AC CHARACTERISTICS (TA = 25°C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
fMAX Maximum Input Clock Frequency 30 40 MHz
VCC = 5.0 V
CL = 15 pF
tPHL Propagation Delay, MR to Output 23 35 ns
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL Propagation Delay, Clock to Output 20
21 30
30 ns
CC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
tWClock or MR Pulse Width 20 ns
VCC = 5.0 V
tsData Setup Time 20 ns
VCC = 5.0 V
thData Hold Time 5.0 ns
VCC = 5.0 V
trec Recovery Time 25 ns
AC WAVEFORMS
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
1.3 V
1.3 V 1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
1.3 V
1.3 V1.3 V
1/fmax tw
ts(H) th(H)
ts(L) th(L)
CP
tPHL
tPLH
tW
tPHL
CP
trec
Q
MR
D
Q
*
1.3 V
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW to HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW to
HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
