MC100ES8011P
Rev 1, 2/2005
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Low Voltage 1:2 Differential
PECL-to-HSTL Clock Fanout Buffer
The MC100ES8011P is a low voltage 1:2 Differential PECL-to-HSTL clock
fanout buffer. Designed for the most demanding clock distribution systems, the
MC100ES8011P supports various applications that require the distribution of
precisely aligned differential clock signals. Using SiGe technology and a fully
differential architecture, the device offers very low skew outputs and superior
digital signal characteristics. Target applications for this clock driver are in high
performance clock distribution in computing, networking and telecommunication
systems.
Features
• 1:2 differential clock fanout buffer
• 20 ps maximum device skew
• SiGe Technology
• Supports DC to 625 MHz operation
• HSTL compatible differential clock outputs
• PECL compatible differential clock inputs
• 3.3V power supply
• Supports industrial temperature range
• Standard 8 lead SOIC package
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
MC100ES8011P
1:2 DIFFERENTIAL PECL TO HSTL
CLOCK FANOUT DRIVER
D SUFFIX
8-LEAD SOIC PACKAGE
CASE 751-06
ORDERING INFORMATION
Device Package
MC100ES8011PD SO-8
MC100ES8011PDR2 SO-8
PIN DESCRIPTION
Pin Function
D, D ECL Data Inputs
Qn, Qn LVDS Data Outputs
VCC Positive Supply
VEE Negative Supply
8
7
6
5
1
2
3
4
VCC
D
D
VEE
Q0
Q0
Q1
Q1
DATA SHEET
MC100ES8011P
IDT™ Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES8011P
1
Low Voltage 1:2 Differential PECL-to
-HSTL Clock Fanout Buffer
Product Group
2Freescale Semiconductor
MC100ES8011P
Table 1. Absolute Maximum Ratings(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol Parameter Conditions Rating Unit
VSUPPLY Power Supply Voltage Difference between VCC & VEE 3.9 V
VIN Input Voltage VCC – VEE ≤ 3.6V VCC + 0.3
VEE – 0.3 V
V
IOUT Output Current Continuous
Surge 50
100 mA
mA
TAOperating Temperature Range –40 to +85 °C
TSTG Storage Temperature Range –65 to +150 °C
Table 2. DC Characteristics (VCC = 3.3 V ± 5%; TJ = 0°C to 110°C)(1)
1. DC characteristics are design targets and pending characterization.
Symbol Characteristic Min Typ Max Unit Condition
PECL differential input signals (D, D)
VPP Differential Input Voltage(2)
2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
0.15 1.0 V Differential Operation
VCMR Differential Cross Point Voltage(3)
3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
1.0 VCC – 0.6 V Differential Operation
IIN Input Current ±150 mA VIN = VIH or VIN
HSTL clock outputs (Q[0:1], Q[0:1])
VX, OUT Output Differential Crosspoint 0.68 0.75 0.9 V
VOH Output High Voltage 1 V
VOL Ouput Low Voltage 0.4 V
Supply Current
ICC Maximum Quiescent Supply Current without
output termination current 80 105 mA VCC pin (core)
MC100ES8011P
Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer NETCOM
IDT™ Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES8011P
2
Product Group
Freescale Semiconductor 3
MC100ES8011P
Table 3. AC Characteristics (VCC = 3.3 V ± 5%; TJ = 0°C to 110°C)(1) (2)
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50Ω to VTT.
Symbol Characteristic Min Typ Max Unit Condition
PECL differential input signals (D, D)
VPP Differential Input Voltage (peak-to-peak)(3)
3. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device
skew.
0.2 1.0 V
VCMR Differential Cross Point Voltage(4)
4. VCMR (AC) is the crosspoint of the differential PECL input signal. No rmal AC operation is obtained when the crosspoint is within the VCMR
(AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP(AC) impacts the device propagation
delay, device and part-to-part skew.
1V
CC – 0.6 V
fCLK Input Frequency 625 MHz Differential
tPD Propagation Delay D to Q[0:1] 600 760 940 ps Differential
HSTL clock outputs (Q[0:1], Q[0:1])
VX, OUT Output Differential Crosspoint 0.68 0.75 0.9 V
VOH Output High Voltage 1 V
VOL Ouput Low Voltage 0.5 V
VO(P-P) Differential Output Voltage (peak-to-peak) 0.5 V
tSK(O) Output-to-Output Skew 20 ps Differential
tSK(PP) Output-to-Output Skew (part-to-part) 340 ps Differential
tSK(P) Output Pulse Skew 75 ps
tJIT(CC) Output Cycle-to-Cycle Jitter 1 ps
tr / tfOutput Rise/Fall Times 150 800 ps 20% to 80%
MC100ES8011P
Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer NETCOM
IDT™ Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES8011P
3
Product Group
4Freescale Semiconductor
MC100ES8011P
Figure 2. MC100ES8011P AC Test Referen ce
Differential Pulse
Generator
Z = 50Ω
RT = 50Ω
ZO = 50Ω
DUT
MC100ES8011P
VTT=GND
RT = 50Ω
ZO = 50Ω
VTT=GND
Figure 3. MC100ES8011P AC Reference Measurement Waveform (PECL Input)
D
tPD (D to Q[0–1])
VCMR=VCC–1.3V
VDIF=0.8V
D
Q[0–1]
Q[0–1]
MC100ES8011P
Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer NETCOM
IDT™ Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES8011P
4
Product Group
Freescale Semiconductor 5
MC100ES8011P
PACKAGE DIMENSIONS
D SUFFIX
8-LEAD SOIC PACKAGE
CASE 751-06
L
h
X 45˚
θ
C
SEATING
PLANE
S
B
M
0.25 A
S
C
B
A1
CA
0.10
1
4
58
M
B
M
0.25
D
EH
A
Be
DIM MIN MAX
MILLIMETERS
A1.35 1.75
A1 0.10 0.25
B0.35 0.49
C0.19 0.25
D4.80 5.00
E
1.27 BSCe
3.80 4.00
H5.80 6.20
h
0˚ 7˚
L0.40 1.25
θ
0.25 0.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MC100ES8011P
Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer NETCOM
IDT™ Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES8011P
5
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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PART NUMBERS
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MPC92459
900 MHz Low Voltage LVDS Clock Synthesizer NETCOM
MC100ES8011P
Low Voltage 1:2 Differential PECL-to-HSTL Clock Fanout Buffer NETCOM
