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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
A ColdFire Instruction Set Enhancements
This appendix details the new opcodes implemented as part of the Revision B (
ISA_B
)
enhancements to the basic ColdFire instruction set architecture. In some cases, the
opcodes represent minor enhancements to existing ColdFire functions, while in other
cases, the functionality is new and not covered in the existing ISA.
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
Bcc Branch Conditionally
Operation: If Condition True
Then PC + dn→ PC
Assembler
Syntax: Bcc <label>
Attributes: Size = Byte, Word, Long
Description: If the specified condition is true, program execution continues at location
(PC) + displacement. The program counter contains the address of the instruction
word for the Bcc instruction, plus two. The displacement is a two’s-complement
integer that represents the relative distance in bytes from the current program
counter to the destination program counter. If the 8-bit displacement field in the
instruction word is 0, a 16-bit displacement (the word immediately following the
instruction) is used. If the 8-bit displacement field in the instr uction word is all ones
($FF), the 32-bit displacement (longword immediately following the instruction) is
used. Condition code cc specifies one of the following conditional tests:
Condition Codes:
Not affected
Mnemonic Condition Mnemonic Condition
CC(HI) Carry Clear LS Low or Same
CS(LO) Carry Set LT Less Than
EQ Equal MI Minus
GE Greater or Equal NE Not Equal
GT Greater Than PL Plus
HI High VC Overflow Clear
LE Less or Equal VS Overflow Set
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
Bcc Branch Conditionally
Instruction Format:
Instruction Fields:
Condition field— binary code for one of the conditions listed in the table.
8-Bit Displacement field—two’s complement integer specifying the number of bytes
between the branch instruction and the next instruction to be executed if the
condition is met.
16-Bit Displacement field—used for the displacement when the 8-bit displacement
field contains $00.
32-Bit Displacement field—used for the displacement when the 8-bit displacement
field contains $FF.
NOTE
A branch to the next immediate instruction automatically uses
the 16-bit displacement format because the 8-bit
displacement field contains $00 (zero offset).
1514131211109876543210
0 1 1 0 CONDITION 8-BIT DISPLACEMENT
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
BRA Branch Always
Operation: PC + dn→ PC
Assembler
Syntax: BRA <label>
Attributes: Size = Byte, Word, Long
Description: Program e x ecution continues at location (PC) + displacement. The progr am
counter contains the address of the instruction word of the BRA instruction, plus two .
The displacement is a two’ s complement integer that represents the relativ e distance
in bytes from the current program counter to the destination program counter. If the
8-bit displacement field in the instruction word is 0, a 16-bit displacement (the word
immediately following the instruction) is used. If the 8-bit displacement field in the
instruction word is all ones ($FF), the 32-bit displacement (longword immediately
following the instruction) is used.
Condition Codes:
Not affected
Instruction Format:
Instruction Fields:
8-Bit Displacement field—two’s complement integer specifying the number of bytes
between the branch instruction and the next instruction to be executed.
16-Bit Displacement field—used for a larger displacement when the 8-bit
displacement is equal to $00.
32-Bit Displacement field—used for the displacement when the 8-bit displacement
field contains $FF.
NOTE
A branch to the next immediate instruction automatically uses
the 16-bit displacement format because the 8-bit
displacement field contains $00 (zero offset).
1514131211109876543210
01100000 8-BIT DISPLACEMENT
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
BSR Branch to Subroutine
Operation: SP – 4 → SP; PC → (SP); PC + dn→ PC
Assembler
Syntax: BSR <label>
Attributes: Size = Byte, Word, Long
Description: Pushes the word address of the instruction immediately following the BSR
instruction onto the system stack. The program counter contains the address of the
instruction word, plus two. Program execution then continues at location (PC) +
displacement. The displacement is a two’s complement integer that represents the
relative distance in bytes from the current program counter to the destination
program counter. If the 8-bit displacement field in the instruction word is 0, a 16-bit
displacement (the word immediately following the instruction) is used. If the 8-bit
displacement field in the instruction word is all ones ($FF), the 32-bit displacement
(longword immediately following the instruction) is used.
Condition Codes:
Not affected
Instruction Format:
1514131211109876543210
01100001 8-BIT DISPLACEMENT
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
BSR Branch to Subroutine
Instruction Fields:
8-Bit Displacement field—two’s complement integer specifying the number of bytes
between the branch instruction and the next instruction to be executed.
16-Bit Displacement field—used for a larger displacement when the 8-bit
displacement is equal to $00.
32-Bit Displacement field—used for the displacement when the 8-bit displacement
field contains $FF.
NOTE
A branch to the next immediate instruction automatically uses
the 16-bit displacement format because the 8-bit
displacement field contains $00 (zero offset).
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
CMP Compare
Operation: Destination – Source → cc
Assembler
Syntax: CMP <ea>y, Rx
Attributes: Size = Byte, Word, Long
Description: Subtracts the source operand from the destination register and sets the
condition codes according to the result; the destination register is not changed. The
size of the operation may be specified as byte, word, or longword when the
destination is a data register, and word or longword when the destination is an
address register. If the destination is an address register, word-sized source
operands are sign-extended to 32-bit values before the operation is peformed.
Condition Codes:
X — not affected
N — set if the result is negative; cleared otherwise
Z — set if the result is zero; cleared otherwise
V — set if an overflow occurs; cleared otherwise
C — set if a borrow occurs; cleared otherwise
Instruction Format:
Instruction Fields:
Register field—specifies the destination register.
Opmode field:
XNZVC
—∗∗∗∗
1514131211109876543210
1 0 1 1 REGISTER OPMODE EFFECTIVE ADDRESS
MODE REGISTER
Byte Word Long Operation
000 001 010 Dx - <ea>y
- 011 111 Ax - <ea>y
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
CMP Compare
Effective Address field—specifies the source operand; use addressing modes as
listed in the following table:
* Allowable for word and longword operands only
Addressing Mode Mode Register Addressing Mode Mode Register
Dy 000 reg. number:Dy (xxx).W 111 000
Ay* 001 reg. number:Ay (xxx).L 111 001
(Ay) 010 reg. number:Ay #<data> 111 100
(Ay) + 011 reg. number:Ay
– (Ay) 100 reg. number:Ay
(d16,Ay) 101 reg. number:Ay (d16,PC) 111 010
(d8,Ay,Xi) 110 reg. number:Ay (d8,PC,Xi) 111 011
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
CMPI Compare Immediate
Operation: Destination – Immediate Data → cc
Assembler
Syntax: CMPI #<data>, Dx
Attributes: Size = Byte, Word, Long
Description: Subtracts the immediate data from the destination operand and sets the
condition codes according to the result; the destination location is not changed. The
size of the operation is specified as a longword. The size of the operation may be
specified as byte, word, or longword.
Condition Codes:
X — not affected
N — set if the result is negative; cleared otherwise
Z — set if the result is zero; cleared otherwise
V — set if an overflow occurs; cleared otherwise
C — set if a borrow occurs; cleared otherwise
Instruction Format:
Instruction Fields:
Register field - destination data register.
Size field:
Note: If size = byte, the immediate is contained in bits[7:0] of
the single extension word. If size = word, the immediate is
contained in bits[15:0] of the single extension word. If size =
long, the immediate is contained in the two extension words.
XNZVC
—∗∗∗∗
1514131211109876543210
00001100 SIZE 0 0 0 REGISTER
UPPER WORD
LOWER WORD
Byte Word Long Operation
00 01 10 Dx - #<data>
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
MOVE Move Data from Source to Destination
Operation: Source → Destination
Assembler
Syntax: MOVE <ea>y, <ea>x
MOVEA <ea>y, Ax
Attributes: Size = Byte, Word, Long
Description: Moves the data at the source to the destination location and sets the
condition codes according to the data. The size of the oper ation ma y be specified as
byte, word, or longword.
Condition Codes:
X — not affected
N — set if the result is negative; cleared otherwise
Z — set if the result is zero; cleared otherwise
V — always cleared
C — always cleared
Instruction Format:
Instruction Fields:
Size field—specifies the size of the operand to be moved:
01 — byte operation
11 — word operation
10 — long operation
XNZVC
—∗∗00
1514131211109876543210
0 0 SIZE DESTINATION SOURCE
REGISTER MODE MODE REGISTER
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
MOVE Move Data from Source to Destination
Destination Effective Address field—specifies the destination location; the possible
data alterable addressing modes are listed in the table below. The ColdFire
MOVE instruction has restrictions on combinations of source and destination
addressing modes. The table shown on the bottom of following page outlines
the restrictions.
*If the destination is an address register, condition codes are unaffected. Some assemblers accept
the MOVEA mnemonic to designate this slight difference.
Addressing Mode Mode Register Addressing Mode Mode Register
Dx 000 reg. number:Dx (xxx).W 111 000
Ax* 001 reg. number: Ax (xxx).L 111 001
(Ax) 010 reg. number:Ax #<data> — —
(Ax) + 011 reg. number:Ax
– (Ax) 100 reg. number:Ax
(d16,Ax) 101 reg. number:Ax (d16,PC) — —
(d8,Ax,Xi) 110 reg. number:Ax (d8,PC,Xi) — —
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
MOVE Move Data from Source to Destination
Source Effective Address field—specifies the source operand; the possible
addressing modes are listed in the tab le below. The ColdFire MOVE instruction
has restrictions on combinations of source and destination addressing modes.
The table shown on the bottom of this page outlines the restrictions.
NOTE
Most assemblers use MOVEA when the destination is an
address register.
Use MOVEQ to move an immediate 8-bit value to a data
register. Use MOV3Q to move a 3-bit immediate value to any
effective destination address.
Not all combinations of source/destination addressing modes
are possible. The table below shows the possible
combinations.
Note: The combination of #<xxx>,d16(Ax) addressing modes
can only be used on move byte and move word opcodes.
Refer to the previous tables for valid source and destination
addressing modes.
Addressing Mode Mode Register Addressing Mode Mode Register
Dy 000 reg. number:Dy (xxx).W 111 000
Ay 001 reg. number:Ay (xxx).L 111 001
(Ay) 010 reg. number:Ay #<data> 111 100
(Ay) + 011 reg. number:Ay
– (Ay) 100 reg. number:Ay
(d16,Ay) 101 reg. number:Ay (d16,PC) 111 010
(d8,Ay,Xi) 110 reg. number:Ay (d8,PC,Xi) 111 011
Source Addressing Mode Destination Addressing Mode
Dy, Ay, (Ay), (Ay)+,-(Ay) All possible
(d16, Ay), (d16, PC) All possible except (d8, Ax, Xi), (xxx).W, (xxx).L
(d8, Ay, Xi), (d8, PC, Xi), (xxx).W, (xxx).L, #<xxx> All possible except (d8, Ax, Xi), (xxx).W,
(xxx).L
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
MOV3Q Move 3-Bit Data Quick
Operation: Immediate Data→ Destination
Assembler MOV3Q #<data>,<ea>x
Syntax:
Attributes: Size = Long
Description: Move the immediate data to the operand at the destination location. The
data range is from -1 to 7, excluding 0. The immediate data is zero-filled to a long
operand and all 32 bits are transferred to the destination location.
Condition Codes:
X — not affected
N — set if the result is negative; cleared otherwise
Z — set if the result is zero; cleared otherwise
V — always cleared
C — always cleared
Instruction Format:
Instruction Fields:
Data field—3 bits of data ha ving a range {-1,1-7} where a data v alue of 0 represents
-1.
Eff ectiv e Address field—specifies the destination operand; use only data addressing
modes listed in the following table:
XNZVC
—∗∗00
1514131211109876543210
1 0 1 0 Data 1 01 MODE REGISTER
Addressing Mode Mode Register Addressing Mode Mode Register
Dx 000 reg. number:Dx (xxx).W 111 000
Ax 001 reg. number:Ax (xxx).L 111 001
(Ax) 010 reg. number:Ax #<data> — —
(Ax) + 011 reg. number:Ax
– (Ax) 100 reg. number:Ax
(d16,Ax) 101 reg. number:Ax (d16,PC) — —
(d8,Ax,Xi) 110 reg. number:Ax (d8,PC,Xi) — —
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
MVS Move with Sign Extend
Operation: (Source with sign extension) → Destination
Assembler MVS <ea>y,Dx
Syntax:
Attributes: Size = Byte, Word
Description: Sign-extend the source operand and move to the destination register. For
the byte oper ation, bit 7 of the source is copied to bits 31-8 of the destination. For the
word operation, bit 15 of the source is copied to bits 31-16 of the destination.
Condition Codes:
X — not affected
N — set if the result is negative; cleared otherwise
Z — set if the result is zero; cleared otherwise
V — always cleared
C — always cleared
Instruction Format:
XNZVC
—∗∗00
1514131211109876543210
0 1 1 1 REGISTER 1 0 SIZE EFFECTIVE ADDRESS
MODE REGISTER
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
MVS Move with Sign Extend
Instruction Fields:
Size field - specifies the size of the operation
0 - byte operation
1 - word operation
Register field—specifies a data register as the destination.
Effective Address field—specifies the source operand; use only data addressing
modes listed in the following table:
Addressing Mode Mode Register Addressing Mode Mode Register
Dy 000 reg. number:Dy (xxx).W 111 000
Ay 001 reg. number:Ay (xxx).L 111 001
(Ay) 010 reg. number:Ay #<data> 111 100
(Ay) + 011 reg. number:Ay
– (Ay) 100 reg. number:Ay
(d16,Ay) 101 reg. number:Ay (d16,PC) 111 010
(d8,Ay,Xi) 110 reg. number:Ay (d8,PC,Xi) 111 011
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
MVZ Move with Zero-Fill
Operation: (Source with zero fill) → Destination
Assembler MVZ <ea>y,Dx
Syntax:
Attributes: Size = Byte, Word
Description: Zero-fill the source operand and move to the destination register. For the
byte operation, the source operand is moved to bits 7-0 of the destination and bits
31-8 are filled with zeros. For the word operation, the source operand is moved to bits
31-9 of the destination and bits 31-16 are filled with zeros.
Condition Codes:
X — not affected
N — always cleared
Z — set if the result is zero; cleared otherwise
V — always cleared
C — always cleared
Instruction Format:
XNZVC
—0∗00
1514131211109876543210
0 1 1 1 REGISTER 1 1 SIZE EFFECTIVE ADDRESS
MODE REGISTER
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
MVZ Move with Zero-Fill
Instruction Fields:
Size field - specifies the size of the operation
0 - byte operation
1 - word operation
Register field—specifies a data register as the destination.
Effective Address field—specifies the source operand; use only data addressing
modes listed in the following table:
Addressing Mode Mode Register Addressing Mode Mode Register
Dy 000 reg. number:Dy (xxx).W 111 000
Ay 001 reg. number:Ay (xxx).L 111 001
(Ay) 010 reg. number:Ay #<data> 111 100
(Ay) + 011 reg. number:Ay
– (Ay) 100 reg. number:Ay
(d16,Ay) 101 reg. number:Ay (d16,PC) 111 010
(d8,Ay,Xi) 110 reg. number:Ay (d8,PC,Xi) 111 011
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
SATS Signed Saturate
Operation: if CCR.V == 1,
then if Dx[31] == 0,
then Dx[31:0] = $80000000
else Dx[31:0] = $7FFFFFFF
else Dx[31:0] is unchanged
Assembler
Syntax: SATS Dx
Attributes: Size = Long
Description: Update the destination register only if the overflow bit of the CCR is set. If
the operand is negativ e, then set the result to greatest positive number , otherwise set
the result to the largest negativ e v alue . The condition codes are set according to the
result.
Condition Codes:
X — not affected
N — set if the result is negative; cleared otherwise
Z — set if the result is zero; cleared otherwise
V — always cleared
C — always cleared
Instruction Format:
Instruction Fields:
Register field—specifies the destination data register.
XNZVC
—∗∗00
1514131211109876543210
0100110010000 REGISTER
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ColdFire Processor Family
Version 4 ColdFire Reference Design
Revision 1.5
TAS Test and Set an Operand
Operation: Destination Tested → CCR; 1 → bit 7 of Destination
Assembler
Syntax: TAS <ea>x
Attributes: Size = Byte
Description: Tests and sets the byte operand addressed by the effective address field.
The instruction tests the current value of the operand and sets the N and Z condition
code bits appropriately. TAS also sets the high order bit of the operand. The operand
uses a read-modify-write memory cycle that completes the operation without
interruption. This instruction supports use of a flag or semaphore to coordinate
several processors.
Condition Codes:
X — not affected
N — set if the most significant bit of the operand is currently set; cleared otherwise
Z — set if the operand was zero; cleared otherwise
V — always cleared
C — always cleared
Instruction Format:
Instruction Fields:
Effective Address field—specifies the destination location; the possible data alterable
addressing modes are listed in the table below.
XNZVC
—∗∗00
1514131211109876543210
0100101011 EFFECTIVE ADDRESS
MODE REGISTER
Addressing Mode Mode Register Addressing Mode Mode Register
— — — (xxx).W 111 000
— — — (xxx).L 111 001
(Ax) 010 reg. number:Ax — — —
(Ax) + 011 reg. number:Ax
– (Ax) 100 reg. number:Ax
(d16,Ax) 101 reg. number:Ax — — —
(d8,Ax,Xi) 110 reg. number:Ax — — —
