NOT RECOMMENDED
FOR NEW DESIGNS
Replacement: FM28V100
Preliminary
This is a product that has fixed target specifications but are subject Ramtron International Corporation
to change pending characterization results. 1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
Rev. 1.91
Aug. 2009 Page 1 of 12
FM20L08
1Mbit Bytewide FRAM Memory – Extended Temp.
Features
1Mbit Ferroelectric Nonvolatile RAM
• Organized as 128Kx8
• Unlimited Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 33MHz
• Advanced High-Reliability Ferroelectric Pro cess
SRAM Replacement
• JEDEC 128Kx8 SRAM pinout
• 60 ns Access Time, 150 ns Cycle Time
System Supervisor
• Low Voltage monitor drives exter nal /LVL signal
• Write P r otects memory for low voltage condition
Superior to B a ttery-backed SRAM Modules
• No battery concerns
• Monolithic reliab ility
• True surface mount solution, no rework steps
• Superior for moisture, shock, and vibration
• Resistant to negative voltage undershoot s
Low Power Operation
• 3.3V +10%, -5% Power Supply
• 25 mA Active Current
Industry Sta ndard Configurat ions
• Extended Temperature -20° C to +85 ° C
• 32-pin “Green”/RoHS TSOP (-TGC)
Description
The FM20L08 is a 128K x 8 nonvolatile memory that
reads and writes like a standard SRAM. A
ferroelectric random access memory or FRAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and unlimited write endurance make
FRAM superior to other types of memory.
In-system operation of the FM20L08 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The FRAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM20L08 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in the form of an SRAM.
The FM20L08 includes a voltage monitor function
that monitors the power supply voltage. It asserts an
active-low signal that indicates the memory is write-
protected when V
DD
drops below a critical threshold.
When the /LVL signal is low, the memory is
protected against an inadvertent access and data
corruption.
Device specifications are guaranteed over the
temperature range -20°C to +85°C.
Pin Configuration
Ordering Information
FM20L08-60-T GC* 60 ns access, 32-pin
“Green”/RoHS TSOP
* End of life. Last time buy Nov. 2009.
TSOP-I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
WE
DNU
A15
VDD
LVL
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
NOT RECOMMENDED
FOR NEW DESIGNS
Replacement: FM28V100
FM20L08 - Extended Temp.
Rev. 1.91
Aug. 2009 Page 2 of 12
Address Latch
CE
Control
Logic
WE
Row Decoder
A(16:3)
A(2:0)
I/O Latch & Bus Driver
OE
DQ(7:0)
16K x 64
F-RAM Array
VDD Monitor
VDD
LVL
A(16:0)
Write
Protect
. . .
Column Decoder
. . .
Figure 1. Block Diagram
Pin Description
Pin Name Type Pin Description
A(16:0) Input Address inputs: The 17 address lines select one of 131,072 bytes in the FRAM array.
The address value is latched on the falling edge of /CE. Addresses A(2:0) are used for
page mode read and write operations.
/CE Input Chip Enable inputs: The device is selected and a new memory access begins when /CE
is low. The entire address is latched internally on the falling edge of chip enable.
Subsequent changes to the A(2:0) address inputs allow page mode operation.
/WE Input Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM20L08 to write the data on the DQ bus to the FRAM arr ay. The falling edge of /WE
latches a new column address for fast page mode write cycles.
/OE Input Output Enable: When /OE is low, the FM20L08 drives the data bus when valid data is
available. Deasserting /OE high tri-states the DQ pins.
DQ(7:0) I/O Data: 8-bit bi-directional data bus for accessing the FRAM array.
/LVL Output Low Voltage Lockout: When the voltage monitor detects that V
DD
is below V
TP
, the
/LVL will be asserted low. While /LVL is low, the memory array cannot be accessed
which prevents a low voltage write from corrupting data. When V
DD
is within its normal
opera ting limits, the /LVL signal will be pulled high.
DNU - Do Not Use: This pin should be left unconnected.
VDD Supply Supply Voltage: 3.3V
VSS Supply Ground
NOT RECOMMENDED
FOR NEW DESIGNS
Replacement: FM28V100
FM20L08 - Extended Temp.
Rev. 1.91
Aug. 2009 Page 3 of 12
Functional Trut h Table
/CE /WE A(16:3) A(2:0) Operation
H X X X Standby/Idle
↓ H V V Read
L H No Change Change Page Mod e Read
L H Change V Random Read
↓ L V V /CE-Controlled Write
L ↓ X V /WE-Controlled Write
2
L ↓ No Change V Page Mode W rite
3
↑ X X X Starts Precharge
Notes:
1) H=Logic High, L=Logic Low, V=Valid Address, X=Don’t Ca re.
2) /WE-cont rolled write cycle begins as a Read cycle and A(16: 3) is latched then.
3) Addresses A(2:0) must remain stable for at least 15 ns during page mode operation.
4) For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.
NOT RECOMMENDED
FOR NEW DESIGNS
Replacement: FM28V100
FM20L08 - Extended Temp.
Rev. 1.91
Aug. 2009 Page 4 of 12
Overview
The FM20L08 is a bytewide FRAM memory
logically organized as 131,072 x 8 and is accessed
using an industry standard parallel interface. All data
written to the part is immediately nonvolatile with no
delay. The device offers page mode operation which
provides higher speed access to addresses within a
page (row). An access to a different page requires that
either /CE transitions low or the upper address
A(16:3) changes.
Memory Operation
Users access 131,072 memory locations with 8 data
bits each through a parallel interface. The FRAM
array is internally organized as 16K rows of 64 bits
each. Within each row (page) there are 8 column
locations, which allow fast access in page mode
opera tion. Once an initial ad dr ess has been latched by
the falling edge of /CE, subsequent column locations
may be accessed without the need to toggle /CE.
When /CE is deasserted high, a precharge operation
begins. Writes occur immediately at the end of the
access with no delay. The /WE pin must be toggled
for each write operation.
Read Operation
A read operation begins on the falling edge of /CE.
The falling edge of /CE causes the address to be
latched and starts a memory read cycle if /WE is high.
Data becomes available on the bus after the access
time has been satisfied. Once the address has been
latched and the access completed, a new access to a
random lo cation (different row) may begin while /CE
is still low. The minimum cycle time for random
addresses is t
RC
. Note that unlike SRAMs, the
FM20L08’s /CE-initiated access time is faster than
the address cycle time.
The FM20L08 will drive the da ta bus only when /OE
is asserted low and the memory access time has been
satisfied. If /OE is asserted prio r to completion of the
memory access, the data bus will not be driven until
valid data is available. This feature minimizes supply
current in the system by eliminating transients caused
by invalid data being driven onto the bus. When /OE
is inactive, the data bus will remain hi-Z.
Write Operation
Writes occur in the FM20L08 in the same time
interval as reads. The FM20L08 supports both /CE-
and /WE-controlled write cycles. In both cases, the
address is latched on the falling edge of /CE.
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the de vice begins the
memory cycle as a write. The FM20L08 will not
drive the data bus regardless of the state of /OE as
long as /WE is low. Input data must be valid when
/CE is d easserted high. I n a /WE-controlled write, the
memory cycle begins on the falling edge of /CE. The
/WE signal falls some time later. Therefore, the
memory cycle begins as a read. The data bus will be
driven if /OE is low, however it will hi-Z once /WE is
asserted low. The /CE- and /WE-controlled write
timing cases are shown on page 9. In the Write Cycle
Timing 2 diagram, the data bus is shown as a hi-Z
condition while the chip is write-enabled and before
the required setup time. Although this is drawn to
look like a mid-level voltage, it is recommended that
all DQ pins comply with the minimum V
IH
/V
IL
oper a ting levels.
Write access to the array begins on the falling edge of
/WE after the memory cycle is initiated. The write
access terminates on the rising edge of /WE or /CE,
whichever comes first. A valid write operation
requires the user to meet the access time specification
prior to deasserting /WE or /CE. Data setup time
indicates the interval during which data cannot
change prior to the end of the write access (/WE or
/CE high).
Unlike other nonvolatile memory technologies, there
is no write delay with FRAM. Since the read and
write access times of the underlying memory are the
same, the user experiences no delay through the bus.
The entire memory operation occurs in a single bus
cycle. Data polling, a technique used with EEP ROMs
to determine if a wr ite is complete, is unnecessary.
Page Mode Operation
The FM20L08 provides the user fast access to any
data within a row element. Each row has eight
column locations. An access can start anywhere
within a row and other column locations may be
accessed without the need to toggle the /CE pin. For
page mode reads, once the first data byte is driven
onto the bus, the column address inputs A(2:0) may
be changed to a new value. A new data byte is then
driven to the DQ pins. For page mode writes, the
first write pulse defines the first write access. While
/CE is low, a subsequent write pulse along with a new
column address provides a page mode write access.
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is prepared for a new
access. Precharge is user-initiated by driving the /CE
signal high. It must remain high for at least the
minimum precharge time t
PC
.
NOT RECOMMENDED
FOR NEW DESIGNS
Replacement: FM28V100
FM20L08 - Extended Temp.
Rev. 1.91
Aug. 2009 Page 5 of 12
Supply Voltage Monitor
An internal voltage monitor circuit continuously
checks the V
DD
supply voltage. When V
DD
is below
the specified threshold V
TP
, the monitor asserts the
/LVL signal to an active-low state. The FM20L08
locks out access to the memory when V
DD
is below
the trip voltage. This prevents the system from
accessing memory when V
DD
is too low and
inadvertently corrupting the data. The /LVL signal
should not be used as a system reset signal because
the system host may attempt to write data to the
FM20L08 below its specified operating voltage. The
/LVL pin may be used as a status indicator that the
memor y is locked out.
On power up, the /LVL signal will begin in a low
state signifying that V
DD
is below the V
TP
threshold. It
will remain low as long as V
DD
is below that level.
Once V
DD
rises ab o ve V
TP
, a hold-off timer will b egin
creating the delay t
PULV
. Once this delay has elapsed,
the /LVL signal will go high or inactive. At this time
the memory can be accessed. The memory is ready
for access prior to t
PU
as shown in the Electrical
Specifications section. The /LVL signal will remain
high until V
DD
drops below the threshold.
SRAM Drop-In Replacement
The FM20L08 has been designed to be a drop-in
replacement for standard asynchronous SRAMs. The
device does not require /CE to toggle for each new
address. /CE may remain low indefinitely while V
DD
is app lied. When /CE is low, the device automatically
detects add ress changes and a new access is begun. It
also allows page mode operation at speeds up to
33MHz.
Although /CE may be held low for extended
periods of time, the pin should not be tied to
ground or held low during power cycles. /CE
must be pulled high and allowed to track V
DD
during powerup and powerdown cycles. It is the
user’s responsibility to ensure that chip enable is
high to prevent incorrect operation. Figure 2
shows a pullup resisto r on /CE w hich w ill keep the
pin high during power cycles assuming the
MCU/MPU pin tri-states during the reset
condition. The pullup resistor value should be
chosen to ensure the /CE pin tracks V
DD
yet a high
enough value that the current drawn when /CE is
low is no t an issue.
Figure 2. Use of Pullup Resistor on /CE
For applications that require the lowest power
consumption, the /CE signal should be active only
during memory accesses. Due to the external pullup
resistor, so me supply current will be drawn while /CE
is low. When /CE is high, the device draws no more
than the maximum standby current I
SB
.
The FM20L08 is backward compatible with the
256Kbit FM18L08 device. So, operating the
FM20L08 with /CE toggling low on every address is
perfectly acceptable.
CE
WE
OE
A(16:0)
DQ
FM20L08
V
DD
MCU/
MPU
R
NOT RECOMMENDED
FOR NEW DESIGNS
Replacement: FM28V100
FM20L08 - Extended Temp.
Rev. 1.91
Aug. 2009 Page 6 of 12
Electrical Specifications
A bsolut e Maximum Ra tings
Symbol Description Ratings
V
DD
Power Supply Voltage with respect to V
SS
-1.0V to +5.0V
V
IN
Voltage on any signal pin with respect to V
SS
-1.0V to +5.0V and
V
IN
< V
DD
+1V
T
STG
Storage Temperature -55°C to +125 °C
T
LEAD
Lead Temperature (Soldering, 10 seconds) 300° C
V
ESD
Electrostatic Discharge Voltage
- Human Body Model (JEDEC Std JESD22-A114-B)
- Charged Device Model (JEDEC Std JESD22-C101-A)
- Machine Model (JEDEC Std JESD22-A115-A)
3kV
750V
200V
Package Moisture Sensitivity Level MSL-2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (T
A
= -20° C to +85 ° C, V
DD
= 3.3V +10%, -5% unless otherwise specified)
Symbol Parameter Min Typ Max Units Notes
V
DD
Power Supply 3.135 3.3 3.63 V
I
DD
V
DD
Supply Current 25 mA 1
I
SB
Standby Current – CMOS 25 µA 2
V
TP
V
DD
trip point to assert (deassert) /LVL 2.7 - 3.0 V 3
I
LI
Input Leakage Current ±1 µA 4
I
LO
Output Leakage Current ±1 µA 4
V
IH
Input High Voltage 2.2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.6 V
V
OH
Output High Volta ge (
I
OH
= -1.0 mA)
2.4 - V
V
OL
Output Low Voltage (
I
OL
= 2.1 mA)
- 0.4 V 5
Notes
1.
V
DD
= 3.6V, /CE cycling at minimum cycle time. All inputs at CMOS levels (0.2V or V
DD
-0.2V), all DQ pins unloaded.
2.
V
DD
= 3.6V, /CE at V
DD
, All other pins at CMOS levels (0.2V or V
DD
-0.2V).
3.
This is the V
DD
trip voltage at which /LVL is asserted or deasserted. When V
DD
rises above V
TP
, /LVL will be deasserted
after satisfying t
PULV
. When V
DD
drops below V
TP
, /LVL will be asserted after satisfying t
PDLV
.
4.
V
IN
, V
OUT
between V
DD
and V
SS
.
5.
For the /LVL pin, the test condition is I
OL
= 80 µA when V
DD
is between 3.135V and 1.2V. The state of the /LVL pin is not
guaranteed when V
DD
is below 1.2V.
NOT RECOMMENDED
FOR NEW DESIGNS
Replacement: FM28V100
FM20L08 - Extended Temp.
Rev. 1.91
Aug. 2009 Page 7 of 12
Read Cycle AC Parameters
(T
A
= -20
° C to +85
° C, C
L
= 30 pF, V
DD
= 3.3V
+10%, -5%
unless otherwise specified)
-60
Symbol Parameter Min Max Units Notes
t
RC
Read Cycle Time 150 - ns
t
CE
Chip Enable Access Time - 60 ns
t
A
A
Address Access Time - 150 ns
t
OH
Output Hold Time 50 - ns
t
AAP
Page Mode Address Access Time - 25 ns
t
OHP
P age Mod e Output Hold Time 5 - ns
t
C
A
Chip Enable Active Time 60 - ns
t
PC
Precharge Time 90 - ns
t
AS
Address Setup T ime (to /CE low) 5 - ns
t
AH
Address Hold Time (/CE-controlled) 60 - ns
t
OE
Output Enable Access T ime - 10 ns
t
HZ
Chip Enable to Outp ut High-Z - 15 ns 1
t
OHZ
Output Enable Hi gh to Output High-Z - 15 ns 1
Write Cycle AC Parameters
(T
A
= -20
° C to +85
° C, V
DD
= 3.3V
+10%, -5%
unless otherwise specified)
-60
Symbol Parameter Min Max Units Notes
t
WC
Write Cycle Time 150 - ns
t
C
A
Chip Enable Active Time 60 - ns
t
CW
Chip Enable to Wr ite Enable High 60 - ns
t
PC
Precharge Time 90 - ns
t
PWC
Page Mode Write Enable Cycle Time 30 - ns
t
WP
Write Enable Pulse Width 15 - ns
t
AS
Address Setup Time (to /CE low) 5 - ns
t
AH
Address Hold Time (/CE-controlled) 60 - ns
t
ASP
Page Mode Address Setup Time (to /WE low) 5 - ns
t
AHP
Page Mode Address Hold Time (to /WE low) 15 - ns
t
WLC
Write Enable Low to /CE High 25 - ns
t
WL
A
Write Enable Low to A(16:3) Change 25 - ns
t
AWH
A(16:3) Change to Write Enable High 150 - ns
t
DS
Data Input Setup Time 20 - ns
t
DH
Data Input Hold Time 0 - ns
t
WZ
Write Enable Low to Output High Z - 15 ns 1
t
WX
Write Enable High to Output Driven 5 - ns 1
t
WS
Write Enable to /CE Low Setup Time 0 - ns 1,2
t
WH
Write Enable to /CE High Hold Time 0 - ns 1,2
Notes
1 This parameter is characterized but not 100% tested.
2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs.
Power Cycle Timing
(T
A
= -20
° C to +85°
C, V
DD
= 3.3V
+10%, -5%
unless otherwise specified)
Symbol Parameter Min Max Units Notes
t
PULV
Power Up to /LVL Inactive Time (V
TP
to /LVL high) 0 5 ms
t
PDLV
Power Down to /LVL Active Time ( V
TP
to /LVL low) 0 15 µs
t
PU
P o wer Up (/LVL high) to First Access Time 0 - µs
t
PD
Last Access (/CE high) to Power Down (V
DD
min) 0 - µs
t
VR
V
DD
Rise Time 50 - µs/V 1
t
VF
V
DD
Fall Time 100 - µs/V 1
Notes
1 Slope measured at an y point on V
DD
waveform.
NOT RECOMMENDED
FOR NEW DESIGNS
Replacement: FM28V100
FM20L08 - Extended Temp.
Rev. 1.91
Aug. 2009 Page 8 of 12
Data Retention
(V
DD
= 3.3V
+10%, -5%
)
Parameter Min Units Notes
Data Retention 10 Years
Capacitance
(T
A
= 25° C , f=1 MHz, V
DD
= 3.3V)
Symbol Parameter Max Units Notes
C
I/O
Input/Output Capacitance (DQ) 8 pF
C
IN
Input Capacitance 6 pF
AC Test Conditions
Input Pulse Levels 0 to 3V
Input rise and fall times 3 ns
Input and outp ut timing levels 1.5 V
Output Load Capacitance 30 pF
Read Cycle Timing 1 (/CE low, /OE low)
A(16:0)
DQ(7:0)
t
RC
t
OH
t
AA
t
OH
Read Cycle Timing 2 (/CE-controlled)
CE
A(16:0)
OE
DQ(7:0)
t
AS
t
CE
t
CA
t
PC
t
OE
t
OHZ
t
HZ
t
AH
NOT RECOMMENDED
FOR NEW DESIGNS
Replacement: FM28V100
FM20L08 - Extended Temp.
Rev. 1.91
Aug. 2009 Page 9 of 12
Page Mode Read Cycle Timing
Although sequential column a ddressing is shown, it is not required.
Write Cycle Timing 1 (/WE-Controlled, /OE low)
Write Cycle Timing 2 (/CE-Controlled)
NOTE: See W r ite Operation section for detailed description (page 4).
NOT RECOMMENDED
FOR NEW DESIGNS
Replacement: FM28V100
FM20L08 - Extended Temp.
Rev. 1.91
Aug. 2009 Page 10 of 12
Write Cycle Timing 3 (/CE low)
Page Mode Write Cycle Timing
CE
A(16:3)
WE
tCA tPC
DQ(7:0)
tCW
A(2:0) Col 0 Col 1
Data 0
Col 2
tAS
tDS
Data 1
tWP
tDH
Data 2
OE
tAHP
tPWC
tWLC
tASP
tAH
Although sequential column a ddressing is shown, it is not required.
Power Cycle Timing
NOT RECOMMENDED
FOR NEW DESIGNS
Replacement: FM28V100
FM20L08 - Extended Temp.
Rev. 1.91
Aug. 2009 Page 11 of 12
Mechanical Drawing
32-pin Shrunk TSOP-I ( 8.0 x 13.4 mm)
All dimensions in millimeters
TSOP Package Marking Scheme
Legend:
XXXXXX= part number, SP= speed/package/temp (blank=ind., C=extended)
R=rev cod e, YY=year, WW=work week, LLLLLL= lot co de
Examples: “Green” TSOP package, Extended temp,
B rev., Year 2006, Work Week 44, Lot 60011TG
RAMTRON
FM20L08-60TGC
B064460011TG
RAMTRON
XXXXXXX-SP
RYYWWLLLLLL
NOT RECOMMENDED
FOR NEW DESIGNS
Replacement: FM28V100
FM20L08 - Extended Temp.
Rev. 1.91
Aug. 2009 Page 12 of 12
Revision History
Revision
Date
Summary
0.6 1/30/04 Added Vdd fall time spec. Changed Power Cycle Timing diagram. Added t
AWH
Write Timing spec. Added typ value to V
TP
in DC Operating table. Changed
software write-pr otect scheme. Changed /LVL to O utput-only pin. Modified
Block Diagram, P in Description and DC Operating tables. Modified package
drawing title.
0.61 5/20/04 Changed t
WX
, t
AAP
, and t
AWH
specs. Added t
AH
to Write Cycle parameters table.
Changed input rise/fall time AC test condition. Changed t
VF
units. Added
“green” package.
0.7 9/3/04 Reduced to one sp eed grade and changed to -60 speed grade. Supply voltage
3.3V +10%, -5%. Temp range 0 to +85C.
0.8 12/20/04 Temp range 0 to +70C. Changed AC timing parameters. Changed part
number/order i ng information.
1.0 3/25/05 Changed to Preliminary status.
1.1 5/23/05 Added “green” packaging option. Added marking scheme.
1.2 6/3/05 Removed –S packaging option.
1.3 6/13/05 Changed address setup and I
DD
specs.
1.4 7/11/05 Added t
VR
parameter. Added note about /CE high during power cycles.
Modified Power Cycle timing diagram and added timing parameters. Removed
references to the use of /LVL as a system reset signal.
1.5 10/18/05 Changed I
SB
. Changed V
TP
limits. Added note to Power Cycle Timing table.
Rewrote text describing use of pullup resistor.
1.6 2/9/06 Order device with or without software WP. Changed t
PULV
to 5ms. Added
ESD and MSL ratings.
1.7 6/16/06 Extended upper temperature limit from 70
°
C to 85
°
C. Devices with date codes
0605 through 0620 comply with this datasheet revision.
1.8 8/21/06 Extended lower temperature limit from 0
°
C to -20
°
C. Changed I
DD
and I
SB
specs. Updated ESD ratings. Removed Note 2 from Power Cycle Timing table.
Devices with date codes 0624 and beyond comply with this datasheet revision.
1.81 4/9/07 Changed Package Marking Scheme. Updated ESD machine model and MSL
ratings.
1.82 5/10/07 Added pcb footprint to package drawing.
1.9 5/6/2008 Removed –TGC1 (software write protect) ordering number.
1.91 8/5/2009 Not Recommended for New Designs. Last time buy Nov. 2009. As a
replacement, use the FM28V100 device.
