Photometric Front Ends ADPD105/ADPD106/ADPD107 Data Sheet FEATURES GENERAL DESCRIPTION Multifunction photometric front end Fully integrated AFE, ADC, LED drivers, and timing core Enables best-in-class ambient light rejection capability without the need for photodiode optical filters Three 370 mA LED drivers Flexible, multiple, short LED pulses per optical sample 20-bit burst accumulator enabling 20 bits per sample period On-board sample to sample accumulator, enabling up to 27 bits per data read Low power operation SPI, I2C interface, and 1.8 V analog/digital core Flexible sampling frequency ranging from 0.122 Hz to 3820 Hz FIFO data operation The ADPD105/ADPD106/ADPD107 are highly efficient, photometric front ends, each with an integrated 14-bit analogto-digital converter (ADC) and a 20-bit burst accumulator that works with flexible light emitting diode (LED) drivers. The accumulator is designed to stimulate an LED and measure the corresponding optical return signal. The data output and functional configuration occur over a 1.8 V I2C interface on the ADPD105 or SPI on the ADPD106 and ADPD107. The control circuitry includes flexible LED signaling and synchronous detection. APPLICATIONS Couple the ADPD105/ADPD106/ADPD107 with a low capacitance photodiode of <100 pF for optimal performance. The ADPD105/ADPD106/ADPD107 can be used with any LED. The ADPD105 is available in a 2.46 mm x 1.4 mm WLCSP and a 4 mm x 4 mm LFCSP. The SPI only versions, ADPD106 and ADPD107, are available in a 2.46 mm x 1.4 mm WLCSP. Wearable health and fitness monitors Clinical measurements, for example, SpO2 Industrial monitoring Background light measurements Rev. A The analog front end (AFE) features best-in-class rejection of signal offset and corruption due to modulated interference commonly caused by ambient light. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADPD105/ADPD106/ADPD107 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 LED Driver Pins and LED Supply Voltage.............................. 31 Applications ....................................................................................... 1 LED Driver Operation ............................................................... 31 General Description ......................................................................... 1 Determining the Average Current ........................................... 31 Revision History ............................................................................... 3 Determining CVLED ..................................................................... 32 Functional Block Diagrams ............................................................. 4 LED Inductance Considerations .............................................. 32 Specifications..................................................................................... 6 Recommended Start-Up Sequence .......................................... 33 Temperature and Power Specifications ..................................... 6 Reading Data............................................................................... 33 Performance Specifications ......................................................... 7 Clocks and Timing Calibration ................................................ 34 Analog Specifications ................................................................... 8 Optional Timing Signals Available on GPIO0 and GPIO1 .. 35 Digital Specifications ................................................................... 9 Calculating Current Consumption .......................................... 37 Timing Specifications ................................................................ 10 Optimizing SNR per Watt ......................................................... 38 Absolute Maximum Ratings.......................................................... 12 Thermal Resistance .................................................................... 12 Optimizing Power by Disabling Unused Channels and Amplifiers .................................................................................... 39 Recommended Soldering Profile ............................................. 12 TIA ADC Mode .......................................................................... 40 ESD Caution ................................................................................ 12 Digital Integrate Mode............................................................... 42 Pin Configurations and Function Descriptions ......................... 13 Pulse Connect Mode .................................................................. 45 Typical Performance Characteristics ........................................... 17 Synchronous ECG and PPG Measurement Using TIA ADC Mode ............................................................................................ 45 Theory of Operation ...................................................................... 19 Introduction ................................................................................ 19 Dual Time Slot Operation ......................................................... 19 Time Slot Switch ......................................................................... 20 Adjustable Sampling Frequency ............................................... 22 State Machine Operation ........................................................... 23 Normal Mode Operation and Data Flow ................................ 23 AFE Operation ............................................................................ 25 AFE Integration Offset Adjustment ......................................... 25 I2C Serial Interface...................................................................... 27 Register Listing ............................................................................... 48 LED Control Registers ............................................................... 52 AFE Global Configuration Registers ....................................... 54 System Registers ......................................................................... 59 ADC Registers ............................................................................ 63 Data Registers ............................................................................. 64 Required Start-Up Load Procedure ......................................... 64 Outline Dimensions ....................................................................... 65 Ordering Guide .......................................................................... 66 SPI Port ........................................................................................ 28 Typical Connection Diagram ................................................... 30 Rev. A | Page 2 of 66 Data Sheet ADPD105/ADPD106/ADPD107 REVISION HISTORY 1/2017--Rev. 0 to Rev. A Added ADPD106................................................................. Universal Changes to Features Section and General Description Section ....... 1 Changes to Figure 1........................................................................... 4 Added Figure 2; Renumbered Sequentially ................................... 5 Changes to Table 2 ............................................................................ 6 Changes to Table 9 ..........................................................................12 Added Figure 6 and Table 11; Renumbered Sequentially ..........13 Added Figure 8 and Table 13 .........................................................15 Changes to ADPD105 LFCSP Input Configurations Section ..............................................................................................20 Added Register 0x14, PD1 to PD8 Input Configurations Section and Figure 19 to Figure 21 .............................................................20 Added Table 16 and WLCSP Input Configurations Section ..... 21 Changes to Register 0x14, PD1 to PD4 Input Configurations Section .............................................................................................. 21 Changes to Typical Connection Diagram Section ..................... 30 Added Figure 37 and Table 22 ....................................................... 31 Added Measuring Voltages Using the Current Input Section, Figure 52, and Figure 53 ................................................................. 47 Changes to Table 28 ........................................................................ 48 Updated Outline Dimensions........................................................ 65 Changes to Ordering Guide ........................................................... 66 7/2016--Revision 0: Initial Version Rev. A | Page 3 of 66 ADPD105/ADPD106/ADPD107 Data Sheet FUNCTIONAL BLOCK DIAGRAMS AVDD PDC TIME SLOT SWITCH DVDD ANALOG BLOCK AFE: SIGNAL CONDITIONING PD1-2 TIA BPF 1 INTEGRATOR VBIAS ADPD105/ ADPD106/ ADPD107 WLCSP VERSIONS VREF AFE: SIGNAL CONDITIONING TIA BPF 14-BIT ADC VBIAS AFE: SIGNAL CONDITIONING PD3-4 TIA PD3-4 ON ADPD105/ ADPD107 ONLY BPF 1 INTEGRATOR AFE CONFIGURATION TIME SLOT B DATA GPIO0 A GPIO1 B VBIAS AFE: SIGNAL CONDITIONING TIA 1F TIME SLOT A DATA 1 INTEGRATOR BPF SLOT SELECT DIGITAL DATAPATH AND INTERFACE CONTROL 1 INTEGRATOR VBIAS MOSI MISO SCLK CS SDA LEDX3 LED3 LEDX2 LED2 LED3 DRIVER LED3 LEVEL AND TIMING CONTROL LED2 DRIVER LED2 LEVEL AND TIMING CONTROL LED1 DRIVER LED1 LEVEL AND TIMING CONTROL LEDX1 VLED ADPD105 ONLY DGND AGND LGND 14693-001 LED1 SCL ADPD106/ ADPD107 ONLY Figure 1. Block Diagram for ADPD105/ADPD106/ADPD107 WLCSP (Chip Scale Package) Versions Rev. A | Page 4 of 66 Data Sheet ADPD105/ADPD106/ADPD107 AVDD PDC TIME SLOT SWITCH ANALOG BLOCK AFE: SIGNAL CONDITIONING PD1 PD5 DVDD TIA BPF ADPD105 LFCSP 1 INTEGRATOR VBIAS VREF AFE: SIGNAL CONDITIONING PD2 TIA PD6 BPF 14-BIT ADC VBIAS AFE: SIGNAL CONDITIONING PD3 TIA PD7 BPF 1 INTEGRATOR AFE: SIGNAL CONDITIONING TIA PD8 AFE CONFIGURATION TIME SLOT B DATA GPIO0 A GPIO1 B VBIAS PD4 1F TIME SLOT A DATA 1 INTEGRATOR BPF SLOT SELECT DIGITAL DATAPATH AND INTERFACE CONTROL 1 INTEGRATOR VBIAS SDA SCL LEDX3 LED3 LEDX2 LED2 LED3 DRIVER LED3 LEVEL AND TIMING CONTROL LED2 DRIVER LED2 LEVEL AND TIMING CONTROL LED1 DRIVER LED1 LEVEL AND TIMING CONTROL DGND LEDX1 VLED LGND AGND 14693-105 LED1 Figure 2. Block Diagram for ADPD105 LFCSP Version Rev. A | Page 5 of 66 ADPD105/ADPD106/ADPD107 Data Sheet SPECIFICATIONS TEMPERATURE AND POWER SPECIFICATIONS Table 1. Operating Conditions Parameter TEMPERATURE RANGE Operating Range Storage Range POWER SUPPLY VOLTAGES VDD Test Conditions/Comments Min Typ -40 -65 Applied at the AVDD and DVDD pins 1.7 1.8 Max Unit +85 +150 C C 1.9 V AVDD = DVDD = 1.8 V, TA = 25C, unless otherwise noted. Table 2. Current Consumption Parameter POWER SUPPLY (VDD) CURRENT VDD Supply Current1 Symbol SLOTx_LED_OFFSET = 25 s; LED_PERIOD =19 s; LED peak current = 25 mA, single-channel mode 100 Hz data rate; Time Slot A only 100 Hz data rate; Time Slot B only 100 Hz data rate; both Time Slot A and Time Slot B 100 Hz data rate; Time Slot A only 100 Hz data rate; Time Slot B only 100 Hz data rate; both Time Slot A and Time Slot B 1 Pulse 10 Pulses Peak VDD Supply Current (1.8 V) 4-Channel Operation 1-Channel Operation Standby Mode Current VLED SUPPLY CURRENT2 Average Supply Current VLEDA or VLEDB 1 Pulse 10 Pulses 1 2 Test Conditions/Comments Min Typ Max Unit 92 75 119 175 155 281 A A A A A A 9.3 4.5 0.3 mA mA A 3.75 7.5 15 38 75 150 A A A A A A IVDD_PEAK IVDD_STANDBY Peak LED current = 25 mA; LED pulse width = 3 s 50 Hz data rate 100 Hz data rate 200 Hz data rate 50 Hz data rate 100 Hz data rate 200 Hz data rate VDD is the voltage applied at the AVDD and DVDD pins. VLED applies to the external LED supply voltage for any given LED being driven by the ADPD105/ADPD106/ADPD107 LED drivers under the listed conditions. Rev. A | Page 6 of 66 Data Sheet ADPD105/ADPD106/ADPD107 PERFORMANCE SPECIFICATIONS AVDD = DVDD = 1.8 V, TA = full operating temperature range, unless otherwise noted. Table 3. Parameter DATA ACQUISITION Resolution Resolution/Sample Resolution/Data Read LED DRIVER LED Current Slew Rate1 Rise Fall LED Peak Current Driver Compliance Voltage LED PERIOD Sampling Frequency3 CATHODE PIN (PDC) VOLTAGE During All Sampling Periods During Slot A Sampling During Slot B Sampling During Sleep Periods Test Conditions/Comments Min Typ Max Unit Single pulse 64 to 255 pulses 64 to 255 pulses and sample average = 128 14 20 27 Bits Bits Bits Slew rate control setting = 0; TA = 25C; ILED = 70 mA Slew rate control setting = 7; TA = 25C; ILED = 70 mA Slew rate control setting = 0, 1, 2; TA = 25C; ILED = 70 mA Slew rate control setting = 6, 7; TA = 25C; ILED = 70 mA LED pulse enabled Voltage above ground required for LED driver operation AFE width = 4 s2 AFE width = 3 s Time Slot A only; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 s; SLOTA_ LED_PERIOD = 19 s Time Slot B only; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 s; SLOTA_ LED_PERIOD = 19 s Both time slots; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 s; SLOTA_ LED_PERIOD = 19 s Time Slot A only; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 s; SLOTA_ LED_PERIOD = 19 s Time Slot B only; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 s; SLOTA_ LED_PERIOD = 19 s Both time slots; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 s; SLOTA_ LED_PERIOD = 19 s 240 1400 3200 4500 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 14 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x04 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x1 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x2 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x35 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x04 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x1 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x2 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x35 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x1 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x2 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x3 PHOTODIODE INPUT PINS/ ANODE VOLTAGE During All Sampling Periods During Sleep Periods 1 0.122 3230 mA/s mA/s mA/s mA/s mA V s s Hz 0.122 3820 Hz 0.122 1750 Hz 0.122 2257 Hz 0.122 2531 Hz 0.122 1193 Hz 370 0.6 19 17 1.8 1.3 1.8 1.3 1.55 0 1.8 1.3 1.55 0 1.8 1.3 1.8 1.3 1.55 0 V V V V V V V V V V V V V V V V 1.3 Cathode voltage V V LED inductance is negligible for these values. The effective slew rate slows with increased inductance. Minimum LED period = (2 x AFE width) + 5 s. 3 The maximum values in this specification are the internal ADC sampling rates in normal mode. The I2C read rates in some configurations may limit the output data rate. 4 This mode may induce additional noise and is not recommended unless absolutely necessary. The 1.8 V setting uses VDD, which contains greater amounts of differential voltage noise with respect to the anode voltage. A differential voltage between the anode and cathode injects a differential current across the capacitance of the photodiode of the magnitude of C x dV/dt. 5 This setting is not recommended for photodiodes because it causes a 1.3 V forward bias of the photodiode. 2 Rev. A | Page 7 of 66 ADPD105/ADPD106/ADPD107 Data Sheet ANALOG SPECIFICATIONS AVDD = DVDD = 1.8 V, TA = full operating temperature range, unless otherwise noted. Compensation of the AFE offset is explained in the AFE Operation section. Table 4. Parameter INPUT CAPACITANCE PULSED SIGNAL CONVERSIONS, 3 s WIDE LED PULSE1 ADC Resolution2 ADC Saturation Level Ambient Signal Headroom on Pulsed Signal PULSED SIGNAL CONVERSIONS, 2 s WIDE LED PULSE1 ADC Resolution2 ADC Saturation Level Ambient Signal Headroom on Pulsed Signal FULL SIGNAL CONVERSIONS3 TIA Saturation Level of Pulsed Signal and Ambient Level Test Conditions/Comments 4 s wide AFE integration; normal operation, Register 0x43/Register 0x45 = 0xADA5 Transimpedance amplifier (TIA) feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k 3 s wide AFE integration; normal operation, Register 0x43/Register 0x45 = 0xADA5 TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k Rev. A | Page 8 of 66 Min Typ Max 100 Unit pF 3.27 1.64 0.82 0.41 nA/LSB nA/LSB nA/LSB nA/LSB 26.8 13.4 6.7 3.35 A A A A 23.6 11.8 5.9 2.95 A A A A 4.62 2.31 1.15 0.58 nA/LSB nA/LSB nA/LSB nA/LSB 37.84 18.92 9.46 4.73 A A A A 12.56 6.28 3.14 1.57 A A A A 50.4 25.2 12.6 6.3 A A A A Data Sheet ADPD105/ADPD106/ADPD107 Parameter SYSTEM PERFORMANCE Total Output Noise Floor Test Conditions/Comments Min Normal mode; per pulse; per channel; no LED; photodiode capacitance (CPD) = 70 pF 25 k; referred to ADC input 25 k; referred to peak input signal for 2 s LED pulse 25 k; referred to peak input signal for 3 s LED pulse 25 k; saturation signal-to-noise ratio (SNR) per pulse per channel4 50 k; referred to ADC input 50 k; referred to peak input signal for 2 s LED pulse 50 k; referred to peak input signal for 3 s LED pulse 50 k; saturation SNR per pulse per channel4 100 k; referred to ADC input 100 k; referred to peak input signal for 2 s LED pulse 100 k; referred to peak input signal for 3 s LED pulse 100 k; saturation SNR per pulse per channel4 200 k; referred to ADC input 200 k; referred to peak input signal for 2 s LED pulse 200 k; referred to peak input signal for 3 s LED pulse 200 k; saturation SNR per pulse per channel4 DC Power Supply Rejection Ratio (DC PSRR) Typ Max Unit 1.0 4.6 3.3 78.3 LSB rms nA rms nA rms dB 1.2 2.8 2.0 76.6 1.7 1.9 1.4 73.6 2.75 1.6 1.1 69.5 -37 LSB rms nA rms nA rms dB LSB rms nA rms nA rms dB LSB rms nA rms nA rms dB dB 1 This saturation level applies to the ADC only and, therefore, includes only the pulsed signal. Any nonpulsatile signal is removed prior to the ADC stage. ADC resolution is listed per pulse when the AFE offset is correctly compensated per the AFE Operation section. If using multiple pulses, divide by the number of pulses. 3 This saturation level applies to the full signal path and, therefore, includes both the ambient signal and the pulsed signal. 4 The noise term of the saturation SNR value refers to the receive noise only and does not include photon shot noise or any noise on the LED signal itself. 2 DIGITAL SPECIFICATIONS DVDD = 1.7 V to 1.9 V, unless otherwise noted. Table 5. Parameter LOGIC INPUTS (GPIOx, SCL, SDA, SCLK, MOSI, CS) Input Voltage Level High Low Input Current Level High Low Input Capacitance LOGIC OUTPUTS Output Voltage Level High Low Output Voltage Level Low Output Current Level Low Symbol Test Conditions/Comments Min Typ Max Unit VIH VIL 0.7 x DVDD 3.6 0.3 x DVDD V V IIH IIL CIN -10 -10 +10 +10 A A pF VOH VOL VOL1 IOL 10 GPIOx, MOSI 2 mA high level output current 2 mA low level output current SDA 2 mA low level output current SDA VOL1 = 0.6 V Rev. A | Page 9 of 66 DVDD - 0.5 6 0.5 V V 0.2 x DVDD V mA ADPD105/ADPD106/ADPD107 Data Sheet TIMING SPECIFICATIONS Table 6. I2C Timing Specifications Parameter I2C PORT1 SCL Frequency Minimum Pulse Width High Low Start Condition Hold Time Setup Time SDA Setup Time SCL and SDA Rise Time Fall Time Stop Condition Setup Time Test Conditions/Comments See Figure 3 Min Typ Max 400 t1 t2 600 1300 ns ns t3 t4 t5 600 600 100 ns ns ns t6 t7 1000 300 t8 600 t5 t3 t3 SDA t6 t1 SCL t7 t4 Figure 3. I2C Timing Diagram Rev. A | Page 10 of 66 t8 ns ns ns Guaranteed by design. t2 Unit kHz 14693-002 1 Symbol Data Sheet ADPD105/ADPD106/ADPD107 Table 7. SPI Timing Specifications Parameter SPI PORT SCLK Frequency Minimum Pulse Width High Low CS Setup Time Symbol Test Conditions/Comments Min Typ fSCLK tSCLKPWH tSCLKPWL tCSS Max Unit 10 MHz 20 20 ns ns CS setup to SCLK rising edge 10 ns Hold Time tCSH CS hold from SCLK rising edge 10 ns Pulse Width High tCSPWH CS pulse width high 10 ns tMOSIS tMOSIH tMISOD MOSI setup to SCLK rising edge MOSI hold from SCLK rising edge MISO valid output delay from SCLK falling edge 10 10 MOSI Setup Time Hold Time MISO Output Delay ns ns 20 ns tCSH tCSS tSCLKPWH CS tCSPWH tSCLKPWL SCLK MOSI tMOSIH MISO tMISOD Figure 4. SPI Timing Diagram Rev. A | Page 11 of 66 14693-003 tMOSIS ADPD105/ADPD106/ADPD107 Data Sheet ABSOLUTE MAXIMUM RATINGS RECOMMENDED SOLDERING PROFILE Table 8. Figure 5 and Table 10 provide details about the recommended soldering profile. Rating -0.3 V to +2.2 V -0.3 V to +2.2 V -0.3 V to +2.2 V -0.3 V to +2.2 V -0.3 V to +3.6 V -0.3 V to +3.9 V -0.3 V to +3.9 V 150C CRITICAL ZONE TL TO TP tP TP RAMP-UP TL tL TSMAX TSMIN tS RAMP-DOWN PREHEAT 1500 V 500 V 100 V 14693-004 TEMPERATURE Parameter AVDD to AGND DVDD to DGND GPIO0 to DGND GPIO1 to DGND LEDXx to LGND SCL to DGND SDA to DGND Junction Temperature ESD Human Body Model (HBM) Charged Device Model (CDM) Machine Model (MM) t25C TO PEAK TIME Figure 5. Recommended Soldering Profile Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Table 9. Thermal Resistance Package Type CP-28-5 CB-16-18 CB-17-1 JA 54.9 60 60 Unit C/W C/W C/W Table 10. Recommended Soldering Profile Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time (TSMIN to TSMAX) (tS) TSMAX to TL Ramp-Up Rate Time Maintained Above Liquidous Temperature Liquidous Temperature (TL) Time (tL) Peak Temperature (TP) Time Within 5C of Actual Peak Temperature (tP) Ramp-Down Rate Time from 25C to Peak Temperature ESD CAUTION Rev. A | Page 12 of 66 Condition (Pb-Free) 3C/sec max 150C 200C 60 sec to 180 sec 3C/sec maximum 217C 60 sec to 150 sec +260 (+0/-5)C <30 sec 6C/sec maximum 8 minutes maximum Data Sheet ADPD105/ADPD106/ADPD107 23 LEDX1 22 NIC 26 LGND 25 LEDX2 24 LEDX3 28 SDA 27 SCL PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 21 NIC GPIO0 1 GPIO1 2 AGND 4 VREF 5 20 NIC 19 NIC ADPD105 18 NIC 17 NIC TOP VIEW (Not to Scale) AVDD 6 PD1 7 16 NIC PD7 14 PD5 12 PD6 13 PD4 10 PDC 11 PD2 PD3 8 9 15 PD8 NOTES 1. NIC = NOT INTERNALLY CONNECTED (NONBONDED PAD). THIS PIN CAN BE GROUNDED. 2. EXPOSED PAD (DIGITAL GROUND). CONNECT THE EXPOSED PAD TO GROUND. 14693-106 DVDD 3 Figure 6. 28-Lead LFCSP Pin Configuration (ADPD105) Table 11. 28-Lead LFCSP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 to 22 23 24 25 26 27 28 1 Mnemonic GPIO0 GPIO1 DVDD AGND VREF AVDD PD1 PD2 PD3 PD4 PDC PD5 PD6 PD7 PD8 NIC LEDX1 LEDX3 LEDX2 LGND SCL SDA EPAD (DGND) Type1 DIO DIO S S REF S AI AI AI AI AO AI AI AI AI R AO AO AO S DI DIO S Description General-Purpose Input/Output (I/O). This pin is used for interrupts and various clocking options. General-Purpose I/O. This pin is used for interrupts and various clocking options. 1.8 V Digital Supply. Analog Ground. Internally Generated ADC Voltage Reference. Buffer this pin with a 1 F capacitor to AGND. 1.8 V Analog Supply. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Common Cathode Bias. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Current Input (Anode). If not in use, leave this pin floating. Photodiode Current Input (Anode). If not in use, leave this pin floating. Not Internally Connected (Nonbonded Pad). This pin can be grounded. LED Driver 1 Current Sink. If not in use, leave this pin floating. LED Driver 3 Current Sink. If not in use, leave this pin floating. LED Driver 2 Current Sink. If not in use, leave this pin floating. LED Driver Ground. I2C Clock Input. I2C Data Input/Output. Exposed Pad (Digital Ground). Connect the exposed pad to ground. DIO means digital input/output, S means supply, REF means voltage reference, AI means analog input, AO means analog output, R means reserved, and DI means digital input. Rev. A | Page 13 of 66 ADPD105/ADPD106/ADPD107 Data Sheet ADPD105 TOP VIEW, BALL SIDE DOWN (Not to Scale) 2 A LGND LEDX2 B LEDX3 LEDX1 SDA C SCL GPIO0 DVDD DGND AGND D 3 E GPIO1 VREF AVDD F PD1-2 PDC PD3-4 14693-005 1 Figure 7. ADPD105 Pin Configuration Table 12. ADPD105 Pin Function Descriptions Pin No. A1 A2 B1 B2 B3 C1 C2 C3 D2 D3 E1 E2 E3 F1 Mnemonic LGND LEDX2 LEDX3 LEDX1 SDA SCL GPIO0 DVDD DGND AGND GPIO1 VREF AVDD PD1-2 Type1 S AO AO AO DIO DI DIO S S S DIO REF S AI F2 F3 PDC PD3-4 AO AI 1 Description LED Driver Ground. LED Driver 2 Current Sink. If not in use, leave this pin floating. LED Driver 3 Current Sink. If not in use, leave this pin floating. LED Driver 1 Current Sink. If not in use, leave this pin floating. I2C Data Input/Output (I/O). I2C Clock Input. General Purpose I/O. This pin is used for interrupts and various clocking options. 1.8 V Digital Supply. Digital Ground. Analog Ground. General Purpose I/O. This pin is used for interrupts and various clocking options. Internally Generated ADC Voltage Reference. Buffer this pin with a 1 F capacitor to AGND. 1.8 V Analog Supply. Photodiode Combined Current Input of Photodiode 1 (PD1) and Photodiode 2 (PD2). If not in use, leave this pin floating. Photodiode Common Cathode Bias. Photodiode Combined Current Input of Photodiode 3 (PD3) and Photodiode 4 (PD4). If not in use, leave this pin floating. S means supply, AO means analog output, DIO means digital input/output, DI means digital input, REF means voltage reference, AI means analog input, and AO means analog output. Rev. A | Page 14 of 66 Data Sheet ADPD105/ADPD106/ADPD107 ADPD106 TOP VIEW, BALL SIDE DOWN (Not to Scale) 2 A LEDX2 LGND B LEDX3 LEDX1 GPIO0 C GPIO1 MISO DGND MOSI SCLK D 3 E CS AGND VREF F AVDD PDC PD1-2 14693-102 1 Figure 8. 16-Ball WLCSP Pin Configuration (ADPD106) Table 13. 16-Ball WLCSP Pin Function Descriptions Pin No. A1 A2 B1 B2 B3 C1 C2 C3 D2 D3 E1 E2 E3 F1 F2 F3 1 Mnemonic LEDX2 LGND LEDX3 LEDX1 GPIO0 GPIO1 MISO DGND MOSI SCLK CS AGND VREF AVDD PDC PD1-2 Type1 AO S AO AO DIO DIO DO S DI DI DI S REF S AO AI Description LED Driver 2 Current Sink. If not in use, leave this pin floating. LED Driver Ground LED Driver 3 Current Sink. If not in use, leave this pin floating. LED Driver 1 Current Sink. If not in use, leave this pin floating. General Purpose I/O. This pin is used for interrupts and various clocking options. General Purpose I/O. This pin is used for interrupts and various clocking options. SPI Data Output. Digital Ground. SPI Data Input. SPI Clock Input. SPI Chip Select, Active Low. Analog Ground. Internally Generated ADC Voltage Reference. Buffer this pin with a 1 F capacitor to AGND. 1.8 V Analog Supply. Photodiode Common Cathode Bias. Photodiode Combined Current Input of PD1 and PD2. If not in use, leave this pin floating. AO means analog output, S means supply, DIO means digital input/output, DO means digital output, DI means digital input, REF means voltage reference, and AI means analog input. Rev. A | Page 15 of 66 ADPD105/ADPD106/ADPD107 Data Sheet ADPD107 TOP VIEW, BALL SIDE DOWN (Not to Scale) 2 3 A LEDX2 LGND B LEDX3 LEDX1 GPIO0 C GPIO1 MISO DGND D CS MOSI SCLK E AVDD AGND VREF F PD1-2 PDC PD3-4 14693-006 1 Figure 9. ADPD107 Pin Configuration Table 14. ADPD107 Pin Function Descriptions Pin No. A1 A2 B1 B2 B3 C1 C2 C3 D1 D2 D3 E1 E2 E3 F1 F2 F3 1 Mnemonic LEDX2 LGND LEDX3 LEDX1 GPIO0 GPIO1 MISO DGND CS MOSI SCLK AVDD AGND VREF PD1-2 PDC PD3-4 Type1 AO S AO AO DIO DIO DO S DI DI DI S S REF AI AO AI Description LED Driver 2 Current Sink. If not in use, leave this pin floating. LED Driver Ground. LED Driver 3 Current Sink. If not in use, leave this pin floating. LED Driver 1 Current Sink. If not in use, leave this pin floating. General Purpose I/O. This pin is used for interrupts and various clocking options. General Purpose I/O. This pin is used for interrupts and various clocking options. Master Input, Slave Output. Digital Ground. SPI Chip Select. Active low. Master Output, Slave Input. SPI Clock Input. 1.8 V Analog Supply. Analog Ground. Internally Generated ADC Voltage Reference. Buffer this pin with a 1 F capacitor to AGND. Photodiode Combined Current Input of PD1 and PD2. If not in use, leave this pin floating. Photodiode Common Cathode Bias. Photodiode Combined Current Input of PD3 and PD4. If not in use, leave this pin floating. AO means analog output, S means supply, DIO means digital input/output, DO means digital output, DI means digital input, REF means voltage reference, and AI means analog input. Rev. A | Page 16 of 66 Data Sheet ADPD105/ADPD106/ADPD107 TYPICAL PERFORMANCE CHARACTERISTICS 70 3.0 50 40 30 20 14693-007 10 0 32 33 34 35 36 37 38 FREQUENCY (Hz) 39 40 NOISE vs. NUMBER OF CHANNELS 2.0 SQUARE ROOT OF CHANNEL COUNT 1.5 1.0 0.5 0 41 1 3.0 RTI NOISE (nA RMS) 50 40 30 20 10 32.0 32.5 33.0 33.5 34.0 34.5 FREQUENCY (Hz) 35.0 35.5 2.5 2.0 1.5 1.0 14693-011 0.5 14693-008 0 0 0 36.0 4.0 50 100 150 200 TIA GAIN (k) Figure 11. 32 MHz Clock Frequency Distribution (Default Settings, Before User Calibration: Register 0x4D = 0x0098) Figure 14. Referred to Input (RTI) Noise vs. TIA Gain 400 NRMS = 0.24 x CPD + 0.81 3.5 LED COARSE SETTING = 0xF DRIVER CURRENT (mA) 350 200k 3.0 NRMS = 0.11 x CPD + 0.97 2.5 100k 2.0 NRMS = 0.04 x CPD + 1.13 50k 1.5 25k NRMS = 0.02 x CPD + 1.16 1.0 300 250 200 150 100 14693-012 LED COARSE SETTING = 0x0 2.6 2.4 2.2 2.0 PHOTODIODE CAPACITANCE (pF) 1.8 0 160 1.6 140 1.4 120 1.2 100 1.0 80 0.8 60 0.6 40 0.4 20 0 0 50 0.2 0.5 14693-009 RMS NOISE (LSB) 4 3.5 60 0 2 3 NUMBER OF CHANNELS Figure 13. Noise Multiple of Channel Sum vs. Number of Channels Figure 10. 32 kHz Clock Frequency Distribution (Default Settings, Before User Calibration: Register 0x4B = 0x2612) PERCENT OF PARTS 2.5 14693-010 NOISE MULTIPLE OF CHANNEL SUM PERCENT OF PARTS 60 LED DRIVER VOLTAGE (V) Figure 12. RMS Noise vs. Photodiode Capacitance Figure 15. LED Driver Current vs. LED Driver Voltage at Various Coarse Settings Rev. A | Page 17 of 66 ADPD105/ADPD106/ADPD107 Data Sheet 360 45 340 DRIVER CURRENT (mA) DRIVER CURRENT (mA) 40 35 30 320 300 280 260 25 20 0 1 2 3 14693-014 14693-013 240 220 0 4 5 6 7 8 9 10 11 12 13 14 15 LED FINE SETTING, REGISTER 0x25 Figure 16. LED Driver Current vs. LED Fine Setting (Coarse Setting = 0x0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LED FINE SETTING, REGISTER 0x25 Figure 17. LED Driver Current vs. LED Fine Setting (Coarse Setting = 0xF) Rev. A | Page 18 of 66 Data Sheet ADPD105/ADPD106/ADPD107 THEORY OF OPERATION INTRODUCTION DUAL TIME SLOT OPERATION The ADPD105/ADPD106/ADPD107 operate as a complete optical transceiver stimulating up to three LEDs and measuring the return signal on up to two separate current inputs. The core consists of a photometric front end coupled with an ADC, digital block, and three independent LED drivers. The core circuitry stimulates the LEDs and measures the return in the analog block through one to eight photodiode inputs, storing the results in discrete data locations. The two inputs can be configured to drive four simultaneous input channels. Data can be read directly by a register, or through a FIFO. This highly integrated system includes an analog signal processing block, digital signal processing block, I2C communication interface on the ADPD105 or an SPI port on the ADPD107, and programmable pulsed LED current sources. The ADPD105/ADPD106/ADPD107 operate in two independent time slots, Time Slot A and Time Slot B, which are carried out sequentially. The entire signal path from LED stimulation to data capture and processing is executed during each time slot. Each time slot has a separate datapath that uses independent settings for the LED driver, AFE setup, and the resulting data. Time Slot A and Time Slot B operate in sequence for every sampling period, as shown in Figure 18. The LED driver is a current sink and is agnostic to LED supply voltage and LED type. The photodiode (PDx) inputs can accommodate any photodiode with an input capacitance of less than 100 pF. The ADPD105/ADPD106/ADPD107 are designed to produce a high SNR for relatively low LED power while greatly reducing the effect of ambient light on the measured signal. tB (s) = SLOTB_LED_OFFSET + nB x SLOTB_LED_PERIOD The timing parameters are defined as follows: tA (s) = SLOTA_LED_OFFSET + nA x SLOTA_LED_PERIOD where nA is the number of pulses for Time Slot A (Register 0x31, Bits[15:8]). where nB is the number of pulses for Time Slot B (Register 0x36, Bits[15:8]). Calculate the LED period using the following equation: LED_PERIOD, minimum = 2 x AFE_WIDTH + 11 t1 and t2 are fixed and based on the computation time for each slot. If a slot is not in use, these times do not add to the total active time. Table 15 defines the values for these LED and sampling time parameters. ACTIVE ACTIVE tA nA PULSES t1 tB t2 nB PULSES TIME SLOT A 14693-015 SLEEP TIME SLOT B 1/fSAMPLE Figure 18. Time Slot Timing Diagram Table 15. LED Timing and Sample Timing Parameters Parameter SLOTA_LED_OFFSET1 SLOTB_LED_OFFSET1 SLOTA_LED_PERIOD2 SLOTB_LED_PERIOD2 t1 t2 tSLEEP 1 2 Register 0x30 0x35 0x31 0x36 Bits [7:0] [7:0] [7:0] [7:0] Test Conditions/Comments Delay from power-up to LEDA rising edge Delay from power-up to LEDB rising edge Time between LED pulses in Time Slot A; SLOTx_AFE_WIDTH = 4 s Time between LED pulses in Time Slot B; SLOTx_AFE_WIDTH = 4 s Compute time for Time Slot A Compute time for Time Slot B Sleep time between sample periods Min 23 23 19 19 68 20 222 Setting the SLOTx_LED_OFFSET below the specified minimum value may cause failure of ambient light rejection for large photodiodes. Setting the SLOTx_LED_PERIOD below the specified minimum value can cause invalid data captures. Rev. A | Page 19 of 66 Typ Max 63 63 63 63 Unit s s s s s s s ADPD105/ADPD106/ADPD107 Data Sheet TIME SLOT SWITCH PD1 ADPD105 LFCSP Input Configurations Up to eight photodiodes (PD1 to PD8) can be connected to the ADPD105 in the LFCSP package. The photodiode anodes are connected to the PD1 to PD8 input pins; the photodiode cathodes are connected to the cathode pin, PDC. The anodes are assigned in three different configurations depending on the settings of Register 0x14 (see Figure 22, Figure 23, and Figure 21). A switch sets which photodiode group is connected during Time Slot A and Time Slot B. See Table 17 for the time slot switch registers. It is important to leave any unused inputs floating for proper operation of the devices. The photodiode inputs are current inputs and as such, these pins are also considered to be voltage outputs. Tying these inputs to a voltage may saturate the analog block. CH1 PD2 PD3 CH2 PD4 PD5 CH3 PD6 PD7 Register 0x14, PD1 to PD8 Input Configurations CH4 PD1 PD8 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 4 REGISTER 0x14[7:4] = 4 14693-110 CH1 PD2 Figure 20. PD5 to PD8 Connection PD3 PD1 CH2 PD4 CH1 PD2 PD5 PD3 CH3 PD6 CH2 PD4 PD7 PD5 CH4 PD8 CH3 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 5 REGISTER 0x14[7:4] = 5 14693-109 PD6 PD7 Figure 19. PD1 to PD4 Connection CH4 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 1 REGISTER 0x14[7:4] = 1 14693-111 PD8 Figure 21. 2 to 1 PD Current Summation Rev. A | Page 20 of 66 Data Sheet ADPD105/ADPD106/ADPD107 Table 16. Time Slot Switch (Register 0x14) Address 0x14 Bits [11:8] Name SLOTB_PD_SEL [7:4] SLOTA_PD_SEL Description Selects connection of photodiode for Time Slot B as shown in Figure 22, Figure 23, and Figure 21. 0x0: inputs are floating in Time Slot B. 0x1: all PDx pins (PD1 to PD8) are connected during Time Slot B. 0x4: PD5 to PD8 are connected during Time Slot B. 0x5: PD1 to PD4 are connected during Time Slot B. Other: reserved. Selects connection of photodiode for Time Slot A as shown in Figure 22, Figure 23, and Figure 21. 0x0: inputs are floating in Time Slot A. 0x1: all PDx pins (PD1 to PD8) are connected during Time Slot A. 0x4: PD5 to PD8 are connected during Time Slot A. 0x5: PD1 to PD4 are connected during Time Slot A. Other: reserved. WLCSP Input Configurations Up to two photodiodes can be connected to four channels of the ADPD105 and ADPD107 WLCSP models. The ADPD106 accommodates a single photodiode that can be connected to Channel 1 and Channel 2. The photodiode anodes are connected to the PD1-2 and PD3-4 input pins; the photodiode cathodes are connected to the cathode pin, PDC. The anodes are assigned in two different configurations depending on the settings of Register 0x14 (see Figure 22 and Figure 23). PD1-2 CH1 CH2 Register 0x14, PD1 to PD4 Input Configurations Figure 22 shows the configuration where each of the PD inputs is connected to two channels. This configuration is the high dynamic range mode used for large photodiode currents. Figure 23 shows the configuration where each of the inputs to the device is connected to a single channel. This mode allows the user to maximize SNR for situations where lower photodiode currents are expected. PD3-4 CH3 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 5 REGISTER 0x14[7:4] = 5 14693-016 CH4 A switch sets which photodiode group is connected during Time Slot A and Time Slot B. See Table 17 for the time slot switch registers. It is important to leave any unused inputs floating for proper operation of the devices. The photodiode inputs are current inputs and, as such, these pins are also considered to be voltage outputs. Tying these inputs to a voltage may saturate the analog block. Figure 22. PD1 to PD4 Connection Note that the ADPD106 only includes the options shown for the PD1-2 input pin shown in Figure 22 and Figure 23. PD1-2 CH1 PD3-4 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 1 REGISTER 0x14[7:4] = 1 14693-017 CH2 Figure 23. Current Summation--Two Photodiodes Summed into One Current Rev. A | Page 21 of 66 ADPD105/ADPD106/ADPD107 Data Sheet Table 17. Time Slot Switch (Register 0x14) Address 0x14 Bits [11:8] Name SLOTB_PD_SEL [7:4] SLOTA_PD_SEL Description Selects connection of photodiode for Time Slot B as shown in Figure 22 and Figure 23. 0x0: inputs are floating in Time Slot B. 0x1: PD1-2 is connected to Channel 1; PD3-4 is connected to Channel 2 during Time Slot B. 0x5: PD1-2 is connected to Channel 1 and Channel 2; PD3-4 is connected to Channel 3 and Channel 4 during Time Slot B. Other: reserved. Selects connection of photodiode for Time Slot A as shown in Figure 22 and Figure 23. 0x0: inputs are floating in Time Slot A. 0x1: PD1-2 is connected to Channel 1; PD3-4 is connected to Channel 2 during Time Slot A. 0x5: PD1-2 is connected to Channel 1 and Channel 2; PD3-4 is connected to Channel 3 and Channel 4 during Time Slot A. Other: reserved. ADJUSTABLE SAMPLING FREQUENCY Register 0x12 controls the sampling frequency setting of the ADPD105/ADPD106/ADPD107 and Register 0x4B, Bits[5:0] further tunes this clock for greater accuracy. The sampling frequency is governed by an internal 32 kHz sample rate clock that also drives the trans-ition of the internal state machine. The maximum sampling frequencies for some sample conditions are listed in Table 3. The maximum sample frequency for all conditions is determined by the following equation: fSAMPLE, MAX = 1/(tA + t1 + tB + t2 + tSLEEP, MIN) 3. 4. 5. The maximum frequency constraints also apply in this case. Providing an External 32kHz Clock where tSLEEP, MIN is the minimum sleep time required between samples. If a given time slot is not in use, elements from that time slot do not factor into the calculation. For example, if Time Slot A is not in use, tA and t1 do not add to the sampling period and the new maximum sampling frequency is calculated as follows: The ADPD105/ADPD106/ADPD107 have an option for the user to provide an external 32 kHz clock to the devices for system synchronization or for situations where a clock with better accuracy than the internal 32 kHz clock is required. The external 32 kHz clock is provided on the GPIO1 pin. To enable the 32 kHz external clock, use the following procedure at startup: 1. fSAMPLE, MAX = 1/(tB + t2 + tSLEEP, MIN) See the Dual Time Slot Operation section for the definitions of tA, t1, tB, and t2. 2. External Sync for Sampling The ADPD105/ADPD106/ADPD107 provide an option to use an external sync signal to trigger the sampling periods. This external sample sync signal can be provided either on the GPIO0 pin or the GPIO1 pin. This functionality is controlled by Register 0x4F, Bits[3:2]. When enabled, a rising edge on the selected input specifies when the next sample cycle occurs. When triggered, there is a delay of one to two internal sampling clock (32 kHz) cycles, and then the normal start-up sequence occurs. This sequence is the same as when the normal sample timer providesthe trigger. To enable the external sync signal feature, use the following procedure: 1. 2. appropriate input buffer using Register 0x4F, Bit 1, for the GPIO0 pin, or Register 0x4F, Bit 5, for the GPIO1 pin. Write 0x4000 to Register 0x38. Write 0x2 to Register 0x10 to start the sampling operations. Apply the external sync signal on the selected pin at the desired rate; sampling occurs at that rate. As with normal sampling operations, read the data using the FIFO or the data registers. 3. 4. 5. 6. Write 0x1 to Register 0x10 to enter program mode. Write the appropriate value to Register 0x4F, Bits[3:2] to select whether the GPIO0 pin or the GPIO1 pin specifies when the next sample cycle occurs. Also, enable the Rev. A | Page 22 of 66 Drive the GPIO1 pin to a valid logic level or with the desired 32 kHz clock prior to enabling the GPIO1 pin as an input. Do not leave the pin floating prior to enabling it. Write 01 to Register 0x4F, Bits[6:5] to enable the GPIO1 pin as an input. Write 10 to Register 0x4B, Bits[8:7] to configure the devices to use an external 32 kHz clock. This setting disables the internal 32 kHz clock and enables the external 32 kHz clock. Write 0x1 to Register 0x10 to enter program mode. Write additional control registers in any order while the devices are in program mode to configure the devices as required. Write 0x2 to Register 0x10 to start the normal sampling operation. Data Sheet ADPD105/ADPD106/ADPD107 when writing registers or changing modes. Because no power cycling occurs in this mode, the devices may consume higher current in program mode than in normal operation. To place the devices in program mode, write 0x1 to Register 0x10, Bits[1:0]. STATE MACHINE OPERATION During each time slot, the ADPD105/ADPD106/ADPD107 operate according to a state machine. The state machine operates in the following sequence, shown in Figure 24. In normal operation, the ADPD105/ADPD106/ADPD107 pulse light and collect data. Power consumption in this mode depends on the pulse count and data rate. To place the devices in normal sampling mode, write 0x2 to Register 0x10, Bits[1:0]. STANDBY REGISTER 0x10 = 0x0000 ULTRALOW POWER MODE NO DATA COLLECTION ALL REGISTER VALUES ARE RETAINED. NORMAL MODE OPERATION AND DATA FLOW In normal mode, the ADPD105/ADPD106/ADPD107 follow a specific pattern set up by the state machine. This pattern is shown in the corresponding data flow in Figure 25. The pattern is as follows: PROGRAM REGISTER 0x10 = 0x0001 SAFE MODE FOR PROGRAMING REGISTERS NO DATA COLLECTION DEVICE IS FULLY POWERED IN THIS MODE. 1. LED pulse and sample. The ADPD105/ADPD106/ADPD107 pulse external LEDs. The response of a photodiode or photodiodes to the reflected light is measured by the ADPD105/ ADPD106/ADPD107. Each data sample is constructed from the sum of n individual pulses, where n is user configurable between 1 and 255. Intersample averaging. If desired, the logic can average n samples, from 2 to 128 in powers of 2, to produce output data. New output data is saved to the output registers every N samples. Data read. The host processor reads the converted results from the data register or the FIFO. Repeat. The sequence has a few different loops that enable different types of averaging while keeping both time slots close in time relative to each other. NORMAL OPERATION STANDARD DATA COLLECTION DEVICE POWER IS CYCLED BY INTERNAL STATE MACHINE. 14693-018 REGISTER 0x10 = 0x0002 LEDs ARE PULSED AND PHOTODIODES ARE SAMPLED 2. Figure 24. State Machine Operation Flowchart The ADPD105/ADPD106/ADPD107 operate in one of three modes: standby, program, and normal sampling mode. Standby mode is a power saving mode in which no data collection occurs. All register values are retained in this mode. To place the devices in standby mode, write 0x0 to Register 0x10, Bits[1:0]. The devices power up in standby mode. 3. 4. Program mode is used for programming registers. Always cycle the ADPD105/ADPD106/ADPD107 through program mode [14 + LOG2(nA x NA)] BITS UP TO 27 BITS [14 + LOG2(nA)] BITS UP TO 20 BITS NA NA 14 BITS nA 14 BITS 1 nA nA 14-BIT ADC 1 ADC OFFSET 20-BIT CLIP IF VAL (220 - 1) VAL = VAL ELSE VAL = 220 - 1 0 16-BIT CLIP 16 BITS IF VAL (216 - 1) VAL = VAL ELSE VAL = 216 - 1 1 REGISTER 0x11[13] [14 + LOG2(nA)] BITS UP TO 22 BITS 32-BIT DATA REGISTERS FIFO 16-BIT DATA REGISTERS SAMPLE 1: TIME SLOT A SAMPLE 1: TIME SLOT B 0 1 SAMPLE N A: TIME SLOT A SAMPLE N B: TIME SLOT B NB NOTES 1. nA AND nB = NUMBER OF LED PULSES FOR TIME SLOT A AND TIME SLOT B. 2. NA AND NB = NUMBER OF AVERAGES FOR TIME SLOT A AND TIME SLOT B. NB 1 [14 + LOG2(nB)] BITS UP TO 20 BITS [14 + LOG2(nB x NB)] BITS UP TO 27 BITS Figure 25. ADPD105/ADPD106/ADPD107 Datapath Rev. A | Page 23 of 66 16-BIT CLIP IF VAL (216 - 1) VAL = VAL ELSE VAL = 216 - 1 16 BITS 14693-019 TIME SLOT A TIME SLOT B ADPD105/ADPD106/ADPD107 Data Sheet LED Pulse and Sample data is still acquired by the AFE at the sampling frequency, fSAMPLE (Register 0x12), but new data is written to the registers at the rate of fSAMPLE/N every Nth sample. This new data consists of the sum of the previous N samples. The full 32-bit sum is stored in the 32-bit registers. However, before sending this data to the FIFO, a divide by N operation occurs. This divide operation maintains bit depth to prevent clipping on the FIFO. At each sampling period, the selected LED driver drives a series of LED pulses, as shown in Figure 26. The magnitude, duration, and number of pulses are programmable over the I2C interface. Each LED pulse coincides with a sensing period so that the sensed value represents the total charge acquired on the photodiode in response to only the corresponding LED pulse. Charge, such as ambient light, that does not correspond to the LED pulse is rejected. Use this between sample averaging to lower the noise while maintaining 16-bit resolution. If the pulse count registers are kept to 8 or less, the 16-bit width is never exceeded. Therefore, when using Register 0x15 to average subsequent pulses, many pulses can be accumulated without exceeding the 16-bit word width. This averaging can reduce the number of FIFO reads required by the host processor. After each LED pulse, the photodiode output relating the pulsed LED signal is sampled and converted to a digital value by the 14-bit ADC. Each subsequent conversion within a sampling period is summed with the previous result. Up to 255 pulse values from the ADC can be summed in an individual sampling period. There is a 20-bit maximum range for each sampling period. Data Read Averaging The host processor reads output data from the ADPD105/ ADPD107 via the I2C protocol on the ADPD105 or the SPI port on the ADPD107. Data is read from the data registers or from the FIFO. New output data is made available every N samples, where N is the user configured averaging factor. The averaging factors for Time Slot A and Time Slot B are configurable independently of each other. If they are the same, both time slots can be configured to save data to the FIFO. If the two averaging factors are different, only one time slot can save data to the FIFO; data from the other time slot can be read from the output registers. The ADPD105/ADPD106/ADPD107 offer sample accumulation and averaging functionality to increase signal resolution. Within a sampling period, the AFE can sum up to 256 sequential pulses. As shown in Figure 25, samples acquired by the AFE are clipped to 20 bits at the output of the AFE. Additional resolution, up to 27 bits, can be achieved by averaging between sampling periods. This accumulated data of N samples is stored as 27-bit values and can be read out directly by using the 32-bit output registers or the 32-bit FIFO configuration. When using the averaging feature set up by Register 0x15, subsequent pulses can be averaged by powers of 2. The user can select from 2, 4, 8 ... up to 128 samples to be averaged. Pulse The data read operations are described in more detail in the Reading Data section. SHOWN WITH fSAMPLE = 10 Hz OPTICAL SAMPLING LOCATIONS 0 0.5 1.0 1.5 2.0 2.5 3.0 TIME (s) NUMBER OF LED PULSES (nA OR nB) 14693-020 LED CURRENT (ILED) Figure 26. Example of a Photoplethysmography (PPG) Signal Sampled at a Data Rate of 10 Hz Using Five Pulses per Sample Rev. A | Page 24 of 66 Data Sheet ADPD105/ADPD106/ADPD107 AFE OPERATION The timing within each pulse burst is important for optimizing the operation of the ADPD105/ADPD106/ADPD107. Figure 27 shows the timing waveforms for a single time slot as an LED pulse response propagates through the analog block of the AFE. The first graph, shown in green, shows the ideal LED pulsed output. The filtered LED response, shown in blue, shows the output of the analog integrator. The third graph, shown in orange, illustrates an optimally placed integration window. When programmed to the optimized value, the full signal of the filtered LED response can be integrated. The AFE integration window is then applied to the output of the band-pass filter (BPF) and the result is sent to the ADC and summed for N pulses. If the AFE window is not correctly sized or located, all of the receive signal is not properly reported and system performance is not optimal; therefore, it is important to verify proper AFE position for every new hardware design or the LED width. AFE INTEGRATION OFFSET ADJUSTMENT The AFE integration width must be equal or larger than the LED width. As AFE width increases, the output noise increases and the ability to suppress high frequency content from the environment decreases. It is therefore desirable to keep the AFE integration width small. However, if the AFE width is too small, the LED signal is attenuated. With most hardware selections, the AFE width produces the optimal SNR at 1 s more than the LED width. After setting LED width, LED offset, and AFE width, the ADC offset can then be optimized. The AFE offset must be manually set such that the falling edge of the first segment of the integration window matches the zero crossing of the filtered LED response. LED WIDTH REGISTER 0x30 [12:8] REGISTER 0x35 [12:8] N LED PULSES LED PERIOD LED DRIVE STRENGTH REGISTER 0x31 [7:0] REGISTER 0x36 [7:0] LED OFFSET REGISTER 0x30 [7:0] REGISTER 0x35 [7:0] REGISTER 0x31 [15:8] REGISTER 0x36 [15:8] REGISTER 0x22, REGISTER 0x23, REGISTER 0x24, REGISTER 0x25 LED PULSE FOR N PULSES FILTERED LED RESPONSE FOR N PULSES AFE INTEGRATION WINDOW FOR N PULSES CONTROLLED BY: TIA SETTINGS AFE SETTINGS REGISTER 0x42, REGISTER 0x43, REGISTER 0x44, REGISTER 0x45 9s + AFE OFFSET REGISTER 0x39 [10:0] REGISTER 0x3B [10:0] AFE WIDTH AFE WIDTH ADC CONVERSION + TIME (s) Figure 27. AFE Operation Diagram Rev. A | Page 25 of 66 ADC CONVERSION 14693-021 REGISTER 0x39 [15:11] REGISTER 0x3B [15:11] ADPD105/ADPD106/ADPD107 Data Sheet LED_FALLING_EDGE = SLOTx_LED_OFFSET + SLOTx_LED_WIDTH and, AFE_INTEGRATION_FALLING_EDGE = 9 + SLOTx_AFE_OFFSET + SLOTx_AFE_WIDTH If both falling edges are set equal to each other, solve for SLOTx_AFE_OFFSET to obtain the following equation: AFE_OFFSET_STARTING_POINT = SLOTx_LED_ OFFSET + SLOTx_LED_WIDTH - 9 - SLOTx_AFE_ WIDTH Setting the AFE offset to any point in time earlier than the starting point is equivalent to setting the integration in the future; the AFE cannot integrate the result from an LED pulse that has not yet occurred. As a result, a SLOTx_AFE_OFFSET value less than the AFE_OFFSET_STARTING_POINT value is an erroneous setting. Such a result may indicate that current in the TIA is operating in the reverse direction from intended, where the LED pulse is causing the current to leave the TIA rather than enter it. Because, for most setups, the SLOTx_AFE_WIDTH is 1 s wider than the SLOTx_LED_WIDTH, the AFE_OFFSET_ STARTING_POINT value is typically 10 s less than the SLOTx_LED_OFFSET value. Any value less than SLOTx_LED_ OFFSET - 10 is erroneous. The optimal AFE offset is some time after the AFE_OFFSET_STARTING_POINT value. The bandpass filter response, LED response, and photodiode response each add some delay. In general, the component choice, board layout, SLOTx_LED_OFFSET, and SLOTx_LED_WIDTH are the variables that can change the SLOTx_AFE_OFFSET value. After a specific design is set, the SLOTx_AFE_OFFSET value can be locked down and does not need to be optimized further. Sweeping the AFE Position The AFE offsets for Time Slot A and Time Slot B are controlled by Bits[10:0] of Register 0x39 and Register 0x3B, respectively. Each LSB represents one cycle of the 32 MHz clock, or 31.25 ns. 100 0.687 95 90 85 80 75 0 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 AFE OFFSET FROM STARTING POINT (s) 1.35 1.50 14693-022 The starting point of this offset, as expressed in microseconds, is set such that the falling edge of the integration window aligns with the falling edge of the LED. The register can be thought of as 211 - 1 of these 31.25 ns steps, or it can be broken into an AFE coarse setting using Bits[10:5] to represent 1 s steps and Bits[4:0] to represent 31.25 ns steps. Sweeping the AFE position from the starting point to find a local maximum is the recommended way to optimize the AFE offset. The setup for this test is to allow the LED light to fall on the photodiode in a static way. This test is typically done with a reflecting surface at a fixed distance. The AFE position can then be swept to look for changes in the output level. When adjusting the AFE position, it is important to sweep the position using the 31.25 ns steps. Typically, a local maximum is found within 2 s of the starting point for most systems. Figure 28 shows an example of an AFE sweep, where 0 on the x-axis represents the AFE starting point defined previously. Each data point in Figure 28 corresponds to one 31.25 ns step of the SLOTx_AFE_OFFSET. The optimal location for SLOTx_AFE_OFFSET in this example is 0.687 s from the AFE starting point. RELATIVE OUTPUT VALUE (%) AFE Integration Offset Starting Point Figure 28. AFE Sweep Example Table 18 lists some typical LED and AFE values after optimization. In general, it is not recommended to use the SLOTx_AFE_OFFSET numbers in Table 18 without first verifying them against the AFE sweep method. Repeat this method for every new LED width and with every new set of hardware made with the ADPD105/ ADPD107. For maximum accuracy, it is recommended that the 32 MHz clock be calibrated prior to sweeping the AFE. Table 18. AFE Window Settings LED Register 0x30 or Register 0x35 0x0219 0x0319 AFE Register 0x39 or Register 0x3B 0x1A08 0x21FE Rev. A | Page 26 of 66 Comment 2 s LED pulse, 3 s AFE width, 25 s LED delay 3 s LED pulse, 4 s AFE width, 25 s LED delay Data Sheet ADPD105/ADPD106/ADPD107 I2C SERIAL INTERFACE 4. The ADPD105 supports an I2C serial interface via the SDA (data) and SCL (clock) pins. All internal registers are accessed through the I2C interface. The ADPD105 is an I2C only device and does not support an SPI. 5. The ADPD105 conforms to the UM10204 I2C-Bus Specification and User Manual, Rev. 05--9 October 2012, available from NXP Semiconductors. It supports a fast mode (400 kbps) data transfer. Register read and write are supported, as shown in Figure 29. Figure 3 shows the timing diagram for the I2C interface. Slave Address The default 7-bit I2C slave address for the device is 0x64, followed by the R/W bit. For a write, the default I2C slave address is 0xC8; for a read, the default I2C address is 0xC9. The slave address is configurable by writing to Register 0x09, Bits[7:1]. When multiple ADPD105 devices are on the same bus lines, the GPIO0 and GPIO1 pins can be used to select specific devices for the address change. Register 0x0D can be used to select a key to enable address changes in specific devices. Use the following procedure to change the slave address when multiple ADPD105 devices are connected to the same I2C bus lines: 1. 2. 3. Using Register 0x4F, enable the input buffer of the GPIO1 pin, the GPIO0 pin, or both, depending on the key being used. For the device identified as requiring an address change, set the GPIO0 and/or GPIO1 pins high or low to match the key being used. Write the SLAVE_ADDRESS_KEY bits using Register 0x0D, Bits[15:0] to match the desired function. The allowed keys are shown in Table 33. 6. Write the desired SLAVE_ADDRESS bits using Register 0x09, Bits[7:1]. While writing to Register 0x09, Bits[7:1], write 0xAD to Register 0x09, Bit[15:8]. Register 0x09 must be written to immediately after writing to Register 0x0D. Repeat Step 1 to Step 4 for all the devices that need SLAVE_ADDRESS changed. Set the GPIO0 and GPIO1 pins as desired for normal operation using the new SLAVE_ADDRESS for each device. I2C Write and Read Operations Figure 29 illustrates the ADPD105 I2C write and read operations. Single-word and multiword read operations are supported. For a single register read, the host sends a no acknowledge (NACK) after the second data byte is read and a new register address is needed for each access. For multiword operations, each pair of data bytes is followed by an acknowledge from the host until the last byte of the last word is read. The host indicates the last read word by sending a no acknowledge. When reading from the FIFO (Register 0x60), the data is automatically advanced to the next word in the FIFO and the space is freed. When reading from other registers, the register address is automatically advanced to the next register, except at Register 0x5F or Register 0x7F, where the address does not increment. This autoincrementing allows lower overhead reading of sequential registers. All register writes are single word only and require 16 bits (one word) of data. The software reset (Register 0x0F, Bit 0) returns an acknowledge. The device then returns to standby mode with all registers in the default state. Table 19. Definition of I2C Terminology Term SCL SDA Master Slave Start (S) Start (Sr) Stop (P) ACK NACK Slave Address Read (R) Write (W) Description Serial clock. Serial address and data. The master is the device that initiates a transfer, generates clock signals, and terminates a transfer. The slave is the device addressed by a master. The ADPD105 operates as a slave device. A high to low transition on the SDA line while SCL is high; all transactions begin with a start condition. Repeated start condition. A low to high transition on the SDA line while SCL is high. A stop condition terminates all transactions. During the acknowledge or no acknowledge clock pulse, the SDA line is pulled low and remains low. During the acknowledge or no acknowledge clock pulse, the SDA line remains high. After a start (S), a 7-bit slave address is sent, which is followed by a data direction bit (read or write). A 1 indicates a request for data. A 0 indicates a transmission. Rev. A | Page 27 of 66 ADPD105/ADPD106/ADPD107 Data Sheet I2C WRITE REGISTER WRITE MASTER START SLAVE ADDRESS + WRITE SLAVE DATA[15:8] REGISTER ADDRESS ACK DATA[7:0] ACK STOP ACK ACK I2C SINGLE WORD READ MODE REGISTER READ MASTER START SLAVE ADDRESS + WRITE SLAVE REGISTER ADDRESS ACK SLAVE ADDRESS + READ Sr ACK ACK ACK DATA[15:8] ACK DATA[15:8] NACK STOP DATA[7:0] I2C MULTIWORD READ MODE REGISTER READ SLAVE ADDRESS + WRITE REGISTER ADDRESS Sr ACK ACK/NACK ACK SLAVE ADDRESS + READ ACK STOP DATA[7:0] 14693-023 MASTER START SLAVE DATA TRANSFERRED n (DATA[15:8]+ACK+DATA[7:0] + ACK/NACK) NOTES 1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING. Figure 29. I2C Write and Read Operations SPI PORT The first byte written in a SPI transaction is a 7-bit address, which is the location of the address being accessed, followed by the W/R bit. This bit determines whether the communication is a write (Logic Level 1) or a read (Logic Level 0). This format is shown in Table 21. The ADPD106 and ADPD107 are SPI only devices. They do not support the I2C interface. The SPI port uses a 4-wire interface, consisting of the CS, MOSI, MISO, and SCLK signals, and it is always a slave port. The CS signal goes low at the beginning of a transaction and high at the end of a transaction. The SCLK signal latches MOSI on a low to high transition. The MISO data is shifted out of the device on the falling edge of SCLK and must be clocked into a receiving device, such as a microcontroller, on the SCLK rising edge. The MOSI signal carries the serial input data, and the MISO signal carries the serial output data. The MISO signal remains three state until a read operation is requested, which allows other SPI-compatible peripherals to share the same MISO line. All SPI transactions have the same basic format shown in Table 20. A timing diagram is shown in Figure 4. Write all data MSB first. Table 21. SPI Address and Write/R Byte Format Bit 0 A6 Byte 2 Data[7:0] Bit 3 A3 Subsequent Bytes Data[15:8], Data[7:0] SCLK (CPOL = 1) CS 1 2 3 4 5 6 7 8 MISO Z 1 2 3 4 5 6 7 8 Z MOSI Z 1 2 3 4 5 6 7 8 Z CYCLE # (CPHA = 1) Bit 4 A2 Bit 5 A1 Bit 6 A0 Bit 7 W/R The maximum read and write speed for the SPI slave port is 10 MHz. 14693-024 Byte 1 Data[15:8] Bit 2 A4 The format for the SPI communications slave port is commonly known as SPI Mode 3, where clock polarity (CPOL) = 1 and clock phase (CPHA) = 1 (see Figure 30). The base value of the clock is 1. Data is captured on the rising edge of the clock, and data is propagated on the falling edge. Table 20. Generic Control Word Sequence Byte 0 Address[6:0], W/R Bit 1 A5 Figure 30. Clock Polarity and Phase for the SPI Slave Port (CPOL = 1, CPHA = 1) Rev. A | Page 28 of 66 Data Sheet ADPD105/ADPD106/ADPD107 read operation is shown in Figure 33. In Figure 31 to Figure 33, rising edges on SCLK are indicated with an arrow, signifying that the data lines are sampled on the rising edge. A sample timing diagram for a multiple word SPI write operation to a register is shown in Figure 31. A sample timing diagram of a single-word SPI read operation is shown in Figure 32. The MISO pin transitions from being three-state to being driven following the reception of a valid R bit. In this example, Byte 0 contains the address and the W/R bit, and subsequent bytes carry the data. A sample timing diagram of a multiple word SPI 0 1 2 3 4 5 6 7 8 When performing multiple word reads or writes, the data address is automatically incremented to the next consecutive address for subsequent transactions except for Address 0x5F, Address 0x60 (FIFO), and Address 0x7F. 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CS ADDRESS[6:0] MOSI DATA BYTE 1 DATA BYTE 2 14693-025 SCLK DATA BYTE N W/R Figure 31. SPI Slave Write Clocking (Burst Write Mode, N Bytes) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS SCLK ADDRESS[6:0] MOSI DATA BYTE 1 MISO DATA BYTE 2 14693-026 W/R Figure 32. SPI Slave Read Clocking (Single-Word Mode, Two Bytes) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CS SCLK MOSI ADDRESS[6:0] MISO DATA BYTE 1 DATA BYTE 2 Figure 33. SPI Slave Read Clocking (Burst Read Mode, N Bytes) Rev. A | Page 29 of 66 DATA BYTE N 14693-027 W/R ADPD105/ADPD106/ADPD107 Data Sheet 1.8V TYPICAL CONNECTION DIAGRAM ADPD105 PDC 0.1F AVDD PD1-2 VLED PD3-4 0.1F AGND DGND LGND 1.8V 10k 4.7F 10k SCL LEDX1 VREF SDA TO DIGITAL INTERFACE GPIO0 GPIO1 1F Figure 34. Typical Wrist-Based HRM Measurement A Provide the 1.8 V supply, VDD, to AVDD and DVDD. The LED supply uses a standard regulator circuit according to the peak current requirements specified in Table 3 and calculated in the LED Driver Pins and LED Supply Voltage section. B C For best noise performance, connect AGND, DGND, and LGND together at a large conductive surface, such as a ground plane, a ground pour, or a large ground trace. 1 2 3 LGND LEDX2 LEDX3 LEDX1 SDA SCL GPIO0 DVDD AGND DGND D E GPIO1 VREF AVDD F PD1-2 PDC PD3-4 14693-029 The number of photodiodes or LEDs used varies depending on the application as well as the dynamic range and SNR required. For example, in an application where a single, large photodiode is used, the dynamic range can be increased by splitting the current between multiple inputs. This is achieved by connecting the anode of the photodiode to multiple channels so that the current can be split evenly among the number of channels connected, effectively increasing the dynamic range over a single channel configuration. Alternatively, in situations where the photodiode is small or the signal is greatly attenuated, SNR can be maximized by connecting the anode of the photodiode to just a single channel. It is important to leave the unused input floating for proper device operation. DVDD 14693-028 Figure 34 shows a typical circuit used for wrist-based heart rate measurement with the ADPD105 WLCSP using a green LED. The 1.8 V I2C communication lines, SCL and SDA, along with the GPIO0 and GPIO1 lines, connect to a system microprocessor or sensor hub. The I2C signals can have pull-up resistors connected to a 1.8 V or a 3.3 V power supply. The GPIO0 and GPIO1 signals are only compatible with a 1.8 V supply and may need a level translator. The circuit shown in Figure 34 is identical for the ADPD107, except the I2C interface is replaced by an SPI. There are multiple ways to connect photodiodes to the 8-channel ADPD105 LFCSP, as shown in Table 22 and Figure 37. The photodiode anodes are connected to the PD1 to PD8 input pins and the photodiode cathodes are connected to the cathode pin, PDC. Figure 35. ADPD105 Connection and PCB Layout Diagram (Top View) 1 A Figure 35 and Figure 36 show the recommended connection diagram and printed circuit board (PCB) layout for the ADPD105 and ADPD107, respectively. The current input pins, PD1-2 and PD3-4, have a typical voltage of 1.3 V during the sampling period. During the sleep period, these pins are connected to the cathode pin. The cathode and anode voltages are listed in Table 3. B C D E LEDX2 LGND LEDX3 LEDX1 3 GPIO0 MISO GPIO1 DGND MOSI CS SCLK AGND AVDD PD1-2 VREF PDC PD3-4 14693-030 F 2 Figure 36. ADPD107 Connection and PCB Layout Diagram, Dashed Line Traces From Blind Vias (Top View) Rev. A | Page 30 of 66 14 PD8 15 15 PD8 14 7 PD7 PD6 PD4 15 PDC PD5 PD2 PD1 14 PD8 14 14693-107 PD7 PD4 8 PDC PD5 7 8 7 8 PDC PD5 PD4 PD1 15 PD2 PD4 PDC PD3 PD2 7 8 PD7 14 PD6 15 PDC 7 8 14 PDC PDC PD1 PD1 15 PD6 7 8 PD3 PD1 14 PD5 15 PD3 7 8 PD2 PD1 ADPD105/ADPD106/ADPD107 PD3 Data Sheet Figure 37. Photodiode Configuration Options for the ADPD105 LFCSP Table 22. Typical Photodiode Anode to Input Channel Connections for the ADPD105 LFCSP1, 2 Photodiode Anode Configuration Single Photodiode (PD1) Two Photodiodes (PD1, PD2) Four Photodiodes (PD1 to PD4) Eight Photodiodes (PD1 to PD8) PD3 NC NC D1 NC NC D1 D3 NC D3 PD6 NC NC NC D1 NC D2 NC D2 D6 PD7 NC NC NC D1 NC D2 NC D3 D7 PD8 NC NC NC D1 NC D2 NC D4 D8 Dx refers to the diode connected to the specified channel. NC means do not connect under the conditions provided in Table 21. Leave all unused inputs floating. LED DRIVER PINS AND LED SUPPLY VOLTAGE The LEDX1, LEDX2, and LEDX3 pins have an absolute maximum voltage rating of 3.6 V. Any voltage exposure over this rating affects the reliability of the device operation and, in certain circumstances, causes the device to cease proper operation. The voltage of the LEDx pins must not be confused with the supply voltages for the LED themselves (VLEDx). VLEDx is the voltage applied to the anode of the external LED, whereas the LEDXx pin is the input of the internal current driver, and the pins are connected to the cathode of the external LED. LED DRIVER OPERATION requirements for the bypass capacitor (CVLED) and the supply voltages of the LEDs (VLEDx). ADPD105/ ADPD106/ ADPD107 LGND C VLED LEDx VLEDx SUPPLY 14693-032 2 PD2 NC NC D1 NC NC D1 D2 NC D2 Figure 38. VLEDx Supply Schematic DETERMINING THE AVERAGE CURRENT The ADPD105/ADPD106/ADPD107 drive an LED in a series of short pulses. Figure 39 shows the typical ADPD105/ADPD106/ ADPD107 configuration of a pulse burst sequence. The LED driver for the ADPD105/ADPD106/ADPD107 is a current sink. The compliance voltage, measured at the driver pin with respect to ground, required to maintain the programmed LED current level is a function of the current required. Figure 15 shows the typical compliance voltages required at the various coarse LED settings. Figure 38 shows the basic schematic of how the ADPD105/ADPD106/ADPD107 connect to an LED through the LED driver. The Determining the Average Current and the Determining CVLED sections define the 19s 3s ILED_MAX 14693-032 1 PD1 D1 NC D1 NC D1 D1 D1 NC D1 Input Channel PD4 PD5 NC NC NC D1 D1 NC NC D1 NC D2 D1 D2 D4 NC NC D1 D4 D5 Figure 39. Typical LED Pulse Burst Sequence Configuration Rev. A | Page 31 of 66 ADPD105/ADPD106/ADPD107 Data Sheet In this example, the LED pulse width, tLED_PULSE, is 3 s, and the LED pulse period, tLED_PERIOD, is 19 s. The LED being driven is a pair of green LEDs driven to a 250 mA peak. The goal of CVLED is to buffer the LED between individual pulses. In the worst case scenario, where the pulse train shown in Figure 39 is a continuous sequence of short pulses, the VLEDx supply must supply the average current. Therefore, calculate ILED_AVERAGE as follows: ILED_AVERAGE = (tLED_PULSE/tLED_PERIOD) x ILED_MAX (1) where: ILED_AVERAGE is the average current needed from the VLEDx supply during the pulse period, and it is also the VLEDx supply current rating. ILED_MAX is the peak current setting of the LED. For the numbers shown in Equation 1, ILED_AVERAGE = 3/19 x ILED_MAX. For typical LED timing, the average VLEDx supply current is 3/19 x 250 mA = 39.4 mA, indicating that the VLEDx supply must support a dc current of 40 mA. DETERMINING CVLED To determine the CVLED capacitor value, determine the maximum forward-biased voltage, VFB_LED_MAX, of the LED in operation. The LED current, ILED_MAX, converts to VFB_LED_MAX as shown in Figure 40. In this example, 250 mA of current through two green LEDs in parallel yields VFB_LED_MAX = 3.95 V. Any series resistance in the LED path must also be included in this voltage. When designing the LED path, keep in mind that small resistances can add up to large voltage drops due to the LED peak current being very large. In addition, these resistances can be unnecessary constraints on the VLEDx supply. TWO 528nm LEDs ONE 850nm LED 4.0 3.5 3.0 2.5 2.0 1.5 CVLED t LED_PULSE I LED _ MAX VLED _ MIN (VFB _ LED _ MAX 0.2) (2) where: tLED_PULSE is the LED pulse width. ILED_MAX is the maximum forward-biased current on the LED used in operating the device. VLED_MIN is the lowest voltage from the VLEDx supply with no load. VFB_LED_MAX is the maximum forward-biased voltage required on the LED to achieve ILED_MAX. The numerator of the CVLED equation sets up the total discharge amount in coulombs from the bypass capacitor to satisfy a single programmed LED pulse of the maximum current. The denominator represents the difference between the lowest voltage from the VLEDx supply and the LED required voltage. The LED required voltage is the voltage of the anode of the LED such that the 0.2 V compliance of the LED driver and the forward-biased voltage of the LED operating at the maximum current is satisfied. For a typical ADPD105/ADPD106/ADPD107 example, assume that the lowest value for the VLEDx supply is 4.4 V, and that the peak current is 250 mA for two 528 nm LEDs in parallel. The minimum value for CVLED is then equal to 3 F. CVLED = (3 x 10-6 x 0.250)/(4.4 - (3.95 + 0.2)) = 3 F (3) As shown in the Equation 3, as the minimum supply voltage drops close to the maximum anode voltage, the demands on CVLED become more stringent, forcing the capacitor value higher. It is important to insert the correct values into Equation 2, Equation 2, and Equation 3. For example, using an average value for VLED_MIN instead of the worst case value for VLED_MIN can cause a serious design deficiency, resulting in a CVLED value that is too small and that causes insufficient optical power in the application. Therefore, adding a sufficient margin on CVLED is strongly recommended. Add additional margin to CVLED to account for derating of the capacitor value over voltage, bias, temperature, and other factors over the life of the component. LED INDUCTANCE CONSIDERATIONS 1.0 0 50 100 150 200 LED DRIVER CURRENT SETTING (mA) 250 14693-033 LED FORWARD-BIAS VOLTAGE DROP (V) 4.5 To correctly size the CVLED capacitor, do not deplete it during the pulse of the LED to the point where the voltage on the capacitor is less than the forward bias on the LED. To calculate the minimum value for the VLEDx bypass capacitor, use the following equation: Figure 40. Example of the Average LED Forward-Bias Voltage Drop as a Function of the Driver Current The LED drivers (LEDXx) on the ADPD105/ADPD106/ADPD107 have configurable slew rate settings (Register 0x22, Bits[6:4], Register 0x23, Bits[6:4], and Register 0x24, Bits[6:4]). These slew rates are defined in Table 3. Even at the lowest setting, careful consideration must be taken in board design and layout. If a large series inductor, such as a long PCB trace, is placed between the LED cathode and one of the LEDXx pins, voltage spikes from the switched inductor can cause violations of absolute maximum and minimum voltages on the LEDXx pins during the slew portion of the LED pulse. Rev. A | Page 32 of 66 Data Sheet ADPD105/ADPD106/ADPD107 To verify that there are no voltage spikes on the LEDXx pins due to parasitic inductance, use an oscilloscope on the LEDXx pins to monitor the voltage during normal operation. Any positive spike >3.6 V may damage the devices. In addition, a negative spike <-0.3 V may also damage the devices. RECOMMENDED START-UP SEQUENCE At power-up, the device is in standby mode (Register 0x10 = 0x0), as shown in Figure 24. The ADPD105/ADPD106/ ADPD107 do not require a particular power-up sequence. 2. 3. 4. Set the CLK32K_EN bit (Register 0x4B, Bit 7) to start the sample clock (32 kHz clock). This clock controls the state machine. If this clock is off, the state machine is not able to transition as defined by Register 0x10. Write 0x1 to Register 0x10 to force the device into program mode. Step 1 and Step 2 can be swapped, but the actual state transition does not occur until both steps occur. Write additional control registers in any order while the device is in program mode to configure the devices as required. Write 0x2 to Register 0x10 to start normal sampling operation. To terminate normal operation, follow this sequence to place the ADPD105/ADPD106/ADPD107 in standby mode: 1. 2. 3. 4. 5. The ADPD105/ADPD106/ADPD107 provide multiple methods for accessing the sample data. Each time slot can be independently configured to provide data access using the FIFO or the data registers. Interrupt signaling is also available to simplify timely data access. The FIFO is available to loosen the system timing requirements for data accesses. Reading Data Using the FIFO From standby mode, to begin measurement, initiate the ADPD105/ADPD106/ADPD107 as follows: 1. READING DATA Write 0x1 to Register 0x10 to force the devices into program mode. Write to the registers in any order while the devices are in program mode. Write 0x00FF to Register 0x00 to clear all interrupts. If desired, clear the FIFO as well by writing 0x80FF to Register 0x00. Write 0x0 to Register 0x10 to force the devices into standby mode. Optionally, stop the 32 kHz clock by resetting the CLK32K_ EN bit (Register 0x4B, Bit 7). Register 0x4B, Bit 7 = 0 is the only write that must be written when the device is in standby mode (Register 0x10 = 0x0). If 0 is written to this bit while in program mode or normal mode, the devices become unable to transition into any other mode, including standby mode, even if they are subsequently written to do so. As a result, the power consumption in what appears to be standby mode is greatly elevated. For this reason, and due to the very low current draw of the 32 kHz clock while in operation, it is recommended from an ease of use perspective to keep the 32 kHz clock running after it is turned on. The ADPD105/ADPD106/ADPD107 include a 128-byte FIFO memory buffer that can be configured to store data from either or both time slots. Register 0x11 selects the kind of data from each time slot to be written to the FIFO. Note that both time slots can be enabled to use the FIFO, but only if their output data rate is the same. Output data rate = fSAMPLE/N where: fSAMPLE is the sampling frequency. N is the averaging factor for each time slot (NA for Time Slot A and NB for Time Slot B). In other words, NA = NB must be true to store data from both time slots in the FIFO. Data packets are written to the FIFO at the output data rate. A data packet for the FIFO consists of a complete sample for each enabled time slot. Data for each photodiode channel can be stored as either 16 or 32 bits. Each time slot can store 2, 4, 8, or 16 bytes of data per sample, depending on the mode and data format. To ensure that data packets are intact, new data is only written to the FIFO if there is sufficient space for a complete packet. Any new data that arrives when there is not enough space is lost. The FIFO continues to store data when sufficient space exists. Always read FIFO data in complete packets to ensure that data packets remain intact. The number of bytes currently stored in the FIFO is available in Register 0x00, Bits[15:8]. A dedicated FIFO interrupt is also available and automatically generates when a specified amount of data is written to the FIFO. Interrupt-Based Method To read data from the FIFO using an interrupt-based method, use the following procedure: 1. 2. 3. 4. Rev. A | Page 33 of 66 In program mode, set the configuration of the time slots as desired for operation. Write Register 0x11 with the desired data format for each time slot. Set FIFO_THRESH in Register 0x06, Bits[13:8] to the interrupt threshold. A recommended value for this is the number of 16-bit words in a data packet, minus 1. This causes an interrupt to generate when there is at least one complete packet in the FIFO. Enable the FIFO interrupt by writing a 0 to the FIFO_ INT_MASK in Register 0x01, Bit 8. Also, configure the interrupt pin (GPIO0) by writing the appropriate value to the bits in Register 0x02. ADPD105/ADPD106/ADPD107 5. 6. Data Sheet Enter normal operation mode by setting Register 0x10 to 0x2. When an interrupt occurs a. There is no requirement to read the FIFO_SAMPLES bits, because the interrupt is generated only if there is one or more full packets. Optionally, the interrupt routine can check for the presence of more than one available packet by reading these bits. b. Read a complete packet using one or more multiword accesses using Register 0x60. Reading the FIFO automatically frees the space for new samples. 2. 3. 4. The FIFO interrupt automatically clears immediately upon reading any data from the FIFO and is set again only when the FIFO is written and the number of words is above the threshold. Polling Method To read data from the FIFO in a polling method, use the following procedure: 1. 2. 3. In program mode, set the configuration of the time slots as desired for operation. Write Register 0x11 with the desired data format for each time slot. Enter normal operation mode by setting Register 0x10 to 2. Next, begin the polling operations. 1. 2. 3. Wait for the polling interval to expire. Read the FIFO_SAMPLES bits (Register 0x00, Bits[15:8]). If FIFO_SAMPLES the packet size, read a packet using the following steps: a. Read a complete packet using one or more multiword accesses via Register 0x60. Reading the FIFO automatically frees the space for new samples. b. Repeat Step 1. When a mode change is required, or any other disruption to normal sampling is necessary, the FIFO must be cleared. Use the following procedure to clear the state and empty the FIFO: 1. 2. Enter program mode by setting Register 0x10 to 0x1. Write 1 to Register 0x00, Bit 15. If both time slots are in use, it is possible to use only the Time Slot B interrupt to signal when all registers can be read. It is recommended to use the multiword read to transfer the data from the data registers. Reading Data from Registers Without Interrupts If the system interrupt response is not fast or predictable enough to use the interrupt method, or if the interrupt pin (GPIOx) is not used, it is possible to obtain reliable data access by using the data hold mechanism. To guarantee that the data read from the registers is from the same sample time, it is necessary to prevent the update of samples while reading the current values. The method for doing register reads without interrupt timing is as follows: 1. 2. 3. Write a 1 to SLOTA_DATA_HOLD or SLOTB_DATA_ HOLD (Register 0x5F, Bit 1 and Bit 2, respectively) for the time slot requiring access (both time slots can be accessed). This setting prevents sample updates. Read the registers as desired. Write a 0 to the SLOTA_DATA_HOLD or SLOTB_DATA_ HOLD bits (Register 0x5F, Bit 1 and Bit 2, respectively) previously set. Sample updates are allowed again. Because a new sample may arrive while the reads are occurring, this method prevents the new sample from partially overwriting the data being read. Reading Data from Registers Using Interrupts The latest sample data is always available in the data registers and is updated simultaneously at the end of each time slot. The data value for each photodiode channel is available as a 16-bit value in Register 0x64 through Register 0x67 for Time Slot A, and Register 0x68 through Register 0x6B for Time Slot B. If allowed to reach their maximum value, Register 0x64 through Register 0x6B clip. If Register 0x64 through Register 0x6B saturate, the unsaturated (up to 27 bits) values for each channel are available in Register 0x70 through Register 0x77 for Time Slot A and Register 0x78 through Register 0x7F for Time Slot B. Sample interrupts are available to indicate when the registers are updated and can be read. To use the interrupt for a given time slot, use the following procedure: 1. write 0 to Bit 5. To enable the interrupt for Time Slot B, write 0 to Bit 6. Either or both interrupts can be set. Configure the interrupt pin (GPIOx) by writing the appropriate value to the bits in Register 0x02. An interrupt generates when the data registers are updated. The interrupt handler must perform the following: a. Read Register 0x00 and observe Bit 5 or Bit 6 to confirm which interrupt has occurred. This step is not required if only one interrupt is in use. b. Read the data registers before the next sample can be written. The system must have interrupt latency and service time short enough to respond before the next data update, based on the output data rate. c. Write a 1 to Bit 5 or Bit 6 in Register 0x00 to clear the interrupt. CLOCKS AND TIMING CALIBRATION The ADPD105/ADPD106/ADPD107 operate using two internal time bases: a 32 kHz clock sets the sample timing, and a 32 MHz clock controls the timing of the internal functions such as LED pulsing and data capture. Both clocks are internally generated and exhibit device to device variation of approximately 10% (typical). Heart rate monitoring applications require an accurate time base to achieve an accurate count of beats per minute. The ADPD105/ADPD106/ADPD107 provide a simple calibration procedure for both clocks. Enable the sample interrupt by writing a 0 to the appropriate bit in Register 0x01. To enable the interrupt for Time Slot A, Rev. A | Page 34 of 66 Data Sheet ADPD105/ADPD106/ADPD107 Calibrating the 32 kHz Clock Calibrating the 32 kHz clock also calibrates items associated with the output data rate. Calibration of this clock is important for applications where an accurate data rate is important, such as heart rate measurements. To calibrate the 32 kHz clock, 1. 2. 3. Set the sampling frequency to the highest the system can handle, such as 2000 Hz. Because the 32 kHz clock controls sample timing, its frequency is readily accessible via the GPIO0 pin. Configure the interrupt by writing the appropriate value to the bits in Register 0x02 and set the interrupt to occur at the sampling frequency by writing 0 to Register 0x01, Bit 5 or Bit 6. Monitor the GPIO0 pin. The interrupt frequency must match the set sample frequency. If the monitored interrupt frequency is less than the set sampling frequency, increase the CLK32K_ADJUST bit (Register 0x4B, Bits[5:0]). If the monitored interrupt frequency is larger than the set sampling frequency, decrease the CLK32K_ADJUST bits. Repeat Step b until the monitored interrupt signal frequency is close enough to the set sampling frequency. OPTIONAL TIMING SIGNALS AVAILABLE ON GPIO0 AND GPIO1 The ADPD105/ADPD106/ADPD107 provide a number of different timing signals, available via the GPIO0 and GPIO1 pins, to enable ease of system synchronization and flexible triggering options. Each of the GPIOx pins can be configured as an opendrain output if they are to share the bus with other drivers, or they can be configured to always drive the bus. Both outputs also have polarity control in situations where a timing signal must be inverted from the default. Table 23. GPIOx Control Settings Pin Name GPIO0 Register[Bits] 0x02[0] 0x02[1] 0x02[2] GPIO1 0x02[8] 0x02[9] Calibrating the 32 MHz Clock Calibrating the 32 MHz clock also calibrates items associated with the fine timing within a sample period, such as LED pulse width and spacing, assuming that the 32 kHz clock has been calibrated. To calibrate the 32 MHz clock, 1. 2. 3. Write 0x1 to Register 0x5F, Bit 0. Enable the CLK_RATIO calculation by writing 0x1 to Register 0x50, Bit 5. This function counts the number of 32 MHz clock cycles in two cycles of the 32 kHz clock. With this function enabled, this cycle value is stored in Register 0x0A, Bits[11:0] and nominally this ratio is 2000 (0x7D0). Calculate the 32 MHz clock error as follows: Clock Error = 32 MHz x (1 - CLK_RATIO/2000) 4. Adjust the frequency by setting Bits[7:0] in Register 0x4D per the following equation: 0x4F[6] The various available timing signals are controlled by the settings in Register 0x0B. Bits[12:8] of this register control the timing signals available on GPIO1, and Bits[4:0] control the timing signals available on GPIO0. All of the timing signals described in this data sheet are available on either (or both) of the GPIO0 and GPIO1 pins. Timing diagrams are shown in Figure 41 and Figure 42. The time slot settings used to generate the timing diagrams are described in Table 24. Table 24. ADPD105/ADPD106/ADPD107 Settings Used for Timing Diagrams Shown in Figure 41 and Figure 42 Register 0x31 0x36 0x15 CLK32M_ADJUST = Clock Error/109 kHz 5. Setting Description 0: polarity active high 1: polarity active low 0: always drives the bus 1: drives the bus when asserted 0: disables the GPIO0 pin drive 1: enables the GPIO0 pin drive 0: polarity active high 1: polarity active low 0: always drives the bus 1: drives the bus when asserted 0: disables the GPIO1 pin drive 1: enables the GPIO1 pin drive Write 0x0 to Register 0x50, Bit 5 to reset the CLK_RATIO function. Repeat Step 2 through Step 5 until the desired accuracy is achieved. Write 0x0 to Register 0x5F, Bit 0. Also, set the GPIO0 pin back to the mode desired for normal operation. Rev. A | Page 35 of 66 Setting 0x0118 0x0418 0x0120 Description Time Slot A: 1 LED pulse Time Slot B: 4 LED pulses Time Slot A decimation = 4, Time Slot B decimation = 2 ADPD105/ADPD106/ADPD107 SLOT A Data Sheet SLEEP SLOT B SLOT A SLOT B 0x02 0x05 0x06 14693-034 0x07 0x0F Figure 41. Optional Timing Signals Available on GPIOx--Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x05, 0x06, 0x07, and 0x0F SLOT A/B SLEEP SLOT A/B SLEEP SLOT A/B SLEEP SLOT A/B SLEEP SLOT A/B SLEEP SLOT A/B 0x02 0x0C 14693-035 0x0D 0x0E Figure 42. Optional Timing Signals Available on GPIOx--Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x0C, 0x0D, and 0x0E ADPD103 Backward Compatibility Pulse Outputs Setting Register 0x0B = 0 provides backward compatibility to the ADPD103. The GPIO0 pin mirrors the functionality of the ADPD103 INT pin. The GPIO1 pin mirrors the functionality of the ADPD103 PDSO pin. Three options are available to provide a copy of the LED pulse outputs. Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x05 provides a copy of the Time Slot A LED pulses on the respective pin. A setting of 0x06 provides the Time Slot B pulses, and a setting of 0x07 provides the pulse outputs of both time slots. Interrupt Function Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x01 configures the respective pin to perform the interrupt function as defined by the settings in Register 0x01. Sample Timing Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02 configures the respective pin to provide a signal that asserts at the beginning of the first time slot of the current sample and deasserts at the end of the last time slot of the current sample. For example, if both time slots are enabled, this signal asserts at the beginning of Time Slot A and deasserts at the end of Time Slot B. If only a single time slot is enabled, the signal asserts at the beginning of the enabled time slot and deasserts at the end of this same time slot. Output Data Cycle Signal There are three options available to provide a signal that indicates when the output data is written to the output data registers or to the FIFO. Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x0C provides a signal that indicates that a data value is written for Time Slot A. A setting of 0x0D provides a signal that indicates that a data value is written for Time Slot B, and 0x0E provides a signal to indicate that a value is written for either time slot. The signal asserts at the end of the time slot, when the output data is already written, and deasserts at the start of the subsequent sample. This timing signal is especially useful in situations where the FIFO is being used. For example, one of the GPIOx pins can be configured to provide an interrupt after the FIFO reaches the FIFO threshold set in Register 0x06, Bits[13:8], while the other GPIOx pin can be configured to provide the output data cycle signal. This signal can be used to trigger a peripheral device, such as an accelerometer, so that time aligned signals are provided to the processor. Rev. A | Page 36 of 66 Data Sheet ADPD105/ADPD106/ADPD107 fS/2 Output CALCULATING CURRENT CONSUMPTION Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x0F configures the respective pin to provide a signal that toggles at half the sampling rate. This timing signal is useful in, for example, situations where more than two LEDs per sample are required. This signal can be used as a select signal to a multiplexer being used to mux two LEDs into a single LED driver, providing the ability to drive up to four separate LEDs per sample period. In such a case, the ADPD105/ADPD106/ADPD107 are operated at 2x the sampling rate and the LED settings can be reconfigured during the sleep period between samples. If identical LED settings (current and timing) are used for the LEDs being muxed, then up to four LEDs can be sampled per sampling period without host inter-vention. An example of this configuration is shown in Figure 43. The current consumption of the ADPD105/ADPD106/ADPD107 depends on the user selected operating configuration, as determined by the following equations. The fS/2 timing signal always starts in an active low state when the device switches from standby mode to normal operating mode and transitions to a high state at the completion of the first sample. Total Power Consumption To calculate the total power consumption, use Equation 4. Total Power = IVDD_AVG x VDD + ILEDA_AVG x VLEDA + ILEDB_AVG x VLEDB (4) Average VDD Supply Current To calculate the average VDD supply current, use Equation 5. IVDD_AVG = DR x ((IAFE_A x tSLOTA) + (IAFE_B x tSLOTB) + QPROC_X) + IVDD_STANDBY (5) where: DR is the data rate in Hz. IVDD_STANDBY = 0.2 A. QPROC_X is an average charge associated with a processing time, as follows: When only Time Slot A is enabled, QPROC_A (C) = 0.135 x 10-6 + (186 x 10-6 x (2.69 x 10-3 + (6.2 x 10-3/SCALE_A x ILEDA_PK)) When only Time Slot B is enabled, QPROC_B (C) = 0.135 x 10-6 + (134 x 10-6 x (2.69 x 10-3 + (6.2 x 10-3/SCALE_A x ILEDA_PK)) 14693-036 When Time Slot A and Time Slot B are enabled, QPROC_AB (C) = 0.135 x 10-6 + (206 x 10-6 x (2.69 x 10-3 + (6.2 x 10-3/SCALE_A x ILEDA_PK)) Figure 43. Example Using the fS/2 Timing Signal IAFE_x (A) = 3.0 x 10-3 + (1.5 x 10-3 x NUM_CHANNELS) + (6) (5.7 x 10-3/SCALE_X x ILEDX_PK) Logic 0 Output Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x10 configures the respective pin to provide a Logic 0 output. tSLOTx (sec) = LEDx_OFFSET + LEDx_PERIOD x PULSE_COUNT Logic 1 Output Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x11 configures the respective pin to provide a Logic 1 output. 32 kHz Oscillator Output Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x13 configures the respective pin to provide a copy of the on-board 32 kHz oscillator. (7) where: NUM_CHANNELS is the number of active channels. ILEDX_PK is the peak LED current, expressed in amps, for whichever LED is enabled in that particular timeslot. Note that in the QPROC calculations, the processing charge only scales as a function of the LED current setting for the LED configured to operate in Time Slot A, regardless of whether or not Time Slot A is enabled. For this reason, be sure to minimize the LED peak current for the Time Slot A LED to save power when Time Slot A is not being used. SCALE_X is the scale factor for the LED current drive determined by Bit 13 of the LEDX_DRV registers: Register 0x22, Register 0x23, and Register 0x24. LEDx_OFFSET is the pulse start time offset expressed in seconds. LEDx_PERIOD is the pulse period expressed in seconds. PULSE_COUNT is the number of pulses. Rev. A | Page 37 of 66 ADPD105/ADPD106/ADPD107 Data Sheet Note that if either Time Slot A or Time Slot B are disabled, IAFE_x = 0 for that respective time slot. Additionally, if operating in digital integrate mode, power savings can be realized by setting Register 0x3C, Bits[8:3] = 010010. This setting disables the band-pass filters that are bypassed in digital integrate mode, changing the AFE power contribution calculation to IAFE_x (mA) = 3.0 x 10-3 + (1.0 x 10-3 x NUM_CHANNELS) + (5.7 x 10-3/SCALE_X x ILEDX_PK) (8) Average VLEDA Supply Current To calculate the average VLEDA supply current, use Equation 9. ILED_AVG_A = SLOTA_LED_WIDTH x ILEDA_PK x DR x PULSE_COUNT (9) where: SLOTA_LED_WIDTH is the LED pulse width expressed in seconds. ILEDA_PK is the peak current, expressed in amps, for whichever LED is selected for Time Slot A. Average VLEDB Supply Current To calculate the average VLEDB supply current, use Equation 10. ILED_AVG_B = SLOTB_LED_WIDTH x ILEDB_PK x DR x PULSE_COUNT optimized, the user can then increase the number of pulses to achieve the desired system SNR. Optimizing SNR per Watt in a Signal Limited System In practice, optimizing for peak SNR is not always practical. One scenario in which the PPG signal has a poor SNR is the signal limited regime. In this scenario, the LED current reaches an upper limit before the desired dc return level is achieved. Tuning in this case starts where the peak SNR tuning stops. The starting point is nominally a 50k gain, as long as the lowest LED current setting of 8 mA does not saturate the photodiode and the 50k gain provides enough protection against intense background light. In these cases, use a 25k gain as the starting point. The goal of the tuning process is to bring the dc return signal to a specific ADC range, such as 50% or 60%. The ADC range choice is a function of the margin of headroom needed to prevent saturation as the dc level fluctuates over time. The SNR of the PPG waveform is always some percentage of the dc level. If the target level cannot be achieved at the base gain, increase the gain and repeat the procedure. The tuning system may need to place an upper limit on the gain to prevent saturation from ambient signals. Tuning the Pulse Count (10) where: SLOTB_LED_WIDTH is the LED pulse width expressed in seconds. ILEDB_PK is the peak current, expressed in amps, for whichever LED is selected for Time Slot B. OPTIMIZING SNR PER WATT The ADPD105/ADPD106/ADPD107 offer a variety of parameters that the user can adjust to achieve the best signal. One of the key goals of system performance is to obtain the best system SNR for the lowest total power. This goal is often referred to as optimizing SNR/watt. Even in systems where only the SNR matters and power is a secondary concern, there may be a lower power or a high power means of achieving the same SNR. Optimizing for Peak SNR The first step in optimizing for peak SNR is to find a TIA gain and LED level that gives the best performance where the number of LED pulses remains constant. If peak SNR is the goal, the noise section of Table 4 can be used as a guide. It is important to note that the SNR improves as a square root of the number of pulses averaged together, whereas the increase in the LED power consumed is directly proportional to the number of LED pulses. In other words, for every doubling of the LED pulse count, there is a doubling of the LED power consumed and a 3 dB SNR improvement. As a result, avoid any change in the gain configuration that provides less than 3 dB of improvement for a 2x power penalty; any TIA gain configuration that provides more than 3 dB of improvement for a 2x power penalty is a good choice. If peak SNR is the goal and there is no issue saturating the photodiode with LED current at any gain, the 50k TIA gain setting is an optimal choice. After the SNR per pulse per channel is After the LED peak current and TIA gain are optimized, increasing the number of pulses per sample increases the SNR by the square root of the number of pulses. There are two ways to increase the pulse count. The pulse count registers (Register 0x31, Bits[15:8], and Register 0x36, Bits[15:8]) change the number of pulses per internal sample. Register 0x15, Bits[6:4] and Bits[10:8], controls the number of internal samples that are averaged together before the data is sent to the output. Therefore, the number of pulses per sample is the pulse count register multiplied by the number of subsequent samples being averaged. In general, the internal sampling rate increases as the number of internal sample averages increase to maintain the desired output data rate. The SNR/watt is most optimal with pulse count values of 16 or less. Above pulse count values of 16, the square root relationship does not hold in the pulse count register. However, this relationship continues to hold when averaged between samples using Register 0x15. Note that increasing LED peak current increases SNR almost directly proportional to LED power, whereas increasing the number of pulses by a factor of n results in only a nominal(n) increase in SNR. When using the sample sum/average function (Register 0x15), the output data rate decreases by the number of summed samples. To maintain a static output data rate, increase the sample frequency (Register 0x12) by the same factor as that selected in Register 0x15. For example, for a 100 Hz output data rate and a sample sum/average of four samples, set the sample frequency to 400 Hz. Rev. A | Page 38 of 66 Data Sheet ADPD105/ADPD106/ADPD107 Dual-Channel AFE Mode OPTIMIZING POWER BY DISABLING UNUSED CHANNELS AND AMPLIFIERS Single-Channel AFE Mode When using a single photodiode in an application, with that photodiode connected to a single AFE channel (either Channel 1 or Channel 2), the ADPD105/ADPD106/ADPD107 have an option to power down the unused channels, placing the device in single AFE channel mode. Because three of the four AFE channels are turned off in this mode, the power consumption is considerably reduced. If only Channel 1 is being used, disable Channel 2, Channel 3, and Channel 4 by writing 0x7 to Register 0x3C, Bits[8:6]. If only Channel 2 is being used, disable Channel 1 by writing 0x7 to Register 0x3C, Bits[5:3], and disable Channel 3 and Channel 4 by writing 0x7 to Register 0x37, Bits[15:13]. In situations where two of the four channels are in use, the other two channels can be disabled. Enable Channel 1 and Channel 2 (with Channel 3 and Channel 4 disabled) by writing 0x7 to Register 0x37, Bits[15:13]. Operate Channel 3 and Channel 4 in dual channel mode (with Channel 1 and Channel 2 disabled) by writing 0x7 to both Register 0x3C, Bits[5:3] and Register 0x37, Bits[12:10]. Three-channel mode can also be achieved with the appropriate settings. See Table 25 for the settings required to power down different combinations of channels. Refer to the Time Slot Switch section to determine the different combinations of the PDx inputs and enabled channels required to optimize the system configuration for maximum SNR and lowest power. Table 25. Channel Power-Down Settings Number of Channels 1 1 2 2 3 4 Channels Enabled Channel 1 Channel 2 Channel 1, Channel 2 Channel 3, Channel 4 Channel 2, Channel 3, Channel 4 All channels Register 0x3C, Bits[8:6] 0x7 0x0 0x0 0x0 0x0 0x0 Register 0x3C, Bits[5:3] 0x0 0x7 0x0 0x7 0x7 0x0 Rev. A | Page 39 of 66 Register 0x37, Bits[15:13] Not applicable 0x7 0x7 0x0 0x0 0x0 Register 0x37, Bits[12:10] Not applicable 0x0 0x0 0x7 0x0 0x0 ADPD105/ADPD106/ADPD107 Data Sheet Powering Down Individual Amplifiers for Additional Power Savings mode from the ADPD103 that is kept in the ADPD105/ ADPD106/ADPD107 for backward compatibility. Each channel includes a TIA, a BPF, and an integrator, which can also be configured as a buffer (see Figure 44).Options are built into the devices to power down individual amplifiers in the signal path. For example, in digital integrate mode, the BPF is bypassed but left powered up by default. The BPF can be disabled completely, which saves 1/3 of the power dissipated by the AFE during the sampling phase. See the descriptions for Register 0x3C and Register 0x37 in Table 30 for information on how to disable the individual amplifiers. The recommended TIA ADC mode is one in which the bandpass filter is bypassed and the integrator is configured as an inverting buffer. This mode is enabled by writing 0xAE65 to Register 0x43 (Time Slot A) and/or Register 0x45 (Time Slot B) to bypass the band-pass filter. Additionally, Bit 7 of Register 0x42 (Time Slot A) and/or Register 0x44 (Time Slot B) must be set to 1 to configure the integrator as a buffer. With the ADC offset register(s) for the desired channel set to 0, the output of the ADC is at ~3000 codes for a single pulse and a zero input current condition. As the input current from the photodiode increases, the ADC output increases toward 16,384. BPF 1 INTEGRATOR VBIAS The ADC output (ADCOUT) is calculated as follows: 14693-037 TIA ADCOUT = 8192 ((2 VBIAS - 2iRF - 1.8 V)/146 V/LSB) (11) Figure 44. Signal Path Block Diagram It is important to leave any unused input channels floating for proper device operation. TIA ADC MODE There is a way to put the devices into a mode that effectively runs the TIA directly into the ADC without using the analog band-pass filter and integrator as shown in Figure 45. This mode is referred to as TIA ADC mode. There are two basic applications of TIA ADC mode. In normal operation, all of the background light is blocked from the signal chain, and therefore cannot be measured. TIA_ ADC mode can be used to measure the amount of background/ ambient light. This mode can also be used to measure other dc input currents, such as leakage resistance. OPTIONAL BUFFER -1 ADC VBIAS In Equation 11, use + for the inverting configuration and use - when using the noninverting configuration with the buffer. Equation 11 is an approximation and does not account for internal offsets and gain errors. The calculation also assumes that the ADC offset registers are set to 0 One time slot can be used in TIA ADC mode at the same time the other time slot is being used in normal pulsed mode. This capability is useful for monitoring ambient and pulsed signals at the same time. The ambient signal is monitored during the time slot configured for TIA ADC mode, while the pulsed signal, with the ambient signal rejected, is monitored in the time slot configured for normal mode. Protecting Against TIA Saturation in Normal Operation 14693-038 TIA where: VBIAS is the bias voltage for the TIA (the default value is 1.265 V). i is the input current to the TIA. RF is the TIA feedback resistor. Figure 45. TIA ADC Mode Block Diagram When the devices are in TIA ADC mode, the band-pass filter and the integrator stage are bypassed. This bypass effectively wires the TIA directly into the ADC. At the set sampling frequency, the ADC samples Channel 1 through Channel 4 in sequential order, and each sample is taken at 1 s intervals. There are two modes of operation in TIA ADC mode. One mode is an inverting configuration where TIA ADC mode directly drives the ADC. This mode is enabled by setting Register 0x43 (Time Slot A) and/or Register 0x45 (Time Slot B) to 0xB065, which bypasses the band-pass filter and the integrator. With the ADC offset register(s) for the desired channel set to 0, the output of the ADC is at ~13,000 codes for a single pulse and a zero input current condition. As the input current from the photodiode increases, the ADC output decreases toward 0. This configuration is a legacy TIA ADC One of the reasons to monitor TIA ADC mode is to protect against environments that may cause saturation. One concern when operating in high light conditions, especially with larger photodiodes, is that the TIA stage may become saturated while the ADPD105/ADPD106/ADPD107 continue to communicate data. The resulting saturation is not typical. The TIA, based on its settings, can only handle a certain level of photodiode current. Based on the way the ADPD105/ADPD106/ADPD107 are configured, if there is a current level from the photodiode that is larger than the TIA can handle, the TIA output during the LED pulse effectively extends the current pulse, making it wider. The AFE timing is then violated because the positive portion of the band-pass filter output extends into the negative section of the integration window. Thus, the photosignal is subtracted from itself, causing the output signal to decrease when the effective light signal increases. To measure the response from the TIA and verify that this stage is not saturating, place the device in TIA ADC mode and slightly modify the timing. Specifically, sweep SLOTx_AFE_OFFSET Rev. A | Page 40 of 66 Data Sheet ADPD105/ADPD106/ADPD107 until two or three of the four channels reach a minimum value (note that TIA is in an inverting configuration). All four channels do not reach this minimum value because, typically, 3 s LED pulse widths are used and the ADC samples the four channels sequentially at 1 s intervals. This procedure aligns the ADC sampling time with the LED pulse to measure the total amount of light falling on the photodetector (for example, background light + LED pulse). between the anode and cathode, or between the anode and some other supply or ground. In normal operation, the ambient rejection feature of the ADPD105/ADPD106/ADPD107 masks the primary effects of these resistances, making it very difficult to detect them. However, even at 1 M to 10 M, such resistance can impact performance significantly through added noise or decreased dynamic range. TIA ADC mode can be used to screen for these assembly issues. If this minimum value is above 0 LSB, the TIA is not saturated. However, take care, because even if the result is not 0 LSB, operating the device near saturation can quickly result in saturation if light conditions change. A safe operating region is typically at 3/4 full scale and lower. Use Table 26 to determine how the input codes map to ADC levels on a per channel per pulse basis. These codes are not the same as in normal mode because the band-pass filter and integrator are not unity-gain elements. Measuring Shunt Resistance on the Photodiode Coarse Ambient Light Measurement Using the typical values in Table 26, TIA ADC mode can be used to measure or quantify the amount of background or ambient light present on the photodetector. The settings are the same in the method described in the Protecting Against TIA Saturation in Normal Operation section, except the timing used in the normal operating mode is sufficient for this mode. There is no need to sweep SLOTx_AFE_OFFSET. If SLOTx_AFE_OFFSET is in the same place as the normal mode operation, the TIA ADC mode does not return the same value, regardless of whether the LED is on or off. In TIA_MODE, the dark level is a high level near 13,000 LSBs per channel per pulse (see Table 26). To measure this value, select no photodiode by writing a 0x0 to Register 0x14, Bits[11:8] for Time Slot B or Register 0x14, Bits[7:4] for Time Slot A. This setting internally opens the photodiode connection and gives a baseline LSB value that coincides with a zero signal input. After Register 0x14 is restored to its normal value, while connecting the photodiode to the TIA, this TIA ADC result can be subtracted from the open photodiode case to yield a background light measurement. Use Table 26 to translate this measurement into an input photocurrent. Use this result for coarse absolute measurements only, because it is typically only accurate to within 10%. Measuring PCB Parasitic Input Resistance During the process of mounting the ADPD105/ADPD106/ ADPD107, undesired resistance can develop on the inputs through assembly errors or debris on the PCB. These resistances can form A shunt resistor across the photodiode does not generally affect the output level of the device in operation because the effective impedance of the TIA is very low, especially if the photodiode is held to 0 V in operation. However, such resistance can add noise to the system, degrading performance. The best way to detect photodiode leakage, also called photodiode shunt resistance, is to place the device in TIA ADC mode in the dark and vary the operation mode cathode voltage. Setting the cathode to 1.3 V places 0 V across the photodiode because the anode is always at 1.3 V while in operation. Setting the cathode to 1.8 V places 0.5 V across the photodiode. Using the register settings in Table 3 to control the cathode voltage, measure the TIA ADC value at both voltages. Next, divide the voltage difference of 0.5 V by the difference of the ADC result after converting it to a current. This result is the approximate shunt resistance. Values greater than 10 M may be difficult to measure, but this method is useful in identifying gross failures. Measuring TIA Input Shunt Resistance A resistance to develop between the TIA input and another supply or ground on the PCB is an example of another problem that can occur. These resistances can force the TIA into saturation prematurely. This premature saturation, in turn, takes away dynamic range from the device in operation and adds a Johnson noise component to the input. To measure these resistances, place the device in TIA ADC mode in the dark and start by measuring the TIA ADC offset level with the photodiode inputs disconnected (Register 0x14, Bits[11:8] = 0 or Register 0x14, Bits[7:4] = 0). From this, subtract the value of TIA ADC mode with the darkened photodiode connected and convert the difference into a current. If the value is positive, and the ADC signal decreased, the resistance is to a voltage higher than 1.3 V, such as VDD. Current entering the TIA causes the output to drop. If the output difference is negative due to an increase of codes at the ADC, current is being pulled out of the TIA and there is a shunt resistance to a lower potential than 1.3 V, such as ground. Rev. A | Page 41 of 66 ADPD105/ADPD106/ADPD107 Data Sheet Table 26. Analog Specifications for TIA ADC and Digital Integrate Modes Parameter TIA ADC/Digital Integration Saturation Levels TIA ADC Resolution Output with No Input Photocurrent Test Conditions/Comments Values expressed per channel, per sample; TIA feedback resistor 25 k 50 k 100 k 200 k Values expressed per channel, per sample; TIA feedback resistor 25 k 50 k 100 k 200 k ADC offset (Register 0x18 to Register 0x21) = 0x0 DIGITAL INTEGRATE MODE Digital integrate mode is built into the ADPD105/ADPD106/ ADPD107 and allows the device to accommodate longer LED/AFE pulse widths and different types of sensors at the input. The analog integration mode described in the AFE Operation section is ideally suited for applications requiring a large LED duty cycle, or applications that require customization of the sampling scheme. Digital integrate mode allows the integration function to be performed after the ADC in the digital domain. This mode enables the device to handle a much wider range of sensors at the input. In digital integrate mode, the ADC performs a conversion every 1 s during the integration window. During the integration window, the digital engine either adds to or subtracts from the previous sample. The band-pass filter is bypassed and the integrator is converted to a voltage buffer, allowing the digital engine to perform the integration function. In this mode, after the timing is optimized, the output of the ADC increases as the light level on the photodiode increases. The integration window is a combination of negative and positive windows where the duration of these windows is set by SLOTx_ AFE_WIDTH. At the end of the digital integration window, the resulting sum is sent to the decimate unit as the sample for that LED pulse. There is one sample per time slot for every sample cycle. Table 27 lists the registers required for placing the device in digital integrate mode. There may also be changes needed in the SLOTx_AFE_OFFSET registers and FIFO configuration register (0x11). To read the final value through the FIFO, set the appropriate values in Register 0x11, Bits[4:2] for Time Slot A, and Register 0x11, Bits[8:6] for Time Slot B. Alternatively, the final output is also available through the data registers; Register 0x64, Register 0x70, and Register 0x74 for Time Slot A, and Register 0x68, Register 0x78, and Register 0x7C for Time Slot B. To put the ADPD105/ADPD106/ADPD107 into digital integration mode during Time Slot A, write 0x1 to Register 0x58, Bit 12. To put the ADPD105/ADPD106/ADPD107 into digital integration mode in Time Slot B, write 0x1 to Register 0x58, Bit 13. Typ Unit 38.32 19.16 9.58 4.79 A A A A 2.92 1.5 0.73 0.37 13,000 nA/LSB nA/LSB nA/LSB nA/LSB LSB The other writes required to switch to digital integration mode are listed in Table 27. When using digital integrate mode, up to two photodiodes can be connected to the ADPD105/ADPD106/ADPD107 inputs; one photodiode per PDx input group (PD1/PD2/PD3/PD4 or PD5/ PD6/PD7/PD8). Never connect the same photodiode across the two PDx groups. In digital integrate mode, there are options to connect the photodiode to all four AFE channels (PD1/PD2/PD3/ PD4 or PD5/PD6/PD7/PD8), or just a single AFE channel (PD1 or PD5). When connecting to a single AFE channel, write 0x1 to Register 0x54, Bit 14 for Time Slot A, or, for Time Slot B, write 0x1 to Register 0x54, Bit 15. When connecting to a single AFE channel, there is also an option to turn off Channel 2, Channel 3, and Channel 4 (and to save power) by writing 0x7 to Register 0x55, Bits[15:13]. When connecting to all four channels (PD1/PD2/PD3/PD4 or PD5/ PD6/PD7/PD8), write 0x0 (default)to Register 0x54, Bit 14 for Time Slot A, or write 0x0 (default) to Register 0x54, Bit 15 for Time Slot B. Ensure that all AFE channels are powered up by writing 0x0 to Register 0x55, Bits[15:13]. Connecting the single photodiode to a single AFE channel offers the best SNR performance in cases where signal is limited, whereas connecting the single photodiode to all four AFE channels offers the best dynamic range in cases where signal is large. Digital Integration Sampling Modes There are two sampling modes that can be used while the device is in digital integration mode. These modes are singlesample pair mode and double-sample pair mode. In single-sample pair mode, there is a single negative sample region and a single positive sample region, shown in Figure 48 and Figure 49. To use single-sample pair mode, write 0x1 to Register 5A, Bit 5 for Time Slot A, or Register 5A, Bit 6 for Time Slot B. The negative sample region starts at SLOTx_AFE_ OFFSET + 9 and its duration (the number of samples taken) is set by SLOTx_AFE_WIDTH. The positive sample region starts at SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_WIDTH, and its duration is also set by SLOTx_AFE_WIDTH. Set the timing such that the negative sample region falls entirely in the flat Rev. A | Page 42 of 66 Data Sheet ADPD105/ADPD106/ADPD107 (dark) portion of the LED response, whereas the positive sample region falls in the pulsed region of the LED response. Placing the LED pulse offset, SLOTx_LED_OFFSET, at the beginning of SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_WIDTH achieves this timing. The output is the difference of the signals in the two regions. Double-sample pair mode is another way to sample. In this mode, there are two negative sample regions and one long positive sample region (see Figure 46 and Figure 47). To use double-sample pair mode, write 0x0 to Register 0x5A, Bit 5 for Time Slot A, or Bit 6 for Time Slot B. The first negative sample region starts at SLOTx_AFE_OFFSET + 9 and its duration is set by SLOTx_AFE_WIDTH. The positive sample region starts at SLOTx_AFE_OFFSET + 9+ SLOTx_AFE_WIDTH and its duration is twice the SLOTx_AFE_WIDTH. After this, there is another negative sample region that starts at SLOTx_AFE_OFFSET + 9 + 3 x SLOTx_AFE_WIDTH, and its duration is SLOTx_AFE_ WIDTH. Set the timing such that both of the negative sample regions fall in the flat (dark) portion of the LED response and the positive sample region falls in the pulsed portion of the LED response. Placing the LED pulse offset, SLOTx_LED_OFFSET at the beginning of SLOTx_AFE_OFFSET + 9 + SLOTx_AFE_ WIDTH achieves this timing. The output is calculated by summing the response of all the regions in a negative/positive/ negative manner. The double-sample pair mode is useful for cases when the background light is not constant because it has better background rejection, but it also uses more power than singlesample pair mode. Sample Timing Modes There are two options for timing the sample regions: gapped mode and continuous mode. In gapped timing mode, there is a space between the negative and positive sample regions. The width of this region is specified by SLOTA_AFE_FOFFSET for Time Slot A and SLOTB_AFE_ FOFFSET for Time Slot B in 31.25 ns steps. To enable this feature, write 0x1 to Register 0x5A, Bit 7. This bit enables gapped timing for the time slot (or time slots) that are in digital integrate mode. This mode is helpful when there are unwanted transients in the LED response that must be ignored for an accurate output. If there are no concerns about LED response transients, select continuous timing mode. In this mode, there is no space between the negative and positive sample regions. Write 0x0 to Register 0x5A, Bit 7 for continuous timing of the sample regions. Background Values In digital integrate mode, the digital integration background value, DI_BACKGROUND, or dark values are also stored and available as output data. This is in addition to the output value during the LED pulse, DI_OUTPUT, which has the dark value subtracted. DI_BACKGROUND is the sum of the negative region samples. To include these values in the FIFO, set Register 0x11, Bits[4:2] for Time Slot A, and Register 0x11, Bits[8:6] for Time Slot B. For 16-bit data, set this value to 0x3; for 32-bit data, set this value to 0x04. These settings are also available through the data registers; Register 0x65, Register 0x71, and Register 0x75 for Time Slot A, and Register 0x69, Register 0x79, and Register 0x7D for Time Slot B. It is recommended that the channel offsets (Register 0x18 to Register 0x21) be set to 0x1F00 when including the background values in the FIFO in digital integration mode. These channel offsets do not affect the sample values, but do provide more headroom for the background values. Saturation Detection in Digital Integrate Mode In normal operation, when using the band-pass filter and the integrator, the ADC almost always saturates before the TIA. Unlike in normal operation, saturation of the TIA or the ADC cannot be detected solely by looking at the signal value where the signal value is the positive sample region minus the reference region in digital integrate mode. This is because the integrated value does not by itself contain any information indicating whether one of the ADC conversions during the integration period exceeded the ADC output range. As a result, the realtime output may have saturated only for a fraction of the ADC conversions within a sample and the final accumulated sum may not reflect this. To detect TIA saturation in digital integration mode, both the background values, DI_BACKGROUND, and the signal values, DI_OUTPUT, must be collected. Refer to the Background Values section for the correct settings for Register 0x11 that provide these values. For single-sample pair mode, saturation has occurred when (DI_OUTPUT/(min(SLOTx_LED_WIDTH, SLOTx_AFE_WIDTH)) + DI_BACKGROUND/ AFE_WIDTH)/NUM_PULSES > 0x3FFF For double-sample pair mode, saturation has occurred when Both gapped and continuous sample timing modes can be used with single-sample pair or double-sample pair mode. Example timing diagrams are shown in Figure 46, Figure 47, Figure 48, and Figure 49. Rev. A | Page 43 of 66 (DI_OUTPUT/(min(SLOTx_LED_WIDTH, 2 x SLOTx_AFE_WIDTH)) + DI_BACKGROUND/(2 x SLOTx_AFE_WIDTH))/NUM_PULSES > 0x3FFF ADPD105/ADPD106/ADPD107 Data Sheet LED SLOTx_AFE_OFFSET + 9 NEGATIVE SAMPLE REGION POSITIVE SAMPLE REGION NEGATIVE SAMPLE REGION 14693-039 SAMPLE Figure 46. Digital Integration Mode in Double-Sample Pair Mode with Continuous Sample Timing LED SAMPLE NEGATIVE SAMPLE REGION POSITIVE SAMPLE REGION SLOTx_AFE_FOFFSET NEGATIVE SAMPLE REGION SLOTx_AFE_FOFFSET 14693-040 SLOTx_AFE_OFFSET + 9 Figure 47. Digital Integration Mode in Double-Sample Pair Mode with Gapped Sample Timing LED SAMPLE NEGATIVE SAMPLE REGION POSITIVE SAMPLE REGION SLOTx_AFE_FOFFSET 14693-041 SLOTx_AFE_OFFSET + 9 Figure 48. Digital Integration Mode in Single-Sample Pair Mode with Gapped Sample Timing LED SLOTx_AFE_OFFSET + 9 NEGATIVE SAMPLE REGION POSITIVE SAMPLE REGION Figure 49. Digital Integration Mode in Single-Sample Pair Mode with Continuous Sample Timing Rev. A | Page 44 of 66 14693-042 SAMPLE Data Sheet ADPD105/ADPD106/ADPD107 Table 27. Configuration Registers to Switch Between the Normal Sample Mode, TIA ADC Mode, and Digital Integration Mode Bit Name SLOTA_AFE_MODE Normal Mode Value 0x1C TIA ADC Mode Value Not applicable Digital Integration Mode Value 0x1D 7 SLOTA_INT_AS_BUF 0x0 0x1 Not applicable 0x43 [15:0] SLOTA_AFE_CFG 0xADA5 0xAE65 0xAE65 0x44 [15:8] SLOTB_AFE_MODE 0x1C Not applicable 0x1D 7 SLOTB_INT_AS_BUF 0x0 0x1 Not applicable 0x45 [15:0] SLOTB_AFE_CFG 0xADA5 0xAE65 0xAE65 0x4E [15:0] ADC_TIMING Not applicable 0x0040 0x58 13 SLOTB_DIGITAL_INT_EN Not applicable 0x0 0x0 0x1 12 SLOTA_DIGITAL_INT_EN 0x0 0x0 0x1 [15:0] DIG_INT_CFG Not applicable Not applicable Variable Address 0x42 0x5A Data Bits [15:8] PULSE CONNECT MODE In pulse connect mode, the photodiode input connections are pulsed according to the timing set up in the LED pulse timing registers. In this mode, if the LED pulse timing is set up to provide a 2 s LED pulse, the device pulses the connection to the photodiode input for 2 s instead of providing a 2 s LED pulse. This mode is an alternate to TIA ADC mode, allowing the entire signal path, including the band-pass filter and integrator, to be used to measure ambient light as well as other types of measurements with different types of sensors (for example, ECGs). Description In normal mode, this setting configures the integrator block for optimal operation. In digital integration mode, this setting configures the integrator block as a buffer. This setting is not important for TIA ADC mode. 0: normal integrator configuration. 1: convert integrator to buffer amplifier (this is done automatically in digital integrate mode). Time Slot A AFE connection. 0xAE65 bypasses the band-pass filter. 0xB065 can also be used in TIA ADC mode. This setting bypasses the BPF and the integrator. In normal mode, this setting configures the integrator block for optimal operation. In digital integration mode, this setting configures the integrator block as a buffer. This setting is not important for TIA ADC mode. 0: normal integrator configuration. 1: convert integrator to buffer amplifier (this is done automatically in digital integrate mode). Time Slot B AFE connection. 0xAE65 bypasses the band-pass filter. 0xB065 can also be used in TIA ADC mode. This setting bypasses the BPF and the integrator. Set ADC clock to 1 MHz in TIA ADC mode. Digital integrate mode enable, Time Slot B. 0: disable. 1: enable. Digital integrate mode enable, Time Slot A. 0: disable. 1: enable. Configuration of digital integration depends on the use case. This register is ignored for other modes. To enable pulse connect mode, the device is configured identically to normal mode, except that Register 0x14, Bits[3:2] = 0 for Time Slot B, and Register 0x14, Bits[1:0] = 0 for Time Slot A. SYNCHRONOUS ECG AND PPG MEASUREMENT USING TIA ADC MODE In wearable devices developed for monitoring the health care of patients, it is often necessary to have synchronized measurements of biomedical signals. For example, a synchronous measurement of patient ECG and PPG can be used to determine the pulse wave transit time (PWTT), which can then be used to estimate blood pressure. Rev. A | Page 45 of 66 ADPD105/ADPD106/ADPD107 Data Sheet ECG measurements. Data can be read out of the on-chip FIFO or straight from data registers. The ADPD105 channel used to process the ECG signal is set up in TIA ADC mode and the input bias voltage must be set to the 0.90 V setting using Bits[5:4] of Register 0x42 if the ECG signal is on Time Slot A, or Register 0x44 on Time Slot B. The TIA gain setting can be set to optimize the dynamic range of the signal path. The channel used to process the PPG signal is configured in its normal operating mode. Figure 51 shows a plot of a synchronized ECG and PPG measurement using the AD8233 with the ADPD105. The circuit shown in Figure 50 shows a synchronous ECG and PPG measurement using the AD8233 and the ADPD105. The AD8233 implements a two-pole high-pass filter with a cutoff frequency at 0.3 Hz, and a two-pole low-pass filter with a cutoff frequency of 37 Hz. The output of the AD8233 is fed to one of the current inputs of the ADPD105 through a 50 k resistor to convert the voltage output of the AD8233 into a current. The ADPD105 is configured to alternately measure the photodiode signal and the ECG signal from the AD8233 on consecutive timeslots to provide fully synchronized PPG and 1.8V 4.7F 10M 180k 4.7F -IN REFIN 0.1F 10M 0.1F 1nF RLD 1M GND AD8233 1.8V FR OPAMP+ AC/DC REFOUT SDN OPAMP- RLD SDN 6.8nF 250k TO DIGITAL INTERFACE LOD ADPD105 50k 1.8V DVDD PD1-2 0.1F AVDD VLED PDC 0.1F AGND DGND LGND PD3-4 1.8V 10k 10k LEDX1 SCL VREF 1F SDA TO DIGITAL INTERFACE GPIO0 GPIO1 Figure 50. Synchronized PPG and ECG Measurement Using ADPD105 with the AD8233 10000 52000 9500 PPG 8500 8000 51000 ECG 7500 ECG (LSBs) 9000 51500 7000 50500 6500 50000 SAMPLE RATE (ms) Figure 51. Plot of Synchronized ECG and PPG Waveforms Rev. A | Page 46 of 66 14693-044 343 325 307 289 271 253 235 127 91 109 73 55 37 6000 14693-043 OUT 1 1M 19 2.7nF 217 100k 10M +VS RLDFB SW 1M 1.8V 199 360k IAOUT PPG (LSBs) RL 10M +IN 181 RA HPSENSE 163 LA HPDRIVE 180k 145 10M Data Sheet ADPD105/ADPD106/ADPD107 In some situations, as in a case where a synchronized ECG and PPG measurement is being attempted, a voltage measurement must be made using the current inputs of the ADPD105/ ADPD106/ADPD107. First, convert the voltage source to a current by placing a series resistor, RS, in series between the voltage source and the current input of the device, as shown in Figure 52. voltage source through a series resistance, RIN must be taken into consideration. The conversion gain from a voltage into a current can be determined by following the schematic in Figure 52. IIN = (VIN - TIA_VREF)/(RS + RIN) Typically, RIN is approximately 13 k. The value of RIN varies as a function of supply voltage. This variability is shown in Figure 53 45 +85C +25C 0C -40C 40 ADPD105/ADPD106/ ADPD107 RIN IIN TIA_VREF TIA ADC Figure 52. Using the ADPD105/ADPD106/ADPD107 Inputs with Voltage Sources Secondly, there is a switch resistance, RIN, that must be taken into consideration when converting a voltage source to a current. This switch resistance is not a factor in a typical photodiode application since the device is only dealing with input currents and these currents are not a function of the input resistance. However, when driving the device inputs from a MEASURED R IN (k) RS 14693-108 VIN 35 30 25 20 15 10 5 0 1.70 1.75 1.80 1.85 VDD SUPPLY VOLTAGE (V) 1.90 1.95 14693-112 Measuring Voltages Using the Current Inputs Figure 53. Variability of Switch Input Resistance as a Function of VDD Supply Voltage Rev. A | Page 47 of 66 ADPD105/ADPD106/ADPD107 Data Sheet REGISTER LISTING Table 28. Numeric Register Listing1 Hex. Addr. Name 0x00 Status 0x01 0x02 0x06 INT_MASK GPIO_DRV FIFO_ THRESH 0x08 DEVID 0x09 I2CS_ID 0x0A CLK_RATIO 0x0B GPIO_CTRL 0x0D SLAVE_ ADDRESS_ KEY SW_RESET 0x0F 0x10 Mode 0x11 SLOT_EN 0x12 FSAMPLE 0x14 PD_LED_ SELECT 0x15 NUM_AVG 0x18 SLOTA_CH1_ OFFSET 0x19 SLOTA_CH2_ OFFSET 0x1A SLOTA_CH3_ OFFSET 0x1B SLOTA_CH4_ OFFSET 0x1E SLOTB_CH1_ OFFSET 0x1F SLOTB_CH2_ OFFSET 0x20 SLOTB_CH3_ OFFSET 0x21 SLOTB_CH4_ OFFSET Bit 15 Bit 7 Bits [15:8] [7:0] Reserved [15:8] Bit 14 Bit 6 Bit 13 Bit 5 SLOTB_INT SLOTA_INT [7:0] SLOTB_INT_ MASK [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] Reserved Bit 12 Bit 11 Bit 4 Bit 3 FIFO_SAMPLES[7:0] Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Reset 0x0000 RW R/W 0x00FF R/W GPIO1_POL 0x0000 GPIO0_POL 0x0000 R/W Reserved Reserved FIFO_INT_ MASK Reserved SLOTA_INT_ MASK Reserved Reserved GPIO0_ENA FIFO_THRESH[5:0] Reserved GPIO1_DRV GPIO0_DRV Reserved REV_NUM[7:0] DEV_ID[7:0] ADDRESS_WRITE_KEY[7:0] SLAVE_ADDRESS[6:0] Reserved R/W 0x0516 R 0x00C8 R/W 0x0000 R 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x1000 R/W 0x0028 R/W 0x0541 R/W 0x0600 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x2000 RW Reserved CLK_RATIO[11:8] CLK_RATIO[7:0] Reserved Reserved GPIO1_ALT_CFG[4:0] GPIO0_ALT_CFG[4:0] SLAVE_ADDRESS_KEY[15:8] SLAVE_ADDRESS_KEY[7:0] Reserved Reserved Reserved Reserved Reserved RDOUT_ FIFO_OVRN_ MODE PREVENT SW_RESET Reserved Mode[1:0] SLOTB_ FIFO_ MODE[2] Reserved SLOTA_EN [7:0] SLOTB_FIFO_MODE[1:0] SLOTB_EN SLOTA_FIFO_MODE[2:0] [15:8] FSAMPLE[15:8] [7:0] FSAMPLE[7:0] [15:8] Reserved SLOTB_PD_SEL[3:0] [7:0] SLOTA_PD_SEL[3:0] SLOTB_LED_SEL[1:0] SLOTA_LED_SEL[1:0] [15:8] Reserved SLOTB_NUM_AVG[2:0] [7:0] Reserved SLOTA_NUM_AVG[2:0] Reserved [15:8] SLOTA_CH1_OFFSET[15:8] [7:0] SLOTA_CH1_OFFSET[7:0] [15:8] SLOTA_CH2_OFFSET[15:8] [7:0] SLOTA_CH2_OFFSET[7:0] [15:8] SLOTA_CH3_OFFSET[15:8] [7:0] SLOTA_CH3_OFFSET[7:0] [15:8] SLOTA_CH4_OFFSET[15:8] [7:0] SLOTA_CH4_OFFSET[7:0] [15:8] SLOTB_CH1_OFFSET[15:8] [7:0] SLOTB_CH1_OFFSET[7:0] [15:8] SLOTB_CH2_OFFSET[15:8] [7:0] SLOTB_CH2_OFFSET[7:0] [15:8] SLOTB_CH3_OFFSET[15:8] [7:0] SLOTB_CH3_OFFSET[7:0] [15:8] SLOTB_CH4_OFFSET[15:8] [7:0] SLOTB_CH4_OFFSET[7:0] Rev. A | Page 48 of 66 Data Sheet ADPD105/ADPD106/ADPD107 Hex. Addr. Name 0x22 ILED3_ COARSE 0x23 0x24 0x25 0x30 0x31 0x34 0x35 0x36 0x37 0x38 0x39 0x3B 0x3C Bits [15:8] [7:0] [15:8] ILED1_ COARSE [7:0] [15:8] ILED2_ COARSE [7:0] ILED_FINE [15:8] [7:0] SLOTA_LED_ [15:8] PULSE [7:0] [15:8] SLOTA_ NUMPULSES [7:0] [15:8] LED_ DISABLE [7:0] SLOTB_LED_ [15:8] PULSE [7:0] [15:8] SLOTB_ NUMPULSES [7:0] [15:8] ALT_PWR_ DN [7:0] EXT_SYNC_ [15:8] STARTUP [7:0] SLOTA_AFE_ [15:8] WINDOW [7:0] SLOTB_AFE_ [15:8] WINDOW [7:0] [15:8] AFE_PWR_ CFG1 0x42 SLOTA_ TIA_CFG 0x43 SLOTA_ AFE_CFG 0x44 SLOTB_ TIA_CFG 0x45 SLOTB_ AFE_CFG 0x4B SAMPLE_ CLK 0x4D 0x4E 0x4F 0x50 0x54 [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] ADC_CLOCK [15:8] [7:0] EXT_SYNC_ [15:8] SEL [7:0] [15:8] CLK32M_ CAL_EN [7:0] CLK32M_ ADJUST AFE_PWR_ CFG2 [15:8] [7:0] 0x55 TIA_INDEP_ GAIN [15:8] [7:0] Bit 15 Bit 7 Bit 14 Bit 6 Reserved Reserved Reserved Reserved Reserved Reserved ILED2_FINE[1:0] Reserved Bit 13 Bit 12 Bit 5 Bit 4 ILED3_SCALE ILED3_SLEW[2:0] ILED1_SCALE ILED1_SLEW[2:0] ILED2_SCALE Reserved ILED2_SLEW[2:0] ILED3_FINE[4:0] Reserved Bit 11 Bit 3 Bit 10 Bit 9 Bit 2 Bit 1 Reserved ILED3_COARSE[3:0] Reserved ILED1_COARSE[3:0] Bit 8 Bit 0 ILED2_COARSE[3:0] ILED2_FINE[4:2] ILED1_FINE[4:0] SLOTA_LED_WIDTH[4:0] SLOTA_LED_OFFSET[7:0] SLOTA_LED_NUMBER[7:0] SLOTA_LED_PERIOD[7:0] Reserved SLOTB_ LED_DIS SLOTA_ LED_DIS Reset 0x3000 RW R/W 0x3000 R/W 0x3000 R/W 0x630C R/W 0x0320 R/W 0x0818 R/W 0x0000 R/W 0x0320 R/W 0x0818 R/W 0x0000 R/W 0x000 R/W 0x22FC R/W 0x22FC R/W 0x3006 R/W 0x1C38 R/W Reserved Reserved SLOTB_LED_WIDTH[4:0] SLOTB_LED_OFFSET[7:0] SLOTB_LED_NUMBER[7:0] SLOTB_LED_PERIOD[7:0] CH34_DISABLE[15:13] CH2_DISABLE[12:10] Reserved Reserved EXT_SYNC_STARTUP[15:8] EXT_SYNC_STARTUP[7:0] SLOTA_AFE_WIDTH[4:0] SLOTA_AFE_OFFSET[5:3] SLOTA_AFE_OFFSET[2:0] SLOTA_AFE_FOFFSET[4:0] SLOTB_AFE_WIDTH[4:0] SLOTB_AFE_OFFSET[5:3] SLOTB_AFE_OFFSET[2:0] SLOTB_AFE_FOFFSET[4:0] Reserved Reserved Reserved V_CATHODE AFE_ POWERDOWN[5] AFE_POWERDOWN[4:0] Reserved SLOTA_AFE_MODE[7:0] SLOTA_TIA_VBIAS[1:0] Reserved (write 0x1) SLOTA_TIA_GAIN[1:0] SLOTA_INT_ SLOTA_TIA_ AS_BUF IND_EN SLOTA_AFE_CFG[15:8] SLOTA_AFE_CFG[7:0] SLOTB_AFE_MODE[7:0] SLOTB_TIA_VBIAS[1:0] Reserved (write 0x1) SLOTB_TIA_GAIN[1:0] SLOTB_INT_ SLOTB_ AS_BUF TIA_IND_EN SLOTB_AFE_CFG[15:8] SLOTB_AFE_CFG[7:0] Reserved CLK32K_ BYP CLK32K_EN Reserved CLK32K_ADJUST[5:0] Reserved CLK32M_ADJUST[7:0] ADC_TIMING[15:8] ADC_TIMING[7:0] Reserved Reserved GPIO1_OE GPIO1_IE Reserved EXT_SYNC_SEL[1:0] GPIO0_IE Reserved Reserved Reserved GPIO1_CTRL Reserved CLK32M_ CAL_EN SLEEP_V_CATHODE [1:0] SLOTB_V_CATHODE[1:0] SLOTA_V_CATHODE[1:0] SLOTB_ SLOTA_ SINGLE_CH_ SINGLE_CH_ DIG_INT DIG_INT Reserved REG54_VCAT_ ENABLE DIGINT_POWER[2:0] Reserved SLOTB_TIA_GAIN_4[1:0] SLOTB_TIA_GAIN_3[1:0] SLOTB_TIA_GAIN_2[1:0] SLOTA_TIA_GAIN_4[1:0] SLOTA_TIA_GAIN_3[1:0] SLOTA_TIA_GAIN_2[1:0] Rev. A | Page 49 of 66 0xADA5 R/W 0x1C38 R/W 0xADA5 R/W 0x2612 R/W 0x0098 R/W 0x0060 R/W 0x2090 R/W 0x0000 R/W 0x0020 R/W 0x0000 R/W ADPD105/ADPD106/ADPD107 Hex. Addr. Name 0x58 DIGITAL_ INT_EN 0x5A 0x5F DIG_ INT_CFG Bit 15 Bit 7 Bits [15:8] [7:0] [15:8] [7:0] DIG_INT_ GAPMODE [15:8] DATA_ ACCESS_CTL [7:0] 0x60 FIFO_ ACCESS 0x64 SLOTA_ PD1_16BIT 0x65 SLOTA_ PD2_16BIT 0x66 SLOTA_ PD3_16BIT 0x67 SLOTA_ PD4_16BIT 0x68 SLOTB_ PD1_16BIT 0x69 SLOTB_ PD2_16BIT 0x6A SLOTB_ PD3_16BIT 0x6B SLOTB_ PD4_16BIT 0x70 A_PD1_ LOW 0x71 A_PD2_ LOW 0x72 A_PD3_ LOW 0x73 A_PD4_ LOW 0x74 A_PD1_ HIGH 0x75 A_PD2_ HIGH 0x76 A_PD3_ HIGH 0x77 A_PD4_ HIGH 0x78 B_PD1_ LOW 0x79 B_PD2_ LOW 0x7A B_PD3_ LOW 0x7B B_PD4_ LOW 0x7C B_PD1_ HIGH 0x7D B_PD2_ HIGH [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 14 Bit 6 Reserved SLOTB_DIG_ INT_SAMPLE_ MODE Data Sheet Bit 13 Bit 5 SLOTB_ DIGITAL_ INT_EN Bit 12 Bit 11 Bit 4 Bit 3 SLOTA_ DIGITAL_INT_ EN Reserved Reserved Bit 10 Bit 2 Bit 9 Bit 1 Reserved Bit 8 Bit 0 Reset 0x0000 RW R/W 0x0000 R/W 0x0000 R/W 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R Reserved SLOTA_DIG_ INT_SAMPLE_ MODE Reserved Reserved SLOTB_ DATA_ HOLD FIFO_DATA[15:8] FIFO_DATA[7:0] SLOTA_CH1_16BIT[15:8] SLOTA_CH1_16BIT[7:0] SLOTA_CH2_16BIT[15:8] SLOTA_CH2_16BIT[7:0] SLOTA_CH3_16BIT[15:8] SLOTA_CH3_16BIT[7:0] SLOTA_CH4_16BIT[15:8] SLOTA_CH4_16BIT[7:0] SLOTB_CH1_16BIT[15:8] SLOTB_CH1_16BIT[7:0] SLOTB_CH2_16BIT[15:8] SLOTB_CH2_16BIT[7:0] SLOTB_CH3_16BIT[15:8] SLOTB_CH3_16BIT[7:0] SLOTB_CH4_16BIT[15:8] SLOTB_CH4_16BIT[7:0] SLOTA_CH1_LOW[15:8] SLOTA_CH1_LOW[7:0] SLOTA_CH2_LOW[15:8] SLOTA_CH2_LOW[7:0] SLOTA_CH3_LOW[15:8] SLOTA_CH3_LOW[7:0] SLOTA_CH4_LOW[15:8] SLOTA_CH4_LOW[7:0] SLOTA_CH1_HIGH[15:8] SLOTA_CH1_HIGH[7:0] SLOTA_CH2_HIGH[15:8] SLOTA_CH2_HIGH[7:0] SLOTA_CH3_HIGH[15:8] SLOTA_CH3_HIGH[7:0] SLOTA_CH4_HIGH[15:8] SLOTA_CH4_HIGH[7:0] SLOTB_CH1_LOW[15:8] SLOTB_CH1_LOW[7:0] SLOTB_CH2_LOW[15:8] SLOTB_CH2_LOW[7:0] SLOTB_CH3_LOW[15:8] SLOTB_CH3_LOW[7:0] SLOTB_CH4_LOW[15:8] SLOTB_CH4_LOW[7:0] SLOTB_CH1_HIGH[15:8] SLOTB_CH1_HIGH[7:0] SLOTB_CH2_HIGH[15:8] SLOTB_CH2_HIGH[7:0] Rev. A | Page 50 of 66 SLOTA_ DATA_ HOLD DIGITAL_ CLOCK_ ENA Data Sheet Hex. Addr. Name 0x7E B_PD3_ HIGH 0x7F 1 B_PD4_ HIGH ADPD105/ADPD106/ADPD107 Bit 15 Bit 7 Bits [15:8] [7:0] [15:8] [7:0] Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 11 Bit 4 Bit 3 SLOTB_CH3_HIGH[15:8] SLOTB_CH3_HIGH[7:0] SLOTB_CH4_HIGH[15:8] SLOTB_CH4_HIGH[7:0] Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Reset 0x0000 RW R 0x0000 R The recommended values are not shown. Only power-on reset values are shown in Table 28. The recommended values are largely dependent on use case. See Table 29 to Table 35 for the recommended values. Rev. A | Page 51 of 66 ADPD105/ADPD106/ADPD107 Data Sheet LED CONTROL REGISTERS Table 29. LED Control Registers Address 0x14 0x22 Data Bit [15:12] [11:8] Default Value 0x0 0x5 Access R/W R/W Name Reserved SLOTB_PD_SEL [7:4] 0x4 R/W SLOTA_PD_SEL [3:2] 0x0 R/W SLOTB_LED_SEL [1:0] 0x1 R/W SLOTA_LED_SEL [15:14] 13 0x0 0x1 R/W R/W Reserved ILED3_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED3_SLEW [3:0] 0x0 R/W ILED3_COARSE Description Write 0x0 to these bits for proper operation. PDx connection selection for Time Slot B. See Figure 22 and Figure 23 0x0: all photodiode inputs are floating. 0x1: all photodiode inputs are connected during Time Slot B. 0x5: PD1/PD2/PD3/PD4 are connected during Time Slot B. Other: reserved. PDx connection selection for Time Slot A. See Figure 22 and Figure 23. 0x0: all photodiode inputs are floating. 0x1: all photodiode inputs are connected during Time Slot A. 0x5: PD1/PD2/PD3/PD4 are connected during Time Slot A. Other: reserved. Time Slot B LED configuration. These bits determine which LED is associated with Time Slot B. 0x0: pulse PDx connection to AFE. 0x1: LEDX1 pulses during Time Slot B. 0x2: LEDX2 pulses during Time Slot B. 0x3: LEDX3 pulses during Time Slot B. Time Slot A LED configuration. These bits determine which LED is associated with Time Slot A. 0x0: pulse PDx connection to AFE. 0x1: LEDX1 pulses during Time Slot A. 0x2: LEDX2 pulses during Time Slot A. 0x3: LEDX3 pulses during Time Slot A. Write 0x0. LEDX3 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX3 driver in low power mode. LEDX3 Current Scale = 0.4 + 0.6 x (Register 0x22, Bit 13). Write 0x1. Write 0x0. LEDX3 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0x0: the slowest slew rate. ... 0x7: the fastest slew rate. LEDX3 coarse current setting. Coarse current sink target value of LEDX3 in standard operation. 0x0: lowest coarse setting. ... 0xF: highest coarse setting. LED3PEAK = LED3COARSE x LED3FINE x LED3SCALE where: LED3PEAK is the LEDX3 peak target value (mA). LED3COARSE = 50.3 + 19.8 x (Register 0x22, Bits[3:0]). LED3FINE = 0.74 + 0.022 x (Register 0x25, Bits[15:11]). LED3SCALE = 0.4 + 0.6 x (Register 0x22, Bit 13). Rev. A | Page 52 of 66 Data Sheet Address 0x23 0x24 ADPD105/ADPD106/ADPD107 Data Bit [15:14] 13 Default Value 0x0 0x1 Access R/W R/W Name Reserved ILED1_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED1_SLEW [3:0] 0x0 R/W ILED1_COARSE [15:14] 13 0x0 0x1 R/W R/W Reserved ILED2_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED2_SLEW [3:0] 0x0 R/W ILED2_COARSE Description Write 0x0. LEDX1 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX1 driver in low power mode. LEDX1 Current Scale = 0.4 + 0.6 x (Register 0x23, Bit 13). Write 0x1. Write 0x0. LEDX1 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0: the slowest slew rate. ... 7: the fastest slew rate. LEDX1 coarse current setting. Coarse current sink target value of LEDX1 in standard operation. 0x0: lowest coarse setting. ... 0xF: highest coarse setting. LED1PEAK = LED1COARSE x LED1FINE x LED1SCALE where: LED1PEAK is the LEDX1 peak target value (mA). LED1COARSE = 50.3 + 19.8 x (Register 0x23, Bits[3:0]). LED1FINE = 0.74 + 0.022 x (Register 0x25, Bits[4:0]). LED1SCALE = 0.4 + 0.6 x (Register 0x23, Bit 13). Write 0x0. LEDX2 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX2 driver in low power mode. LED2 Current Scale = 0.4 + 0.6 x (Register 0x24, Bit 13) Write 0x1. Write 0x0. LEDX2 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0: the slowest slew rate. ... 7: the fastest slew rate. LEDX2 coarse current setting. Coarse current sink target value of LEDX2 in standard operation. 0x0: lowest coarse setting. ... 0xF: highest coarse setting. LED2PEAK = LED2COARSE x LED2FINE x LED2SCALE where: LED2PEAK is the LEDX2 peak target value (mA). LED2COARSE = 50.3 + 19.8 x (Register 0x24, Bits[3:0]). LED2FINE = 0.74 + 0.022 x (Register 0x25, Bits[10:6]). LED2SCALE = 0.4 + 0.6 x (Register 0x24, Bit 13). Rev. A | Page 53 of 66 ADPD105/ADPD106/ADPD107 Address 0x25 0x30 0x31 0x34 0x35 0x36 Data Sheet Data Bit [15:11] Default Value 0xC Access R/W Name ILED3_FINE [10:6] 0xC R/W ILED2_FINE 5 [4:0] 0x0 0xC R/W R/W Reserved ILED1_FINE [15:13] [12:8] [7:0] [15:8] 0x0 0x3 0x20 0x08 R/W R/W R/W R/W Reserved SLOTA_LED_WIDTH SLOTA_LED_OFFSET SLOTA_LED_NUMBER [7:0] [15:10] 9 0x18 0x00 0x0 R/W R/W R/W SLOTA_LED_PERIOD Reserved SLOTB_LED_DIS 8 0x0 R/W SLOTA_LED_DIS [7:0] [15:13] [12:8] [7:0] [15:8] 0x00 0x0 0x3 0x20 0x08 R/W R/W R/W Reserved Reserved SLOTB_LED_WIDTH SLOTB_LED_OFFSET SLOTB_LED_NUMBER [7:0] 0x18 R/W SLOTB_LED_PERIOD Description LEDX3 fine adjust. Current adjust multiplier for LED3. LEDX3 fine adjust = 0.74 + 0.022 x (Register 0x25, Bits[15:11]). See Register 0x22, Bits[3:0], for the full LED3 formula. LEDX2 fine adjust. Current adjust multiplier for LED2. LEDX2 fine adjust = 0.74 + 0.022 x (Register 0x25, Bits[10:6]). See Register 0x24, Bits[3:0], for the full LED2 formula. Write 0x0. LEDX1 fine adjust. Current adjust multiplier for LED1. LEDX1 fine adjust = 0.74 + 0.022 x (Register 0x25, Bits[4:0]). See Register 0x23, Bits[3:0], for the full LED1 formula. Write 0x0. LED pulse width (in 1 s step) for Time Slot A. LED offset width (in 1 s step) for Time Slot A. LED Time Slot A pulse count. nA: number of LED pulses in Time Slot A. This is typically LED1. Adjust in the application. A setting of six pulses (0x06) is typical. LED Time Slot A pulse period (in 1 s step). Write 0x0. Time Slot B LED disable. 1: disables the LED assigned to Time Slot B. Register 0x34 keeps the drivers active and prevents them from pulsing current to the LEDs. Disabling both LEDs via this register is often used to measure the dark level. Use Register 0x11 instead to enable or disable the actual time slot usage and not only the LED. Time Slot A LED disable. 1: disables the LED assigned to Time Slot A. Use Register 0x11 instead to enable or disable the actual time slot usage and not only the LED. Write 0x00. Write 0x0. LED pulse width (in 1 s step) for Time Slot B. LED offset width (in 1 s step) for Time Slot B. LED Time Slot B pulse count. nB: number of LED pulses in Time Slot B. This is typically LED2. A setting of six pulses (0x06) is typical. LED Time Slot B pulse period (in 1 s step). AFE GLOBAL CONFIGURATION REGISTERS Table 30. AFE Global Configuration Registers Address 0x37 Data Bit [15:13] Default Value 0x0 Access R/W Name CH34_DISABLE [12:10] 0x0 R/W CH2_DISABLE [9:0] 0x000 R/W Reserved Rev. A | Page 54 of 66 Description Power-down options for Channel 3 and Channel 4 only. Bit 13: power down Channel 3, Channel 4 TIA op amp. Bit 14: power down Channel 3, Channel 4 BPF op amp. Bit 15: power down Channel 3, Channel 4 integrator op amp. Bit 10: power down Channel 2 TIA op amp. Bit 11: power down Channel 2 BPF op amp. Bit 12: power down Channel 2 integrator op amp. Write 0x000. Data Sheet Address 0x3C 0x54 ADPD105/ADPD106/ADPD107 Data Bit [15:14] [13:11] 10 9 Default Value 0x0 0x6 0x0 0x0 Access R/W R/W R/W R/W Name Reserved Reserved Reserved V_CATHODE [8:3] 0x00 R/W AFE_POWERDOWN [2:0] 15 0x6 0x0 R/W R/W Reserved SLOTB_SINGLE_CH_DIG_INT 14 0x0 R/W SLOTA_SINGLE_CH_DIG_INT [13:12] 0x0 R/W SLEEP_V_CATHODE [11:10] 0x0 R/W SLOTB_V_CATHODE [9:8] 0x0 R/W SLOTA_V_CATHODE 7 0x0 R/W REG54_VCAT_ENABLE [6:0] 0x20 R/W Reserved Rev. A | Page 55 of 66 Description Write 0x0. Write 0x6. Reserved. 0x0: 1.3 V (identical to anode voltage); recommended setting. 0x1: 1.8 V (reverse bias photodiode by 550 mV). This setting may add noise. AFE channels power-down select. 0x0: keeps all channels on. Bit 3: power down Channel 1 TIA op amp. Bit 4: power down Channel 1 BPF op amp. Bit 5: power down Channel 1 integrator op amp. Bit 6: power down Channel 2, Channel 3, and Channel 4 TIA op amp. Bit 7: power down Channel 2, Channel 3, and Channel 4 BPF op amp. Bit 8: power down Channel 2, Channel 3, and Channel 4 integrator op amp. Write 0x6. 0: in Time Slot B, use all four photodiode channels in parallel for digital integration (default setting for highest dynamic range). 1: in Time Slot B, use only Channel 1 for digital integration. This limits connection to PD1 or PD5. 0: in Time Slot A, use all four photodiode channels in parallel for digital integration (default setting for highest dynamic range) 1: in Time Slot A, use only Channel 1 for digital integration. This limits connection to PD1 or PD5. If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in sleep mode. The anode voltage is always set to the cathode voltage in sleep mode. 0x0: VDD (1.8 V). 0x1: 1.3 V. 0x2: 1.55 V. 0x3: 0.0 V. If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in Time Slot B operation. The anode voltage is always 1.3 V in Time Slot B mode. 0x0: VDD (1.8 V). 0x1: 1.3 V. 0x2: 1.55 V. 0x3: 0.0 V (this forward biases a diode at the input). If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in Time Slot A operation. The anode voltage is always 1.3 V in Time Slot A mode. 0x0: VDD (1.8 V). 0x1: 1.3 V. 0x2: 1.55 V. 0x3: 0.0 V (this forward biases a diode at the input). 0: use the cathode voltage settings defined by Register 0x3C, Bit 9. 1: override Register 0x3C, Bit 9 with cathode settings defined by Register 0x54, Bits[13:8]. Reserved. ADPD105/ADPD106/ADPD107 Address 0x58 0x5A Data Sheet Data Bit [15:14] 13 Default Value 0x0 0x0 Access R/W R/W Name Reserved SLOTB_DIGITAL_INT_EN 12 0x0 R/W SLOTA_DIGITAL_INT_EN [11:0] [15:8] 7 0x000 0x00 0x0 R/W R/W R/W Reserved Reserved DIG_INT_GAPMODE 6 0x0 R/W SLOTB_DIG_INT_SAMPLE_ MODE 5 0x0 R/W SLOTA_DIG_INT_SAMPLE_ MODE [4:0] 0x00 R/W Reserved Description Reserved. 0x0: Time Slot B operating in normal mode. 0x1: Time Slot B operating in digital integration mode. 0x0: Time Slot A operating in normal mode. 0x1: Time Slot A operating in digital integration mode. Reserved. Write 0x0. Digital integrate gapped mode enable. 0: no gap between negative and positive sample regions. 1: use SLOTA_AFE_FOFFSET for Time Slot A or SLOTB_AFE_ FOFFSET for Time Slot B to specify the gap in s. Digital integrate single sample pair mode for Time Slot B. 0: double sample pair mode. 1: single sampled pair mode. Digital integrate single sample pair mode for Time Slot A. 0: double sample pair mode. 1: single sampled pair mode. Write 0x00. Table 31. AFE Configuration Registers, Time Slot A Address 0x39 0x42 Data Bit [15:11] [10:5] Default Value 0x4 0x17 Access R/W R/W Name SLOTA_AFE_WIDTH SLOTA_AFE_OFFSET [4:0] 0x1C R/W SLOTA_AFE_FOFFSET [15:8] 0x1C R/W SLOTA_AFE_MODE 7 0x0 R/W SLOTA_INT_AS_BUF 6 0x0 R/W SLOTA_TIA_IND_EN [5:4] 0x3 R/W SLOTA_TIA_VBIAS [3:2] [1:0] 0x2 0x0 R/W R/W Reserved SLOTA_TIA_GAIN Rev. A | Page 56 of 66 Description AFE integration window width (in 1 s step) for Time Slot A. AFE integration window coarse offset (in 1 s step) for Time Slot A. AFE integration window fine offset (in 31.25 ns step) for Time Slot A. 0x1C: Time Slot A AFE setting for normal mode. All four blocks of the signal chain are in use during normal mode (the TIA, the BPF, followed by the integrator, and finally the ADC). 0x1D: Time Slot A AFE setting for digital integrate mode. 0: normal integrator configuration. 1: converts integrator to buffer amplifier (this is done automatically in digital integrate mode). Enable Time Slot A TIA gain individual settings. When it is enabled, the Channel 1 TIA gain is set via Register 0x42, Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set via Register 0x55, Bits[5:0]. 0: disable TIA gain individual setting. 1: enable TIA gain individual setting. Set VBIAS of the TIA for Time Slot A. 0: 1.14 V. 1: 1.01 V. 2: 0.90 V. 3: 1.27 V (default recommended). Reserved. Write 0x1. Transimpedance amplifier gain for Time Slot A. When SLOTA_TIA_IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTA_TIA_IND_EN is disabled, it is for all four Time Slot A channel TIA gain settings. 0: 200 k. 1: 100 k. 2: 50 k. 3: 25 k. Data Sheet ADPD105/ADPD106/ADPD107 Address 0x43 Data Bit [15:0] Default Value 0xADA5 Access R/W Name SLOTA_AFE_CFG 0x55 [15:13] 0x0 R/W DIGINT_POWER [12] [11:10] 0x0 0x0 R/W R/W Reserved SLOTB_TIA_GAIN_4 [9:8] 0x0 R/W SLOTB_TIA_GAIN_3 [7:6] 0x0 R/W SLOTB_TIA_GAIN_2 [5:4] 0x0 R/W SLOTA_TIA_GAIN_4 [3:2] 0x0 R/W SLOTA_TIA_GAIN_3 [1:0] 0x0 R/W SLOTA_TIA_GAIN_2 [15:8] [7] 0x00 0x0 R/W R/W Reserved DIG_INT_GAPMODE [6] 0x0 R/W SLOTB_DIG_INT_SAMPLEMODE [5] 0x0 R/W SLOTA_DIG_INT_SAMPLEMODE [4:0] 0x00 R/W Reserved 0x5A Rev. A | Page 57 of 66 Description AFE connection in Time Slot A. 0xADA5: analog full path mode (TIA_BPF_INT_ADC). 0xAE65: TIA ADC mode (if Register 0x42, Bit 7 = 1). 0xB065: TIA ADC mode (if Register 0x42, Bit 7 = 0). 0xAE65: digital integration mode. Others: reserved. Power-down for Channel 2, Channel 3, and Channel 4 in digital integration mode. 0: keep all channels powered up. 7: powers down Channel 2, Channel 3, and Channel 4. Write 0x0. TIA gain for Time Slot B, Channel 4 (PD4). 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot B, Channel 3 (PD3). 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot B, Channel 2 (PD2). 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot A, Channel 4 (PD4). 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot A, Channel 3 (PD3). 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot A, Channel 2 (PD2). 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. Write 0x0. Digital integration gapped mode enable. 0: no gap between negative and positive sample regions. 1: use SLOTA_AFE_FOFFSET for Time Slot A or SLOTB_AFE_ FOFFSET for Time Slot B to specify the gap in s. Digital integration single-sample pair mode for Time Slot B. 0: double-sample pair mode. 1: single-sampled pair mode. Digital integration single-sample pair mode for Time Slot A. 0: double-sample pair mode. 1: single-sampled pair mode. Write 0x0. ADPD105/ADPD106/ADPD107 Data Sheet Table 32. AFE Configuration Registers, Time Slot B Data Bit [15:11] [10:5] Default Value 0x04 0x17 Access R/W R/W Name SLOTB_AFE_WIDTH SLOTB_AFE_OFFSET [4:0] 0x1C R/W SLOTB_AFE_FOFFSET [15:8] 0x1C R/W SLOTB_AFE_MODE 7 0x0 R/W SLOTB_INT_AS_BUF 6 0x0 R/W SLOTB_TIA_IND_EN [5:4] 0x3 R/W SLOTB_TIA_VBIAS [3:2] [1:0] 0x2 0x0 R/W R/W Reserved SLOTB_TIA_GAIN 0x45 [15:0] 0xADA5 R/W SLOTB_AFE_CFG 0x58 [15:14] 13 0x0 0x0 R/W R/W Reserved SLOTB_DIGITAL_INT_EN 12 0x0 R/W SLOTA_DIGITAL_INT_EN [11:0] 0x0000 R/W Reserved Address 0x3B 0x44 Rev. A | Page 58 of 66 Description AFE integration window width (in 1 s step) for Time Slot B. AFE integration window coarse offset (in 1 s step) for Time Slot B. AFE integration window fine offset (in 31.25 ns step) for Time Slot B. 0x1C: Time Slot B AFE setting for normal mode (TIA_BPF_INT_ADC). 0x1D: Time Slot B AFE setting for digital integrate mode. 0: normal integrator configuration. 1: convert integrator to buffer amplifier (this is done automatically in digital integrate mode). Enable Time Slot B TIA gain individual settings. When it is enabled, the Channel 1 TIA gain is set via Register 0x44, Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set via Register 0x55, Bits[11:6]. 0: disable TIA gain individual setting. 1: enable TIA gain individual setting. Set VBIAS of the TIA for Time Slot B. 0: 1.14 V. 1: 1.01 V. 2: 0.90 V. 3: 1.27 V (default recommended). Write 0x1. Transimpedance amplifier gain for Time Slot B. When SLOTB_TIA_IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTB_TIA_IND_EN is disabled, it is for all four Time Slot B channel TIA gain settings. 0: 200 k. 1: 100 k. 2: 50 k. 3: 25 k. AFE connection in Time Slot B. 0xADA5: analog full path mode (TIA_BPF_INT_ADC). 0xAE65: TIA ADC mode (if Register 0x44, Bit 7 = 1). 0xB065: TIA ADC mode (if Register 0x44, Bit 7 = 0). 0xAE65: digital integration mode. Others: reserved. Write 0x0. Digital integration mode, enable Time Slot B. 0: disable. 1: enable. Digital integration mode, enable Time Slot A. 0: disable. 1: enable. Write 0x0000. Data Sheet ADPD105/ADPD106/ADPD107 SYSTEM REGISTERS Table 33. System Registers Address 0x00 0x01 0x02 Data Bit [15:8] Default 0x00 Access R/W Name FIFO_SAMPLES 7 6 0x0 0x0 R/W R/W Reserved SLOTB_INT 5 0x0 R/W SLOTA_INT [4:0] [15:9] 8 0x00 0x00 0x1 R/W R/W R/W Reserved Reserved FIFO_INT_MASK 7 6 0x1 0x1 R/W R/W Reserved SLOTB_INT_MASK 5 0x1 R/W SLOTA_INT_MASK [4:0] [15:10] 9 0x1F 0x00 0x0 R/W R/W R/W Reserved Reserved GPIO1_DRV 8 0x0 R/W GPIO1_POL [7:3] 2 0x00 0x0 R/W R/W Reserved GPIO0_ENA 1 0x0 R/W GPIO0_DRV 0 0x0 R/W GPIO0_POL Description FIFO status. Number of available bytes to be read from the FIFO. When comparing this to the FIFO length threshold (Register 0x06, Bits[13:8]), note that the FIFO status value is in bytes and the FIFO length threshold is in words, where one word = two bytes. Write 1 to Bit 15 to clear the contents of the FIFO. Write 0x1 to clear this bit to 0x0. Time Slot B interrupt. Describes the type of interrupt event. A 1 indicates an interrupt of a particular event type has occurred. Write a 1 to clear the corresponding interrupt. After clearing, the register goes to 0. Writing a 0 to this register has no effect. Time Slot A interrupt. Describes the type of interrupt event. A 1 indicates an interrupt of a particular event type has occurred. Write a 1 to clear the corresponding interrupt. After clearing, the register goes to 0. Writing a 0 to this register has no effect Write 0x1F to clear these bits to 0x00. Write 0x00. Sends an interrupt when the FIFO data length has exceeded the FIFO length threshold in Register 0x06, Bits[13:8]. A 0 enables the interrupt. Write 0x1. Sends an interrupt on the Time Slot B sample. Write a 1 to disable the interrupt. Write a 0 to enable the interrupt. Sends an interrupt on the Time Slot A sample. Write a 1 to disable the interrupt. Write a 0 to enable the interrupt. Write 0x1F. Write 0x0000. GPIO1 drive. 0: the GPIO1 pin is always driven. 1: the GPIO1 pin is driven when the interrupt is asserted; otherwise, it is left floating and requires a pull-up or pull-down resistor, depending on polarity (operates as open drain). Use this setting if multiple devices must share the GPIO1 pin. GPIO1 polarity. 0: the GPIO1 pin is active high. 1: the GPIO1 pin is active low. Write 0x00 GPIO0 pin enable. 0: disable the GPIO0 pin. The GPIO0 pin floats, regardless of interrupt status. The status register (Address 0x00) remains active. 1: enable the GPIO0 pin. GPIO0 drive. 0: the GPIO0 pin is always driven. 1: the GPIO0 pin is driven when the interrupt is asserted; otherwise, it is left floating and requires a pull-up or pull-down resistor, depending on polarity (operates as open drain). Use this setting if multiple devices must share the GPIO0 pin. GPIO0 polarity. 0: the GPIO0 pin is active high. 1: the GPIO0 pin is active low. Rev. A | Page 59 of 66 ADPD105/ADPD106/ADPD107 Address 0x06 0x08 0x09 0x0A 0x0B Data Sheet Data Bit [15:14] [13:8] Default 0x0 0x00 Access R/W R/W Name Reserved FIFO_THRESH [7:0] [15:8] [7:0] [15:8] [7:1] 0 [15:12] [11:0] 0x00 0x04 0x16 0x00 0x64 0x0 0x0 0x000 R/W R R W R/W R R R Reserved REV_NUM DEV_ID ADDRESS_WRITE_KEY SLAVE_ADDRESS Reserved Reserved CLK_RATIO [15:13] [12:8] 0x0 0x00 R/W R/W Reserved GPIO1_ALT_CFG [7:5] [4:0] 0x0 0x00 R/W R/W Reserved GPIO0_ALT_CFG Description Write 0x0. FIFO length threshold. An interrupt is generated when the number of data-words in the FIFO exceeds the value in FIFO_THRESH. The interrupt pin automatically deasserts when the number of data-words available in the FIFO no longer exceeds the value in FIFO_THRESH. Write 0x00. Revision number. Device ID. Write 0xAD when writing to SLAVE_ADDRESS. Otherwise, do not access. I2C slave address. Do not access. Write 0x0. When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the device calculates the number of 32 MHz clock cycles in two cycles of the 32 kHz clock. The result, nominally 2000 (0x07D0), is stored in the CLK_RATIO bits. Write 0x0. Alternate configuration for the GPIO1 pin. 0x0: GPIO1 is backward compatible to the ADPD103 PDSO pin functionality. 0x1: interrupt function provided on GPIO1, as defined in Register 0x01. 0x2: asserts at the start of the first time slot, deasserts at end of last time slot. 0x5: Time Slot A pulse output. 0x6: Time Slot B pulse output. 0x7: pulse output of both time slots. 0xC: output data cycle occurred for Time Slot A. 0xD: output data cycle occurred for Time Slot B. 0xE: output data cycle occurred. 0xF: toggles on every sample, which provides a signal at half the sampling rate. 0x10: ouput = 0 0x11: output = 1 0x13: 32 kHz oscillator output. Remaining settings are not supported. Write 0x0. Alternate configuration for the GPIO0 pin. 0x0: GPIO0 is backward compatible to the ADPD103 INT pin functionality. 0x1: interrupt function provided on GPIO0, as defined in Register 0x01. 0x2: asserts at the start of the first time slot, deasserts at end of last time slot. 0x5: Time Slot A pulse output. 0x6: Time Slot B pulse output. 0x7: pulse output of both time slots. 0xC: output data cycle occurred for Time Slot A. 0xD: output data cycle occurred for Time Slot B. 0xE: output data cycle occurred. 0xF: toggles on every sample, which provides a signal at half the sampling rate. 0x10: output = 0. 0x11: output = 1. 0x13: 32 kHz oscillator output. Remaining settings are not supported. Rev. A | Page 60 of 66 Data Sheet ADPD105/ADPD106/ADPD107 Data Bit [15:0] Default 0x0000 Access R/W Name SLAVE_ADDRESS_KEY 0x0F [15:1] 0 0x0000 0x0 R R/W Reserved SW_RESET 0x10 [15:2] [1:0] 0x0000 0x0 R/W R/W Reserved Mode 0x11 [15:14] 13 0x0 0x0 R/W R/W Reserved RDOUT_MODE 12 0x1 R/W FIFO_OVRN_PREVENT [11:9] [8:6] 0x0 0x0 R/W R/W Reserved SLOTB_FIFO_MODE 5 [4:2] 0x0 0x0 R/W R/W SLOTB_EN SLOTA_FIFO_MODE 1 0 0x0 0x0 R/W R/W Reserved SLOTA_EN Address 0x0D Description Enable changing the I2C address using Register 0x09. 0x04AD: enable address change always. 0x44AD: enable address change if GPIO0 is high. 0x84AD: enable address change if GPIO1 is high. 0xC4AD: enable address change if both GPIO0 and GPIO1 are high. Write 0x0000. Software reset. Write 0x1 to reset the device. This bit clears itself after a reset. For I2C communications, this command returns an acknowledge and the device subsequently returns to standby mode with all registers reset to the default state. Write 0x000. Determines the operating mode of the ADPD105/ADPD106/ADPD107. 0x0: standby. 0x1: program. 0x2: normal operation. Reserved. Readback data mode for extended data registers. 0x0: block sum of N samples. 0x1: block average of N samples. 0x0: wrap around FIFO, overwriting old data with new. 0x1: new data if FIFO is not full (recommended setting). Reserved. Time Slot B FIFO data format. 0: no data to FIFO. 1: 16-bit sample in digital integration mode or 16-bit sum of all four channels when not in digital integration mode. 2: 32-bit sample in digital integration mode or 32-bit sum of all four channels when not in digital integration mode. 3: 16-bit sample and 16-bit background value in digital integration mode. 4: 32-bit sample and 32-bit background value in digital integration mode or four channels of 16-bit sample data for Time Slot B when not in digital integration mode. 6: four channels of 32-bit extended sample data for Time Slot B when not in digital integration mode. Others: reserved. The selected Time Slot B data is saved in the FIFO. Available only if Time Slot A has the same averaging factor, N (Register 0x15, Bits[10:8] = Bits[6:4]), or if Time Slot A is not saving data to the FIFO (Register 0x11, Bits[4:2] = 0). Time Slot B enable. 1: enables Time Slot B. Time Slot A FIFO data format. 0: no data to FIFO. 1: 16-bit sample in digital integration mode or 16-bit sum of all four channels when not in digital integration mode. 2: 32-bit sample in digital integration mode or 32-bit sum of all four channels when not in digital integration mode. 3: 16-bit sample and 16-bit background value in digital integration mode. 4: 32-bit sample and 32-bit background value in digital integration mode or four channels of 16-bit sample data for Time Slot B when not in digital integration mode. 6: four channels of 32-bit extended sample data for Time Slot B when not in digital integration mode. Others: reserved. Write 0x0. Time Slot A enable. 1: enables Time Slot A. Rev. A | Page 61 of 66 ADPD105/ADPD106/ADPD107 Data Sheet Data Bit [15:0] [15:9] 8 Default 0x0000 0x13 0x0 Access R/W R/W R/W Name EXT_SYNC_STARTUP Reserved CLK32K_BYP 7 0x0 R/W CLK32K_EN 6 [5:0] 0x0 0x12 R/W R/W Reserved CLK32K_ADJUST 0x4D [15:8] [7:0] 0x00 0x98 R/W R/W Reserved CLK32M_ADJUST 0x4E1 [15:0] 0x0060 R/W ADC_TIMING1 0x4F [15:8] 7 6 5 4 [3:2] 0x20 0x1 0x0 0x0 0x1 0x0 R/W R/W R/W R/W R/W R/W Reserved Reserved GPIO1_OE GPIO1_IE Reserved EXT_SYNC_SEL 1 0 [15:7] 6 0x0 0x0 0x000 0x0 R/W R/W R/W R/W GPIO0_IE Reserved Reserved GPIO1_CTRL 5 0x0 R/W CLK32M_CAL_EN [4:0] 0x00 R/W Reserved Address 0x38 0x4B 0x50 Description Write 0x4000 when EXT_SYNC_SEL is b01 or b10. Otherwise, write 0x0. Write 0x26. Bypass internal 32 kHz oscillator. 0x0: normal operation. 0x1: provide external clock on the GPIO1 pin. The user must set Register 0x4F, Bits[6:5] = 01 to enable the GPIO1 pin as an input. Sample clock power-up. Enables the data sample clock. 0x0: clock disabled. 0x1: normal operation. Write 0x0. Data sampling (32 kHz) clock frequency adjust. This register is used to calibrate the sample frequency of the device to achieve high precision on the data rate as defined in Register 0x12. Adjusts the sample master 32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample rate as defined in Register 0x12, 1 LSB of Register 0x4B, Bits[5:0], is 1.9 Hz. Note that a larger value produces a lower frequency. See the Clocks and Timing Calibration section for more information regarding clock adjustment. 00 0000: maximum frequency. 10 0010: typical center frequency. 11 1111: minimum frequency. Write 0x00. Internal timing (32 MHz) clock frequency adjust. This register is used to calibrate the internal clock of the device to achieve precisely timed LED pulses. Adjusts the 32 MHz clock by 109 kHz per LSB. See the Clocks and Timing Calibration section for more information regarding clock adjustment. 0000 0000: minimum frequency. 1001 1000: default frequency. 1111 1111: maximum frequency. 0x0040: ADC clock speed = 1 MHz. 0x0060: ADC clock speed = 500 kHz. Write 0x20. Write 0x1. GPIO1 pin output enable. GPIO1 pin input enable. Write 0x1. Sample sync select. 00: use the internal 32 kHz clock with FSAMPLE to select sample timings. 01: use the GPIO0 pin to trigger sample cycle. 10: use the GPIO1 pin to trigger sample cycle. 11: reserved. GPIO0 pin input enable. Write 0x0. Write 0x000. Controls the GPIO1 output when the GPIO1 output is enabled (GPIO1_OE = 0x1). 0x0: GPIO1 output driven low. 0x1: GPIO1 output driven by the AFE power-down signal. As part of the 32 MHz clock calibration routine, write 1 to begin the clock ratio calculation. Read the result of this calculation from the CLK_RATIO bits in Register 0x0A. Reset this bit to 0 prior to reinitiating the calculation. Write 0x0. Rev. A | Page 62 of 66 Data Sheet Address 0x5F 1 ADPD105/ADPD106/ADPD107 Data Bit [15:3] 2 Default 0x0000 0x0 Access R/W R/W Name Reserved SLOTB_DATA_HOLD 1 0x0 R/W SLOTA_DATA_HOLD 0 0x0 R/W DIGITAL_CLOCK_ENA Description Write 0x0000. Setting this bit prevents the update of the data registers corresponding to Time Slot B. Set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: hold data registers for Time Slot B. 0: allow data register update. Setting this bit prevents the update of the data registers corresponding to Time Slot A. Set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: hold data registers for Time Slot A. 0: allow data register update. Set to 1 in order to enable the 32 MHz clock when calibrating the 32 MHz clock. Always disable the 32 MHz clock following the calibration by resetting this bit to 0. Clock speed setting is only relevant during digital integrate mode. ADC REGISTERS Table 34. ADC Registers Data Bits [15:0] Default 0x0028 Access R/W Name FSAMPLE [15:11] [10:8] 0x00 0x6 R/W R/W Reserved SLOTB_NUM_AVG 7 [6:4] 0x0 0x0 R/W R/W Reserved SLOTA_NUM_AVG 0x18 [3:0] [15:0] 0x0 0x2000 R/W R/W Reserved SLOTA_CH1_OFFSET 0x19 [15:0] 0x2000 R/W SLOTA_CH2_OFFSET 0x1A [15:0] 0x2000 R/W SLOTA_CH3_OFFSET 0x1B [15:0] 0x2000 R/W SLOTA_CH4_OFFSET 0x1E [15:0] 0x2000 R/W SLOTB_CH1_OFFSET Address 0x12 0x15 Description Sampling frequency: fSAMPLE = 32 kHz/(Register 0x12, Bits[15:0] x 4). For example, 100 Hz = 0x0050; 200 Hz = 0x0028. Write 0x0. Sample sum/average for Time Slot B. Specifies the averaging factor, NB, which is the number of consecutive samples that is summed and averaged after the ADC. Register 0x70 to Register 0x7F hold the data sum. Register 0x64 to Register 0x6B and the data buffer in Register 0x60 hold the data average, which can be used to increase SNR without clipping, in 16-bit registers. The data rate is decimated by the value of the SLOTB_NUMB_AVG bits. 0: 1. 1: 2. 2: 4. 3: 8. 4: 16. 5: 32. 6: 64. 7: 128. Write 0x0. Sample sum/average for Time Slot A. NA: same as Bits[10:8] but for Time Slot A. See description in Register 0x15, Bits[10:8]. Write 0x0. Time Slot A Channel 1 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 2 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 3 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 4 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 1 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Rev. A | Page 63 of 66 ADPD105/ADPD106/ADPD107 Data Sheet Address 0x1F Data Bits [15:0] Default 0x2000 Access R/W Name SLOTB_CH2_OFFSET 0x20 [15:0] 0x2000 R/W SLOTB_CH3_OFFSET 0x21 [15:0] 0x2000 R/W SLOTB_CH4_OFFSET Description Time Slot B Channel 2 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 3 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 4 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. DATA REGISTERS Table 35. Data Registers Address 0x60 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Data Bits [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Access R R R R R R R R R R R R R R R R R R R R R R R R R Name FIFO_DATA SLOTA_CH1_16BIT SLOTA_CH2_16BIT SLOTA_CH3_16BIT SLOTA_CH4_16BIT SLOTB_CH1_16BIT SLOTB_CH2_16BIT SLOTB_CH3_16BIT SLOTB_CH4_16BIT SLOTA_CH1_LOW SLOTA_CH2_LOW SLOTA_CH3_LOW SLOTA_CH4_LOW SLOTA_CH1_HIGH SLOTA_CH2_HIGH SLOTA_CH3_HIGH SLOTA_CH4_HIGH SLOTB_CH1_LOW SLOTB_CH2_LOW SLOTB_CH3_LOW SLOTB_CH4_LOW SLOTB_CH1_HIGH SLOTB_CH2_HIGH SLOTB_CH3_HIGH SLOTB_CH4_HIGH Description Next available word in FIFO. 16-bit value of Channel1 in Time Slot A. 16-bit value of Channel 2 in Time Slot A. 16-bit value of Channel 3 in Time Slot A. 16-bit value of Channel 4 in Time Slot A. 16-bit value of Channel 1 in Time Slot B. 16-bit value of Channel 2 in Time Slot B. 16-bit value of Channel 3 in Time Slot B. 16-bit value of Channel 4 in Time Slot B. Low data-word for Channel 1 in Time Slot A. Low data-word for Channel 2 in Time Slot A. Low data-word for Channel 3 in Time Slot A. Low data-word for Channel 4 in Time Slot A. High data-word for Channel 1 in Time Slot A. High data-word for Channel 2 in Time Slot A. High data-word for Channel 3 in Time Slot A. High data-word for Channel 4 in Time Slot A. Low data-word for Channel 1 in Time Slot B. Low data-word for Channel 2 in Time Slot B. Low data-word for Channel 3 in Time Slot B. Low data-word for Channel 4 in Time Slot B. High data-word for Channel 1 in Time Slot B. High data-word for Channel 2 in Time Slot B. High data-word for Channel 3 in Time Slot B. High data-word for Channel 4 in Time Slot B. 2. 3. REQUIRED START-UP LOAD PROCEDURE The required start-up load procedure is as follows: 1. Write to 0x1 to Register 0x4B, Bit 7 to enable the clock that drives the state machine. 4. Rev. A | Page 64 of 66 Write 0x0001 to Register 0x10 to enter program mode. Write to the other registers; the register order is not important while the device is in program mode. Write 0x0002 to Register 0x10 to start normal sampling operation. Data Sheet ADPD105/ADPD106/ADPD107 OUTLINE DIMENSIONS 0.25 0.20 0.15 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 22 0.40 BSC PIN 1 INDICATOR 28 1 21 2.70 2.60 SQ 2.50 EXPOSED PAD 7 15 TOP VIEW 0.80 0.75 0.70 14 8 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PKG-003523 SEATING PLANE 0.20 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 06-23-2015-B 0.45 0.40 0.35 COMPLIANT TO JEDEC STANDARDS MO-220-WGGE. Figure 54. 28-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.75 mm Package Height (CP-28-5) Dimensions shown in millimeters 1.44 1.40 1.36 0.225 3 2 1 A BALL A1 IDENTIFIER B 2.00 REF 2.50 2.46 2.42 C D 0.40 BSC E F TOP VIEW 0.235 0.300 (BALL SIDE DOWN) PKG-004659 SEATING PLANE (BALL SIDE UP) 0.330 0.300 0.270 END VIEW COPLANARITY 0.05 0.300 0.260 0.220 0.230 0.200 0.170 Figure 55. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-18) Dimensions shown in millimeters Rev. A | Page 65 of 66 02-03-2015-B 0.560 0.500 0.440 BOTTOM VIEW ADPD105/ADPD106/ADPD107 Data Sheet 1.44 1.40 1.36 3 2 1 A BALL A1 IDENTIFIER B 2.00 REF 2.50 2.46 2.42 C D 0.40 BSC E F BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) 0.80 REF 0.330 0.300 0.270 END VIEW COPLANARITY 0.05 SEATING PLANE PKG-005139 0.300 0.260 0.220 0.230 0.200 0.170 03-03-2016-A 0.560 0.500 0.440 TOP VIEW Figure 56. 17-Ball Wafer Level Chip Scale Package [WLCSP] (CB-17-1) Dimensions shown in millimeters ORDERING GUIDE Model1 ADPD105BCPZ ADPD105BCPZRL ADPD105BCBZR7 ADPD106BCBZR7 ADPD107BCBZR7 EVAL-ADPD105Z-GEN 1 2 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 28-Lead Lead Frame Chip Scale Package [LFCSP] 28-Lead Lead Frame Chip Scale Package [LFCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] 16-Ball Wafer Level Chip Scale Package [WLCSP] 17-Ball Wafer Level Chip Scale Package [WLCSP] Generic ADPD105 Evaluation Board2 Z = RoHS Compliant Part. This evaluation board is used for the ADPD105, ADPD106, and ADPD107. (c)2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14693-0-1/17(A) Rev. A | Page 66 of 66 Package Option CP-28-5 CP-28-5 CB-16-18 CB-16-18 CB-17-1