1/23July 2000
M48T513Y
M48T513V
3.3V-5V 4 Mbit (512Kb x8) TIMEKEEPERSRAM
■INTEGRATED ULTRA LOW POWER SRAM,
REAL TIMECLOCK, POWER-FAIL CONTROL
CIRCUIT, BATTERY, and CRYSTAL
■YEAR 2000 COMPLIANT
■BCD CODED CENTURY, YEAR, MONTH,
DAY, DATE, HOURS, MINUTES, and
SECONDS
■BATTERY LOW WARNING FLAG
■AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■TWO WRITE PROTECT VOLTAGES:
(VPFD = Power-fail Deselect Voltage)
– M48T513Y: 4.2V ≤VPFD ≤4.5V
– M48T513V: 2.7V ≤VPFD ≤3.0V
■CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
■SOFTWARE CONTROLLED CLOCK
CALIBRATION for HIGH ACCURACY
APPLICATIONS
■10 YEARS of DATA RETENTION and CLOCK
OPERATION in the ABSENCE of POWER
■SELF CONTAINED BATTERY and CRYSTAL
in DIP PACKAGE
■MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
■PROGRAMMABLE ALARM OUTPUT ACTIVE
in BATTERY BACK-UP MODE
■SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 44-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
■SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY and CRYSTAL
■SNAPHATHOUSING (BATTERY/CRYSTAL)
IS REPLACEABLE
Figure 1. Logic Diagram
AI02308
19
A0-A18 DQ0-DQ7
VCC
M48T513Y
M48T513V
G
VSS
8
E
W RST
IRQ/FT
RSTIN
WDI
SOH44
Surface Mount Chip Set Solution (CS)
SNAPHAT (SH)
Battery
PMLDIP36 (PL)
Module
32
1
TSOP II 32
(10 x 20mm)
36
1
M48T513Y, M48T513V
2/23
Figure 2. DIP Connections
VSS
VCC
AI02307
M48T513Y
M48T513V
10
1
2
5
6
7
8
9
11
12
13
16
17
18
30
29
26
25
24
23
22
21
20
19
3
4
28
27
32
31
14
15
34
33
36
35
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
A15
A11
G
E
DQ5DQ1
DQ2 DQ3
DQ4
DQ6
A16
A18
A12
A14 W
A17
RSTIN
RST
IRQ/FT
WDI
Table 2. Absolute Maximum Ratings (1)
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Symbol Parameter Value Unit
TAAmbient Operating Temperature 0 to 70 °C
TSTG Storage Temperature (VCC Off, Oscillator Off) –40 to 85 °C
VIO Input or Output Voltages –0.3 to VCC +0.3 V
VCC Supply Voltage M48T513Y –0.3 to 7.0 V
M48T513V –0.3 to 4.6 V
IOOutput Current 20 mA
PDPower Dissipation 1 W
DESCRIPTION
The M48T513Y/V TIMEKEEPER RAM is a 512Kb
x 8 non-volatile static RAM and real time clock,
with programmable alarms and a watchdog timer.
The special DIP package provides a fully integrat-
ed battery back-up memoryand realtime clock so-
lution. TheM48T513Y/V directly replaces industry
standard 512Kb x 8 SRAM. It also provides the
non-volatility of Flash without any requirement for
special write timingor limitations on the number of
writes that can be performed.
Table 1. Signal Names
A0-A18 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E Chip Enable Input
G Output Enable Input
W Write Enable Input
WDI Watchdog input
RST Reset Output (open drain)
RSTIN Reset Input
IRQ/FT Interrupt / Frequency Test
Output (open drain)
VCC Supply Voltage
VSS Ground
For surface mount environments ST provides a
Chip Set solution consisting of a 44 pin 330mil
SOIC TIMEKEEPER Supervisor (M48T201V/Y)
and a 32 pin TSOP Type II (10 x 20mm) LPSRAM
(M68Z512/W) packages.
The 44 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery.
3/23
M48T513Y, M48T513V
Figure 3. Block Diagram
AI02584
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VPFD
VCC VSS
32,768
Hz
CRYSTAL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
16 x
8
TIMEKEEPER
REGISTERS
524,272 x
8
SRAM ARRAY
A0-A18
DQ0-DQ7
E
W
G
POWER
RST
IRQ/FT
WDI
RSTIN
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the hightemperatures required fordevice surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is ”M4Txx-BR12SH1”.
Figure 3 illustratesthe static memoryarray and the
quartz controlled clock oscillator. The clock loca-
tions contain the century, year, month, date, day,
hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year), 30, and 31 day
months are made automatically. The nine clock
bytes (7FFFFh-7FFF9h and 7FFF1h) are not the
actual clock counters, they are memory locations
consisting of BiPORTread/write memory cells
within the static RAM array.
The M48T513Y/V includes a clock control circuit
which updates the clock bytes with current infor-
mation once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array. Byte
7FFF8his the clockcontrol register. This byte con-
trols user access to the clock information andalso
stores the clock calibration setting.
Byte 7FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the Watch-
dog Steering bit (WDS). Bytes 7FFF6h-7FFF2h in-
clude bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and seconds of the clock
registers. Byte 7FFF1h contains century informa-
tion.Byte 7FFF0h contains additionalflag informa-
tion pertaining to the watchdog timer, the alarm
condition and the battery status. The M48T513Y/V
also has its own Power-Fail Detect circuit. This
control circuitry constantly monitors the supply
voltage for an out of tolerance condition. When
VCC is out of tolerance, the circuit write protects
the TIMEKEEPER register data and external
SRAM, providing data security in the midst of un-
predictable system operation. As VCC falls, the
control circuitry automatically switches to the bat-
tery, maintaining data and clock operation until
valid power is restored.
M48T513Y, M48T513V
4/23
Figure 4. Hardware Hookup for SMT Chip Set (1)
Note: 1. For pin connections, see individual data sheets for M48T201Y/V and M68Z512/W at www.st.com.
2. For 5V, M48T129Y (M48T201Y + M68Z512). For 3.3V, M48T129V (M48T201V + M68Z512W).
3. SNAPHAT Top ordered separately.
AI03633
32,768
Hz
CRYSTAL
LITHIUM
CELL
A0-A18
DQ0-DQ7
E
VCC
W
G
WDI
RSTIN1
RSTIN2
VSS
E
W
G
VCC
VSS
A0-A18
DQ0-DQ7
0.1µF
0.1µF
5V
ECON
GCON
RST
IRQ/FT
SQW
M48T201Y/V (2)
M68Z512/W(2)
VOUT
SNAPHAT
(3)
BATTERY/CRYSTAL
READ MODE
The M48T513Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 524,272
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within tAVQV (Ad-
dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latterof the Chip Enable Access Times (tELQV)
or Output Enable Access Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlledby E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for tAXQX (Output
Data Hold Time) but will go indeterminate until the
next Address Access.
WRITE MODE
The M48T513Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a write is referencedfrom the latter oc-
curring falling edge of W orE. A write is terminated
by the earlier risingedge of W or E. The addresses
must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from Chip
Enable or tWHAX from Write Enable prior to the ini-
tiation of another read or write cycle. Data-in must
be valid tDVWH prior to the end of write and remain
valid for tWHDX afterward. G should be kept high
during write cycles to avoid bus contention; al-
though, if the output bus has been activated by a
low on E and G a low on W will disable the outputs
tWLQZ after W falls.
5/23
M48T513Y, M48T513V
Table 3. Operating Modes (1)
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Mode VCC E G W DQ0-DQ7 Power
Deselect
4.5V to 5.5V
or
3.0V to 3.6V
VIH X X High Z Standby
Write VIL XV
IL DIN Active
Read VIL VIL VIH DOUT Active
Read VIL VIH VIH High Z Active
Deselect VSO to VPFD (min) (2) X X X High Z CMOS Standby
Deselect ≤VSO (2) X X X High Z Battery Back-up Mode
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data isno longer
driven.
Input Rise and Fall Times ≤5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V
referred to as BiPORTTIMEKEEPER cells).
The external copies are independent of internal
functions except that they are updatedperiodically
by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER and Alarm Registers
store data in BCD.
DATA RETENTION MODE
With valid VCC applied, the M48T513Y/V operates
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automati-
cally deselect, write protecting itself when VCC
falls between VPFD (max), VPFD (min) window. All
outputs become high impedance and all inputs are
treated as ”don’t care”.
Note: A power failure during a writecycle may cor-
rupt data at the current addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below VPFD (min), the memory will be
in a write protected state, provided the VCC fall
time is not less than tF. The M48T513Y/V may re-
spond to transient noise spikes on VCC that cross
into the deselect window during the time the de-
vice issampling VCC. Therefore, decoupling of the
power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery, preserving
data and powering the clock. The internal energy
source will maintain data in the M48T513Y/V for
an accumulated periodof at least 10 years atroom
temperature. As system power rises above VSO,
the battery is disconnected, and the power supply
is switched toexternal VCC. Deselectcontinues for
tREC after VCC reaches VPFD (max). For a further
more detailed review of lifetime calculations,
please see Application Note AN1012.
TIMEKEEPER REGISTERS
The M48T513Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Interrupt, Flag, and Control data. These registers
are memory locations whichcontain external (user
accessible) and internal copies of the data (usually
Figure 5. AC Testing Load Circuit
Note: Excluding open drain output pins.
AI01803C
CL= 100pF
CLincludes JIG capacitance
650Ω
DEVICE
UNDER
TEST
1.75V
M48T513Y, M48T513V
6/23
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control Register (7FFF8h). As
long as a ’1’ remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; thatis, the day,date, and time that were
current at the moment the halt command was is-
sued. All of the TIMEKEEPER registers are updat-
ed simultaneously. A halt will not interrupt an
update in progress. Updating occurs 1 second af-
ter the READ bit is reset to a’0’.
Setting the Clock
Bit D7 of the Control Register (7FFF8h) is the
WRITE bit. Setting the WRITE bit to a ’1’, like the
READ bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 11).
Resetting the WRITE bit to a ’0’then transfers the
values of all time registers (7FFFFh-7FFF9h,
7FFF1h) to theactual TIMEKEEPER counters and
allows normal operation to resume. After the
WRITE bit is reset, the nextclock update will occur
approximately one second later.
Note: Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ’0’.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is located at Bit D7 within 7FFF9h. Setting it to
a ’1’ stops the oscillator. When reset to a ’0’, the
M48T513Y/V oscillator starts within one second.
Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
SETTING ALARM CLOCK
Registers 7FFF6h-7FFF2h contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every month, day,
hour, minute, or second. It can also be pro-
grammed to go off while the M48T513Y/V is in the
battery back-upto serve as a system wake-up call.
Bits RPT5-RPT1 putthe alarm in the repeat mode
of operation. Table 12 shows the possible config-
urations. Codes not listed in the table defaultto the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Note: User must transition address (or toggleChip
Enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT pin. To disable alarm,
write ’0’ to the Alarm Date register and RPT1-4.
The IRQ/FT output is cleared by a read to the
Flags register as shown in Figure 12. A subse-
quent read of the Flags register will reset the
Alarm Flag (D6; Register 7FFF0h).
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T513Y/V was in the deselect mode
during power-up. Figure 13 illustrates the back-up
mode alarm timing.
WATCHDOG TIMER
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
7FFF7h. Bits BMB4-BMB0 store abinary multiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 sec-
ond, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication of the five bit multiplier valuewith the
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ±the selected
resolution.
7/23
M48T513Y, M48T513V
Table 5. Capacitance (1)
(TA=25°C, f = 1 MHz)
Note: 1. Effective capacitance measured with power supply at 5V (M48T513Y) or 3.3V (M48T513V). Sampled only, not 100% tested.
2. Outputs deselected.
Table 6A. DC Characteristics - M48T513Y
(TA= 0 to 70 °C; VCC = 4.5Vto 5.5V)
Note: 1. Outputs deselected.
Table 6B. DC Characteristics - M48T513V
(TA= 0 to 70 °C; VCC = 3.0Vto 3.6V)
Note: 1. Outputs deselected.
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN =0V 20 pF
CIO (2) Input / OutputCapacitance VOUT =0V 20 pF
Symbol Parameter Test Condition Min Max Unit
ILI (1) Input Leakage Current 0V ≤VIN ≤VCC ±2µA
ILO (1) Output Leakage Current 0V ≤VOUT ≤VCC ±2µA
ICC Supply Current Outputs open 115 mA
ICC1 Supply Current (Standby) TTL E=V
IH 8mA
I
CC2 Supply Current (Standby) CMOS E=V
CC – 0.2V 4mA
V
IL Input Low Voltage –0.3 0.8 V
VIH Input High Voltage 2.2 VCC + 0.3 V
VOL Output Low Voltage IOL = 2.1mA 0.4 V
VOH Output High Voltage IOH = –1mA 2.4 V
Symbol Parameter Test Condition Min Max Unit
ILI (1) Input Leakage Current 0V ≤VIN ≤VCC ±2µA
ILO (1) Output Leakage Current 0V ≤VOUT ≤VCC ±2µA
ICC Supply Current Outputs open 60 mA
ICC1 Supply Current (Standby) TTL E = VIH 4mA
I
CC2 Supply Current (Standby) CMOS E=V
CC – 0.2V 3mA
V
IL Input Low Voltage –0.3 0.4 V
VIH Input High Voltage 2.2 VCC + 0.3 V
VOL Output Low Voltage IOL = 2.1mA 0.4 V
VOH Output High Voltage IOH = –1mA 2.2 V
M48T513Y, M48T513V
8/23
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA= 0 to 70 °C)
Note: 1. All voltages referenced to VSS.
2. At 25°C.
Table 8. Power Down/Up AC Characteristics
(TA= 0 to 70 °C)
Note: 1. VPFD (max) toVPFD (min) fall time of less than tFmay result in deselection/write protection not occurring until 200ms after VCC pass-
es VPFD (min).
2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Symbol Parameter Min Typ Max Unit
VPFD Power-fail Deselect Voltage M48T513Y 4.2 4.35 4.5 V
M48T513V 2.7 2.9 3.0 V
VSO Battery Back-up Switchover Voltage M48T513Y 3.0 V
M48T513V VPFD –100mV
tDR (2) Expected Data Retention Time 10 YEARS
Symbol Parameter Min Max Unit
tF(1) VPFD (max) to VPFD (min) VCC Fall Time 300 µs
tFB (2) VPFD (min) to VSS VCC Fall Time M48T513Y 10 µs
M48T513V 150 µs
tRVPFD (min) to VPFD (max) VCC Rise Time 0µs
tRB VSS to VPFD (min) VCC Rise Time 1µs
tREC VPFD (max) to RST High 40 200 ms
Figure 6. Power Down/Up Mode AC Waveforms
AI01805
VCC
INPUTS
OUTPUTS
DON’T CARE
HIGH-Z
tF
tFB
tR
tRB
VALID VALID
RECOGNIZEDRECOGNIZED
VPFD (max)
VPFD (min)
VSO
tREC
RST
9/23
M48T513Y, M48T513V
Table 9. Read Mode AC Characteristics
(TA= 0 to 70 °C)
Note: 1. CL= 100pF.
2. CL= 5pF.
Symbol Parameter
M48T513Y M48T513Y/M48T513V
Unit-70 -85
Min Max Min Max
tAVAV Read Cycle Time 70 85 ns
tAVQV (1) Address Valid to Output Valid 70 85 ns
tELQV (1) Chip Enable Low toOutput Valid 70 85 ns
tGLQV (1) Output Enable Low to Output Valid 40 55 ns
tELQX (2) Chip Enable Low toOutput Transition 5 5 ns
tGLQX (2) Output Enable Low to Output Transition 5 5 ns
tEHQZ (2) Chip Enable High to Output Hi-Z 25 30 ns
tGHQZ (2) Output Enable High to Output Hi-Z 25 30 ns
tAXQX (1) Address Transition to Output Transition 10 5 ns
Figure 7. Address Controlled, Read Mode AC Waveforms
AI02324
tAVAV
tAVQV
tAXQX
DATA VALID
A0-A16
DQ0-DQ7
VALID
DATA VALID
M48T513Y, M48T513V
10/23
Table 10. Write Mode AC Characteristics
(TA= 0 to 70 °C)
Note: 1. CL= 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Symbol Parameter
M48T513Y M48T513Y/M48T513V
Unit-70 -85
Min Max Min Max
tAVAV Write Cycle Time 70 85 ns
tAVWL Address Valid to Write Enable Low 0 0 ns
tAVEL Address Valid to Chip Enable Low 0 0 ns
tWLWH Write Enable Pulse Width 50 60 ns
tELEH Chip Enable Low to Chip Enable High 55 65 ns
tWHAX Write Enable High to Address Transition 5 5 ns
tEHAX Chip Enable High to Address Transition 10 15 ns
tDVWH Input Valid to Write Enable High 30 35 ns
tDVEH Input Valid to Chip Enable High 30 35 ns
tWHDX Write Enable High to Input Transition 5 5 ns
tEHDX Chip Enable High to Input Transition 10 15 ns
tWLQZ (1, 2) Write Enable Low to Output Hi-Z 25 30 ns
tAVWH Address Valid to Write Enable High 60 70 ns
tAVEH Address Valid to Chip Enable High 60 70 ns
tWHQX (1, 2) Write Enable High to Output Transition 5 5 ns
If the processor does not reset the timer within the
specified period, the M48T513Y/V sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address7FFF0h). The
most significantbit of the Watchdog Register is the
Watchdog Steering Bit (WDS). When set to a ’0’,
the watchdog will activate the IRQ/FT pin when
timed-out. When WDS is set to a ’1’, the watchdog
will output a negative pulse on the RST pin for 40
to 200 ms. The Watchdog register and the FT bit
will reset toa ’0’ at the endof a Watchdog time-out
when theWDS bit is set toa ’1’. The watchdog tim-
er can be reset by two methods: 1) a transition
(high-to-low or low-to-high) can be applied to the
Watchdog Input pin (WDI) or 2) the microproces-
sor can perform a write of the Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to VSS if not used. The watchdog
will be reset on each transition (edge) seen by the
WDI pin. In the order to perform a software reset
of the watchdog timer, the original time-out period
can be written into the Watchdog Register, effec-
tively restarting the count-down cycle.
Should the watchdog timer time-out,and the WDS
bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis-
able the watchdog function until it is again pro-
grammed correctly. A read of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
7FFF0h).
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
POWER-ON RESET
The M48T513Y/V continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for 40 to 200ms after VCC passes VPFD.
The RST pin is an open drain output and an appro-
priate pull-up resistor to VCC should be chosen to
control the rise time.
11/23
M48T513Y, M48T513V
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
Figure 9. Write Enable Controlled, Write AC Waveforms
AI01197
tAVAV
tAVQV tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
DATA OUT
A0-A16
E
G
DQ0-DQ7
VALID
AI02382
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A16
E
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
M48T513Y, M48T513V
12/23
RESET INPUT (RSTIN)
The M48T513Y/V provides an independent input
which can generate an output reset. The duration
and functionof thisreset is identical to a reset gen-
erated by a power cycle. Table 13 and Figure 14
illustrate the AC reset characteristics of this func-
tion. Pulses shorter than tRwill not generate a re-
set condition. RSTIN is internally pulled upto VCC
through a 100KΩresistor.
CALIBRATING THE CLOCK
The M48T513Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25°C and
tested for accuracy. Clock accuracy will not ex-
ceed 35 ppm (parts per million) oscillator frequen-
cy error at 25°C, which equates to about * 1.53
minutes per month. When the Calibration circuit is
properly employed, accuracy improves to better
than 4ppm at 25°C. The oscillation rate of crystals
changes with temperature. The M48T513Y/V de-
sign employs periodic counter correction. The cal-
ibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage,
as shown in Figure 11.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed intothe five Calibration bits foundin theControl
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down. The Calibra-
tion bitsoccupy the five lower order bits (D4-D0) in
the Control Register 7FFF8h. These bits can be
set to represent any value between 0 and 31 in bi-
nary form. Bit D5 is a Sign bit; ’1’indicates positive
calibration, ’0’ indicates negative calibration. Cali-
bration occurs within a 64 minute cycle. The first
62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles.
If a binary ’1’ is loaded into the register, only the
first 2 minutes inthe 64 minute cycle will be modi-
fied; if a binary 6 is loaded, the first 12 will be af-
fected, and so on. Therefore, each calibration step
has the effect of adding512 or subtracting 256 os-
cillator cycles for every 125, 829, 120 actual oscil-
lator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration
register. Assuming that the oscillator is running at
exactly 32,768Hz, each of the 31 increments in the
Calibration byte would represent +10.7 or –5.35
seconds per month which corresponds to a total
range of +5.5 or –2.75 minutes per month. Figure
11 illustrates a TIMEKEEPER calibration wave-
form.
Two methods are available for ascertaining how
much calibration a given M48T513Y/V may re-
quire. The first involves setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference and recording deviation over a fixed
period of time.
Calibration values, including the number of sec-
onds lost or gained in a given period, can be found
in Application Note: TIMEKEEPER CALIBRA-
TION.
Figure 10. Chip Enable Controlled, Write AC Waveforms
AI02582
tAVAV
tEHAX
tDVWH
A0-A16
E
W
DQ0-DQ7
VALID
tAVEL
tAVWL
tELEH
tWHDX
DATA INPUT
13/23
M48T513Y, M48T513V
Figure 11. Calibration Waveform
AI00594B
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
Table 11. TIMEKEEPER Register Map
Address Data Function/Range
BCD Format
D7 D6 D5 D4 D3 D2 D1 D0
7FFFFh 10 Years Year Year 00-99
7FFFEh 0 0 0 10 M Month Month 01-12
7FFFDh 0 0 10 Date Date Date 01-31
7FFFCh 0 FT 0 0 0 Day of Week Day 01-07
7FFFBh 0 0 10 Hours Hours (24 Hour Format) Hour 00-23
7FFFAh 0 10 Minutes Minutes Minutes 00-59
7FFF9h ST 10 Seconds Seconds Seconds 00-59
7FFF8h W R S Calibration Control
7FFF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
7FFF6h AFE 0 ABE Al 10M Alarm Month A Month 01-12
7FFF5h RPT4 RPT5 Al 10 Date Alarm Date Al Date 01-31
7FFF4h RPT3 0 Al 10 Hours Alarm Hours A Hours 00-23
7FFF3h RPT2 Al 10 Minutes Alarm Minutes A Min 00-59
7FFF2h RPT1 Al 10 Seconds Alarm Seconds A Sec 00-59
7FFF1h 1000 Year 100 Year Century 00-99
7FFF0h WDF AF 0 BL Y Y Y Y Flag
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit
R = READ Bit
W = WRITEBit
ST = STOP Bit
0 = Must be set to ’0’
Y = ’1’or ’0’
BL = Battery Low
AF = Alarm Flag
WDS = Watchdog Steering Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable
ABE = Alarm in Battery Back-up Mode Enable
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF =Watchdog Flag
M48T513Y, M48T513V
14/23
Figure 12. Alarm Interrupt Reset Waveform
Figure 13. Back-up Mode Alarm Waveforms
AI02581
AD0-AD7
ACTIVE FLAG BIT
ADDRESS 1FF0h
IRQ/FT
HIGH-Z
15ns Min
AI01678C
VCC
IRQ/FT
HIGH-Z
VPFD (max)
VPFD (min)
AFE bit in Interrupt Register
AF bit in Flags Register
HIGH-Z
VSO
tREC
15/23
M48T513Y, M48T513V
Table 12. Alarm Repeat Mode
RPT4 RPT3 RPT2 RPT1 Alarm Activated
1111Once per Second
1110Once per Minute
1100Once per Hour
1000Once per Day
1000Once per Month
This allows the designer to give the end user the
ability to calibrate theclock as theenvironment re-
quires, even if the final product is packaged in a
non-user serviceable enclosure. The designer
could provide a simple utility that accesses the
Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz, when the
Stop bit (ST, D7 of 7FFF9h) is ’0’, the Frequency
Test bit (FT, D6 of 7FFFCh) is ’1’, the Alarm Flag
Enable bit (AFE, D7 of 7FFF6h) is ’0’, and the
Watchdog Steering bit (WDS, D7 of 7FFF7h) is ’1’
or the Watchdog Register (7FFF7h = 0) is reset.
Note: A 4 second settling time must be allowed
before reading the 512Hz output.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequencyshift atthe test
temperature. For example, a reading of
512.010124Hz wouldindicatea +20ppm oscillator
frequency error, requiringa –10 (WR001010)to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency testoutput frequen-
cy.
The IRQ/FT pin is an open drain output which re-
quires a pull-up resistor for proper operation. A
500-10kΩresistor is recommended in order to
control the rise time. The FT bit is cleared on pow-
er-up.
BATTERY LOW WARNING
The M48T513Y/V automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) bit, Bit D4 of Flags
Register 7FFF0h, will be asserted if the battery
voltage is found to be less than approximately
2.5V.
If a battery lowis generated during apower-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal VCC is
supplied.
The M48T513Y/V only monitors the battery when
a nominalVCC isapplied to the device. Thus appli-
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
POWER-ON DEFAULTS
Upon application of power to the device, the fol-
lowing register bits are set to a ’0’ state: WDS,
BMB0-BMB4, RB0,RB1, AFE, ABE, W, R and FT.
M48T513Y, M48T513V
16/23
Table 13. Reset AC Characteristics
(TA= 0 to 70 °C, VCC = 3.0Vto 3.6V or VCC = 4.5V to 5.5V)
Note: 1. CL= 5pF (see Figure 5)
Symbol Parameter Min Max Unit
tRRSTIN Low to RST Low 20 100 ms
tRHRZ (1) RSTIN High to RST Hi-Z 40 200 ms
Figure 14. RSTIN Timing Waveform
AI02585
tRHRZ
RSTIN
RST
tR
Hi-Z Hi-Z
POWER SUPPLY DECOUPLING
and UNDERSHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, re-
sulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store en-
ergy, which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (see Figure 15) is
recommended in order to provide the needed fil-
tering. In addition to transients that are caused by
normal SRAM operation, powercycling can gener-
ate negative voltage spikes on VCC that drive it to
values below VSS by as much as one volt. These
negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, ST recommends con-
necting aschottky diode from VCC toVSS(cathode
connected to VCC, anode to VSS). (Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surfacemount).
Figure 15. Supply Voltage Protection
AI02169
VCC
0.1µF DEVICE
VCC
VSS
17/23
M48T513Y, M48T513V
Table 14. Ordering Information Scheme
Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT)which is ordered separately under the part number
”M4Txx-BR12SH1” in plastic tube or ”M4Txx-BR12SH1TR” in Tape & Reel form.
Caution: Donot place theSNAPHAT battery package ”M4Txx-BR12SH1” in conductive foam since thiswill drain the lithium button-cell
battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
Example: M48T513Y -70 PL 1
Device Type
M48T
Supply Voltage and Write Protect Voltage
513Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V
513V = VCC = 3.0V to 3.6V; VPFD = 2.7V to 3.0V
Speed
-70 = 70ns
-85 = 85 ns
Package
PL = PMLDIP36
CS(1) = Surface Mount Chip Set solution M48T201Y/V (SOH44) + M68Z512/W (TSOP32)
Temperature Range
1=0to70°C
Table 15. Revision History
Date Revision Details
April 2000 Chipset datasheet First Issue
06/20/00 From Preliminary Data to data Sheet
07/03/00 85ns speed class for M48T513Y added (Table 9, 10)
07/26/00 Ordering Information Scheme Changed (Table 14)
M48T513Y, M48T513V
18/23
Table 16. PMLDIP36 - 36 pin Plastic DIP Long Module, Package Mechanical Data
Symb mm inches
Typ Min Max Typ Min Max
A 9.27 9.52 0.3650 0.3748
A1 0.38 0.0150
B 0.43 0.59 0.0169 0.0232
C 0.20 0.33 0.0079 0.0130
D 52.58 53.34 2.0701 2.1000
E 18.03 18.80 0.7098 0.7402
e1 2.30 2.81 0.0906 0.1106
e3 38.86 47.50 1.5300 1.8701
eA 14.99 16.00 0.5902 0.6299
L 3.05 3.81 0.1201 0.1500
S 4.45 5.33 0.1752 0.2098
N36 36
Figure 16. PMLDIP36 - 36 pin Plastic DIP Long Module, Package Outline
Drawing is not to scale.
PMDIP
A1
A
L
Be1
D
E
N
1
eA
e3
SC
19/23
M48T513Y, M48T513V
Table 17. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Mechanical Data
Symbol mm inch
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041
b 0.30 0.52 0.012 0.020
C 0.12 0.21 0.005 0.008
CP 0.10 0.004
D 20.82 21.08 0.820 0.830
e 1.27 – – 0.050 – –
E 11.56 11.96 0.455 0.471
E1 10.03 10.29 0.395 0.405
L 0.40 0.60 0.016 0.024
α0°5°0°5°
N32 32
Figure 17. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Outline
Drawing is not to scale.
TSOP-d
16
17
CP
A
1
L
A1 α
32
D
eb
E1 E
C
A2
M48T513Y, M48T513V
20/23
Table 18. SH- 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
Symb mm inches
Typ Min Max Typ Min Max
A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
Figure 18. SH - 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
Drawing is not to scale.
SHTK-A
A1 A
D
E
eA
eB
A2
BL
A3
21/23
M48T513Y, M48T513V
Table 19. SH- 4-pin SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data
Symb mm inches
Typ Min Max Typ Min Max
A 10.54 0.415
A1 8.00 8.51 0.315 .0335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 .0710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
Figure 19. SH - 4-pin SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline
Drawing is not to scale.
SHTK-A
A1 A
D
E
eA
eB
A2
BL
A3
M48T513Y, M48T513V
22/23
Table 20. SOH44 - 44 lead Plastic Small Outline, 4-socket battery, SNAPHAT,
Package Mechanical Data
Symb mm inches
Typ Min Max Typ Min Max
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.46 0.014 0.018
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e 0.81 – – 0.032 – –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α0°8°0°8°
N44 44
CP 0.10 0.004
Figure 20. SOH44 - 44 lead Plastic Small Outline, 4-socket battery, SNAPHAT, Package Outline
Drawing is not to scale.
SOH-A
E
N
D
C
LA1 α
1
H
A
CP
Be
A2
eB
23/23
M48T513Y, M48T513V
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of use ofsuch information nor for any infringement of patents or other rights of third parties which may result from itsuse. No license is granted
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