Micropower, 3-Axis, 200 g Digital Output, MEMS ADXL372 Data Sheet FEATURES GENERAL DESCRIPTION 200 g measurement range 200 Hz to 3200 Hz user selectable bandwidth with 4-pole antialiasing filter Selectable oversampling ratio Adjustable high-pass filter Ultralow power Power can be derived from a coin cell battery 22 A at 3200 Hz ODR, 2.5 V supply Low power, wake-up mode for low g activity detection 1.4 A instant on mode with adjustable threshold <0.1 A standby mode Built in features for system level power savings Autonomous interrupt processing without processor intervention Deep embedded FIFO to minimize host processor load Ultralow power event monitoring detects impacts and wakes up fast enough to capture the transient events Ability to capture and store peak acceleration values of events Adjustable, low g threshold activity and inactivity detection Wide supply range: 1.6 V to 3.5 V Acceleration sample synchronization via external trigger SPI digital interface and limited I2C interface format support 12-bit output at 100 mg/LSB scale factor Wide temperature range: -40C to +105C Small, thin, 3 mm x 3.25 mm x 1.06 mm package The ADXL372 is an ultralow power, 3-axis, 200 g MEMS accelerometer that consumes 22 A at a 3200 Hz output data rate (ODR). The ADXL372 does not power cycle its front end to achieve its low power operation and therefore does not run the risk of aliasing the output of the sensor. In addition to its ultralow power consumption, the ADXL372 has many features to enable impact detection while providing system level power reduction. The device includes a deep multimode output first in, first out (FIFO), several activity detection modes, and a method for capturing only the peak acceleration of over threshold events. Two additional lower power modes with interrupt driven, wake-up features are available for monitoring motion during periods of inactivity. In wake-up mode, acceleration data can be averaged to obtain a low enough output noise to trigger on low g thresholds. In instant on mode, the ADXL372 consumes 1.4 A while continuously monitoring the environment for impacts. When an impact event that exceeds the internally set threshold is detected, the device switches to normal operating mode fast enough to record the event. High g applications tend to experience acceleration content over a wide range of frequencies. The ADXL372 includes a 4-pole lowpass antialiasing filter to attenuate out of band signals that are common in high g applications. The ADXL372 also incorporates a high-pass filter to eliminate initial and slow changing errors, such as ambient temperature drift. APPLICATIONS The ADXL372 provides 12-bit output data at 100 mg/LSB scale factor. The user can access configuration and data registers via the serial peripheral interface (SPI) or limited I2C protocol. The ADXL372 operates over a wide supply voltage range and is available in a 3 mm x 3.25 mm x 1.06 mm package. Impact and shock detection Asset health assessment Portable Internet of Things (IoT) edge nodes Concussion and head trauma detection Multifunction pin names may be referenced by their relevant function only. FUNCTIONAL BLOCK DIAGRAM VS VDDI/O INT1 INT2 3-AXIS MEMS SENSOR 12-BIT ADC DIGITAL LOGIC, FIFO, AND SPI MOSI MISO CS AXIS DEMODULATORS 4-POLE ANTIALIASING FILTERS ADXL372 15430-001 SCLK GND Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2017-2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADXL372 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Multibyte Transfers .................................................................... 26 Applications ....................................................................................... 1 Invalid Addresses and Address Folding .................................. 27 General Description ......................................................................... 1 Register Map ................................................................................... 30 Functional Block Diagram .............................................................. 1 Register Details ............................................................................... 32 Revision History ............................................................................... 3 Analog Devices ID Register ...................................................... 32 Specifications..................................................................................... 4 Analog Devices MEMS ID Register......................................... 32 Absolute Maximum Ratings............................................................ 6 Device ID Register ..................................................................... 32 Thermal Resistance ...................................................................... 6 Product Revision ID Register ................................................... 32 Recommended Soldering Profile ............................................... 6 Status Register ............................................................................. 33 ESD Caution .................................................................................. 6 Activity Status Register .............................................................. 33 Pin Configuration and Function Descriptions ............................. 7 FIFO Entries Register, MSB ...................................................... 34 Typical Performance Characteristics ............................................. 8 FIFO Entries Register, LSB ........................................................ 34 Theory of Operation ...................................................................... 13 X-Axis Data Register, MSB ....................................................... 34 Mechanical Device Operation .................................................. 13 X-Axis Data Register, LSB ......................................................... 34 Operating Modes ........................................................................ 13 Y-Axis Data Register, MSB ........................................................ 35 Bandwidth ................................................................................... 13 Y-Axis Data Register, LSB ......................................................... 35 Power/Noise Trade-Off .............................................................. 14 Z-Axis Data Register, MSB ....................................................... 35 Power Savings ............................................................................. 15 Z-Axis Data Register, LSB ......................................................... 35 Autonomous Event Detection....................................................... 16 Highest Peak Data Registers ..................................................... 36 Activity and Inactivity................................................................ 16 X-Axis Highest Peak Data Register, MSB ............................... 36 Motion Warning ......................................................................... 18 X-Axis Highest Peak Data Register, LSB ................................. 36 Impact Detection Features ............................................................ 19 Y-Axis Highest Peak Data Register, MSB ................................ 36 Wide Bandwidth ......................................................................... 19 Y-Axis Highest Peak Data Register, LSB ................................. 37 Instant On Impact Detection .................................................... 19 Z-Axis Highest Peak Data Register, MSB ............................... 37 Capturing Impact Events ........................................................... 19 Z-Axis Highest Peak Data Register, LSB ................................. 37 FIFO ................................................................................................. 20 Offset Trim Registers ................................................................. 38 Benefits of the FIFO ................................................................... 20 X-Axis Offset Trim Register, LSB ............................................. 38 Using the FIFO ........................................................................... 20 Y-Axis Offset Trim Register, LSB ............................................. 38 Retrieving Data from FIFO ....................................................... 21 Z-Axis Offset Trim Register, LSB ............................................. 38 Interrupts ......................................................................................... 22 X-Axis Activity Threshold Register, MSB ............................... 39 Interrupt Pins .............................................................................. 22 X-Axis of Activity Threshold Register, LSB ............................ 39 Types of Interrupts ..................................................................... 22 Y-Axis Activity Threshold Register, MSB ............................... 39 Additional Features ........................................................................ 24 Y-Axis of Activity Threshold Register, LSB ............................ 40 Using an External Clock ............................................................ 24 Z-Axis Activity Threshold Register, MSB ............................... 40 Synchronized Data Sampling .................................................... 24 Z-Axis of Activity Threshold Register, LSB ............................ 40 Self Test ........................................................................................ 24 Activity Time Register ............................................................... 41 User Register Protection ............................................................ 25 X-Axis Inactivity Threshold Register, MSB ............................ 41 User Offset Trims ....................................................................... 25 X-Axis of Inactivity Threshold Register, LSB ......................... 42 Serial Communications ................................................................. 26 Y-Axis Inactivity Threshold Register, MSB ............................ 42 Serial Interface ............................................................................ 26 Y-Axis of Inactivity Threshold Register, LSB ......................... 43 Rev. B | Page 2 of 56 Data Sheet ADXL372 Z-Axis Inactivity Threshold Register, MSB .............................43 INT2 Function Map Register .................................................... 50 Z-Axis of Inactivity Threshold Register, LSB ..........................43 External Timing Control Register ............................................ 50 Inactivity Time Registers............................................................44 Measurement Control Register ................................................. 51 Inactivity Timer Register, MSB .................................................44 Power Control Register .............................................................. 52 Inactivity Timer Register, LSB ...................................................44 Self Test Register ......................................................................... 53 X-Axis Motion Warning Threshold Register, MSB ................45 RESET (Clears) Register, Part in Standby Mode .................... 53 X-Axis of Motion Warning Notification Register, LSB ..........45 FIFO Access Register .................................................................. 53 Y-Axis Motion Warning Notification Threshold Register, MSB ...............................................................................................46 Applications Information ............................................................... 54 Y-Axis of Motion Warning Notification Register, LSB ..........46 Operation at Voltages Other Than 2.5 V ................................. 54 Z-Axis Motion Warning Notification Threshold Register, MSB ...............................................................................................46 Operation at Temperatures Other Than Ambient.................. 54 Z-Axis Motion Warning Notification Register, LSB...............47 High-Pass Filter Settings Register .............................................47 FIFO Samples Register ...............................................................48 FIFO Control Register ................................................................48 Interrupt Pin Function Map Registers .....................................49 Application Examples ................................................................. 54 Mechanical Considerations for Mounting .............................. 54 Axes of Acceleration Sensitivity ................................................ 55 Layout and Design Recommendations .................................... 55 Outline Dimensions ........................................................................ 56 Ordering Guide ........................................................................... 56 REVISION HISTORY 8/2018--Rev. A to Rev. B Changes to Figure 34 ......................................................................19 Changes to I2C Protocol Section ...................................................26 Added Note 1, Table 14; Renumbered Sequentially ...................31 12/2017--Rev. 0 to Rev. A Changes to Turn-On Time, Measurement Mode Instruction to Valid Data Parameter; Table 1 ......................................................... 5 Changes to Instant On Impact Detection Section ......................19 Changes to Address: 0x3A, Reset: 0x00, Name: FIFO_CTL Section ..............................................................................................48 3/2017--Revision 0: Initial Version Rev. B | Page 3 of 56 ADXL372 Data Sheet SPECIFICATIONS TA = 25C, VS = 2.5 V, VDDI/O = 2.5 V, 3200 Hz ODR, 1600 Hz bandwidth, acceleration = 0 g, default register settings, unless otherwise noted. All minimum and maximum specifications are guaranteed. Typical specifications may not be guaranteed. Table 1. Parameter SENSOR INPUT Measurement Range Nonlinearity Sensor Resonant Frequency Cross Axis Sensitivity1 OUTPUT RESOLUTION All Operating Modes SCALE FACTOR Scale Factor Calibration Error Scale Factor at XOUT, YOUT, ZOUT Scale Factor Change Due to Temperature2 0 g OFFSET 0 g Output 0 g Offset vs. Temperature2 Normal Operation Low Noise Mode NOISE PERFORMANCE RMS Noise Normal Operation Low Noise Mode BANDWIDTH ODR High-Pass Filter, -3 dB Corner3 Low-Pass (Antialiasing) Filter, -3 dB Corner4 POWER SUPPLY Operating Voltage Range (VS) Input/Output Voltage Range (VDDI/O) Supply Current Measurement Mode Normal Operation Low Noise Mode Instant On Mode Wake-Up Mode Standby Power Supply Rejection Ratio (PSRR) Test Conditions/Comments Each axis Min Percentage of full scale Typ Max Unit 200 0.5 16 2.5 g % kHz % 12 Bits Each axis Each axis Expressed in mg/LSB Expressed in LSB/g Each axis XOUT, YOUT, ZOUT At VS = 2.5 V 1.6 V VS 3.5 V 10 % mg/LSB LSB/g %/C +3 +7 g g 100 10 0.1 -3 -7 XOUT, YOUT, ZOUT XOUT, YOUT, ZOUT 1 1 50 35 mg/C mg/C 3.5 3 LSB LSB Each axis User selectable 4-pole low-pass filter 400 0.24 200 1.6 1.6 2.5 2.5 6400 30.48 ODR/2 Hz Hz Hz 3.5 VS V V 3200 Hz ODR Varies with wake-up rate At slowest wake-up rate 22 33 1.4 A A A 0.77 <0.1 A A -20 -17 dB dB CS = 1.1 F, CIO = 1.1 F, input is 100 mV sine wave on VS Input Frequency 100 Hz to 1 kHz 1 kHz to 250 kHz Rev. B | Page 4 of 56 Data Sheet ADXL372 Parameter Turn-On Time Power-Up to Standby Measurement Mode Instruction to Valid Data Test Conditions/Comments 3200 Hz ODR CS = 1.1 F, CIO = 1.1 F Filter settle bit = 1 Filter settle bit = 0 Instant On ULP Monitoring to Full Bandwidth Data ENVIRONMENTAL TEMPERATURE Operating Temperature Range Min Cross axis sensitivity is defined as coupling between any two axes. -40C to +25C or +25C to +105C. 3 This parameter has an available corner frequency scale with the ODR setting. 4 Bandwidth and ODR are set independent of each other. 2 Rev. B | Page 5 of 56 Max 5 16 370 1 -40 1 Typ Unit ms ms ms ms +105 C ADXL372 Data Sheet ABSOLUTE MAXIMUM RATINGS RECOMMENDED SOLDERING PROFILE Table 2. Figure 2 and Table 4 provide details about the recommended soldering profile. 10000 g 10000 g -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to VS Indefinite 2000 V -50C to +150C THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 3. Package Type CC-16-4 1 1 JA 150 JC 85 Unit C/W RAMP-UP TL tL TSMAX TSMIN tS RAMP-DOWN PREHEAT Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Device Weight 18 mg Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESD51. CRITICAL ZONE TL TO TP tP TP 15430-002 Rating TEMPERATURE Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VS VDDI/O All Other Pins Output Short-Circuit Duration (Any Pin to Ground) ESD, Human Body Model (HBM) Temperature Range (Storage) t25C TO PEAK TIME Figure 2. Recommended Soldering Profile Table 4. Recommended Soldering Profile Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time (TSMIN to TSMAX) (tS) TSMAX to TL Ramp-Up Rate Time Maintained Above Liquidous (TL) Liquidous Temperature (TL) Time (tL) Peak Temperature (TP) Time Within 5C of Actual Peak Temperature (tP) Ramp-Down Rate Time 25C to Peak Temperature ESD CAUTION Rev. B | Page 6 of 56 Sn63/Pb37 3C/sec max Condition Pb-Free 3C/sec max 100C 150C 60 sec to 120 sec 150C 200C 60 sec to 180 sec 3C/sec max 3C/sec max 183C 60 sec to 150 sec 240 + 0/-5C 10 sec to 30 sec 217C 60 sec to 150 sec 260 + 0/-5C 20 sec to 40 sec 6C/sec max 6 minutes max 6C/sec max 8 minutes max Data Sheet ADXL372 GND NIC VS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 15 14 VDDI/O 1 13 GND NIC 2 12 GND 11 INT1 10 RESERVED ADXL372 RESERVED 5 9 6 7 8 INT2 NOTES 1. NIC = NO CONNECT. THIS PIN IS NOT INTERNALLY CONNECTED. 15430-003 4 CS/SCL SCLK TOP VIEW (Not to Scale) MISO 3 MOSI/SDA RESERVED Figure 3. Pin Configuration (Top View) Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic VDDI/O NIC RESERVED SCLK RESERVED MOSI/SDA MISO CS/SCL INT2 RESERVED INT1 GND GND VS NIC GND Description Supply Voltage for Digital Input/Output. No Connect. This pin is not internally connected. Reserved. This pin may be left unconnected or connected to GND. SPI Serial Communications Clock. Reserved. This pin may be left unconnected or connected to GND. SPI Master Output, Slave Input (MOSI). I2C Serial Data (SDA). SPI Master Input, Slave Output. SPI Chip Select (CS). I2C Serial Communications Clock (SCL). Interrupt 2 Output. This pin also serves as an input for synchronized sampling. Reserved. This pin may be left unconnected or connected to GND. Interrupt 1 Output. This pin also serves as an input for external clocking. Ground. This pin must be connected to ground. Ground. This pin must be connected to ground. Supply Voltage. No Connect. This pin is not internally connected. Ground. This pin must be connected to ground. Rev. B | Page 7 of 56 ADXL372 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 60 35 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 144 PARTS FROM THREE DIFFERENT PRODUCTION LOTS, FLIPPED IN 1g FIELD. 30 50 PERCENT OF POPULATION (%) 40 30 20 10 20 15 10 5 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 ZERO g OFFSET (LSB) 0 15430-004 0 25 8.0 8.4 8.8 9.2 9.6 10.0 10.4 10.8 11.2 11.6 12.0 SENSITIVITY (LSB/g) Figure 4. X-Axis Zero g Offset at 25C, VS = 2.5 V 15430-007 PERCENT OF POPULATION (%) DISTRIBUTIONS SHOWN ARE OBTAINED FROM 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. Figure 7. X-Axis Sensitivity at 25C, VS = 2.5 V 70 50 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. DISTRIBUTIONS SHOWN ARE OBTAINED FROM 144 PARTS FROM THREE DIFFERENT PRODUCTION LOTS, FLIPPED IN 1g FIELD. PERCENT OF POPULATION (%) PERCENT OF POPULATION (%) 60 50 40 30 20 40 30 20 10 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 ZERO g OFFSET (LSB) 0 15430-005 0 8.0 8.8 9.2 9.6 10.0 10.4 10.8 11.2 11.6 12.0 SENSITIVITY (LSB/g) Figure 5. Y-Axis Zero g Offset at 25C, VS = 2.5 V Figure 8. Y-Axis Sensitivity at 25C, VS = 2.5 V 60 45 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. 40 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 144 PARTS FROM THREE DIFFERENT PRODUCTION LOTS, FLIPPED IN 1g FIELD. PERCENT OF POPULATION (%) 50 40 30 20 10 35 30 25 20 15 10 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 ZERO g OFFSET (LSB) 30 0 8.0 8.4 8.8 9.2 9.6 10.0 10.4 10.8 11.2 11.6 12.0 SENSITIVITY (LSB/g) Figure 6. Z-Axis Zero g Offset at 25C, VS = 2.5 V Figure 9. Z-Axis Sensitivity at 25C, VS = 2.5 V Rev. B | Page 8 of 56 15430-009 5 0 15430-006 PERCENT OF POPULATION (%) 8.4 15430-008 10 Data Sheet 12 10 8 6 4 2 -40 -30 -20 -10 0 10 20 30 40 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/C) 0 -1 -2 -3 -4 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 13. X-Axis Zero g Normalized Offset vs. Temperature, 36 Parts Soldered to PCB, ODR = 3200 Hz 20 5 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 143 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. TEMPERATURE COEFFICIENTS ARE MEASURED BETWEEN -40C TO 25C AND BETWEEN 25C TO 105C. THE DISPLAYED TEMPERATURE COEFFICIENT IS THE LARGER OF THE TWO. Y-AXIS ZERO g NORMALIZED OFFSET (g) PERCENT OF POPULATION (%) 1 Figure 10. X-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V 18 16 14 12 10 8 6 4 2 -40 -30 -20 -10 0 10 20 30 40 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/C) 4 3 2 1 0 -1 -2 -3 -4 -5 -60 15430-011 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 11. Y-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V Figure 14. Y-Axis Zero g Normalized Offset vs. Temperature, 36 Parts Soldered to PCB, ODR = 3200 Hz 25 5 Z-AXIS ZERO g NORMALIZED OFFSET (g) DISTRIBUTIONS SHOWN ARE OBTAINED FROM 143 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. TEMPERATURE COEFFICIENTS ARE MEASURED BETWEEN -40C TO 25C AND BETWEEN 25C TO 105C. THE DISPLAYED TEMPERATURE COEFFICIENT IS THE LARGER OF THE TWO. 20 15 10 5 0 -40 -30 -20 -10 0 10 20 30 40 ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/C) 4 3 2 1 0 -1 -2 -3 -4 -5 -60 15430-012 PERCENT OF POPULATION (%) 2 -5 -60 15430-010 0 3 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 15. Z-Axis Zero g Normalized Offset vs. Temperature, 36 Parts Soldered to PCB, ODR = 3200 Hz Figure 12. Z-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V Rev. B | Page 9 of 56 15430-013 14 4 15430-014 16 15430-015 PERCENT OF POPULATION (%) 18 5 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 143 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. TEMPERATURE COEFFICIENTS ARE MEASURED BETWEEN -40C TO 25C AND BETWEEN 25C TO 105C. THE DISPLAYED TEMPERATURE COEFFICIENT IS THE LARGER OF THE TWO. X-AXIS ZERO g NORMALIZED OFFSET (g) 20 ADXL372 ADXL372 Data Sheet 1.05 70 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. X-AXIS NORMALIZED SENSITIVITY DEVIATION FROM 25C 1.04 60 PERCENT OF POPULATION (%) 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 50 40 30 20 10 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 0 15430-016 0.94 -60 Figure 16. X-Axis Normalized Sensitivity Deviation from 25C vs. Temperature, 18 Parts Soldered to PCB, ODR = 3200 Hz 16 18 20 22 24 26 28 15430-019 0.95 30 CURRENT CONSUMPTION (A) Figure 19. Current Consumption at 25C, Normal Mode, 3200 Hz Output Data Rate, VS = 2.5 V 1.04 70 60 PERCENT OF POPULATION (%) 1.02 1.01 1.00 0.99 0.98 20 0 40 60 80 100 120 Figure 17. Y-Axis Normalized Sensitivity Deviation from 25C vs. Temperature, 17 Parts Soldered to PCB, ODR = 3200 Hz 20 0 24 26 28 30 32 34 36 38 40 CURRENT CONSUMPTION (A) Figure 20. Current Consumption at 25C, Low Noise Mode, 3200 Hz Output Data Rate, VS = 2.5 V 1.04 70 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. 1.03 60 PERCENT OF POPULATION (%) Z-AXIS NORMALIZED SENSITIVITY DEVIATION FROM 25C 30 15430-020 -20 15430-017 -40 TEMPERATURE (C) 1.02 1.01 1.00 0.99 0.98 0.97 50 40 30 20 10 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 15430-018 0.96 -60 40 10 0.97 0.96 -60 50 Figure 18. Z-Axis Normalized Sensitivity Deviation from 25C vs. Temperature, 18 Parts Soldered to PCB, ODR = 3200 Hz 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 CURRENT CONSUMPTION (A) 2.0 2.2 15430-021 Y-AXIS NORMALIZED SENSITIVITY DEVIATION FROM 25C DISTRIBUTIONS SHOWN ARE OBTAINED FROM 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. 1.03 Figure 21. Current Consumption at 25C, Instant On Mode, VS = 2.5 V Rev. B | Page 10 of 56 Data Sheet ADXL372 60 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. 60 PERCENT OF POPULATION (%) 40 30 20 10 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 CURRENT CONSUMPTION (A) 30 20 0 0 10 15 20 25 30 35 40 Figure 25. Current Consumption at 25C, Standby Mode, VS = 2.5 V 4.5 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. VDD = 1.6V VDD = 2.5V VDD = 3.5V 4.0 50 3.5 STANDBY CURRENT (A) PERCENT OF POPULATION (%) 5 CURRENT CONSUMPTION (nA) Figure 22. Current Consumption at 25C, Wake-Up Mode, VS = 2.5 V 60 40 10 15430-022 0 50 15430-025 PERCENT OF POPULATION (%) 50 70 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. 40 30 20 3.0 2.5 2.0 1.5 1.0 10 -10 -5 0 5 10 15 20 25 30 0 -50 40 MEASUREMENT MODE CURRENT (A) PERCENT OF POPULATION (%) DISTRIBUTIONS SHOWN ARE OBTAINED FROM 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. 50 40 30 20 10 -5 0 5 10 15 20 25 CLOCK FREQUENCY DEVIATION FROM IDEAL (%) 30 15430-024 -10 30 50 70 90 110 VDD = 1.6V VDD = 2.5V VDD = 3.5V 35 30 25 20 15 10 -50 -15 10 Figure 26. Standby Current vs. Temperature 60 -20 -10 TEMPERATURE (C) Figure 23. Clock Frequency Deviation from Ideal at 25C, ODR = 3200 Hz, VS = 2.5 V 0 -30 -30 -10 10 30 50 70 90 110 TEMPERATURE (C) Figure 24. Clock Frequency Deviation from Ideal at 25C, ODR = 6400Hz, VS = 2.5 V Rev. B | Page 11 of 56 Figure 27. Measurement Mode Current vs. Temperature 15430-027 -15 CLOCK FREQUENCY DEVIATION FROM IDEAL (%) 15430-023 -20 15430-026 0.5 0 ADXL372 6 VDD = 1.6V VDD = 2.5V VDD = 3.5V WAKE-UP CURRENT (A) 5 4 3 2 1 0 -50 4 3 2 1 -30 -10 10 30 50 70 90 TEMPERATURE (C) 110 0 -50 15430-028 INSTANT ON CURRENT (A) 5 VDD = 1.6V VDD = 2.5V VDD = 3.5V -30 -10 10 30 50 70 90 TEMPERATURE (C) Figure 28. Instant On Current vs. Temperature Figure 29. Wake-Up Current vs. Temperature Rev. B | Page 12 of 56 110 15430-029 6 Data Sheet Data Sheet ADXL372 THEORY OF OPERATION The ADXL372 is a complete 3-axis acceleration measurement system that operates at extremely low power levels. Acceleration is reported digitally, and the device communicates via the SPI and I2C protocols. Built in digital logic enables autonomous operation and implements functions that enhance system level power savings. MECHANICAL DEVICE OPERATION The moving component of the sensor is a polysilicon surface micromachined structure built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces. Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. Acceleration deflects the structure and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. Phase sensitive demodulation determines the magnitude and polarity of the acceleration. OPERATING MODES The ADXL372 has three operating modes: measurement mode for continuous, wide bandwidth sensing; an instant on mode for low power impact detection; and wake-up mode for limited bandwidth low g activity detection. Measurement can be suspended by placing the device in standby mode. Measurement Mode Measurement mode is the default operating mode of the ADXL372. In this mode, acceleration data is read continuously, and the accelerometer consumes 22 A (typical) at an ODR of 3200 Hz using a 2.5 V supply. Actual current consumption is dependent on the ODR chosen. All features described in this data sheet are available when operating the ADXL372 in this mode. Instant On Mode Instant on mode enables extremely low power impact detection. In this mode, the accelerometer constantly monitors the environment while consuming a very low current of 1.4 A (typical). When an event that exceeds an internal threshold is detected, the device switches into measurement mode to record the event. The target default threshold is 10 g to 15 g, but it can vary. A register option allows the threshold to be increased to a target of 30 g to 40 g if the default threshold is too low. To save power, no new digital acceleration data is made available until the accelerometer switches into normal operation. However, all registers have normal read/write functionality. Wake-Up Mode Wake-up mode is ideal for simple detection of the presence or absence of motion at an extremely low power consumption. Wakeup mode is particularly useful for the implementation of a low g motion activated on/off switch, allowing the rest of the system to be powered down until sustained activity is detected. In wake-up mode, the device is powered down for a duration of time equal to the wake-up timer, set by the WAKEUP_RATE bits in the TIMING register, and then turns on for a duration equal to the filter settling time (see the Filter Settling Time section). The current drawn in this mode is determined by both these parameters. Table 6. Wake-Up Current in A at Different Wake-Up Timer and Filter Settings Wake-Up Timer (ms) 52 104 208 512 2048 4096 8192 24576 Filter Settling Time 16 ms 370 ms 5.8 A 19.4 A 3.6 A 17.3 A 2.3 A 14.4 A 1.4 A 9.7 A 0.91 A 4 A 0.83 A 2.5 A 0.79 A 1.7 A 0.77 A 1.1 A If motion is detected, the accelerometer can respond autonomously in several ways, depending on the device configuration, such as the following: * * * Switch into full bandwidth measurement mode. Signal an interrupt to a microcontroller. Wake up downstream circuitry. While in wake-up mode, all registers and the FIFO have normal read/write functionality, and real-time data can be read from the data registers at the reduced wake-up rate. However, no new data is stored in the FIFO during wake-up mode, and there are no interrupts available in wake-up mode. Standby Placing the ADXL372 in standby mode suspends measurement and reduces current consumption to less than 100 nA. All interrupts are cleared, and no new interrupts are generated. The ADXL372 powers up in standby mode with all sensor functions turned off. BANDWIDTH Low-Pass Antialiasing Filter High g events often include acceleration content over a wide range of frequencies. The analog-to-digital converter (ADC) of the ADXL372 samples the input acceleration at the user selected ODR. In the absence of antialiasing filters, input signals whose frequency is more than half the ODR alias or that fold into the measurement bandwidth can lead to inaccurate measurements. To mitigate this inaccuracy, a four-pole, low-pass filter is provided at the input of the ADC. The filter bandwidth is user selectable, and the default bandwidth is 200 Hz. The maximum bandwidth is constrained to at most half of the ODR, to ensure that the Nyquist criteria is not violated. Rev. B | Page 13 of 56 ADXL372 Data Sheet High-Pass Filter 50 The ADXL372 offers a one-pole, high-pass filter with a user selectable -3 dB frequency. Applications that do not require dc acceleration measurements can use the high-pass filter to minimize constant or slow varying offset errors including initial bias, bias drift due to temperature, and bias drift due to supply voltage. CURRENT (A) 40 The high-pass filter is a first-order infinite impulse response (IIR) filter. Table 7 lists the available -3 dB frequencies, which are user selectable and dependent on the output data rate. The high-pass and low-pass filters can be used simultaneously to set up a band-pass option. 6400 30.48 15.58 7.88 3.96 3200 15.24 7.79 3.94 1.98 0 800 3.81 1.94 0.98 0.49 256 1024 4096 ODR (Hz) Figure 30. Measurement Mode Current vs. ODR for Five Parts 400 1.9 0.97 0.49 0.24 POWER/NOISE TRADE-OFF Filter Settling Time After entering measurement mode, the first output value does not appear until after the filter settling time has passed. This time is selectable using the FILTER_SETTLE bit in the POWER_CTL register. The recommended (and default) settling time to acquire valid data when using either the high-pass filter or the low-pass activity detect filter is 370 ms. The filter settling time of 16 ms is ideal for when both the high-pass filter and low-pass activity detect filter are disabled. Selectable ODR The ADXL372 can report acceleration data at 400 Hz, 800 Hz, 1600 Hz, 3200 Hz, or 6400 Hz. The ODR is user selectable and the default is 400 Hz. In the event that the user selects an antialiasing filter bandwidth greater than half the ODR, the device defaults the bandwidth to half the ODR. Increasing or decreasing the ODR increases or decreases the current consumption accordingly, as shown in Figure 30. The noise performance of the ADXL372 in normal operation, typically 3.5 LSB rms at 3200 Hz ODR and 1600 Hz bandwidth, is adequate for most applications, depending on bandwidth and the desired resolution. For cases where lower noise is needed, the ADXL372 provides a lower noise operating mode that trades reduced noise for a somewhat higher current consumption. In all cases, operating at a higher bandwidth setting increases the rms noise and operating with a lower bandwidth decreases the noise. Table 8 lists the current consumption and noise densities obtained for normal operation and the lower noise mode at a typical 2.5 V supply. Operating the ADXL372 at a higher supply voltage also decreases noise. Table 9 lists the current consumption and noise densities obtained for normal operation and the lower noise mode at the highest recommended supply, 3.5 V. Table 8. Noise and Current Consumption for VS = 2.5 V Mode Normal Operation1 Low Noise1 1 Typical RMS Noise (LSB) 3.5 3 Typical Current Consumption (A) 22 33 VS = 2.5 V, ODR = 3200 Hz, and bandwidth = 1600 Hz. Table 9. Noise and Current Consumption for VS = 3.5 V Mode Normal Operation1 Low Noise1 1 15430-030 ODR (Hz) 1600 7.61 3.89 1.97 0.99 20 10 Table 7. High-Pass Filter -3 dB Corner Frequencies Setting 00 01 10 11 30 Typical RMS Noise (LSB) 3 2.5 VS = 3.5 V, ODR = 3200 Hz, and bandwidth = 1600 Hz. Rev. B | Page 14 of 56 Typical Current Consumption (A) 32 44 Data Sheet ADXL372 * POWER SAVINGS The digital interface of the ADXL372 is implemented with system level power savings in mind. The following features enhance power savings: * * Burst reads and writes reduce the number of SPI communication cycles required to configure the device and retrieve data. Concurrent operation of activity and inactivity detection enables set it and forget it operation. Loop modes further reduce communications power by enabling the clearing of interrupts without processor intervention. Rev. B | Page 15 of 56 The FIFO is implemented such that consecutive samples can be read continuously via a multibyte read of unlimited length; thus, one FIFO read instruction can clear the entire contents of the FIFO. The ADXL372 FIFO construction also allows the use of direct memory access (DMA) to read the FIFO contents. ADXL372 Data Sheet AUTONOMOUS EVENT DETECTION ACTIVITY AND INACTIVITY The ADXL372 features built in logic that detects activity (defined as acceleration above a user set threshold) and inactivity (defined as acceleration below a user set threshold). Activity and inactivity events can be used as triggers to manage the accelerometer operating mode, trigger an interrupt to a host processor, and/or autonomously drive a motion switch. Detection of an activity or inactivity event is indicated in the STATUS2 register and can be configured to generate an interrupt. In addition, the activity status of the device, that is, whether it is moving or stationary, is indicated by the AWAKE bit, described in the Using the AWAKE Bit section. Activity and inactivity detection can be used when the accelerometer is in either measurement mode or wake-up mode. However, the activity and inactivity interrupts are not available in wake-up mode because the device is inherently looking for activity in this mode, and any changes to activity or inactivity detection features must be made while the device is in standby mode. Low-Pass Activity Detect Filter The ADXL372 combines high g impact detection and low g movement detection in one device. For low g detection, an internal low-pass filter with a -3 dB corner of approximately 10 Hz averages data to reduce the rms noise, allowing accurate detection of activity or inactivity thresholds as low as 500 mg. For high g impact detection, the low-pass activity detect filter can be turned off through a register setting. When using both the lowpass activity detect filter and the high-pass filter, the user must select a high-pass filter corner that does not exceed 10 Hz; otherwise, activity detection data is severely attenuated. Activity Detection An activity event is detected when acceleration in at least one enabled axis remains above a specified threshold for a specified time. Enabled axes, thresholds, and time are user selected. Each axis has its own activity threshold, but the activity timer is shared among all three axes. When multiple axes are selected, an overthreshold event on any one enabled axis triggers the activity detection. Referenced and Absolute Configurations Activity detection can be configured as referenced or absolute mode for all axes through the ACT_REF bit in the THRESH_ ACT_X_L register. When using absolute activity detection, acceleration samples are compared directly to a user set threshold to determine whether motion is present. For example, if a threshold of 0.5 g is set and the acceleration on the z-axis is 1 g longer than the user defined activity time, the activity status asserts. In many applications, it is advantageous for activity detection to be based not on an absolute threshold, but on a deviation from a reference point or orientation. The referenced activity detection is particularly useful because it removes the effect on activity detection of the static 1 g imposed by gravity as well as any static offset errors, which can be up to several g. In absolute activity detection, when the threshold is set to less than 1 g, activity is immediately detected in this case. In the referenced configuration, activity is detected when acceleration samples are above an internally defined reference by a user defined amount for the user defined amount of time, as described by Abs(Acceleration - Reference) > Threshold where Abs is the absolute value. Consequently, activity is detected only when the acceleration has deviated sufficiently from the initial orientation. The default setting for the accelerometer is in absolute mode. After it is placed in referenced mode through the appropriate register setting, the reference for activity detection is calculated as soon as full bandwidth measurement mode is turned on. To reset the reference, it is necessary to put the device back into absolute mode and then back to referenced mode. The new reference is set as soon as the device enters full bandwidth measurement mode again. If using both activity and inactivity detection in referenced mode, both must be set back to absolute mode before the reference can be reset. Activity Timer Ideally, the intent of activity detection is to wake up a system only when motion is intentional, ignoring noise or small, unintentional movements. In addition to being sensitive to low g events, the ADXL372 activity detection algorithm is robust in filtering out undesired triggers. The ADXL372 activity detection functionality includes a timer to filter out unwanted motion and ensure that only sustained motion is recognized as activity. The timer period depends on the ODR selected. At 3200 Hz and below, it is ~6.6 ms; at 6400 Hz, it is ~3.3 ms. For activity detection to trigger, above threshold activity must be sustained for a time equal to the number of activity timer periods specified in the activity time register. For example, a setting of 10 in this register means that above threshold activity must be sustained for 66 ms at 3200 Hz ODR. A register value of zero results in single sample activity detection. The maximum allowable activity time is ~1.68 sec (or 841.5 ms at 6400 Hz ODR). Note that the activity timer is operational in measurement mode only. Rev. B | Page 16 of 56 Data Sheet ADXL372 Activity Detection in Wake-Up Mode Inactivity Timer If activity detection is enabled while the device is in wake-up mode, the device uses single sample activity detection, no matter the activity time register setting. If activity is detected, the device automatically returns to full bandwidth measurement mode. However, the activity interrupt is not generated unless the activity time setting is zero. If it is not zero, after entering measurement mode, the interrupt is not generated until the device sees sustained activity for the amount of time given in the activity time register. The awake interrupt automatically goes high upon entering measurement mode if the device is in default mode or autosleep mode. If it is in linked or loop mode (but not autosleep), it is linked to the activity interrupt, which behaves as previously mentioned. The ADXL372 inactivity detect functionality includes a timer to allow detection of sustained inactivity. The timer period depends on the ODR selected. At 3200 Hz and below, it is ~26 ms; at 6400 Hz, it is ~13 ms. For inactivity detection to trigger, below threshold inactivity must be sustained for a time equal to the number of inactivity timer periods specified in the inactivity time registers. For example, a setting of 10 in these registers means that below threshold inactivity must be sustained for 260 ms at 3200 Hz ODR. A value of zero in these registers results in single sample, inactivity detection. The maximum allowable inactivity time is ~28.4 minutes at 3200 Hz ODR (or ~14.2 minutes at 6400 Hz ODR). After the device automatically enters measurement mode due to activity detection, if autosleep is not on, it must be placed manually back into wake-up mode. When in measurement mode or wake-up mode, the activity and inactivity detection functions can be used concurrently and processed manually by a host processor, or they can be configured to interact in several other ways, such as those that follow. An inactivity event is detected when acceleration in all enabled axes remains below a specified threshold for a specified time. Enabled axes, threshold, and time are user selected. Each axis has its own inactivity threshold, but the inactivity timer is shared among all three axes. When multiple axes are selected, all enabled axes must stay under the threshold for the required amount of time to trigger inactivity detection. Referenced and Absolute Configurations Default Mode In default mode, activity and inactivity detection are both available simultaneously, and all interrupts must be serviced by a host processor; that is, a processor must read each interrupt before it is cleared and can be used again. Refer to the Interrupts section for information on clearing interrupts. The flowchart in Figure 31 illustrates default mode operation. AWAKE = 1 INACTIVITY INTERRUPT TRIGGERS ACTIVITY INTERRUPT TRIGGERS When using referenced inactivity detection, inactivity is detected when acceleration samples are within a user specified amount from an internally defined reference for a user defined amount of time. AWAKE = 1 WAIT FOR PROCESSOR TO CLEAR INTERRUPT Abs(Acceleration - Reference) < Threshold Referenced inactivity, like referenced activity, is particularly useful for eliminating the effects of the static acceleration due to gravity, as well as other static offsets. With absolute inactivity, if the inactivity threshold is set lower than 1 g, a device resting motionless may never detect inactivity. With referenced inactivity, the same device under the same configuration detects inactivity. The default setting for the accelerometer is in absolute mode. After it is placed in referenced mode through the appropriate register setting, the reference for inactivity detection is calculated as soon as full bandwidth measurement mode is turned on. To reset the reference, it is necessary to put the device back into absolute mode and then back to referenced mode. The new reference is set as soon as the device enters full bandwidth measurement mode again. If using both inactivity and activity detection in referenced mode, both must be set back to absolute mode before the reference can be reset. WAIT FOR PROCESSOR TO CLEAR INTERRUPT WAIT FOR ACTIVITY EVENT Inactivity detection is also configurable as referenced or absolute through the INACT_REF bit in the THRESH_INACT_X_L register. When using absolute inactivity detection, acceleration samples are compared directly to a user set threshold for the user set time to determine the absence of motion. Inactivity is detected when enough consecutive samples are all below the threshold. WAIT FOR INACTIVITY EVENT NOTES 1. THE AWAKE BIT DEFAULTS TO 1 WHEN ACTIVITY AND INACTIVITY ARE NOT LINKED. 15430-031 Inactivity Detection Linking Activity and Inactivity Detection Figure 31. Flowchart Illustrating Activity and Inactivity Operation in Default Mode Rev. B | Page 17 of 56 ADXL372 Data Sheet Linked Mode Autosleep In linked mode, activity and inactivity detection are linked to each other such that only one of the functions is enabled at any given time. As soon as activity is detected, the device is assumed to be moving (or awake) and stops looking for activity; rather, inactivity is expected as the next event. Therefore, only inactivity detection operates. If autosleep is selected, after the device is placed in wake-up mode (see the Wake-Up Mode section), it automatically sets to loop mode and begins looking for activity. When activity is detected, the device automatically enters measurement mode and immediately begins looking for inactivity. When inactivity is detected, the device automatically re-enters wake-up mode. Note that the device must be manually placed in wake-up mode before autosleep can begin functioning. It does not automatically enter wake-up mode if the device is started up manually in measurement mode. Similarly, when inactivity is detected, the device is assumed to be stationary (or asleep). Thus, activity is expected as the next event; therefore, only activity detection operates. In linked mode, each interrupt must be serviced by a host processor before the next interrupt is enabled. The flowchart in Figure 32 illustrates linked mode operation. ACTIVITY INTERRUPT AWAKE = 1 AWAKE = 0 WAIT FOR PROCESSOR TO CLEAR INTERRUPT INACTIVITY INTERRUPT WAIT FOR INACTIVITY EVENT 15430-032 WAIT FOR PROCESSOR TO CLEAR INTERRUP WAIT FOR ACTIVITY EVENT Figure 32. Flowchart Illustrating Activity and Inactivity Operation in Linked Mode Loop Mode Using the AWAKE Bit The AWAKE bit is a status bit that indicates whether the ADXL372 is awake or asleep. In default mode or autosleep mode, the AWAKE bit is high whenever the device is in measurement mode. In linked or loop mode, the AWAKE bit is high whenever the device experiences an activity condition, and it is low when the device experiences an inactivity condition. The awake signal can be mapped to the INT1 or the INT2 pin allowing the pin to serve as a status output to connect or disconnect power to downstream circuitry based on the awake status of the accelerometer. Used in conjunction with loop mode, this configuration implements a simple, autonomous motion activated switch. In loop mode, motion detection operates as described in the Linked Mode section, but interrupts do not need to be serviced by a host processor. This configuration simplifies the implementation of commonly used motion detection and enhances power savings by reducing the amount of power used in bus communication. If the turn-on time of downstream circuitry can be tolerated, this motion switch configuration can save significant system level power by eliminating the standby current consumption of the remainder of the application circuit. This standby current can often exceed the full operating current of the ADXL372. The flowchart in Figure 33 illustrates loop mode operation. In addition to the activity threshold previously described, the ADXL372 offers a secondary threshold. This second threshold, the motion warning threshold, can be set independently of the activity threshold. It does not have any functionality related to autosleep, linked, or loop mode, or the device awake status. The purpose of the motion warning functionality is to issue a notification to the system, via the status bit and/or interrupt, that the observed acceleration has exceeded the second threshold. It is controlled by the THRESH_ACT2_x_x registers, and by the ACTIVITY2 interrupt, which is sent only to the INT2 pin. Each axis has its own motion warning threshold. However, the motion warning activity interrupt does not have an activity timer. It is only used for single sample, activity detection. The motion warning threshold also shares the same referenced vs. absolute configuration as the primary activity detection. AWAKE = 1 AWAKE = 0 15430-033 WAIT FOR INACTIVITY EVENT WAIT FOR ACTIVITY EVENT Figure 33. Flowchart Illustrating Activity and Inactivity Operation in Loop Mode MOTION WARNING Rev. B | Page 18 of 56 Data Sheet ADXL372 IMPACT DETECTION FEATURES Impact detection applications often require high g and high bandwidth acceleration measurements, and the ADXL372 is designed with these applications in mind. Several features are included that target impact detection and aim to simplify the system design. CAPTURING IMPACT EVENTS WIDE BANDWIDTH An impact is a transient event that produces an acceleration pulse with frequency content over a wide range. A sufficiently wide bandwidth is needed to capture the impact event because lowering bandwidth has the effect of reducing the magnitude of the recorded signal, resulting in measurement inaccuracy. The ADXL372 can operate with bandwidths of up to 3200 Hz at extremely low power levels. A steep filter roll-off is also useful for effective suppression of out of band content, and the ADXL372 incorporates a four-pole, low-pass antialiasing filter for this purpose. In certain applications, a single (3-axis) acceleration sample at the peak of an impact event contains sufficient information about the event, and the full acceleration history is not required. For these applications, the ADXL372 provides the capability to store only the peak acceleration of each over threshold event. The x, y, and z acceleration samples at the peak of the event can be stored in the FIFO. Applications that do not require the full event profile can greatly increase the time between FIFO reads by storing only peak acceleration information. A peak is defined as the x, y, and z acceleration sample that has the highest magnitude (root sum squared) of all other values within a particular over threshold event. In addition to recording the peak of each over threshold impact event in the FIFO, the ADXL372 can also keep track of the absolute highest peak recorded in separate registers. The ADXL372 instant on mode is an ultralow power mode that continuously monitors the environment for impact events that exceed a built in threshold. When an impact is detected, the device switches into full measurement mode and captures the impact profile. User must enter instant on mode from full bandwidth measurement mode with 16 ms delay before the first valid data gets ready. No digital data is available in this mode of operation. The user can configure the device to detect an impact between a threshold level of either 10 g to 15 g or 30 g to 40 g by using the INSTANT_ON_ THRESH bit in the POWER_CTL register. When an impact beyond the selected threshold is detected, the ADXL372 switches to full bandwidth measurement mode and begins outputting digital data. TIME INACT Figure 35. Capturing Impact Events Enable peak detection by doing the following: ACCELERATION < THRESHOLD INSTANT ON MODE (~2A) MEASUREMENT MODE Figure 34. Instant On Mode Using Default Threshold After the accelerometer is in full bandwidth measurement mode, it must be set back into instant on mode manually. It cannot return to instant on mode automatically. 15430-034 ACCELERATION (g) DATA IS RECORDED AS SOON AS IT ENTERS MEASUREMENT MODE 20 15430-035 ACCELERATION (g) INSTANT ON IMPACT DETECTION Put the FIFO in peak detect and stream mode (b0011101x to Register 0x3A). Set the desired activity threshold and time settings (Register 0x23 to Register 0x29). Set the desired inactivity threshold and time settings (Register 0x2A to Register 0x31). Set the activity mode to linked or loop mode (Register 0x3E). As soon as the activity interrupt is triggered, the device records the x, y, and z values of the peak acceleration event that occurs between the activity interrupt trigger and the next inactivity interrupt trigger, as shown in Figure 35 in the FIFO. It continues to do this for each period of activity between the triggering of the activity interrupt and consequent triggering of the inactivity interrupt. The process does work in linked mode, but the user must be clear each interrupt before the device looks for the next activity or inactivity interrupt. For as long as peak detect mode is selected, the device also stores the highest overall peak recorded in the MAXPEAK_x_x registers. When these values are read out of the registers, the register data is cleared, and the device begins looking for the new highest peak. Rev. B | Page 19 of 56 ADXL372 Data Sheet FIFO The ADXL372 includes a deep, 512 sample FIFO buffer. FIFO Disabled BENEFITS OF THE FIFO When the FIFO is disabled, no new data is stored in it, and any data already in it is cleared. The FIFO buffer is an important feature in ultralow power applications in two ways: system level power savings and data recording/event context. The FIFO is disabled by setting the FIFO_MODE bits in the FIFO_CTL register (Register 0x3A) to 0b00. System Level Power Savings Oldest Saved Mode (First N) Appropriate use of the FIFO enables system level power savings by enabling the host processor to sleep for extended periods while the accelerometer autonomously collects data. Alternatively, using the FIFO to collect data can unburden the host while it tends to other tasks. In oldest saved mode, the FIFO accumulates data until it is full and then stops. After reading the data, the FIFO must be disabled and re-enabled to save a new set of data. One possible use case for this mode is to enable it right after entering instant on mode. After a shock is detected, the data immediately stores in the FIFO to be read whenever convenient. Data Recording/Event Context The FIFO can be used in a triggered mode to record all data leading up to an activity detection event, thereby providing context for the event. In the case of a system that identifies impact events, for example, the accelerometer can keep the entire system off while it stores acceleration data in its FIFO and looks for an activity event. When the impact event occurs, data collected prior to the event is frozen in the FIFO. The accelerometer can now wake the rest of the system and transfer this data to the host processor, thereby providing context for the impact event. Generally, the more context available, the more intelligent decisions a system can achieve, making a deep FIFO especially useful. For example, the ADXL372 FIFO can store up to 512 1-axis samples at 400 Hz ODR, providing a 1.28 sec window, or 170 3-axis samples at 3200 Hz to provide a 50 ms window, which is a typical duration for impact events. USING THE FIFO The FIFO is a 512 sample memory buffer that can save power, unburden the host processor, and autonomously record data. FIFO operation is configured via Register 0x39 and Register 0x3A. The 512 FIFO samples can be allotted in several ways, such as the following: * * * * 170 sample sets of concurrent 3-axis data 256 sample sets of concurrent 2-axis data (user selectable) 512 sample sets of single-axis data 170 sets of impact event peak (x, y, z) All FIFO modes must be configured while in standby mode. When reading data from multiple axes from the FIFO, to ensure that data is not overwritten and stored out of order, at least one sample set must be left in the FIFO after every read (therefore, a set of 3-axis data must have 169 samples at most). The FIFO is placed into oldest saved mode by setting the FIFO_MODE bits in the FIFO_CTL register (Register 0x3A) to 0b11. Stream Mode (Last N) In stream mode, the FIFO always contains the most recent data. The oldest sample is discarded when space is needed to make room for a newer sample. Stream mode is useful for unburdening a host processor. The processor can tend to other tasks while data is being collected in the FIFO. When the FIFO fills to a certain number of samples (specified by the FIFO_SAMPLES register along with Bit 0 in the FIFO_CTL register), it triggers a watermark interrupt (if this interrupt is enabled). At this point, the host processor can read the contents of the entire FIFO and then return to its other tasks as the FIFO fills again. The FIFO is placed into stream mode by setting the FIFO_MODE bits in the FIFO_CTL register (Register 0x3A) to 0b01. Triggered Mode In triggered mode, the FIFO operates as in stream mode until an activity detection event, after which it saves the samples surrounding that event. The operation is similar to a one-time run trigger on an oscilloscope. The number of samples to be saved after the activity event is specified in FIFO_SAMPLES (Register 0x39[7:0], along with Bit 0 in the FIFO_CTL register, Register 0x3A). For example if the FIFO_SAMPLE is set to 12, there are 500 samples before the trigger and 12 after the trigger. The trigger can be reset by clearing the activity interrupt and reading all 512 locations of the FIFO. If this is not complete, future FIFO data reads may contain invalid data. Place the FIFO into triggered mode by setting the FIFO_MODE bits in the FIFO_CTL register (Register 0x3A) to 0b10. The FIFO operates in one of the following four modes: FIFO disabled, oldest saved mode (first N), stream mode (last N), and triggered mode. Rev. B | Page 20 of 56 Data Sheet ADXL372 RETRIEVING DATA FROM FIFO Access FIFO data by reading the FIFO_DATA register. A multibyte read to this register does not auto-increment the address, and instead continues to pop data from the FIFO. Data is left justified and formatted as shown in Table 10. When reading data, the most significant byte (Bits[B15:B8]) is read first, followed by the least significant byte (Bits[B7:B0]). Bits[B15:B4] represent the 12-bit, twos complement acceleration data. Bit 0 serves as a series start indicator: only the first data byte of a series contains a 1 in this bit, and the remaining items contain a 0. Table 10. FIFO Buffer Data Format B15 (MSB) B14 B7 B6 B13 B5 Data B12 B11 B4 B3 B10 Data B2 Reserved Rev. B | Page 21 of 56 B9 B8 B1 B0 Series start indicator ADXL372 Data Sheet INTERRUPTS Several of the built in functions of the ADXL372 can trigger interrupts to alert the host processor of certain status conditions. The functionality of these interrupts is described in this section. INTERRUPT PINS Interrupts can be mapped to either (or both) of two designated output pins, INT1 and INT2, by setting the appropriate bits in the INT1_MAP register and INT2_MAP register, respectively. All functions can be used simultaneously. If multiple interrupts are mapped to one pin, the OR combination of the interrupts determines the status of the pin. If no functions are mapped to an interrupt pin, that pin is automatically configured to a high impedance (high-Z) state. The pins are also placed in the high-Z state upon a reset. When a certain status condition is detected, the pin that condition is mapped to is activated. The configuration of the pin is active high by default so when it is activated, the pin goes high. However, this configuration can be switched to active low by setting the INTx_LOW bit in the appropriate INTx_MAP register. The INTx pins can connect to the interrupt input of a host processor where interrupts are responded to with an interrupt routine. Because multiple functions can be mapped to the same pin, the STATUS register can determine which condition caused the interrupt to trigger. Interrupts are cleared in several of the following ways: * * * * Reading the STATUS2 register clears ACTIVITY and INACT interrupts. However, if activity detection is operating in default mode, and the activity or inactivity timers are set to 0, the only way to clear the activity or inactivity bits, respectively, is to set the device into standby mode and restart full bandwidth measurement mode. Setting the device into standby mode and back into full bandwidth measurement mode clears the ACTIVITY2 interrupt. Reading from the data registers clears the DATA_RDY interrupt. Reading enough data from the FIFO buffer so that interrupt conditions are no longer met, and then reading the STATUS register (Register 0x04) clears the FIFO_RDY, FIFO_FULL, and FIFO_OVR interrupts. Both interrupt pins are push-pull low impedance pins with an output impedance of about 500 (typical) and digital output specifications as shown in Table 11. Both have bus keepers that hold them to a valid logic state when they are in a high impedance mode. To prevent interrupts from being falsely triggered during configuration, disable interrupts while their settings, such as thresholds, timings, or other values, are configured. Alternate Functions The INT1 and INT2 pins can be configured for use as input pins instead of for signaling interrupts. INT1 is used as an external clock input when the EXT_CLK bit in the TIMING register is set. INT2 is used as the trigger input for synchronized sampling when the EXT_SYNC bit in the TIMING register is set. One or both of these alternate functions can be used concurrently; however, if an interrupt pin is used for its alternate function, it cannot simultaneously be used to signal interrupts. TYPES OF INTERRUPTS Activity and Inactivity Interrupts The ACTIVITY bit and INACT bit are set when activity and inactivity are detected, respectively. Detection procedures and criteria are described in the Autonomous Event Detection section. Data Ready Interrupt The DATA_RDY bit is set when new valid data is available, and it is cleared when no new data is available. The DATA_RDY bit does not set while any of the data registers are being read. If DATA_RDY = 0 prior to a register read and new data becomes available during the register read, DATA_RDY remains 0 until the read is complete and only then sets to 1. If DATA_RDY = 1 prior to a register read, it is cleared at the start of the register read. If DATA_RDY = 1 prior to a register read and new data becomes available during the register read, DATA_RDY is cleared to 0 at the start of the register read and remains 0 throughout the read. When the read is complete, DATA_RDY is set to 1. FIFO Interrupts FIFO Watermark The FIFO_FULL bit is set when the number of samples stored in the FIFO is equal to or exceeds the number specified in FIFO_SAMPLES (Register 0x39 together with Bit 0 in the FIFO_CTL register). The FIFO_FULL bit is cleared automatically when enough samples are read from the FIFO, such that the number of samples remaining is lower than that specified. If the number of FIFO samples is set to 0, the watermark interrupt is set. To avoid unexpectedly triggering this interrupt, the default value of the FIFO_SAMPLES register is 0x80. FIFO Ready The FIFO_RDY bit is set when there is at least one valid sample available in the FIFO output buffer. This bit is cleared when no valid data is available in the FIFO. In FIFO triggered mode, it is only set after the activity interrupt is detected, and the data surrounding the event is saved in the FIFO. Rev. B | Page 22 of 56 Data Sheet ADXL372 Overrun The FIFO_OVR bit is set when the FIFO has overrun or overflowed, such that new data replaces unread data, which may indicate a full FIFO that has not yet been emptied or a clocking error caused by a slow SPI transaction. If the FIFO is configured to oldest saved mode, an overrun event indicates that there is insufficient space available for a new sample. The FIFO_OVR bit is cleared when both the contents of the FIFO and the STATUS register are read. It is also cleared when the FIFO is disabled. Table 11. Interrupt Pin Digital Output Parameter Digital Output Low Level Output Voltage (VOL) High Level Output Voltage (VOH) Low Level Output Current (IOL) High Level Output Current (IOH) Pin Capacitance Rise/Fall Time Rise Time (tR)2 Fall Time (tF)3 Test Conditions IOL = 500 A IOH = -300 A VOL = VOL, MAX VOH = VOH, MIN fIN = 1 MHz, VIN = 2.0 V Min Limit1 Max 0.2 x VDDI/O -300 8 V V A A pF 210 150 ns ns 0.8 x VDDI/O 500 CLOAD = 150 pF CLOAD = 150 pF Limits based on characterization results, not production tested. Rise time is measured as the transition time from VOL, MAX to VOH, MIN of the interrupt pin. 3 Fall time is measured as the transition time from VOH, MIN to VOL, MAX of the interrupt pin. 1 2 Rev. B | Page 23 of 56 Unit ADXL372 Data Sheet ADDITIONAL FEATURES USING AN EXTERNAL CLOCK When operating at 3200 Hz ODR or lower, the ADXL372 has a built in 307.2 kHz (typical) clock that, by default, serves as the time base for internal operations. At 6400 Hz ODR, this clock speed increases to 614.4 kHz (typical). If desired, an external clock can be provided instead, for either improved clock frequency accuracy or for control of the output data rate. To use an external clock, set the EXT_CLK bit (Bit 1) in the TIMING register (Register 0x3D) and apply a clock to the INT1 pin. These values are doubled when an ODR rate of 6400 Hz is selected. Additionally, the trigger signal applied to the INT2 pin must meet the following criteria: * * * The trigger signal must be active high. The pulse width of the trigger signal must be at least 53 s. The minimum sampling frequency is set only by system requirements. Samples need not be polled at any minimum rate; however, if samples are polled at a rate lower than the bandwidth set by the antialiasing filter, aliasing may occur. The external clock can operate at the nominal 307.2 kHz or slower (when using ODR 3200 Hz), or 614.4 kHz or slower (when using ODR = 6400 Hz) to allow the user to achieve any desired output data rate. Lower external clock rates must be used with caution because it may result in aliasing of high frequency signals that may be present in certain applications. The EXT_SYNC is an active high signal. Due to the asynchronous nature of the internal clock and external sync, there may be a one ODR clock cycle difference between consecutive external sync pulses. The external sync sets the ODR of the system. For example, if sending an external sync at a 2 kHz rate, all 3 axes (if enabled) are sampled in that 2 kHz window. ODR and bandwidth scale proportionally with the clock. The ADXL372 provides a discrete number of options for ODR. ODRs other than those provided are achieved by selecting an appropriate clock frequency. For example, to achieve a 2560 Hz ODR, use the 3200 Hz setting with a clock frequency that is 80% of nominal, or 245.76 kHz. Bandwidth also scales by the same ratio, so if a 400 Hz bandwidth is selected, the resulting bandwidth is 320 Hz. SELF TEST SYNCHRONIZED DATA SAMPLING For applications that require a precisely timed acceleration measurement, the ADXL372 features an option to synchronize acceleration sampling to an external trigger. The EXT_SYNC bit in the TIMING register enables this feature. When the EXT_SYNC bit is set to 1, the INT2 pin automatically reconfigures for use as the sync trigger input. When external triggering is enabled, it is up to the system designer to ensure that the sampling frequency meets system requirements. Sampling too infrequently causes aliasing. Noise can be lowered by oversampling; however, sampling at too high a frequency may not allow enough time for the accelerometer to process the acceleration data and convert it to valid digital output data. The ADXL372 incorporates a pass or fail self test feature that effectively tests its mechanical and electronic systems simultaneously. When the self test function is invoked, an electrostatic force is applied to the mechanical sensor. This electrostatic force moves the mechanical sensing element in the same manner as acceleration, and the acceleration experienced by the device increases because of this force. Self Test Procedure The self test function is enabled via the ST bit in the SELF_TEST register, Register 0x40. The recommended procedure for using the self test functionality is as follows: 1. 2. 3. Read the self test status bits, ST_DONE and USER_ST, after approximately 300 ms to check the pass or fail condition. When the Nyquist criterion is met, signal integrity is maintained. An internal antialiasing filter is available in the ADXL372 and can assist the system designer in maintaining signal integrity. To prevent aliasing, set the filter bandwidth to a frequency no greater than half the sampling rate. For example, when sampling at 1600 Hz, set the filter bandwidth to no higher than 800 Hz. Because of internal timing requirements, the maximum allowable external trigger frequencies are as follows: * * * Place the device into measurement mode. Make sure the low-pass activity filter is enabled. Assert self test by setting the ST bit in the SELF_TEST register (Register 0x40). 1-axis data = 3100 Hz 2-axis data = 2700 Hz 3-axis data = 2200 Hz Rev. B | Page 24 of 56 Data Sheet ADXL372 USER REGISTER PROTECTION USER OFFSET TRIMS The ADXL372 includes user register protection for single event upsets (SEUs). An SEU is a change of state caused by ions or electromagnetic radiation striking a sensitive node in a microelectronic device. The state change is a result of the free charge created by ionization in or close to an important node of a logic element (for example, a memory bit). The SEU itself is not considered permanently damaging to transistor or circuit functionality, but can create erroneous register values. The registers protected from SEU are Register 0x20 to Register 0x3F. The ADXL372 has a 4-bit offset trim for each axis that allows users to add positive or negative offset to the default static acceleration values and correct any deviations from ideal that may result as a consequence of varying the operating parameters of the device. The offset trims have a full-scale range of about 60 LSB with a trim profile as shown in Figure 36. 40 20 0 -20 -40 -60 -80 0 2 4 6 8 10 12 REGISTER VALUE Figure 36. User Offset Trim Profile Rev. B | Page 25 of 56 14 16 15430-036 The ERR_USER_REGS bit in the STATUS register starts high when set on an unconfigured device and clears upon the first register write. X-AXIS Y-AXIS Z-AXIS 60 OFFSET CHANGE (LSB) Protection is implemented via a 99-bit error correcting (Hamming type) code and detects both single bit and double bit errors. The check bits are recomputed any time a write to any of the protected registers occurs. At any time, if the stored version of the check bits is not in agreement with the current check bit calculation, the ERR_USER_REGS status bit is set. 80 ADXL372 Data Sheet SERIAL COMMUNICATIONS SERIAL INTERFACE The ADXL372 is designed to communicate in either the SPI or the I2C protocol. It autodetects the format being used, requiring no configuration control to select the format. SPI Protocol The timing scheme is as follows: CPHA = CPOL = 0. The ADXL372 supports a SCLK frequency up to 10 MHz. Wire the ADXL372 for SPI communication as shown in Figure 37. For successful communication, follow the logic thresholds and timing parameters in Table 12. The command structure for the read register and write register are shown in Figure 40 and Figure 41, respectively. The read and write register commands support multibyte (burst) read/write access. The waveform diagrams for multibyte read and write commands are shown in Figure 42 and Figure 43, respectively. There are no internal pull-up or pull-down resistors for any unused pins; therefore, there is no known state or default state for the pins if left floating or unconnected. It is a requirement that SCLK be connected to ground when communicating to the ADXL372 using the I2C. Due to communication speed limitations, the maximum output data rate when using 400 kHz I2C is 800 Hz and scales linearly with a change in the I2C communication speed. For example, using I2C at 100 kHz limits the maximum ODR to 200 Hz. Operation at an output data rate above the recommended maximum can result in undesirable effect on the acceleration data, including missing samples or additional noise. VDD I/O ADXL372 Ignore data transmitted from the ADXL372 to the master device during writes to the ADXL372. RP RP PROCESSOR MISO SDA D IN/OUT DOUT MOSI DOUT MISO DIN SCLK DOUT SCL D OUT Figure 38. I2C Connection Diagram (ADXL372 Device ID = 0x53) If other devices are connected to the same I2C bus, the nominal operating voltage level of these other devices cannot exceed VDDI/O by more than 0.3 V. External pull-up resistors, RP, are necessary for proper I2C operation. Single byte or multibyte reads/writes are supported, as shown from Figure 45 to Figure 47. 15430-037 CS 15430-038 SCLK PROCESSOR Figure 37. 4-Wire SPI Connection Diagram I C Protocol 2 The ADXL372 supports point to point I2C communication. However, for devices with REVID = 0x02, when sharing an SDA bus, the ADXL372 may prevent communication with other devices on that bus. If at any point, even when the ADXL372 is not being addressed, the 0x3A or 0x3B bytes (when the ADXL372 Device ID is set to 0x1D), or the 0xA6 or 0xA7 bytes (when the ADXL372 Device ID is set to 0x53) are transmitted on the SDA bus, the ADXL372 responds with an acknowledge bit and pulls the SDA line down. For example, this can happen when reading or writing the data bytes to another sensor on the bus. When the ADXL372 pulls the SDA line down, communication with other devices on the bus may be interrupted. To work around this issue, the ADXL372 must be connected to a separate SDA bus, or the SCLK pin must be switched high when communication with the ADXL372 is not desired (it must be normally grounded). The ADXL372 supports standard (100 kHz), fast (up to 1 MHz), and high speed (up to 3.4 MHz) data transfer modes if the bus parameters given in Table 13 are met. There is no minimum SCL frequency, with the exception that when reading data, the clock must be fast enough to read an entire sample set before new data overwrites it. Single byte or multibyte reads/writes are supported. With the MISO pin low, the I2C address for the device is 0x1D, and an alternate I2C address of 0x53 can be chosen by pulling the MISO pin high. MULTIBYTE TRANSFERS Both the SPI and I2C protocols support multibyte transfers, also known as burst transfers. A register read or write begins with the address specified in the command and auto-increments for each additional byte in the transfer. Always read acceleration data using multibyte transfers to ensure a concurrent and complete set of x-, y-, and z-acceleration data is read. The FIFO runs on the serial port clock during FIFO reads and can sustain bursting at the SPI clock rate as long as the SPI clock is 1 MHz or faster. The address auto-increment function is disabled when the FIFO address is used, which is so that data can be read continuously from the FIFO as a multibyte transaction. In cases where the starting address of a multibyte transaction is less than the FIFO address, the address auto-increments until the FIFO address is reached, and then it stops at the FIFO address. When writing data to the ADXL372 in I2C mode, the no acknowledge (NACK) is never generated. Instead, the acknowledge (ACK) bit is sent after every received byte because it is not known how many bytes are included in the transfer. The master decides how many bytes are sent and ends the transaction with the stop condition. Rev. B | Page 26 of 56 Data Sheet ADXL372 Register 0x00 to Register 0x42 are for customer access, as described in Table 14. Register 0x43 to Register 0x67 are reserved for factory use. INVALID ADDRESSES AND ADDRESS FOLDING The ADXL372 has a 6-bit address bus, mapping only 104 registers in the possible 256 register address space. The addresses do not fold to repeat the registers at addresses above 0x104. Attempted access to register addresses above 0x104 are mapped to the invalid register at 0x67 and have no functional effect. TA = 25C, VS = 2.5 V, VDDI/O = 2.5 V, unless otherwise noted. Table 12. SPI Logic Levels and Timing Parameter INPUT DC LEVELS VIL VIH IIL IIH OUTPUT DC LEVELS VOL VOH IOL IOH INPUT AC SCLK Frequency tHIGH tLOW tCSS tCSH tCSD tSCLKS tSU tHD OUTPUT AC tP tEN tDIS Description Min Typ Low level input voltage High level input voltage Low level input current, VIN = 0 V High level input current, VIN = VDDI/O 0.7 x VDDI/O -0.1 Low level output voltage, IOL = IOL, MIN High level output voltage, IOL = IOH, MAX Low level output current, VOL = VOL, MAX High level output current, VOL = VOH, MIN 0.8 x VDDI/O -10 Max Unit 0.3 x VDDI/O V V A A 0.1 0.2 x VDDI/O V V mA mA 4 0.1 40 40 20 20 40 20 20 20 SCLK high time SCLK low time CS setup time CS hold time CS disable time Rising SCLK setup time MOSI setup time MOSI hold time Propagation delay, CLOAD = 30 pF Enable MISO time Disable MISO time 10 MHz ns ns ns ns ns ns ns ns 30 ns ns ns 30 20 SPI Timing Diagrams tCSD CS tCSS tHIGH tLOW tSCLKS tCSH SCLK tSU tHD MOSI tP tDIS 15430-046 tEN MISO Figure 39. SPI Timing Diagram Rev. B | Page 27 of 56 ADXL372 Data Sheet CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK MOSI D7 D6 D5 D4 D3 D2 D1 D0 MISO 15430-039 A6 A5 A4 A3 A2 A1 A0 RW Figure 40. SPI Timing Diagram, Single Byte Read CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0 MOSI MISO 15430-040 SCLK Figure 41. SPI Timing Diagram, Single Byte Write CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SCLK A6 A5 A4 A3 A2 A1 A0 RW BYTE n BYTE 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 MISO D0 D7 D6 D5 D4 D3 D2 D1 D0 15430-041 MOSI Figure 42. SPI Timing Diagram, Mulitbyte Read CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SCLK A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 MISO Figure 43. SPI Timing Diagram, Multibyte Write Rev. B | Page 28 of 56 15430-042 BYTE n BYTE 1 MOSI Data Sheet ADXL372 TA = 25C, VS = 2.5 V, VDDI/O = 1.8 V, unless otherwise noted. Table 13. I2C Logic Level and Timing Parameter INPUT AC SCLK Frequency tHIGH tLOW tSUSTA tHDSTA tSUDAT tHDDAT tSUSTO tBUF tRCL tFCL tRDA tFDA OUTPUT AC CLOAD Description I2C_HSM_EN = 0 Typ Min 0 260 500 260 260 50 0 260 500 SCLK high time SCLK low time Start setup time Start hold time Data setup time Data hold time Stop setup time Bus free time SCL input rise time SCL input fall time SDA input rise time SDA input fall time Max 1 0 120 320 160 160 10 0 160 120 120 120 120 20 x (VDD/5.5) 20 x (VDD/5.5) I2C_HSM_EN = 1 Min Typ Max Unit 3.4 80 80 160 160 MHz ns ns ns ns ns ns ns ns ns ns ns ns 400 pF 150 20 20 20 20 550 I2C Timing Diagrams tFDA tRDA tBUF SDA tSUDAT tHDDAT tLOW tHIGH tRCL tSUSTA tSUSTO tFCL 15430-047 tSUSTA tHDSTA SCL Figure 44. I2C Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 SCL DEVICE ADDRESS REGISTER ADDRESS A6 A5 A4 A3 A2 A1 A0 RW AK 0 RPT. START A6 A5 A4 A3 A2 A1 A0 AK DEVICE ADDRESS DATA BYTE STOP A6 A5 A4 A3 A2 A1 A0 RW AK D7 D6 D5 D4 D3 D2 D1 D0 AK INDICATES SDA IS CONTROLLED BY ADXL372 15430-043 START SDA Figure 45. I2C Timing Diagram, Single Byte Read 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SCL DEVICE ADDRESS REGISTER ADDRESS A6 A5 A4 A3 A2 A1 A0 RW AK 0 DATA BYTE A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK INDICATES SDA IS CONTROLLED BY ADXL372 STOP 15430-044 START SDA Figure 46. I2C Timing Diagram, Single Byte Write 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 19 SCL DEVICE ADDRESS A6 A5 A4 A3 A2 A1 A0 RW AK REGISTER ADDRESS 0 DATA BYTE 1 A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK D7 INDICATES SDA IS CONTROLLED BY ADXL372 Figure 47. I2C Timing Diagram, Multibyte Write Rev. B | Page 29 of 56 DATA BYTE n D0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK 15430-045 START SDA ADXL372 Data Sheet REGISTER MAP Table 14. Register Map Reg Name Bits Bit 7 0x00 DEVID_AD [7:0] Bit 6 Bit 5 DEVID_AD 0xAD R 0x01 DEVID_MST [7:0] DEVID_MST 0x1D R 0x02 PARTID [7:0] DEVID_PRODUCT 0xFA R 0x03 REVID [7:0] REVID 0x031 R 0x04 STATUS [7:0] ERR_USER_ AWAKE REGS USER_NVM_BUSY RESERVED 0x05 STATUS2 [7:0] RESERVED ACTIVITY2 ACTIVITY INACT 0x06 FIFO_ENTRIES2 [7:0] 0x07 FIFO_ENTRIES [7:0] FIFO_ENTRIES[7:0] 0x00 R 0x08 XDATA_H [7:0] XDATA[11:4] 0x00 R 0x09 XDATA_L [7:0] 0x0A YDATA_H [7:0] 0x0B YDATA_L [7:0] 0x0C ZDATA_H [7:0] 0x0D ZDATA_L [7:0] 0x15 MAXPEAK_X_H [7:0] 0x16 MAXPEAK_X_L [7:0] 0x17 MAXPEAK_Y_H [7:0] 0x18 MAXPEAK_Y_L [7:0] 0x19 MAXPEAK_Z_H [7:0] 0x1A MAXPEAK_Z_L [7:0] MAXPEAK_Z[3:0] RESERVED 0x20 OFFSET_X [7:0] RESERVED OFFSET_X 0x00 R/W 0x21 OFFSET_Y [7:0] RESERVED OFFSET_Y 0x00 R/W 0x22 OFFSET_Z [7:0] RESERVED OFFSET_Z 0x00 R/W 0x23 THRESH_ACT_X_H [7:0] 0x24 THRESH_ACT_X_L [7:0] 0x25 THRESH_ACT_Y_H [7:0] 0x26 THRESH_ACT_Y_L [7:0] 0x27 THRESH_ACT_Z_H [7:0] 0x28 THRESH_ACT_Z_L [7:0] 0x29 TIME_ACT [7:0] FIFO_OVR Bit 1 FIFO_FULL FIFO_RDY Bit 0 DATA_RDY RESERVED RESERVED 0xA0 R 0x00 R 0x00 R 0x00 R YDATA[3:0] RESERVED 0x00 R ZDATA[11:4] 0x00 R ZDATA[3:0] RESERVED 0x00 R MAXPEAK_X[11:4] 0x00 R MAXPEAK_X[3:0] RESERVED 0x00 R MAXPEAK_Y[11:4] 0x00 R MAXPEAK_Y[3:0] RESERVED 0x00 R MAXPEAK_Z[11:4] 0x00 R 0x00 R THRESH_ACT_X[10:3] THRESH_ACT_X[2:0] Reset RW 0x00 R FIFO_ENTRIES[9:8] YDATA[11:4] 0x00 R/W RESERVED ACT_REF ACT_X_EN THRESH_ACT_Y[10:3] THRESH_ACT_Y[2:0] RESERVED THRESH_ACT_Z[2:0] 0x00 R/W 0x00 R/W ACT_Y_EN THRESH_ACT_Z[10:3] 0x00 R/W 0x00 R/W RESERVED ACT_Z_EN 0x00 R/W ACT_COUNT 0x00 R/W THRESH_INACT_X[10:3] 0x00 R/W THRESH_INACT_X[2:0] RESERVED THRESH_INACT_Y[10:3] THRESH_INACT_Y[2:0] 0x2E THRESH_INACT_Z_H [7:0] 0x2F THRESH_INACT_Z_L [7:0] Bit 2 XDATA[3:0] 0x2C THRESH_INACT_Y_H [7:0] 0x2D THRESH_INACT_Y_L [7:0] Bit 3 RESERVED 0x2A THRESH_INACT_X_H [7:0] 0x2B THRESH_INACT_X_L [7:0] Bit 4 0x00 R/W RESERVED INACT_Y_EN 0x00 R/W RESERVED INACT_Z_EN 0x00 R/W THRESH_INACT_Z[10:3] THRESH_INACT_Z[2:0] INACT_REF INACT_X_EN 0x00 R/W 0x00 R/W 0x30 TIME_INACT_H [7:0] INACT_COUNT[15:8] 0x00 R/W 0x31 TIME_INACT_L [7:0] INACT_COUNT[7:0] 0x00 R/W 0x32 THRESH_ACT2_X_H [7:0] THRESH_ACT2_X[10:3] 0x00 R/W 0x33 THRESH_ACT2_X_L [7:0] 0x34 THRESH_ACT2_Y_H [7:0] 0x35 THRESH_ACT2_Y_L [7:0] 0x36 THRESH_ACT2_Z_H [7:0] 0x37 THRESH_ACT2_Z_L [7:0] THRESH_ACT2_X[2:0] RESERVED THRESH_ACT2_Y[10:3] THRESH_ACT2_Y[2:0] 0x00 R/W RESERVED ACT2_Y_EN 0x00 R/W RESERVED ACT2_Z_EN 0x00 R/W THRESH_ACT2_Z[10:3] THRESH_ACT2_Z[2:0] Rev. B | Page 30 of 56 ACT2_REF ACT2_X_EN 0x00 R/W 0x00 R/W Data Sheet ADXL372 Reg Name Bits Bit 7 0x38 HPF [7:0] 0x39 FIFO_SAMPLES [7:0] 0x3A FIFO_CTL [7:0] 0x3B INT1_MAP [7:0] INT1_LOW AWAKE_ INT1 ACT_INT1 INACT_INT1 FIFO_OVR_ INT1 FIFO_FULL_ INT1 FIFO_RDY_ DATA_RDY_ 0x00 R/W INT1 INT1 0x3C INT2_MAP [7:0] INT2_LOW AWAKE_ INT2 ACT2_INT2 INACT_INT2 FIFO_OVR_ INT2 FIFO_FULL_ INT2 FIFO_RDY_ DATA_RDY_ 0x00 R/W INT2 INT2 0x3D TIMING [7:0] 0x3E MEASURE [7:0] USER_OR_ AUTOSLEEP DISABLE 0x3F POWER_CTL [7:0] I2C_HSM_ RESERVED EN 0x40 SELF_TEST [7:0] 0x41 RESET [7:0] RESET 0x00 W 0x42 FIFO_DATA [7:0] FIFO_DATA 0x00 R 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RESERVED Bit 0 HPF_CORNER FIFO_SAMPLES[7:0] RESERVED FIFO_FORMAT ODR FIFO_MODE USER_ST Rev. B | Page 31 of 56 EXT_SYNC BANDWIDTH INSTANT_ON_THRESH FILTER_SETTLE LPF_DISABLE HPF_DISABLE The reset value of the REVID register is either 0x03 or 0x02 for the ADXL372. 0x00 R/W FIFO_ SAMPLES[8] EXT_CLK LOW_NOISE RESERVED 0x00 R/W 0x80 R/W WAKEUP_RATE LINKLOOP Reset RW 0x00 R/W MODE ST_DONE 0x00 R/W ST 0x00 R/W 0x00 R/W ADXL372 Data Sheet REGISTER DETAILS ANALOG DEVICES ID REGISTER Address: 0x00, Reset: 0xAD, Name: DEVID_AD This register contains the Analog Devices, Inc., ID, 0xAD. 7 6 5 4 3 2 1 0 1 0 1 0 1 1 0 1 [ 7 :0 ] D EV ID _AD ( R) Analog Devices ID, 0xAD. Table 15. Bit Descriptions for DEVID_AD Bits Bit Name [7:0] DEVID_AD Settings Description Reset Access Analog Devices ID, 0xAD. 0xAD R ANALOG DEVICES MEMS ID REGISTER Address: 0x01, Reset: 0x1D, Name: DEVID_MST This register contains the Analog Devices MEMS ID, 0x1D. 7 6 5 4 3 2 1 0 0 0 0 1 1 1 0 1 [ 7 :0 ] D EV ID _M ST ( R) Analog Dev ices MEMS ID, 0x 1D. Table 16. Bit Descriptions for DEVID_MST Bits Bit Name [7:0] DEVID_MST Settings Description Reset Access Analog Devices MEMS ID, 0x1D. 0x1D R Description Reset Access Device ID, 0xFA (372 Octal). 0xFA R DEVICE ID REGISTER Address: 0x02, Reset: 0xFA, Name: PARTID This register contains the device ID, 0xFA (372 octal). 7 6 5 4 3 2 1 0 1 1 1 1 1 0 1 0 [ 7 :0 ] D EV ID _PROD U CT ( R) Dev ice ID, 0x FA (372 Oct al). Table 17. Bit Descriptions for PARTID Bits Bit Name [7:0] DEVID_PRODUCT Settings PRODUCT REVISION ID REGISTER Address: 0x03, Reset: 0x02, Name: REVID This register contains the mask revision ID, beginning with 0x00 and incrementing for each subsequent revision. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 [ 7 :0 ] REV ID ( R) Mask rev ision. Table 18. Bit Descriptions for REVID Bits Bit Name [7:0] REVID Settings Description Reset Access Mask revision. 0x2 R Rev. B | Page 32 of 56 Data Sheet ADXL372 STATUS REGISTER Address: 0x04, Reset: 0xA0, Name: STATUS This register includes the following bits that describe various conditions of the ADXL372. 7 6 1 0 5 4 3 2 1 0 1 0 0 0 0 0 [ 7 ] ERR_USER_REGS ( R) SEU Eve nt. [ 0 ] D AT A_RD Y ( R) Data re ad y status includ e s d ata w ritte n to Use r d ata re g iste rs o r FIFO. Status is hig h afte r the full d ata se t has co m p le te d . [ 6 ] AW AKE ( R) Aw ake Status. [ 1 ] FIFO _RD Y ( R) FIFO Re ad y. [ 5 ] USER_N VM _BUSY ( R) 1 = no nvo latile m e m o ry (NVM) is b usy p ro g ram m ing fuse s. [ 2 ] FIFO _FULL ( R) FIFO Wate rm ark. [ 4 ] RESERVED [ 3 ] FIFO _O VR ( R) FIFO Ove rrun. Table 19. Bit Descriptions for STATUS Bits Bit Name 7 Settings Description Reset Access ERR_USER_REGS SEU Event. An SEU event has been detected in a user register. 0x1 R 6 AWAKE Awake Status. Activity has been detected and the device is moving. 0x0 R 5 USER_NVM_BUSY 1 = nonvolatile memory (NVM) is busy programming fuses. 0x1 R 4 RESERVED Reserved. 0x0 R 3 FIFO_OVR FIFO Overrun. FIFO has overflowed, and data has been lost. 0x0 R 2 FIFO_FULL FIFO Watermark. The FIFO watermark level, specified in FIFO_SAMPLES, has been reached. 0x0 R 1 FIFO_RDY FIFO Ready. At least one valid sample is available in the FIFO. 0x0 R 0 DATA_RDY Data ready status includes data written to user data registers or FIFO. Status is high after the full data set has completed. A complete x, y, and z measurement has been made and results can be read. 0x0 R ACTIVITY STATUS REGISTER Address: 0x05, Reset: 0x00, Name: STATUS2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] RES ERV ED [ 3 :0 ] RES ERV ED [ 6 ] ACT IV IT Y2 ( R) Status o f ACTIVITY2 . [ 4 ] IN ACT ( R) Inactivity. [ 5 ] ACT IV IT Y ( R) Activity. Table 20. Bit Descriptions for STATUS2 Bits Bit Name 7 Settings Description Reset Access RESERVED Reserved. 0x0 R 6 ACTIVITY2 Status of ACTIVITY2. 0x0 R 5 ACTIVITY Activity. Activity has been detected. 0x0 R 4 INACT Inactivity. Inactivity has been detected. 0x0 R [3:0] RESERVED Reserved. 0x0 R Rev. B | Page 33 of 56 ADXL372 Data Sheet FIFO ENTRIES REGISTER, MSB Address: 0x06, Reset: 0x00, Name: FIFO_ENTRIES2 The FIFO_ENTRIES2 and FIFO_ENTRIES registers indicate the number of valid data samples present in the FIFO buffer. The number ranges from 0 to 512 or 0x00 to 0x200. FIFO_ENTRIES contains the least significant byte, and FIFO_ENTRIES2 contains the two most significant bits. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :2 ] RESERV ED [ 1 :0 ] FIFO_EN TRIES[ 9 :8 ] ( R) Num ber of dat a sam ples st ored in t he FIFO. Table 21. Bit Descriptions for FIFO_ENTRIES2 Bits Bit Name [7:2] [1:0] Settings Description Reset Access RESERVED Reserved. 0x0 R FIFO_ENTRIES[9:8] Number of data samples stored in the FIFO. 0x0 R Description Reset Access Number of data samples stored in the FIFO. 0x0 R FIFO ENTRIES REGISTER, LSB Address: 0x07, Reset: 0x00, Name: FIFO_ENTRIES 7 5 6 3 4 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] FIFO_EN TRIES[ 7 :0 ] ( R) Num ber of dat a sam ples st ored in t he FIFO. Table 22. Bit Descriptions for FIFO_ENTRIES Bits Bit Name [7:0] FIFO_ENTRIES[7:0] Settings X-AXIS DATA REGISTER, MSB Address: 0x08, Reset: 0x00, Name: XDATA_H These two registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement. XDATA_H contains the eight most significant bits (MSBs), and XDATA_L contains the four least significant bits (LSBs) of the 12-bit value. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] X D ATA[ 1 1 :4 ] ( R) X-ax is dat a. Table 23. Bit Descriptions for XDATA_H Bits Bit Name [7:0] XDATA[11:4] Settings Description Reset Access X-axis data. 0x0 R Description Reset Access X-axis data. 0x0 R Reserved. 0x0 R X-AXIS DATA REGISTER, LSB Address: 0x09, Reset: 0x00, Name: XDATA_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] X D ATA[ 3 :0 ] ( R) X-ax is dat a. [ 3 :0 ] RESERV ED Table 24. Bit descriptions for XDATA_L Bits Bit Name [7:4] XDATA[3:0] [3:0] RESERVED Settings Rev. B | Page 34 of 56 Data Sheet ADXL372 Y-AXIS DATA REGISTER, MSB Address: 0x0A, Reset: 0x00, Name: YDATA_H The YDATA_H and YDATA_L registers contain the y-axis, LSB acceleration data. Data is left justified and formatted as twos complement. YDATA_H contains the eight most significant bits (MSBs), and YDATA_L contains the four least significant bits (LSBs) of the 12-bit value. YDATA_L latches on a read of YDATA_H to ensure data integrity. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] YD ATA[ 1 1 :4 ] ( R) Y-ax is dat a. Table 25. Bit Descriptions for YDATA_H Bits Bit Name [7:0] YDATA[11:4] Settings Description Reset Access Y-axis data. 0x0 R Description Reset Access Y-AXIS DATA REGISTER, LSB Address: 0x0B, Reset: 0x00, Name: YDATA_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] YD ATA[ 3 :0 ] ( R) Y-ax is dat a. [ 3 :0 ] RESERV ED Table 26. Bit Descriptions for YDATA_L Bits Bit Name Settings [7:4] YDATA[3:0] Y-axis data. 0x0 R [3:0] RESERVED Reserved. 0x0 R Z-AXIS DATA REGISTER, MSB Address: 0x0C, Reset: 0x00, Name: ZDATA_H These two registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement. ZDATA_H contains the eight most significant bits (MSBs), and ZDATA_L contains the four least significant bits (LSBs) of the 12-bit value. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] Z D ATA[ 1 1 :4 ] ( R) Z-ax is dat a. Table 27. Bit Descriptions for ZDATA_H Bits Bit Name [7:0] ZDATA[11:4] Settings Description Reset Access Z-axis data. 0x0 R Z-AXIS DATA REGISTER, LSB Address: 0x0D, Reset: 0x00, Name: ZDATA_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] Z D ATA[ 3 :0 ] ( R) Z-ax is dat a. [ 3 :0 ] RESERV ED Table 28. Bit Descriptions for ZDATA_L Bits Bit Name [7:4] [3:0] Settings Description Reset Access ZDATA[3:0] Z-axis data. 0x0 R RESERVED Reserved. 0x0 R Rev. B | Page 35 of 56 ADXL372 Data Sheet HIGHEST PEAK DATA REGISTERS The highest peak data registers contain the acceleration data corresponding to the highest magnitude sample recorded since the last read of this register. Data is left justified and formatted as twos complement. X-AXIS HIGHEST PEAK DATA REGISTER, MSB Address: 0x15, Reset: 0x00, Name: MAXPEAK_X_H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] M AX PEAK_X [ 1 1 :4 ] ( R) St ores t he highest m agnit ude observed since t he last read of t his regist er. Table 29. Bit Descriptions for MAXPEAK_X_H Bits Bit Name [7:0] MAXPEAK_X[11:4] Settings Description Reset Access Stores the highest magnitude observed since the last read of this register. The 8 MSBs of the x-axis value. 0x0 R Description Reset Access X-AXIS HIGHEST PEAK DATA REGISTER, LSB Address: 0x16, Reset: 0x00, Name: MAXPEAK_X_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] M AX PEAK_X [ 3 :0 ] ( R) St ores t he highest m agnit ude observed since t he last read of t his regist er. [ 3 :0 ] RESERV ED Table 30. Bit Descriptions for MAXPEAK_X_L Bits Bit Name Settings [7:4] MAXPEAK_X[3:0] Stores the highest magnitude observed since the last read of this register. The 4 LSBs of the x-axis value. 0x0 R [3:0] RESERVED Reserved. 0x0 R Description Reset Access Stores the highest magnitude observed since the last read of this register. The 8 MSBs of the y-axis value. 0x0 R Y-AXIS HIGHEST PEAK DATA REGISTER, MSB Address: 0x17, Reset: 0x00, Name: MAXPEAK_Y_H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] M AX PEAK_Y[ 1 1 :4 ] ( R) St ores t he highest m agnit ude observed since t he last read of t his regist er. Table 31. Bit Descriptions for MAXPEAK_Y_H Bits Bit Name [7:0] MAXPEAK_Y[11:4] Settings Rev. B | Page 36 of 56 Data Sheet ADXL372 Y-AXIS HIGHEST PEAK DATA REGISTER, LSB Address: 0x18, Reset: 0x00, Name: MAXPEAK_Y_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] M AX PEAK_Y[ 3 :0 ] ( R) St ores t he highest m agnit ude observed since t he last read of t his regist er. [ 3 :0 ] RESERV ED Table 32. Bit Descriptions for MAXPEAK_Y_L Bits Bit Name [7:4] [3:0] Settings Description Reset Access MAXPEAK_Y[3:0] Stores the highest magnitude observed since the last read of this register. The 4 LSBs of the y-axis value. 0x0 R RESERVED Reserved. 0x0 R Description Reset Access Stores the highest magnitude observed since the last read of this register. The 8 MSBs of the z-axis value. 0x0 R Description Reset Access Z-AXIS HIGHEST PEAK DATA REGISTER, MSB Address: 0x19, Reset: 0x00, Name: MAXPEAK_Z_H 7 5 6 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] M AX PEAK_Z [ 1 1 :4 ] ( R) St ores t he highest m agnit ude observed since t he last read of t his regist er. Table 33. Bit Descriptions for MAXPEAK_Z_H Bits Bit Name [7:0] MAXPEAK_Z[11:4] Settings Z-AXIS HIGHEST PEAK DATA REGISTER, LSB Address: 0x1A, Reset: 0x00, Name: MAXPEAK_Z_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] M AX PEAK_Z [ 3 :0 ] ( R) St ores t he highest m agnit ude observed since t he last read of t his regist er. [ 3 :0 ] RESERV ED Table 34. Bit Descriptions for MAXPEAK_Z_L Bits Bit Name Settings [7:4] MAXPEAK_Z[3:0] Stores the highest magnitude observed since the last read of this register. The 4 LSBs of the z-axis value. 0x0 R [3:0] RESERVED Reserved. 0x0 R Rev. B | Page 37 of 56 ADXL372 Data Sheet OFFSET TRIM REGISTERS Offset trim registers are each four bits and offer user set, offset adjustments in twos complement format. The scale factor of these registers is shown in Figure 36. X-AXIS OFFSET TRIM REGISTER, LSB Address: 0x20, Reset: 0x00, Name: OFFSET_X 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] RESERV ED [ 3 :0 ] OFFSET_X ( R/W ) Offset added t o X-ax is dat a. Table 35. Bit Descriptions for OFFSET_X Bits Bit Name [7:4] [3:0] Settings Description Reset Access RESERVED Reserved. 0x0 R OFFSET_X Offset added to x-axis data. 0x0 R/W Description Reset Access Y-AXIS OFFSET TRIM REGISTER, LSB Address: 0x21, Reset: 0x00, Name: OFFSET_Y 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] RESERV ED [ 3 :0 ] OFFSET_Y ( R/W ) Offset added t o Y-ax is dat a. Table 36. Bit Descriptions for OFFSET_Y Bits Bit Name Settings [7:4] RESERVED Reserved. 0x0 R [3:0] OFFSET_Y Offset added to y-axis data. 0x0 R/W Description Reset Access Z-AXIS OFFSET TRIM REGISTER, LSB Address: 0x22, Reset: 0x00, Name: OFFSET_Z 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :4 ] RESERV ED [ 3 :0 ] OFFSET_Z ( R/W ) Offset added t o Z-ax is dat a. Table 37. Bit Descriptions for OFFSET_Z Bits Bit Name Settings [7:4] RESERVED Reserved. 0x0 R [3:0] OFFSET_Z Offset added to z-axis data. 0x0 R/W Rev. B | Page 38 of 56 Data Sheet ADXL372 X-AXIS ACTIVITY THRESHOLD REGISTER, MSB Address: 0x23, Reset: 0x00, Name: THRESH_ACT_X_H This 11-bit unsigned value sets the threshold for activity detection. This value is set in codes and the scale factor is 100 mg/code. To detect activity, the absolute value of the 12-bit acceleration data is compared with the 11-bit (unsigned) activity threshold value. The THRESH_ACT_x_L register contains the least significant bits and the THRESH_ACT_x_H register contains the most significant byte of the activity threshold value. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] TH RESH _ACT_X [ 1 0 :3 ] ( R/W ) Threshold for act iv it y det ect ion. Table 38. Bit Descriptions for THRESH_ACT_X_H Bits Bit Name Settings [7:0] THRESH_ACT_X[10:3] Description Reset Access Threshold for activity detection. The 8 MSBs of x-axis threshold. 0x0 R/W X-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB Address: 0x24, Reset: 0x00, Name: THRESH_ACT_X_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :5 ] TH RESH _ACT_X [ 2 :0 ] ( R/W ) Threshold for act iv it y det ect ion. [ 0 ] ACT_X _EN ( R/W ) Enable act iv it y det ect ion using X-ax is dat a. 0: X-ax is ignored. 1: X-ax is used. [ 4 :2 ] RESERV ED [ 1 ] ACT_REF ( R/W ) Select s referenced or absolut e act iv it y processing. 1: Referenced act iv it y processing. 0: Absolut e act iv it y processing. Table 39. Bit Descriptions for THRESH_ACT_X_L Bits Bit Name [7:5] [4:2] 1 0 Settings Description Reset Access THRESH_ACT_X[2:0] Threshold for activity detection. The 3 LSBs of x-axis threshold. 0x0 R/W RESERVED Reserved. 0x0 R ACT_REF Selects referenced or absolute activity processing. 0x0 R/W 0x0 R/W 1 Referenced activity processing. 0 Absolute activity processing. ACT_X_EN Enable activity detection using X-axis data. 0 X-axis ignored. 1 X-axis used. Y-AXIS ACTIVITY THRESHOLD REGISTER, MSB Address: 0x25, Reset: 0x00, Name: THRESH_ACT_Y_H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] TH RESH _ACT_Y[ 1 0 :3 ] ( R/W ) Threshold for act iv it y det ect ion. Table 40. Bit Descriptions for THRESH_ACT_Y_H Bits Bit Name [7:0] THRESH_ACT_Y[10:3] Settings Description Reset Access Threshold for activity detection. The 8 MSBs of y-axis threshold. 0x0 R/W Rev. B | Page 39 of 56 ADXL372 Data Sheet Y-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB Address: 0x26, Reset: 0x00, Name: THRESH_ACT_Y_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 0 ] ACT_Y_EN ( R/W ) Enable act iv it y det ect ion using Y-ax is dat a. 0: Y-ax is ignored. 1: Y-ax is used. [ 7 :5 ] TH RESH _ACT_Y[ 2 :0 ] ( R/W ) Threshold for act iv it y det ect ion. [ 4 :1 ] RESERV ED Table 41. Bit Descriptions for THRESH_ACT_Y_L Bits Bit Name [7:5] Settings Description Reset Access THRESH_ACT_Y[2:0] Threshold for activity detection. The 3 LSBs of y-axis threshold. 0x0 R/W [4:1] RESERVED Reserved. 0x0 R 0 ACT_Y_EN Enable activity detection using y-axis data. 0x0 R/W 0 Y-axis ignored. 1 Y-axis used. Z-AXIS ACTIVITY THRESHOLD REGISTER, MSB Address: 0x27, Reset: 0x00, Name: THRESH_ACT_Z_H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] TH RESH _ACT_Z [ 1 0 :3 ] ( R/W ) Threshold for act iv it y det ect ion. Table 42. Bit Descriptions for THRESH_ACT_Z_H Bits Bit Name Settings [7:0] THRESH_ACT_Z[10:3] Description Reset Access Threshold for activity detection. The 8 MSBs of z-axis threshold. 0x0 R/W Z-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB Address: 0x28, Reset: 0x00, Name: THRESH_ACT_Z_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :5 ] TH RESH _ACT_Z [ 2 :0 ] ( R/W ) Threshold for act iv it y det ect ion. [ 0 ] ACT_Z _EN ( R/W ) Enable act iv it y det ect ion using Z-ax is dat a. 0: Z-ax is ignored. 1: Z-ax is used. [ 4 :1 ] RESERV ED Table 43. Bit Descriptions for THRESH_ACT_Z_L Bits Bit Name [7:5] Settings Description Reset Access THRESH_ACT_Z[2:0] Threshold for activity detection. The 3 LSBs of z-axis threshold. 0x0 R/W [4:1] RESERVED Reserved. 0x0 R 0 ACT_Z_EN Enable activity detection using Z-axis data. 0x0 R/W 0 Z-axis ignored. 1 Z-axis used. Rev. B | Page 40 of 56 Data Sheet ADXL372 ACTIVITY TIME REGISTER Address: 0x29, Reset: 0x00, Name: TIME_ACT The activity timer implements a robust activity detection that minimizes false positive motion triggers. When the timer is used, only sustained motion can trigger activity detection. The time (in milliseconds) is given by the following equation: Time = TIME_ACT x 3.3 ms per code where: TIME_ACT is the value set in this register. 3.3 ms per code is the scale factor of the TIME_ACT register for ODR = 6400 Hz. It is 6.6 ms per code for ODR = 3200 Hz and below. See the Activity Timer section for more information. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] ACT _CO UN T ( R/W ) Num b e r o f m ultip le s o f 3 .3 m s activity tim e r fo r w hich ab o ve thre sho ld re q uire d to d e te ct activity. Table 44. Bit Descriptions for TIME_ACT Bits Bit Name [7:0] ACT_COUNT Settings Description Reset Access Number of multiples of 3.3 ms activity timer for which above threshold acceleration is required to detect activity. It is 3.3 ms per code for 6400 Hz ODR, and it is 6.6 ms per code for 3200 Hz ODR and below. 0x0 R/W X-AXIS INACTIVITY THRESHOLD REGISTER, MSB Address: 0x2A, Reset: 0x00, Name: THRESH_INACT_X_H This 11-bit unsigned value sets the threshold for inactivity detection. This value is set in codes and the scale factor is 100 mg/code. To detect inactivity, the absolute value of the 12-bit acceleration data is compared with the 11-bit (unsigned) inactivity threshold value. The THRESH_INACT_x_L register contains the least significant bits and the THRESH_INACT_x_H register contains the most significant byte of the inactivity threshold value. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] TH RESH _IN ACT_X [ 1 0 :3 ] ( R/W ) Threshold for inact iv it y det ect ion. Table 45. Bit Descriptions for THRESH_INACT_X_H Bits Bit Name [7:0] THRESH_INACT_X[10:3] Settings Description Reset Access Threshold for inactivity detection. The 8 MSBs of x-axis. 0x0 R/W Rev. B | Page 41 of 56 ADXL372 Data Sheet X-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB Address: 0x2B, Reset: 0x00, Name: THRESH_INACT_X_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :5 ] TH RESH _IN ACT_X [ 2 :0 ] ( R/W ) Threshold for inact iv it y det ect ion. [ 0 ] IN ACT_X _EN ( R/W ) X ax is m asked from part icipat ing in inact iv it y det ect ion. 0: X-ax is ignored. 1: X-ax is used. [ 4 :2 ] RESERV ED [ 1 ] IN ACT_REF ( R/W ) Select s referenced or absolut e act iv it y processing. 1: Referenced act iv it y processing. 0: Absolut e act iv it y processing. Table 46. Bit Descriptions for THRESH_INACT_X_L Bits Bit Name [7:5] [4:2] 1 0 Settings Description Reset Access THRESH_INACT_X[2:0] Threshold for inactivity detection. The 3 LSBs of the x-axis. 0x0 R/W RESERVED Reserved. 0x0 R INACT_REF Selects referenced or absolute inactivity processing. 0x0 R/W 0x0 R/W 1 Referenced inactivity processing. 0 Absolute inactivity processing. INACT_X_EN X-axis masked from participating in inactivity detection. 0 X-axis ignored. 1 X-axis used. Y-AXIS INACTIVITY THRESHOLD REGISTER, MSB Address: 0x2C, Reset: 0x00, Name: THRESH_INACT_Y_H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] TH RESH _IN ACT_Y[ 1 0 :3 ] ( R/W ) Threshold for inact iv it y det ect ion. Table 47. Bit Descriptions for THRESH_INACT_Y_H Bits Bit Name [7:0] THRESH_INACT_Y[10:3] Settings Description Reset Access Threshold for inactivity detection. The 8 MSBs of the y-axis. 0x0 R/W Rev. B | Page 42 of 56 Data Sheet ADXL372 Y-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB Address: 0x2D, Reset: 0x00, Name: THRESH_INACT_Y_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :5 ] TH RESH _IN ACT_Y[ 2 :0 ] ( R/W ) Threshold for inact iv it y det ect ion. [ 0 ] IN ACT_Y_EN ( R/W ) Y ax is m asked from part icipat ing in inact iv it y det ect ion. 0: Y-ax is ignored. 1: Y-ax is used. [ 4 :1 ] RESERV ED Table 48. Bit Descriptions for THRESH_INACT_Y_L Bits Bit Name [7:5] Settings Description Reset Access THRESH_INACT_Y[2:0] Threshold for inactivity detection. The 3 LSBs of the y-axis. 0x0 R/W [4:1] RESERVED Reserved. 0x0 R 0 INACT_Y_EN Y-axis masked from participating in inactivity detection. 0x0 R/W Description Reset Access Threshold for inactivity detection. The 8 MSBs of the z-axis. 0x0 R/W 0 Y-axis ignored. 1 Y-axis used. Z-AXIS INACTIVITY THRESHOLD REGISTER, MSB Address: 0x2E, Reset: 0x00, Name: THRESH_INACT_Z_H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] TH RESH _IN ACT_Z [ 1 0 :3 ] ( R/W ) Threshold for inact iv it y det ect ion. Table 49. Bit Descriptions for THRESH_INACT_Z_H Bits Bit Name Settings [7:0] THRESH_INACT_Z[10:3] Z-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB Address: 0x2F, Reset: 0x00, Name: THRESH_INACT_Z_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 0 ] IN ACT_Z _EN ( R/W ) Z ax is m asked from part icipat ing in inact iv it y det ect ion. 0: Z-ax is ignored. 1: Z-ax is used. [ 7 :5 ] TH RESH _IN ACT_Z [ 2 :0 ] ( R/W ) Threshold for inact iv it y det ect ion. [ 4 :1 ] RESERV ED Table 50. Bit Descriptions for THRESH_INACT_Z_L Bits Bit Name [7:5] Settings Description Reset Access THRESH_INACT_Z[2:0] Threshold for inactivity detection. The 3 LSBs of the z-axis. 0x0 R/W [4:1] RESERVED Reserved. 0x0 R 0 INACT_Z_EN Z-axis masked from participating in inactivity detection. 0x0 R/W 0 Z-axis ignored. 1 Z-axis used. Rev. B | Page 43 of 56 ADXL372 Data Sheet INACTIVITY TIME REGISTERS The 16-bit value in these registers sets the time that all enabled axes must be lower than the inactivity threshold for an inactivity event to be detected. The TIME_INACT_L register holds the eight LSBs, and the TIME_INACT_H register holds the eight MSBs of the 16-bit TIME_INACT value. Calculate the time as follows: Time = TIME_INACT x 26 ms per code where: TIME_INACT is the 16-bit value set by the TIME_INACT_L register (eight LSBs) and the TIME_INACT_H register (eight MSBs). 26 ms per code is the scale factor of the TIME_INACT_L and TIME_INACT_H registers for 3200 Hz and below. It is 13 ms per code of ODR = 6400 Hz. See the Inactivity Timer section for more information. INACTIVITY TIMER REGISTER, MSB Address: 0x30, Reset: 0x00, Name: TIME_INACT_H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] IN ACT _CO UN T [ 1 5 :8 ] ( R/W ) Num b e r o f m ultip le s o f 2 6 m s inactivity tim e r fo r w hich b e lo w thre sho ld re q uire d to d e te ct inactivity. Table 51. Bit Descriptions for TIME_INACT_H Bits Bit Name [7:0] INACT_COUNT[15:8] Settings Description Reset Access Number of multiples of 26 ms inactivity timer for which below threshold acceleration is required to detect inactivity. It is 26 ms per code for 3200 Hz ODR and below, and it is 13 ms per code for 6400 Hz ODR. 0x0 R/W Description Reset Access Number of multiples of 26 ms inactivity timer for which below threshold acceleration is required to detect inactivity. 0x0 R/W INACTIVITY TIMER REGISTER, LSB Address: 0x31, Reset: 0x00, Name: TIME_INACT_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] IN ACT _CO UN T [ 7 :0 ] ( R/W ) Num b e r o f m ultip le s o f 2 6 m s inactivity tim e r fo r w hich b e lo w thre sho ld re q uire d to d e te ct inactivity. Table 52. Bit Descriptions for TIME_INACT_L Bits Bit Name [7:0] INACT_COUNT[7:0] Settings Rev. B | Page 44 of 56 Data Sheet ADXL372 X-AXIS MOTION WARNING THRESHOLD REGISTER, MSB Address: 0x32, Reset: 0x00, Name: THRESH_ACT2_X_H This 11-bit unsigned value sets the threshold for motion detection. This value is set in codes and the scale factor is 100 mg/code. To detect motion, the absolute value of the 12-bit acceleration data is compared with the 11-bit (unsigned) ACTIVITY2 threshold value. The THRESH_ACT2_x_L register contains the least significant bits and the THRESH_ACT2_x_H register contains the most significant byte of the ACTIVITY2 threshold value. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] TH RESH _ACT2 _X [ 1 0 :3 ] ( R/W ) OTN Threshold. Table 53. Bit Descriptions for THRESH_ACT2_X_H Bits Bit Name [7:0] THRESH_ACT2_X[10:3] 1 Settings Description1 Reset Access OTN Threshold. The 8 MSBs of the x-axis threshold for motion warning interrupt. 0x0 R/W Description1 Reset Access OTN stands for other threshold notification. X-AXIS OF MOTION WARNING NOTIFICATION REGISTER, LSB Address: 0x33, Reset: 0x00, Name: THRESH_ACT2_X_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 0 ] ACT2 _X _EN ( R/W ) X axis ACT2 enable. 0: X-axis ignored. 1: X-axis used. [ 7 :5 ] TH RESH _ACT2 _X [ 2 :0 ] ( R/W ) OTN Threshold. [ 4 :2 ] RESERV ED [ 1 ] ACT2 _REF ( R/W ) Select s referenced or absolut e over-t hreshold not ificat ion processing. 1: Referenced act ivit y processing. 0: Absolut e act ivit y processing. Table 54. Bit Descriptions for THRESH_ACT2_X_L Bits Bit Name [7:5] THRESH_ACT2_X[2:0] OTN Threshold. The 3 LSBs of the x-axis threshold for motion warning interrupt. 0x0 R/W [4:2] RESERVED Reserved. 0x0 R 1 ACT2_REF Selects referenced or absolute motion warning notification processing. 0x0 R/W 0x0 R/W 0 1 Settings 1 Referenced activity processing. 0 Absolute activity processing. ACT2_X_EN X-axis ACT2 enable. When set to 1, the x-axis participates in motion warning notification detection. 0 X-axis ignored. 1 X-axis used. OTN stands for other threshold notification, and ACT2 stands for ACTIVITY2. Rev. B | Page 45 of 56 ADXL372 Data Sheet Y-AXIS MOTION WARNING NOTIFICATION THRESHOLD REGISTER, MSB Address: 0x34, Reset: 0x00, Name: THRESH_ACT2_Y_H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] TH RESH _ACT2 _Y[ 1 0 :3 ] ( R/W ) OTN Threshold. Table 55. Bit Descriptions for THRESH_ACT2_Y_H Bits Bit Name [7:0] THRESH_ACT2_Y[10:3] 1 Settings Description1 Reset Access OTN Threshold. The 8 MSBs of the y-axis threshold for motion warning interrupt. 0x0 R/W Description1 Reset Access OTN stands for other threshold notification. Y-AXIS OF MOTION WARNING NOTIFICATION REGISTER, LSB Address: 0x35, Reset: 0x00, Name: THRESH_ACT2_Y_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :5 ] TH RESH _ACT2 _Y[ 2 :0 ] ( R/W ) OTN Threshold. [ 0 ] ACT2 _Y_EN ( R/W ) Y ax is ACT2 enable. 0: Y-ax is ignored. 1: Y-ax is used. [ 4 :1 ] RESERV ED Table 56. Bit Descriptions for THRESH_ACT2_Y_L Bits Bit Name [7:5] THRESH_ACT2_Y[2:0] OTN Threshold. The 3 LSBs of the y-axis threshold for motion warning interrupt. 0x0 R/W [4:1] RESERVED Reserved. 0x0 R 0 ACT2_Y_EN Y-axis ACT2 enable. When 1, the y-axis participates in motion warning notification detection. 0x0 R/W Description1 Reset Access OTN Threshold. The 8 MSBs of the z-axis threshold for motion warning interrupt. 0x0 R/W 1 Settings 0 Y-axis ignored. 1 Y-axis used. OTN stands for other threshold notification, and ACT2 stands for ACTIVITY2. Z-AXIS MOTION WARNING NOTIFICATION THRESHOLD REGISTER, MSB Address: 0x36, Reset: 0x00, Name: THRESH_ACT2_Z_H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] TH RESH _ACT2 _Z [ 1 0 :3 ] ( R/W ) OTN Threshold. Table 57. Bit Descriptions for THRESH_ACT2_Z_H Bits Bit Name [7:0] THRESH_ACT2_Z[10:3] 1 Settings OTN stands for other threshold notification. Rev. B | Page 46 of 56 Data Sheet ADXL372 Z-AXIS MOTION WARNING NOTIFICATION REGISTER, LSB Address: 0x37, Reset: 0x00, Name: THRESH_ACT2_Z_L 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :5 ] TH RESH _ACT2 _Z [ 2 :0 ] ( R/W ) OTN Threshold. [ 0 ] ACT2 _Z _EN ( R/W ) Z ax is ACT2 enable. 0: Z-ax is ignored. 1: Z-ax is used. [ 4 :1 ] RESERV ED Table 58. Bit Descriptions for THRESH_ACT2_Z_L Bits Bit Name [7:5] Description1 Reset Access THRESH_ACT2_Z[2:0] OTN Threshold. The 3 LSBs of the z-axis threshold for motion warning interrupt. 0x0 R/W [4:1] RESERVED Reserved. 0x0 R 0 ACT2_Z_EN Z-axis ACT2 enable. When 1, the z-axis participates in motion warning notification detection. 0x0 R/W Description Reset Access Reserved. 0x0 R High-Pass Filter Corner Frequency Selection. 0x0 R/W 1 Settings 0 Z-axis ignored. 1 Z-axis used. OTN stands for other threshold notification, and ACT2 stands for ACTIVITY2. HIGH-PASS FILTER SETTINGS REGISTER Address: 0x38, Reset: 0x00, Name: HPF Use this register to specify parameters for the internal high-pass filter. [ 7 :2 ] RESERV ED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 1 :0 ] H PF_CORN ER ( R/W ) High-Pass Filt er Corner Frequency Select ion. 00: High Pass Filt er Corner 0. 01: High Pass Filt er Corner 1. 10: High Pass Filt er Corner 2. 11: High Pass Filt er Corner 3. Table 59. Bit Descriptions for HPF Bits Bit Name [7:2] RESERVED [1:0] HPF_CORNER Settings 00 High Pass Filter Corner 0. At ODR 6400 Hz = 30.48 Hz, at ODR 3200 Hz = 15.24 Hz, at ODR 1600 Hz = 7.61 Hz, at ODR 800 Hz = 3.81 Hz, and at ODR 400 Hz = 1.90 Hz. 01 High Pass Filter Corner 1. At ODR 6400 Hz = 15.58 Hz, at ODR 3200 Hz = 7.79 Hz, at ODR 1600 Hz = 3.89 Hz, at ODR 800 Hz = 1.94 Hz, and at ODR 400 Hz = 0.97 Hz. 10 High Pass Filter Corner 2. At ODR 6400 Hz = 7.88 Hz, at ODR 3200 Hz = 3.94 Hz, at ODR 1600 Hz = 1.97 Hz, at ODR 800 Hz = 0.98 Hz, and at ODR 400 Hz = 0.49 Hz. 11 High Pass Filter Corner 3. At ODR 6400 Hz = 3.96 Hz, at ODR 3200 Hz = 1.98 Hz, at ODR 1600 Hz = 0.99 Hz, at ODR 800 Hz = 0.49 Hz, and at ODR 400 Hz = 0.24 Hz. Rev. B | Page 47 of 56 ADXL372 Data Sheet FIFO SAMPLES REGISTER Address: 0x39, Reset: 0x80, Name: FIFO_SAMPLES Use the FIFO_SAMPLES value to specify the number of samples to store in the FIFO. The 8 least significant bits (LSBs) of the FIFO_SAMPLES value are stored in this register. The most significant bit (MSB) of the FIFO_SAMPLES value is Bit 0 of the FIFO_CTL register. The default value of this register is 0x80 to avoid triggering the FIFO watermark interrupt (see the FIFO Watermark section for more information). In trigger FIFO mode, FIFO_SAMPLES program the number of samples to be saved after the trigger is detected. 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [ 7 :0 ] FIFO_SAM PLES[ 7 :0 ] ( R/W ) FIFO Sam ples. Table 60. Bit Descriptions for FIFO_SAMPLES Bits Bit Name Settings [7:0] FIFO_SAMPLES[7:0] Description Reset Access FIFO Samples. Watermark number of FIFO samples that triggers a FIFO_FULL condition when reached. Values range from 0 to 512. 0x80 R/W Description Reset Access FIFO CONTROL REGISTER Address: 0x3A, Reset: 0x00, Name: FIFO_CTL Use this register to specify the operating parameters for the FIFO. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :6 ] RESERVED [ 5 :3 ] FIFO _FO RM AT ( R/W ) FIFO Fo rm at. 111: FIFO sto re s p e ak acce le ratio n (x, y, and z) o f e ve ry o ve r-thre sho ld e ve nt. 0 0 1: FIFO sto re s x-axis acce le ratio n d ata o nly. 0 10 : FIFO sto re s y-axis acce le ratio n d ata o nly. 0 11: FIFO sto re s x- and y-axis acce le ratio n d ata. 10 0 : FIFO sto re s z-axis acce le ratio n d ata o nly. 10 1: FIFO sto re s x- and z-axis acce le ratio n d ata. 110 : FIFO sto re s y- and z-axis acce le ratio n d ata. 0 0 0 : FIFO sto re s x-, y- and z-axis acce le ratio n d ata. [ 0 ] FIFO _SAM PLES[ 8 ] ( R/W ) FIFO Sam p le s. [ 2 :1 ] FIFO _M O D E ( R/W ) FIFO Mo d e . 0 : FIFO is b yp asse d . 1: FIFO o p e rate s in stre am m o d e . 10 : FIFO o p e rate s in trig g e r m o d e . 11: FIFO o p e rate s in o ld e st save d m o d e . Table 61. Bit Descriptions for FIFO_CTL Bits Bit Name Settings [7:6] RESERVED Reserved. 0x0 R [5:3] FIFO_FORMAT FIFO Format. Specifies which data is stored in the FIFO buffer. 0x0 R/W 111 FIFO stores peak acceleration (x, y, and z) of every over threshold event. 001 FIFO stores x-axis acceleration data only. 010 FIFO stores y-axis acceleration data only. 011 FIFO stores x- and y-axis acceleration data. 100 FIFO stores z-axis acceleration data only. 101 FIFO stores x- and z-axis acceleration data. 110 FIFO stores y- and z-axis acceleration data. 000 FIFO stores x-, y- and z-axis acceleration data. Rev. B | Page 48 of 56 Data Sheet Bits Bit Name [2:1] FIFO_MODE 0 FIFO_SAMPLES[8] ADXL372 Settings Description Reset Access FIFO Mode. Specifies FIFO operating mode. 0x0 R/W 0x0 R/W 0 FIFO is bypassed. 1 FIFO operates in stream mode. 10 FIFO operates in trigger mode. 11 FIFO operates in oldest saved mode. FIFO Samples. Watermark number of FIFO samples that triggers a FIFO_FULL condition when reached. Values range from 0 to 512. INTERRUPT PIN FUNCTION MAP REGISTERS Address: 0x3B, Reset: 0x00, Name: INT1_MAP The INT1_MAP and INT2_MAP registers configure the INT1 and INT2 interrupt pins, respectively. Bits[6:0] select which function(s) generate an interrupt on the pin. If its corresponding bit is set to 1, the function generates an interrupt on the INTx pin. Bit B7 configures whether the pin operates in active high (B7 low) or active low (B7 high) mode. Any number of functions can be selected simultaneously for each pin. If multiple functions are selected, their conditions are OR'ed together to determine the INTx pin state. The status of each function can be determined by reading the status register. If no interrupts are mapped to an INTx pin, the pin remains in a high impedance state. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] IN T 1 _LO W ( R/W ) Co nfig ure s INT1 fo r active lo w o p e ratio n. [ 0 ] D AT A_RD Y_IN T 1 ( R/W ) Map d ata re ad y inte rrup t o nto INT1. [ 6 ] AW AKE_IN T 1 ( R/W ) Map aw ake inte rrup t o nto INT1. [ 1 ] FIFO _RD Y_IN T 1 ( R/W ) Map FIFO_READY inte rrup t o nto INT1. [ 5 ] ACT _IN T 1 ( R/W ) Map activity inte rrup t o nto INT1. [ 2 ] FIFO _FULL_IN T 1 ( R/W ) Map FIFO_FULL inte rrup t o nto INT1. [ 4 ] IN ACT _IN T 1 ( R/W ) Map inactivity inte rrup t o nto INT1. [ 3 ] FIFO _O VR_IN T 1 ( R/W ) Map FIFO_OVERRUN inte rrup t o nto INT1. Table 62. Bit Descriptions for INT1_MAP Bits Bit Name 7 Settings Description Reset Access INT1_LOW Configures INT1 for active low operation. 0x0 R/W 6 AWAKE_INT1 Map awake interrupt onto INT1. 0x0 R/W 5 ACT_INT1 Map activity interrupt onto INT1. 0x0 R/W 4 INACT_INT1 Map inactivity interrupt onto INT1. 0x0 R/W 3 FIFO_OVR_INT1 Map FIFO_OVERRUN interrupt onto INT1. 0x0 R/W 2 FIFO_FULL_INT1 Map FIFO_FULL interrupt onto INT1. 0x0 R/W 1 FIFO_RDY_INT1 Map FIFO_READY interrupt onto INT1. 0x0 R/W 0 DATA_RDY_INT1 Map data ready interrupt onto INT1. 0x0 R/W Rev. B | Page 49 of 56 ADXL372 Data Sheet INT2 FUNCTION MAP REGISTER Address: 0x3C, Reset: 0x00, Name: INT2_MAP 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] IN T 2 _LO W ( R/W ) Co nfig ure s INT2 fo r active lo w o p e ratio n. [ 0 ] D AT A_RD Y_IN T 2 ( R/W ) Map d ata re ad y inte rrup t o nto INT2 . [ 6 ] AW AKE_IN T 2 ( R/W ) Map aw ake inte rrup t o nto INT2 . [ 1 ] FIFO _RD Y_IN T 2 ( R/W ) Map FIFO_READY inte rrup t o nto INT2 . [ 5 ] ACT 2 _IN T 2 ( R/W ) Map activity 2 inte rrup t o nto INT2 . [ 2 ] FIFO _FULL_IN T 2 ( R/W ) Map FIFO_FULL inte rrup t o nto INT2 . [ 4 ] IN ACT _IN T 2 ( R/W ) Map inactivity inte rrup t o nto INT2 . [ 3 ] FIFO _O VR_IN T 2 ( R/W ) Map FIFO_OVERRUN inte rrup t o nto INT2 . Table 63. Bit Descriptions for INT2_MAP Bits Bit Name 7 Settings Description Reset Access INT2_LOW Configures INT2 for active low operation. 0x0 R/W 6 AWAKE_INT2 Map awake interrupt onto INT2. 0x0 R/W 5 ACT2_INT2 Map Activity 2 (motion warning) interrupt onto INT2. 0x0 R/W 4 INACT_INT2 Map inactivity interrupt onto INT2. 0x0 R/W 3 FIFO_OVR_INT2 Map FIFO_OVERRUN interrupt onto INT2. 0x0 R/W 2 FIFO_FULL_INT2 Map FIFO_FULL interrupt onto INT2. 0x0 R/W 1 FIFO_RDY_INT2 Map FIFO_READY interrupt onto INT2. 0x0 R/W 0 DATA_RDY_INT2 Map data ready interrupt onto INT2. 0x0 R/W EXTERNAL TIMING CONTROL REGISTER Address: 0x3D, Reset: 0x00, Name: TIMING Use this register to control the ADXL372 timing parameters: ODR and external timing triggers. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :5 ] O D R ( R/W ) Outp ut d ata rate . 0 0 0 : 4 0 0 Hz ODR. 0 0 1: 8 0 0 Hz ODR. 0 10 : 16 0 0 Hz ODR. 0 11: 3 2 0 0 Hz ODR. 10 0 : 6 4 0 0 Hz ODR. [ 0 ] EXT _SYN C ( R/W ) Enab le e xte rnal trig g e r. [ 1 ] EXT _CLK ( R/W ) Enab le e xte rnal clo ck. [ 4 :2 ] W AKEUP_RAT E ( R/W ) Tim e r Rate fo r Wake -Up Mo d e . 0 : 5 2 m s. 1: 10 4 m s. 10 : 2 0 8 m s. 11: 5 12 m s. 10 0 : 2 0 4 8 m s. 10 1: 4 0 9 6 m s. 110 : 8 19 2 m s. 111: 2 4 5 7 6 m s. Table 64. Bit Descriptions for TIMING Bits Bit Name [7:5] ODR Settings Description Reset Access Output data rate. 0x0 R/W 000 400 Hz ODR. 001 800 Hz ODR. 010 1600 Hz ODR. 011 3200 Hz ODR. 100 6400 Hz ODR. Rev. B | Page 50 of 56 Data Sheet Bits Bit Name [4:2] WAKEUP_RATE ADXL372 Settings Description Reset Access Timer Rate for Wake-Up Mode. 0x0 R/W 0 52 ms. 1 104 ms. 10 208 ms. 11 512 ms. 100 2048 ms. 101 4096 ms. 110 8192 ms. 111 24576 ms. 1 EXT_CLK Enable external clock. 0x0 R/W 0 EXT_SYNC Enable external trigger. 0x0 R/W MEASUREMENT CONTROL REGISTER Address: 0x3E, Reset: 0x00, Name: MEASURE Use this register to control several measurement settings. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] U SER_OR_D ISABLE ( R/W ) User overange disable. [ 2 :0 ] BAN D W ID TH ( R/W ) Bandw idt h. 000: 200 Hz Bandw idt h. 001: 400 Hz Bandw idt h. 010: 800 Hz Bandw idt h. 011: 1600 Hz Bandw idt h. 100: 3200 Hz Bandw idt h. [ 6 ] AU TOSLEEP ( R/W ) Aut osleep. [ 5 :4 ] LIN KLOOP ( R/W ) Link/Loop Act ivit y Processing. 0: Default Mode. 1: Linked Mode. 10: Looped Mode. [ 3 ] LOW _N OISE ( R/W ) Low Noise. 0: Norm al operat ion. 1: Low noise operat ion. Table 65. Bit Descriptions for MEASURE Bits Bit Name 7 Settings Description Reset Access USER_OR_DISABLE User overange disable. 0x0 R/W 6 AUTOSLEEP Autosleep. When set to 1, autosleep is enabled, and the device enters wake-up mode automatically upon detection of inactivity. Activity and inactivity detection must be in linked mode or loop mode (the LINKLOOP bits in the MEASURE register) to enable autosleep; otherwise, the bit is ignored. 0x0 R/W [5:4] LINKLOOP Link/Loop Activity Processing. These bits select how activity and inactivity processing are linked. 0x0 R/W 0 Default Mode. Activity and inactivity detection, when enabled, operate simultaneously and their interrupts (if mapped) must be acknowledged by the host processor by reading the status register. Autosleep is disabled in this mode. 1 Linked Mode. Activity and inactivity detection are linked sequentially such that only one is enabled at a time. Their interrupts (if mapped) must be acknowledged by the host processor by reading the status register. 10 Looped Mode. Activity and inactivity detection are linked sequentially such that only one is enabled at a time, and their interrupts are internally acknowledged (do not need to be serviced by the host processor). To use either linked or looped mode, both ACT_x_EN and INACT_x_EN must be set to 1; otherwise, the default mode is used. For additional information, refer to the Linking Activity and Inactivity Detection section. Rev. B | Page 51 of 56 ADXL372 Bits Bit Name 3 LOW_NOISE [2:0] Data Sheet Settings Description Reset Access Low Noise. Selects low noise operation. 0x0 R/W 0x0 R/W Description Reset Access 0 Normal operation. Device operates at the normal noise level and ultralow current consumption 1 Low noise operation. Device operates at ~1/3 the normal noise level. BANDWIDTH Bandwidth. Select the desired output signal bandwidth. A 4-pole low-pass filter at the selected frequency limits the signal bandwidth. 000 200 Hz Bandwidth. 001 400 Hz Bandwidth. 010 800 Hz Bandwidth. 011 1600 Hz Bandwidth. 100 3200 Hz Bandwidth. POWER CONTROL REGISTER Address: 0x3F, Reset: 0x00, Name: POWER_CTL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 ] I2 C_H SM _EN ( R/W ) I2 C sp e e d se le ct. 1= Hig h sp e e d m o d e . [ 6 ] RESERVED [ 5 ] IN ST AN T _O N _T H RESH ( R/W ) Use r se le ctab le instant o n thre sho ld se le ct. 0 = lo w thre sho ld 1 = hig h thre sho ld . 0 : Se le cts the lo w instant o n thre sho ld . 1: Se le cts the hig h instant o n thre sho ld . [ 1 :0 ] M O D E ( R/W ) Mo d e o f o p e ratio n. 11: Full b and w id th m e asure m e nt m o d e . 10 : Instant o n m o d e . 0 1: Wake up m o d e . 0 0 : Stand b y. [ 2 ] H PF_D ISABLE ( R/W ) Disab le s the d ig ital hig h-p ass filte r. [ 3 ] LPF_D ISABLE ( R/W ) Disab le s the d ig ital lo w -p ass filte r. [ 4 ] FILT ER_SET T LE ( R/W ) Use r se le ctab le filte r se ttling p e rio d . 0 = 3 7 0 m s se ttle p e rio d , and 1 = 16 m s se ttle p e rio d . 1: Filte r se ttling se t to 16 m s. Id e al fo r w he n HPF and LPF are d isab le d . 0 : Filte r se ttling se t to 3 7 0 m s. Table 66. Bit Descriptions for POWER_CTL Bits Bit Name 7 I2C_HSM_EN I2C speed select. 1 = high speed mode. 0x0 R/W 6 RESERVED Reserved. 0x0 R 5 INSTANT_ON_THRESH User selectable instant on threshold select. 0 = low threshold, 1 = high threshold. 0x0 R/W 0x0 R/W 4 Settings 0 Selects the low instant on threshold. 1 Selects the high instant on threshold. FILTER_SETTLE User selectable filter settling period. 0 = 370 ms settle period, and 1 = 16 ms settle period. 0 Filter settling set to 370 ms. 1 Filter settling set to 16 ms. Ideal for when HPF and LPF are disabled. 3 LPF_DISABLE Disables the digital low-pass filter. 0x0 R/W 2 HPF_DISABLE Disables the digital high-pass filter. 0x0 R/W [1:0] MODE Mode of operation. 0x0 R/W 11 Full bandwidth measurement mode. 10 Instant on mode. 01 Wake up mode. 00 Standby. Rev. B | Page 52 of 56 Data Sheet ADXL372 SELF TEST REGISTER Address: 0x40, Reset: 0x00, Name: SELF_TEST Refer to the Self Test section for information on the operation of the self test feature, and see the Self Test Procedure section for guidelines on how to use this functionality. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :3 ] RESERVED [ 0 ] ST ( R/W 1 ) Se lf te st. [ 2 ] USER_ST ( R) Use r se lf te st p ass if = 1. [ 1 ] ST _D O N E ( R) Se lf te st finishe d . Table 67. Bit Descriptions for SELF_TEST Bits Bit Name [7:3] Settings Description Reset Access RESERVED Reserved. 0x0 R 2 USER_ST User self test pass if = 1. 0x0 R 1 ST_DONE Self test finished. 0x0 R 0 ST Self test. Writing a 1 to this bit initiates self test. Writing a 0 clears self test. 0x0 R/W1 RESET (CLEARS) REGISTER, PART IN STANDBY MODE Address: 0x41, Reset: 0x00, Name: RESET 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] RESET ( W ) Writ ing code " 0x 52" reset s t he dev ice. Table 68. Bit Descriptions for RESET Bits Bit Name [7:0] Reset Settings Description Reset Access Writing code 0x52 resets the device. 0x0 W FIFO ACCESS REGISTER Address: 0x42, Reset: 0x00, Name: FIFO_DATA Read this register to access data stored in the FIFO. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [ 7 :0 ] FIFO_D ATA ( R) FIFO Dat a. Table 69. Bit Descriptions for FIFO_DATA Bits Bit Name [7:0] FIFO_DATA Settings Description Reset Access FIFO Data. A read to this address pops a 2-byte word of axis data from the FIFO. FIFO data is formatted to 2 bytes (16 bits), most significant byte first. Two subsequent reads complete the transaction of this data onto the interface. Continued reading of this field continues to pop the FIFO every third read. Multibyte reads to this address do not increment the address pointer. If this address is read due to an auto-increment from the previous address, it does not pop the FIFO. It returns zeros and increment on to the next address. 0x0 R Rev. B | Page 53 of 56 ADXL372 Data Sheet APPLICATIONS INFORMATION APPLICATION EXAMPLES Figure 50 is an application diagram for using the INT2 pin as a trigger for synchronized sampling. Acceleration samples are produced every time this trigger is activated. Set the EXT_SYNC bit in the TIMING register to enable this feature. This section includes a few application circuits, highlighting useful features of the ADXL372. Power Supply Decoupling VDD I/O ADXL372 CIO VS INTERRUPT CONTROL VDD I/O ADXL372 INT2 SCLK CS GND SAMPLING TRIGGER SPI INTERFACE 15430-048 MOSI MISO INT1 Figure 48. Recommended Bypass Capacitors A 0.1 F ceramic capacitor (CS) at VS and a 0.1 F ceramic capacitor (CIO) at VDDI/O placed as close as possible to the ADXL372 supply pins are recommended to adequately decouple the accelerometer from noise on the power supply. It is recommended that VS and VDDI/O be separate supplies to minimize digital clocking noise on the VS supply. If this is not possible, additional filtering of the supplies may be necessary. If additional decoupling is necessary, a resistor or ferrite bead, no larger than 100 , in series with VS, is recommended. Additionally, increasing the bypass capacitance on VS to a 1 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor may also improve noise. Ensure that the connection from the ADXL372 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through VS. Using External Timing Triggers Figure 49 shows an application diagram for using the INT1 pin as the input for an external clock. In this mode, the external clock determines all accelerometer timing, including the output data rate and bandwidth. Set the EXT_CLK bit in the TIMING register to enable this feature. VDD I/O VS CIO CS VDD I/O VS CS INTERRUPT CONTROL CIO CS MOSI MISO INT1 SCLK INT2 GND SPI INTERFACE CS 15430-050 VS VDD I/O VS Figure 48 shows the recommended bypass capacitors for use with the ADXL372. Figure 50. Using the INT2 Pin to Trigger Synchronized Sampling OPERATION AT VOLTAGES OTHER THAN 2.5 V The ADXL372 is tested and specified at a supply voltage of VS = 2.5 V; however, it can be powered with a VS as high as 3.5 V or as low as 1.6 V. Some performance parameters change as the supply voltage changes, including the supply current, noise, offset, and sensitivity. OPERATION AT TEMPERATURES OTHER THAN AMBIENT The ADXL372 is tested and specified at an ambient temperature; however, it is rated for temperatures between -40C and +105C. Some performance parameters change along with temperature, such as offset, sensitivity, clock performance, and current. Some of these temperature variations are characterized in Table 1, and others are shown in the figures within the Typical Performance Characteristics section. MECHANICAL CONSIDERATIONS FOR MOUNTING Mount the ADXL372 on the PCB in a location close to a hard mounting point of the PCB to the case. Mounting the ADXL372 at an unsupported PCB location, as shown in Figure 51, can result in large, apparent measurement errors due to undamped PCB vibration. Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer is above the mechanical sensor resonant frequency of the accelerometer and, therefore, effectively invisible to the accelerometer. Multiple mounting points, close to the sensor, and/or a thicker PCB also help to reduce the effect of system resonance on the performance of the sensor. ACCELEROMETERS VDD I/O VS PCB ADXL372 INTERRUPT CONTROL INT2 MISO SCLK GND SPI INTERFACE CS 15430-049 INT1 Figure 49. INT1 Pin as Input for External Clock Rev. B | Page 54 of 56 MOUNTING POINTS Figure 51. Incorrectly Placed Accelerometers 15430-051 MOSI EXTERNAL CLOCK Data Sheet ADXL372 AXES OF ACCELERATION SENSITIVITY AZ AX 15430-052 AY Figure 52. Axes of Acceleration Sensitivity (Corresponding Output Increases When Accelerated Along the Sensitive Axis) XOUT = 1g YOUT = 0g ZOUT = 0g TOP XOUT = 0g YOUT = -1g ZOUT = 0g TOP TOP XOUT = 0g YOUT = 1g ZOUT = 0g GRAVITY TOP XOUT = 0g YOUT = 0g ZOUT = 1g XOUT = 0g YOUT = 0g ZOUT = -1g Figure 53. Output Response vs. Orientation to Gravity LAYOUT AND DESIGN RECOMMENDATIONS Figure 54 shows the recommended printed wiring board land pattern. 0.9250 0.3000 3.3500 0.5000 3.5000 15430-054 0.8000 Figure 54. Recommended Printed Wiring Board Land Pattern (Dimensions Shown in Millimeters) Rev. B | Page 55 of 56 15430-053 XOUT = -1g YOUT = 0g ZOUT = 0g ADXL372 Data Sheet OUTLINE DIMENSIONS PIN 1 CORNER 3.30 3.25 3.15 1.00 REF 0.10 REF 3.10 3.00 2.90 0.50 BSC 0.375 REF 0.25 x 0.35 REF 13 1 14 16 8 6 9 5 0.475 x 0.25 REF BOTTOM VIEW TOP VIEW 0.3375 REF END VIEW 05-07-2015-C PKG-003967 1.14 1.06 1.00 SEATING PLANE Figure 55. 16-Terminal Land Grid Array [LGA] (CC-16-4) Dimensions shown in millimeters ORDERING GUIDE Model1 ADXL372BCCZ-RL ADXL372BCCZ-RL7 EVAL-ADXL372Z 1 Temperature Range -40C to +105C -40C to +105C -40C to +105C Package Description 16-Terminal Land Grid Array [LGA] 16-Terminal Land Grid Array [LGA] Breakout Board Z = RoHS Compliant Part. (c)2017-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15430-0-8/18(B) Rev. B | Page 56 of 56 Package Option CC-16-4 CC-16-4 Quantity 5,000 1,500