Description
The A6276 is specifically designed for LED-display
applications. Each BiCMOS device includes a 16-bit CMOS
shift register, accompanying data latches, and 16 NPN constant-
current sink drivers. Except for package style and allowable
package power dissipation, the device options are identical.
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 5 V logic supply,
typical serial data-input rates are up to 20 MHz. The LED drive
current is de ter mined by the user selection of a single resistor.
A CMOS serial data output permits cascaded connections in
applications requiring additional drive lines. For inter-digit
blanking, all output drivers can be disabled with an ENABLE
input high. Similar 8-bit devices are available as the A6275.
Three package styles are provided: through-hole DIP (suffix A),
surface-mount SOIC (suffix LW), and TSSOP with exposed
thermal pad (suffix LP). In normal applications, the copper
leadframe and low logic-power dissipation of the DIP allow it
to sink maximum rated current through all outputs con tin u ous ly
over the operating temperature range (90 mA, 0.75 V drop,
85°C). All packages are lead (Pb) free, with 100% matte tin
leadframe plating.
26185.201H
Features and Benefits
▪ Up to 90 mA constant-current outputs
▪ Undervoltage lockout
▪ Low-power CMOS logic and latches
▪ High data input rate
▪ Functional replacement for TB62706BN/BF
16-Bit Serial Input, Constant-Current
Latched LED Driver
Functional Block Diagram
A6276
Packages
Not to scale
24-pin DIP
(A package)
24-pin SOICW
(LW package)
24-pin TSSOP
with exposed thermal pad
(LP package)
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection Guide
Part Number Package Packing Ambient
Temperature (°C)
A6276EA-T 24-pin DIP 15 per tube –40 to 85
A6276ELPTR-T*24-pin TSSOP 4000 per reel –40 to 85
A6276ELWTR-T 24-pin SOICW 1000 per reel –40 to 85
A6276SLWTR-T*24-pin SOICW 1000 per reel –20 to 85
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is
obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant
should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer
available. Status date change November 1, 2008. Deadline for receipt of LAST TIME BUY orders is April 25, 2009.
Absolute Maximum Ratings*
Characteristic Symbol Notes Rating Units
Supply Voltage VDD 7.0 V
Output Voltage VO–0.5 to 17 V
Input Voltage VROUT –0.4 to VDD + 0.4 V
Output Current IO90 mA
Ground Current IGND 1475 mA
Operating Ambient Temperature TA
Range S –20 to 85 ºC
Range E –40 to 85 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
*Caution: These CMOS devices have input static protection (Class 2) but are still sus cep ti ble to damage if exposed to extremely high
static electrical charges.
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA
Package A, 1-layer PCB based on JEDEC standard 50 ºC/W
Package LP, 2-layer PCB with 3.8 in.
2 copper area each side 32 ºC/W
Package LW, 1-layer PCB based on JEDEC standard 85 ºC/W
*Additional thermal information available on the Allegro website
2.5
0.5
2.0
3.5
3.0
4.0
1.5
1.0
050 75 100 125 150
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN °°
°°C
25
24-PIN DIP, R
θJA
= 50°C/W
24-PIN TSSOP*, R
θJA
= 32°C/W
24-LEAD SOIC, R
θJA
= 85°C/W
*Mounted on single-layer, two-sided PCB, with 3.8 in
2
copper each side;
additional information on Allegro Web site
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright © 2000, 2003 Allegro MicroSystems, Inc.
Terminal Description
Terminal No. Terminal Name Function
1 GND Reference terminal for control logic.
2 SERIAL DATA IN Serial-data input to the shift-register.
3 CLOCK Clock input terminal for data shift on rising edge.
4 LATCH ENABLE Data strobe input terminal; serial data is latched with high-level input.
5-20 OUT0-15 The 16 current-sinking output ter mi nals.
21 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
22 SERIAL DATA OUT CMOS serial-data output to the following shift-register.
23 REXT An external resistor at this terminal establishes the output current for all
sink drivers.
24 SUPPLY (VDD) The logic supply voltage (typically 5 V).
GROUND
REGISTER
LATCHES
1
2
3
18
19
20
21
23
4
5
6
7
22
24
SERIAL
DATA OUT
LOGIC
SUPPLY
SERIAL
DATA IN
OUTPUT
ENABLE
LATCH
ENABLE
CLOCK CK
V
DD
OE
OUT
1
OUT
2
OUT
0
OUT
12
OUT
14
OUT
13
OUT
3
OUT
15
R
EXT
I
REGULATOR
L
O
12
9
10
11
OUT
5
OUT
6
OUT
4
OUT
7
13
14
15
16
817
OUT
8
OUT
10
OUT
9
OUT
11
Pin-out Diagram
(A, LP, and LW packages)
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
CLOCK and SERIAL DATA IN SERIAL DATA OUT
LATCH ENABLEOUTPUT ENABLE (active low)
Dwg. EP-010-11
IN
VDD
Dwg. EP-010-12
IN
VDD
Dwg. EP-010-13
IN
VDD
TRUTH TABLE
Serial Shift Register Contents Serial Latch Latch Contents Output Output Con tents
Data Clock Data Enable Enable
Input Input I1 I
2 I
3 ... IN-1 I
N Output Input I1 I
2 I
3 ... IN-1 I
N Input I1 I
2 I
3 ... IN-1 IN
H H R1 R2 ... RN-2 R
N-1 R
N-1
L L R1 R2 ... RN-2 R
N-1 RN-1
X R1 R2 R3 ... RN-1 RN RN
X X X ... X X X L R1 R2 R3 ... RN-1 RN
P
1 P2 P3 ... PN-1 PN P
N H P1 P2 P3 ... PN-1 PN L P1 P
2 P
3 ... PN-1 PN
X X X ... X X H H H H ... H H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
VDD
Dwg. EP-063-6
OUT
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Supply Voltage Range VDD Operating 4.5 5.0 5.5 V
Under-Voltage Lockout VDD(UV) VDD = 0 5 V 3.4 – 4.0 V
Output Current IO V
CE = 0.7 V, REXT = 250 64.2 75.5 86.8 mA
(any single output) V
CE = 0.7 V, REXT = 470 34.1 40.0 45.9 mA
Output Current Matching ∆IO 0.4 V VCE(A) = VCE(B) 0.7 V:
(difference between any REXT = 250 – ±1.5 ±6.0 %
two outputs at same VCE) R
EXT = 470 – ±1.5 ±6.0 %
Output Leakage Current ICEX V
OH = 15 V – 1.0 5.0 μA
Logic Input Voltage VIH 0.7VDD – VDD V
V
IL GND – 0.3VDD V
SERIAL DATA OUT VOL I
OL = 500 μA – – 0.4 V
Voltage V
OH I
OH = -500 μA 4.6 – – V
Input Resistance RI ENABLE Input, Pull Up 150 300 600 k
LATCH Input, Pull Down 100 200 400 k
Supply Current IDD(OFF) R
EXT = open, VOE = 5 V – 0.8 1.4 mA
R
EXT = 470 Ω, VOE = 5 V 3.5 6.0 8.0 mA
R
EXT = 250 Ω, VOE = 5 V 6.5 11 15 mA
I
DD(ON) R
EXT = 470 , VOE = 0 V 7.0 13 20 mA
R
EXT = 250 , VOE = 0 V 10 22 32 mA
Typical Data is at VDD = 5 V and is for design information only.
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V,
REXT = 470 Ω, IO = 40 mA, VL = 3 V, RL = 65 Ω, CL = 10.5 pF.
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Propagation Delay Time tpHL CLOCK-OUTn – 350 1000 ns
LATCH-OUTn – 350 1000 ns
ENABLE-OUTn – 350 1000 ns
CLOCK-SERIAL DATA OUT – 40 – ns
Propagation Delay Time tpLH CLOCK-OUTn – 300 1000 ns
LATCH-OUTn – 300 1000 ns
ENABLE-OUTn – 300 1000 ns
CLOCK-SERIAL DATA OUT – 40 – ns
Output Fall Time tf 90% to 10% voltage 150 350 1000 ns
Output Rise Time tr 10% to 90% voltage 150 300 600 ns
RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Conditions Min. Typ. Max. Unit
Supply Voltage VDD 4.5 5.0 5.5 V
Output Voltage VO – 1.0 4.0 V
Output Current IO Continuous, any one output – – 90 mA
I
OH SERIAL DATA OUT – – -1.0 mA
I
OL SERIAL DATA OUT – – 1.0 mA
Logic Input Voltage VIH 0.7VDD – VDD + 0.3 V
V
IL -0.3 – 0.3VDD V
Clock Frequency fCK Cascade operation – – 10 MHz
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
Serial data present at the input is transferred to the shift
register on the logic 0-to-logic 1 transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data in-
formation towards the SERIAL DATA OUTPUT. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-to-
par al lel con ver sion). The latches continue to accept new data as
long as the LATCH ENABLE is held high. Ap pli ca tions where
the latches are bypassed (LATCH ENABLE tied high) will
require that the OUTPUT EN ABLE input be high during serial
data entry.
When the OUTPUT ENABLE input is high, the output sink
driv ers are disabled (OFF). The in for ma tion stored in the latches
is not affected by the OUTPUT ENABLE input. With the OUT-
PUT ENABLE input low, the outputs are con trolled by the state
of their re spec tive latches.
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ............................. 50 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ................................. 20 ns
C. Clock Pulse Width, tw(CK) .................................. 50 ns
D. Time Between Clock Ac ti va tion
and Latch Enable, tsu(L) ............................... 100 ns
E. Latch Enable Pulse Width, tw(L) ...................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................... 4.5 μs
NOTE: Timing is representative of a 10 MHz clock. Sig-
nif i cant ly higher speeds are attainable.
Max. Clock Transition Time, tr or tf ....................... 10 μs
CLOCK
SERIAL
DATA IN
LATCH
ENABLE
OUTPUT
ENABLE
OUTN
Dwg. WP-029-1
50%
SERIAL
DATA OUT
DATA
DATA
50%
50%
50%
C
A B
D E
LOW = ALL OUTPUTS ENABLED
p
t
DATA
50%
p
t
LOW = OUTPUT ON
HIGH = OUTPUT OFF
OUTPUT
ENABLE
OUT
N
Dwg. WP-030-1A
DATA
10%
50%
pHL
t
pLH
t
HIGH = ALL OUTPUTS DISABLED (BLANKED)
f
t
r
t
90%
F
50%
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE
WLE6726AAE6726A
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-11
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
V
CE
= 3 V
V
CE
= 4 V
80
T
A
= +25oC
V
DD
= 5 V
R
Q
JA
= 50oC/W
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-10
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
T
A
= +50oC
V
DD
= 5 V
R
Q
JA
= 50oC/W
V
CE
= 3 V
V
CE
= 4 V
80
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-6
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
V
CE
= 3 V
80
V
CE
= 4 V
T
A
= +25oC
V
DD
= 5 V
RQ
JA
= 75oC/W
VCE = 0.7 V
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-7
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
V
CE
= 3 V
80
T
A
= +50oC
V
DD
= 5 V
R
Q
JA
= 75oC/W
V
CE
= 0.7 V
V
CE
= 4 V
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-9
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
T
A
= +85oC
V
DD
= 5 V
R
QJA
= 50oC/W
V
CE
= 3 V
V
CE
= 0.7 V
V
CE
= 4 V
80
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
WLE6726AAE6726A
TYPICAL CHARACTERISTICS
0.5
Dwg. GP-063
1.0 2.0
1.5
V
CE
IN VOLTS
0
60
40
OUTPUT CURRENT IN mA/BIT
20
0
T
A
= +25oC
R
EXT
= 500 7
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-8
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
V
CE
= 3 V
80
T
A
= +85oC
V
DD
= 5 V
R
Q
JA
= 75oC/W
V
CE
= 4 V
V
CE
= 0.7 V
V
CE
= 0.4 V
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ALLOWABLE OUTPUT CURRENT AS A FUNC TION OF DUTY CYCLE (cont.)
A6276ELP
020
DUTY CYCLE IN PER CENT
100
0
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
=1V
V
CE
=2V
V
CE
=3V
V
CE
=4V
80
T
A
=+25ı°C
V
DD
=5V
R
ˇ
QJA
=40ı°C/W
020
DUTY CYCLE IN PER CENT
100
0
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
=1V
V
CE
=2V
T
A
=+50ı°C
V
DD
=5V
R
ˇ
QJA
=40ı°C/W
V
CE
=3V
V
CE
=4V
80
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The load current per bit (IO) is set by the external re sis tor
(REXT) as shown in the figure below.
300 500 700 1 k 2 k
CURRENT-CONTROL RESISTANCE, R EXT IN OHMS
100
0100
Dwg. GP-061
5 k
200 3 k
20
40
60
80
V
CE
= 0.7 V
Package Power Dissipation (PD). The maximum al-
low able package power dissipation is determined as
PD(max) = (150 - TA)/RJA.
The actual package power dissipation is
PD(act) = DC • (VCE • IO • 16) + (VDD • IDD) ,
where DC is the duty cycle.
When the load supply voltage is greater than 3 V to 5 V,
considering the package power dissipating limits of these
devices, or if PD(act) > PD(max), an external voltage re-
ducer (VDROP) should be used.
Load Supply Voltage (VLED). These devices are de-
signed to operate with driver voltage drops (VCE) of
0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to
4.0 V. If higher voltages are dropped across the driver,
package power dissipation will be increased significantly.
To minimize package power dissipation, it is rec om -
mend ed to use the lowest possible load supply voltage or
to set any series dropping voltage (VDROP) as
VDROP = VLED - VF - VCE
with VDROP = Io • RDROP for a single driver, or a Zener
diode (VZ), or a series string of diodes (approximately
0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
pro vide supply voltages as low as 3.3 V.
For reference, typical LED forward voltages are:
White 3.5 – 4.0 V
Blue 3.0 – 4.0 V
Green 1.8 – 2.2 V
Yellow 2.0 – 2.1 V
Amber 1.9 – 2.65 V
Red 1.6 – 2.25 V
Infrared 1.2 – 1.5 V
Pattern Layout. This device has a common logic-ground
and power-ground terminal. If ground pattern layout
con tains large common-mode resistance, and the voltage
between the system ground and the LATCH ENABLE or
CLOCK terminals ex ceeds 2.5 V (because of switching
noise), these devices may not operate correctly.
Dwg. EP-064
VLED
VDROP
VF
VCE
Applications Information
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package A, 24-pin DIP
2
0.018
1
24
A
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
For Reference Only
(reference JEDEC MS-001 BE)
Dimensions in millimeters
5.33 MAX
0.46 ±0.12
1.27 MIN
6.35 +0.76
–0.25
3.30 +0.51
–0.38
10.92 +0.38
–0.25
30.10 +0.25
–0.64
1.52 +0.25
–0.38
0.38 +0.10
–0.05
7.62
2.54
1.20 MAX
C
SEATING
PLANE
0.15 MAX
C0.10
24X
0.65
6.103.00
4.32
1.65
0.45
0.65
0.25
21
24
3.00
4.32
(1.00)
GAUGE PLANE
SEATING PLANE
B
A
ATerminal #1 mark area
B
For Reference Only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
PCB Layout Reference View
Exposed thermal pad (bottom surface)
C
C
7.80 ±0.10
4.40 ±0.10 6.40 ±0.20 0.60 ±0.15
4° ±4
0.25 +0.05
–0.06
0.15 +0.05
–0.06
Package A, 24-pin TSSOP
with exposed thermal pad
16-Bit Serial Input, Constant-Current
Latched LED Driver
A6276
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2000-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Package LW, 24-pin SOICW
1.27
BReference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
B
0.20 ±0.10
0.41 ±0.10
2.20
0.65
9.60
1.27
21
24
A
15.40±0.20
2.65 MAX
10.30±0.33
7.50±0.10
C
SEATING
PLANE
C0.10
24X
For Reference Only
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
0.25
GAUGE PLANE
SEATING PLANE PCB Layout Reference View
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
21
24
