EL8300 (R) Data Sheet May 20, 2005 200MHz Rail-to-Rail Amplifier Features The EL8300 represents a triple rail-to-rail amplifier with a 3dB bandwidth of 200MHz and slew rate of 200V/s. Running off a very low supply current of 2mA per channel, the EL8300 also features inputs that go to 0.15V below the VS- rail. * 200MHz -3dB bandwidth The EL8300 includes a fast-acting disable/power-down circuit. With a 25ns disable and a 200ns enable, the EL8300 is ideal for multiplexing applications. * Rail-to-rail output The EL8300 is designed for a number of general purpose video, communication, instrumentation, and industrial applications. The EL8300 is available in an 16-pin SO and 16-pin QSOP packages and is specified for operation over the -40C to +85C temperature range. Pinout FN7347.2 * 200V/s slew rate * Low supply current = 2mA per amplifier * Supplies from 3V to 5.5V * Input to 0.15V below VS* Fast 25ns disable * Low cost * Pb-Free pus Anneal available (RoHS compliant) Applications * Video amplifiers EL8300 (16-PIN SO, QSOP) TOP VIEW INA+ 1 CEA 2 16 INA+ VS- 3 CEB 4 14 VS+ + - INB+ 5 NC 6 CEC 7 15 OUTA + - INC+ 8 * Portable/hand-held products * Communications devices Ordering Information PART NUMBER PACKAGE TAPE & REEL PKG. DWG. # EL8300IS 16-Pin SO - MDP0027 13 OUTB EL8300IS-T7 16-Pin SO 7" MDP0027 12 INB- EL8300IS-T13 16-Pin SO 13" MDP0027 11 NC EL8300ISZ (See Note) 16-Pin SO (Pb-free) - MDP0027 EL8300ISZ-T7 (See Note) 16-Pin SO (Pb-free) 7" MDP0027 EL8300ISZ-T13 (See Note) 16-Pin SO (Pb-free) 13" MDP0027 EL8300IU 16-Pin QSOP - MDP0040 EL8300IU-T7 16-Pin QSOP 7" MDP0040 EL8300IU-T13 16-Pin QSOP 13" MDP0040 EL8300IUZ (See Note) 16-Pin QSOP (Pb-free) - MDP0040 EL8300IUZ-T7 (See Note) 16-Pin QSOP (Pb-free) 7" MDP0040 EL8300IUZ-T13 (See Note) 16-Pin QSOP (Pb-free) 13" MDP0040 10 OUTC 9 INC- NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL8300 Absolute Maximum Ratings (TA = 25C) Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to VS- -0.3V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = 5V, VS- = GND, TA = 25C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified DESCRIPTION CONDITIONS MIN TYP MAX UNIT -5 -0.8 +5 mV INPUT CHARACTERISTICS VOS Offset Voltage TCVOS Offset Voltage Temperature Coefficient Measured from TMIN to TMAX IB Input Bias Current VIN = 0V IOS Input Offset Current VIN = 0V TCIOS Input Bias Current Temperature Coefficient Measured from TMIN to TMAX CMRR Common Mode Rejection Ratio VCM = -0.15V to +3.5V CMIR Common Mode Input Range RIN Input Resistance CIN Input Capacitance AVOL Open Loop Gain -3 3 V/C -1.4 A 0.2 70 A 2 nA/C 90 dB VS- - 0.15 Common Mode 0.55 VS+ - 1.5 V 16 M 0.5 pF 90 dB VOUT = +1.5V to +3.5V, RL = 150 to GND 80 dB 30 m VOUT = +1.5V to +3.5V, RL = 1k to GND 75 OUTPUT CHARACTERISTICS ROUT Output Resistance AV = +1 VOP Positive Output Voltage Swing RL = 1k 4.85 4.88 V RL = 150 4.65 4.68 V VON Negative Output Voltage Swing RL = 150 150 200 mV RL = 1k 50 65 mV IOUT Linear Output Current 65 mA ISC (source) Short Circuit Current RL = 10 50 75 mA ISC (sink) Short Circuit Current RL = 10 90 130 mA VS+ = 4.5V to 5.5V 70 100 dB POWER SUPPLY PSRR Power Supply Rejection Ratio IS-ON Supply Current - Enabled per Amplifier 2 2.6 mA IS-OFF Supply Current - Disabled per Amplifier 40 90 A tEN Enable Time 200 ns tDS Disable Time 25 ns VIH-ENB ENABLE Pin Voltage for Power-up 0.8 V VIL-ENB ENABLE Pin Voltage for Shut-down 2 V ENABLE 2 EL8300 Electrical Specifications PARAMETER VS+ = 5V, VS- = GND, TA = 25C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT IIH-ENB ENABLE Pin Input Current High 8.6 A IIL-ENB ENABLE Pin Input for Current Low 0.01 A AV = +1, RF = 0, CL = 1.5pF 200 MHz AV = -1, RF = 1k, CL = 1.5pF 90 MHz AV = +2, RF = 1k, CL = 1.5pF 90 MHz AV = +10, RF = 1k, CL = 1.5pF 10 MHz AC PERFORMANCE BW -3dB Bandwidth BW 0.1dB Bandwidth AV = +1, RF = 0, CL = 1.5pF 20 MHz Peak Peaking AV = +1, RF = 1k, CL = 5pF 1 dB GBWP Gain Bandwidth Product 100 MHz PM Phase Margin RL = 1k, CL = 1.5pF 55 SR Slew Rate AV = 2, RL = 100, VOUT = 0.5V to 4.5V 200 V/s tR Rise Time 2.5VSTEP, 20% - 80% 8 ns tF Fall Time 2.5VSTEP, 20% - 80% 7 ns OS Overshoot 200mV step 10 % tPD Propagation Delay 200mV step 2 ns tS 0.1% Settling Time 200mV step 20 ns dG Differential Gain AV = +2, RF = 1k, RL = 150 0.035 % dP Differential Phase AV = +2, RF = 1k, RL = 150 0.05 eN Input Noise Voltage f = 10kHz 10 nV/Hz iN+ Positive Input Noise Current f = 10kHz 1 pA/Hz iN- Negative Input Noise Current f = 10kHz 0.8 pA/Hz eS Channel Separation f = 100kHz 95 dB 160 Pin Descriptions PIN NAME 1, 5, 8 INA+, INB+, INC+ Non-inverting input for each channel 2, 4, 7 CEA, CEB, CEC Enable and disable input for each channel 3 VS- Negative power supply 6, 11 NC Not connected 9, 12, 16 INC-, INB-, INA- 10, 13, 15 OUTC, OUTB, OUTA 14 VS+ 3 FUNCTION Inverting input for each channel Amplifier output for each channel Positive power supply EL8300 Typical Performance Curves GAIN (dB) 2 4 VS=5V AV=1 RL=1k CL=1.5pF 2 VOP-P=200mV GAIN (dB) 4 0 VOP-P=1V -2 -6 100K 1M 10M RL=330 0 RL=1k -2 RL=100 VOP-P=2V -4 VS=5V AV=1 CL=1.5pF -4 100M -6 100K 1G 1M 10M FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGE LEVELS FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS RLOAD 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 2 AV=1 AV=2 0 -2 AV=5 -4 AV=10 -6 100K 1M 10M 100M 2 VS=5V RL=1k CL=1.5pF RF=1k AV=-2 -2 AV=-10 -4 -6 100K 1G AV=-5 0 1M FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS NON-INVERTING GAINS 100M 1G FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS INVERTING GAINS 14 5 CL=10pF -12 3 CL=7pF 10 1 CL=5pF CL=1.5pF -1 1M 6 -4 -2 4 10M 100M 1G FREQUENCY (Hz) FIGURE 5. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS CL 4 CL=15pF 2 0 VS=5V AV=1 RL=1k VOP-P=200mV -5 100K CL=56pF CL=35pF -8 GAIN (dB) GAIN (dB) 10M FREQUENCY (Hz) FREQUENCY (Hz) -3 1G FREQUENCY (Hz) FREQUENCY (Hz) VS=5V RL=1k CL=1.5pF 100M VS=5V AV=2 RL=1k RF=RG=1k -6 100K 1M CL=1.5pF 10M 100M 1G FREQUENCY (Hz) FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS CL EL8300 Typical Performance Curves (Continued) 10 110 8 RF=RG=500 2 VS=5V AV=2 RL=1k CL=1.5pF 0 100K 30 225 RL=150 -10 RL=1k -50 1M 10M 100M 1G 135 -90 1K 10K 45 100K FREQUENCY (Hz) 1M 230 -30 190 BANDWIDTH (MHz) 210 CMRR (dB) 100M -45 1G FIGURE 8. OPEN LOOP GAIN AND PHASE vs FREQUENCY -10 -50 -70 -90 AV=1 170 150 130 110 90 RL=1k CL=1.5pF 70 50 1M 10M FREQUENCY (Hz) FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS RF AND RG -110 100K PHASE () 6 4 315 RL=150 GAIN (dB) GAIN (dB) 70 RF=RG=1k RF=RG=2k 405 RL=1k 10M 100M 3 3.5 AV=2 4.5 4 5 5.5 VS (V) FREQUENCY (Hz) FIGURE 9. COMMON-MODE REJECTION RATIO vs FREQUENCY FIGURE 10. SMALL SIGNAL BANDWIDTH vs SUPPLY VOLTAGE 2.5 100 PEAKING (dB) IMPEDANCE () 2 10 1 0.1 0.01 10K 1.5 1 AV=1 RL=1k CL=1.5pF 0.5 0 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY 5 3 3.5 4 4.5 5 5.5 VS (V) FIGURE 12. SMALL SIGNAL PEAKING vs SUPPLY VOLTAGE EL8300 -10 -45 -30 -55 DISTORTION (dBc) PSRR (dB) Typical Performance Curves (Continued) PSRR- -50 -70 PSRR+ VS=5V RL=1k CL=1.5pF AV=2 HD2 MHz @10 HD3 Hz HD3@5M -65 -75 HD2@5MH z HD2@ -85 -90 MH z @10 1MHz HD3@1MHz -95 -110 1K 10K 100K 1M 10M 100M 2 1 3 -30 VS=5V AV=1 RL=1k CL=1.5pF VS=5V RL=1k VO=1VP-P for AV=1 VO=2VP-P for AV=2 -40 DISTORTION (dBc) GAIN (dB) -30 -50 -70 -90 -50 -60 =2 AV 2@ D H -70 -80 3@ HD -90 -100 -110 1K 100K 10K 1M 10M 100M 1G 2 AV= 1 40 10 FIGURE 16. HARMONIC DISTORTION vs FREQUENCY -60 1K HD 3@ -70 -75 HD -80 AV = 2 HD2@A =1 V 3@ A V= AV =2 VOLTAGE NOISE (nV/Hz) CURRENT NOISE (pA/Hz) H D 2@ -65 DISTORTION (dBc) =1 AV FREQUENCY (MHz) FIGURE 15. DISABLED OUTPUT ISOLATION FREQUENCY RESPONSE 1 -85 -95 2@ HD HD3@AV=1 FREQUENCY (Hz) -90 5 FIGURE 14. HARMONIC DISTORTION vs OUTPUT VOLTAGE FIGURE 13. POWER SUPPLY REJECTION RATIO vs FREQUENCY -10 4 VOP-P (V) FREQUENCY (Hz) VS=5V VO=1VP-P for AV=1 VO=2VP-P for AV=2 -100 100 1K 2K RLOAD () FIGURE 17. HARMONIC DISTORTION vs LOAD RESISTANCE 6 100 eN 10 IN+ 1 IN0.1 10 100 1K 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 18. VOLTAGE AND CURRENT NOISE vs FREQUENCY EL8300 Typical Performance Curves (Continued) VS=5V, AV=1, RL=1k to 2.5V CHANNELL SEPARATION (dB) -10 -20 -30 5 -40 -50 -60 2.5 CH1<=>CH2 CH2<=>CH3 -70 -80 CH1<=>CH3 0 -90 -100 100K 1M 10M 100M 1G 10ns/DIV FREQUENCY (Hz) FIGURE 19. CHANNEL SEPARATION vs FREQUENCY FIGURE 20. LARGE SIGNAL TRANSIENT RESPONSE VS=5V, AV=1, RL=1k to 2.5V CL=1.5pF VS=5V, AV=5, RL=1k to 2.5V 5 2.6 2.5 2.5 2.4 0 10ns/DIV 2s/DIV FIGURE 21. OUTPUT SWING FIGURE 22. SMALL SIGNAL TRANSIENT RESPONSE VS=2.5V, AV=1, RL=1k VS=5V, AV=5, RL=1k to 2.5V 5 CH1 ENABLE INPUT 2.5 CH2 0 2s/DIV FIGURE 23. OUTPUT SWING 7 OUTPUT CH1, CH2, 0.5V/DIV, M=20ns FIGURE 24. DISABLED RESPONSE EL8300 Typical Performance Curves (Continued) JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD VS=2.5V, AV=1, RL=1k CH1 POWER DISSIPATION (W) 1.2 ENABLE INPUT CH2 VOUT 1 0.8 0.6 633mW 0.4 J 0.2 0 CH1, CH2, 1V/DIV, M=100ns SO 1 JA 6 ( 0 =1 . 10 150 C ") /W 909mW 0 25 QS A= OP 16 15 8 C/ W 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) FIGURE 25. ENABLED RESPONSE POWER DISSIPATION (W) 1.4 FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 1.250W SO JA 1 0.8 893mW 0.6 JA 0.4 QS =1 OP 12 C 16 (0 .1 =8 0 50" ) C/ W 16 /W 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 8 EL8300 Simplified Schematic Diagram VS+ I1 I2 Q5 IN+ Q1 R8 VBIAS1 Q6 R3 R1 R7 R6 Q7 R2 Q2 DIFFERENTIAL TO SINGLE ENDED DRIVE GENERATOR IN- VBIAS2 Q3 OUT Q4 Q8 R4 R5 R9 VS- Description of Operation and Application Information Product Description The EL8300 is wide bandwidth, single supply, low power and rail-to-rail output voltage feedback operational amplifier. The amplifiers are internally compensated for closed loop gain of +1 of greater. Connected in voltage follower mode and driving a 1k load, the EL8300 has a -3dB bandwidth of 200MHz. Driving a 150 load, the bandwidth is about 130MHz while maintaining a 200V/us slew rate. The EL8300 is available with a power down pin for each channel to reduce power to 30A typically while the amplifier is disabled. Input, Output and Supply Voltage Range The EL8300 has been designed to operate with a single supply voltage from 3V to 5.0V. Split supplies can also be used as long as their total voltage is within 3V to 5.0V. The amplifiers have an input common mode voltage range from 0.15V below the negative supply (VS- pin) to within 1.5V of the positive supply (VS+ pin). If the input signal is outside the above specified range, it will cause the output signal to be distorted. The output of the EL8300 can swing rail to rail. As the load resistance becomes lower, the ability to drive close to each rail is reduced. For the load resistor 1k, the output swing is about 4.9V at a 5V supply. For the load resistor 150, the output swing is about 4.6V. Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +1, no feedback resistor is required. Just short the output pin to the inverting input pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting 9 input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. As far as the output stage of the amplifier is concerned, the output stage is also a gain stage with the load. RF and RG appear in parallel with RL for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum performance. For gain of +1, RF=0 is optimum. For the gains other than +1, optimum response is obtained with RF between 300 to 1k. The EL8300 has a gain bandwidth product of 100MHz. For gains 5, its bandwidth can be predicted by the following equation: Gain x BW = 100MHz Video Performance For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150, because the change in output current with DC level. Special circuitry has been incorporated in the EL8300 to reduce the variation of the output impedance with the current output. This results in dG and dP specifications of 0.03% and 0.05, while driving 150 at a gain of 2. Driving high impedance loads would give a similar or better dG and dP performance. EL8300 Driving Capacitive Loads and Cables The EL8100, EL8101 can drive 10pF loads in parallel with 1k with less than 5dB of peaking at gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with the output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing: 3 When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. For sinking: Disable/Power-Down Where: The EL8300 can be disabled and placed its output in a high impedance state. The turn off time for each channel is about 25ns and the turn on time is about 200ns. When disabled, the amplifier's supply current is reduced to 30A typically, thereby effectively eliminating the power consumption. The amplifier's power down can be controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS- pin. Letting the ENABLE pin float or applying a signal that is less than 0.8V above VS- will enable the amplifier. The amplifier will be disabled when the signal at ENABLE pin is 2V above VS-. Output Drive Capability The EL8300 does not have internal short circuit protection circuitry. They have a typical short circuit current of 70mA sourcing and 140mA sinking for the output is connected to half way between the rails with a 10 resistor. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds 40mA. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the EL8300, it is possible to exceed the 125C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX - T AMAX PD MAX = ------------------------------------------- JA 10 PD MAX = V S x I SMAX + V OUTi ( VS - VOUTi ) x ---------------R Li i=1 3 PD MAX = V S x I SMAX + ( VOUTi - VS - ) x ILOADi i=1 VS = Total supply voltage ISMAX = Maximum quiescent supply current VOUTi = Maximum output voltage of the application for each channel RLOADi = Load resistance tied to ground for each channel ILOADi = Load current for each channel By setting the two PDMAX equations equal to each other, we can solve the output current and RLOADi to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. EL8300 Typical Applications VIDEO SYNC PULSE REMOVER +2.5V Many CMOS analog to digital converters have a parasitic latch up problem when subjected to negative input voltage levels. Since the sync tip contains no useful video information and it is a negative going pulse, we can chop it off. Figure 28 shows a gain of 2 connections for EL8300. Figure 29 shows the complete input video signal applied at the input, as well as the output signal with the negative going sync pulse removed. B 2MHz 1VP-P + 75 -2.5V 1K 1K VOUT +2.5V A 2MHz 2VP-P 75 + - 75 -2.5V MULTIPLEXER Besides the normal power down usage, the ENABLE pin of the EL8300 can be used for multiplexing applications. Figure 30 shows two channels with the outputs tied together, driving a back terminated 75 video load. A 2VP-P 2MHz sine wave is applied to Amp A and a 1VP-P 2MHz sine wave is applied to Amp B. Figure 31 shows the ENABLE signal and the resulting output waveform at VOUT. Observe the break-before-make operation of the multiplexing. Amp A is on and VIN1 is passed through to the output when the ENABLE signal is low and turns off in about 25ns when the ENABLE signal is high. About 200ns later, Amp B turns on and VIN2 is passed through to the output. The break-beforemake operation ensures that more than one amplifier isn't trying to drive the bus at the same time. 75 1K 1K ENABLE FIGURE 30. TWO TO ONE MULTIPLEXER 0V -0.5V ENABLE -1.5V -2.5V 1V 0V 5V VIN + - 75 1K -1V VOUT VS- 75 B A 75 VS+ M = 50ns/DIV FIGURE 31. ENABLE SIGNAL 1K SINGLE SUPPLY VIDEO LINE DRIVER FIGURE 28. SYNC PULSE REMOVER 1V 0.5V VIN 0V 1V 0.5V VOUT 0V M = 10s/DIV FIGURE 29. VIDEO SIGNAL 11 The EL8300 is wideband rail-to-rail output op amplifiers with large output current, excellent dG, dP, and low distortion that allow them to drive video signals in low supply applications. Figure 32 is the single supply non-inverting video line driver configuration and Figure 33 is the inverting video ling driver configuration. The signal is AC coupled by C1. R1 and R2 are used to level shift the input and output to provide the largest output swing. RF and RG set the AC gain. C2 isolates the virtual ground potential. RT and R3 are the termination resistors for the line. C1, C2 and C3 are selected big enough to minimize the droop of the luminance signal. EL8300 5V VIN C1 47F R1 10K R3 C3 470F 75 + RT 75 VOUT - R2 10K 75 RF 1k RG 1k C2 220F FIGURE 32. 5V SINGLE SUPPLY NON INVERTING VIDEO LINE DRIVER RF 1k VIN C1 RG 47F 500 5V RT 75 5V - R3 C3 470F 75 VOUT + R1 10K R2 10K 75 C2 220F FIGURE 33. 5V SINGLE SUPPLY INVERTING VIDEO LINE DRIVER 5 NORMALIZED GAIN (dB) 4 3 2 1 AV = 2 0 AV = -2 -1 -2 -3 -4 -5 100K 1M 10M FREQUENCY (Hz) 100M 200M FIGURE 34. VIDEO LINE DRIVER FREQUENCY RESPONSE 12 EL8300 SO Package Outline Drawing 13 EL8300 QSOP Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14