Supertex inc. TC7920 Two Pair, N- and P-Channel Enhancement-Mode MOSFET with Drain-Diodes Features General Description High voltage Vertical DMOS technology Integrated drain output high voltage diodes Integrated gate-to-source resistor Integrated gate-to-source Zener diode Low threshold, Low on-resistance Low input & output capacitance Fast switching speeds Electrically isolated N- and P-MOSFET pairs The Supertex TC7920 consists of two pairs of high voltage, low threshold N-channel and P-channel MOSFETs in a 12-Lead DFN package. All MOSFETs have integrated the output drain high voltage diodes, gate-to-source resistors and gate-to-source Zener diode clamps which are desired for high voltage pulser applications. The complimentary, high-speed, high voltage, gateclamped N and P-channel MOSFET pairs utilize an advanced vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Applications High voltage pulsers Amplifiers Buffers Piezoelectric transducer drivers General purpose line drivers Logic level interfaces Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. Supertex's vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input and output capacitance, and fast switching speeds are desired. Typical Application Circuit VPP +100V +10V 0.47F 0.1F ENAB +PULSE 1.8 to 5.0V Logic Imputs -PULSE DAMP OE VDD VH OUTA INA VNN -100V OUTB INB OUTC INC 1.0F OUTD IND GND 1.0F VL VSS Supertex MD1822 10nF Supertex TC7920 Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com TC7920 Ordering Information Device TC7920 4.00x4.00mm body 1.0mm height (max) 0.50mm pitch RDS(ON) BVDSS/BVDGS 12-Lead DFN (max) () (V) N-Channel P-Channel N-Channel P-Channel 200 -200 7.0 8.0 TC7920K6-G -G indicates package is RoHS compliant (`Green') Pin Configuration Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Operating and storage temperature Soldering temperature* -55C to +150C +300C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. GN1 1 12 SN1 11 DN1 10 DP1 9 SP1 GP1 2 GN2 3 SN2 4 GP2 5 8 DN2 SP2 6 7 DP2 Thermal Pad 12-Lead DFN (K6) (top view) Package Marking C7920 YWLL Y = Last Digit of Year Sealed W = Code for Week Sealed L = Lot Number = "Green" Packaging Package may or may not include the following marks: Si or 12-Lead DFN (K6) Thermal Characteristics Package Value 12-Lead DFN (K6) ja = 42OC/W Note: 1.0oz, 4-layer, 3"x4" PCB. Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 2 TC7920 N-Channel Electrical Characteristics (T = 25C unless otherwise specified) A Sym Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 2.0mA VGS(th) Gate threshold voltage 1.0 - 2.0 V VGS = VDS, ID = 1.0mA - - -4.5 mV/OC VGS = VDS, ID = 1.0mA VGS(th) Change in VGS(th) with temperature Conditions RGS Gate-to-source shunt resistor 10 - 50 K IGS = 100A VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = 2.0mA - - 10.0 A VDS = Max rating, VGS = 0V - - 1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC 1.0 - - 2.0 - - - - 8.0 - - 7.0 - - 1.0 %/OC VGS = 4.5V, ID =150mA 400 - - mmho VDS = 25V, ID = 500mA IDSS Zero gate voltage drain current ID(ON) On-state drain current RDS(ON) Static drain-to-source on-state resistance RDS(ON) Change in RDS(ON) with temperature GFS Forward transconductance CISS Input capacitance - 52 - COSS Common source output capacitance - 6.9 - CRSS Reverse transfer capacitance - 1.3 - td(ON) Turn-on delay time - - 10 Rise time - - 15 Turn-off delay time - - 20 Fall time - - 15 Diode forward voltage drop - - Reverse recovery time - 300 tr td(OFF) tf VSD trr A VGS = 4.5V, VDS = 25V VGS = 10V, VDS = 25V VGS = 4.5V, ID = 150mA VGS = 10V, ID = 1.0A pF VGS = 0V, VDS = 25V, f = 1.0MHz ns VDD =25V, ID = 1.0A, RGEN = 25 1.8 V VGS = 0V, ISD = 500mA - ns VGS = 0V, ISD = 500mA Notes: 1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. N-Channel Switching Waveforms and Test Circuit 10V VDD 90% INPUT 0V 10% t(OFF) t(ON) td(ON) VDD Pulse Generator tr 10% td(OFF) RGEN tf 10% RL OUTPUT D.U.T INPUT OUTPUT 0V Supertex inc. 90% 90% 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 3 TC7920 P-Channel Electrical Characteristics (T = 25C unless otherwise specified) A Sym Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -2.0mA VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID = -1.0mA - - 4.5 mV/OC VGS = VDS, ID = -1.0mA VGS(th) Change in VGS(th) with temperature Conditions RGS Gate-to-source shunt resistor 10 - 50 K IGS = 100A VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = -2.0mA - - -10 A VDS = Max rating, VGS = 0V - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC -1.0 - - -2.0 - - - - 10 - - 8.0 - - 1.0 %/OC VGS = -10V, ID =-200mA 400 - - mmho VDS = -25V, ID = -500mA IDSS Zero gate voltage drain current ID(ON) On-state drain current RDS(ON) RDS(ON) Static drain-to-source on-state resistance Change in RDS(ON) with temperature GFS Forward transconductance CISS Input capacitance - 54 - COSS Common source output capacitance - 7.5 - CRSS Reverse transfer capacitance - 2.6 - td(ON) Turn-on delay time - - 10 Rise time - - 15 Turn-off delay time - - 20 Fall time - - 15 Diode forward voltage drop - - Reverse recovery time - 300 tr td(OFF) tf VSD trr A VGS = -4.5V, VDS = -25V VGS = -10V, VDS = -25V VGS = -4.5V, ID = -150mA VGS = -10V, ID = -1.0A pF VGS = 0V, VDS = -25V, f = 1.0MHz ns VDD = -25V, ID = -1.0A, RGEN = 25 -1.8 V VGS = 0V, ISD = -500A - ns VGS = 0V, ISD = -500A Notes: 1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. P-Channel Switching Waveforms and Test Circuit 0V 10% Pulse Generator INPUT -10V 90% td(ON) 0V RGEN D.U.T t(OFF) t(ON) td(OFF) tr 90% tf Input OUTPUT 90% RL OUTPUT VDD Supertex inc. 10% 10% VDD 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 4 TC7920 Drain Output Diodes Sym Parameter Min Typ Max Unit Condition VR Breakdown voltage 200 - - V IR = 100A VF Forward voltage - 1.25 - V IF = 100mA IFM Park forward current - 3.0 - A Pulse width = 1.0s, D% = 1%, One diode IR Reverse current - 1.0 - - 100 - trr Reverse recovery time - 1.0 - A s VR = 100 V, TA = 25OC VR = 100 V, TA = 125OC IF = IR = 10mA, IRR = 1.0 mA, RL = 100 Pin Description Pin # Function 1 GN1 2 Pin # Function Gate of N-MOSFET 1 7 DP2 Drain of P-MOSFET 2 GP1 Gate of P-MOSFET 1 8 DN2 Drain of N-MOSFET 2 3 GN2 Gate of N-MOSFET 2 9 SP1 Source of P-MOSFET 1 4 SN2 Source of N-MOSFET 2 10 DP1 Drain of P-MOSFET 1 5 GP2 Gate of P-MOSFET 2 11 DN1 Drain of N-MOSFET 1 6 SP2 Source of P-MOSFET 2 12 SN1 Source of N-MOSFET 1 Thermal Pad Description Description Die attachment substrate, must be grounded externally Note: Thermal Pad must be grounded. Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 5 TC7920 12-Lead DFN Package Outline (K6) 4.00x4.00mm body, 1.00mm height (max), 0.50mm pitch D 12 D2 12 E E2 Note 1 (Index Area D/2 x E/2) 1 View B Top View 1 e b Note 1 (Index Area D/2 x E/2) Bottom View Note 3 A A3 L Seating Plane L1 Note 2 A1 View B Side View Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 e 0.18 3.85 3.19 3.85 2.29 0.25 4.00 3.34 4.00 2.44 0.30 4.15 3.44 4.15 2.54 0.50 BSC L L1 0.30 0.00 0O 0.40 - - 0.50 0.15 14O Drawings not to scale. Supertex Doc.#: DSPD-12DFNK64X4P050, Version A030210. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate "product liability indemnification insurance agreement." Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. (c)2010 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-TC7920 A121010 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 6