Document Number: MC34830
Rev. 1.0, 9/2008
Freescale Semiconductor
Product Preview
© Freescale Semiconductor, Inc., 2008. All rights reserved.
*This document contains certain information on a product under development. Free-
scale reserves the right to change or discontinue this product without notice
HD to SD Adjustable Bandwidth
Video Buffer with DC Restore
The 34830 is a very high performance video buffer that can handle
HDTV bandwidths up to 1080p resolution. The integrated input clamp
works with all sync formats and all types of video signals. The 34830
includes an innovative capability to set the bandwidth to the optimum
trade-off of performance versus power dissipation. It can be adjusted
all the way from HD frequencies to SD frequencies while benefiting
from the lower power dissipation with lower bandwidths.
The 34830 can drive two standard video loads which are DC or AC
coupled. Input signals can be DC or AC coupled. For the DC coupled
case, the input sync should be close to ground. The 34830 can be
disabled, with shutdown current being 0.12μA.
The 34830 is offered in an ultra thin UDFN package for space critical
applications. It operates on a single 3.0 to 5.5V supply over a -40°C to
85°C temperature range.
Features
• 1080p / UXGA to 480i / VGA video buffer with 6dB gain
• Integrated input clamp
• Adjustable BW to save power
• Handles CV, Y, C, Pb, Pr, R, G, B signals
• Drives two video loads
• Single supply operation
• 3.0 to 5.5V range
• Rail to rail output
• 0.3% dG / 0.3% dθ for SD
• 0.6% THD for HD
•0.12μA shutdown current
• Ultra thin UDFN package
• Pb-free packaging designated by suffix code EP
Applications
• Cellular phones
• DVD players
• Portable Game Players, Set-top boxes
• Laptop PCs, Desktop PCs,
• Projectors, Digital Cameras, Camcorders, Portable
Media Players, Security Systems
Figure 1. 34830 Simplified Application Diagram
HD VIDEO BUFFER IC
EP SUFFIX (PB-FREE)
98ASA10819D
6-PIN UDFN
34830
ORDERING INFORMATION
Device Temperature
Range (TA)Package
PC34830EP/R2 -40°C to 85°C 6-UDFN
Bottom
View
34830
VCC
IN
ENABLE
OUT
RFREQ
GND
Video cable
Analog Integrated Circuit Device Data
2Freescale Semiconductor
34830
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
Figure 2. 34830 Simplified Internal Block Diagram
Bias
Bandwidth
Adjust
0dB 6dB
VCLAMP
250mV
Levelshift
ENABLE
OUT
RFREQ
GND
IN
VCC
Analog Integrated Circuit Device Data
Freescale Semiconductor 3
34830
PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. 34830 Pin Connections
Table 1. 34830 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number Pin Name Pin Function Formal Name Definition
1VCC Power VCC Supply voltage input
2IN Input Video Input Video Input
3GND Ground Ground Ground return for the IC
4RFREQ Passive Frequency Bandwidth
Set
Connection for the resistor to GND to set operating bandwidth
5OUT Output Video Output Video output
6EN Input Enable Low = device disabled; High = device enabled
EP -Passive Exposed Pad Exposed pad for thermal dissipation. Connect the EP to GND or leave
floating. The EP is electrically connected to ground.
6
5
4
1
2
3
Transparent
Top View
VCC
IN
GND
EN
OUT
RFREQ
Analog Integrated Circuit Device Data
4Freescale Semiconductor
34830
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings Symbol Value Unit
ELECTRICAL RATINGS
Maximum Pin Voltage (Except as below)
All other pins -0.3V to Vcc + 0.3V
VCC 6.0 V
Maximum Current (into any pin) ±100 mA
THERMAL RATINGS
Ambient Temperature Range TA-40 to 85 °C
Operating Junction Temperature TJ-40 to 125 °C
Maximum Junction Temperature TJMAX 150 °C
Storage Temperature Range TSTORE -40 to 150 °C
Power Dissipation (UDFN package with EP soldered to ground plane)
TA = 25°C
TA = 70°C
1790
1140
W
Thermal Resistance (6-LD UDFN)
θJA
θJC
70
10
°C/W
Peak Package Soldering Temperature During Reflow(2),(3) TPPRT 260 °C
Notes
1. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100pF, RZAP = 1500Ω), the Machine Model (MM)
(CZAP = 200pF, RZAP = 0Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF).
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
3. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
Analog Integrated Circuit Device Data
Freescale Semiconductor 5
34830
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions VCC = 3.0V to 5.5V, TA = -40°C to 85°C, RFREQ = 9.0kΩ, CIN = 0.1μF, RL = 150Ω, CL
= 5.0pF. Typical values are at TA = 27°C, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Input Voltage Range (inferred from gain)
VCC = 3V TO 3.4V
VCC = 3.4V TO 5.5V
VINP
VINPCLAMP
VINPCLAMP
-
-
(VCC-1)/2
1.2
V
Input Clamping Level(4) VINPCLAMP -50 0+50 mV
Output Clamping Level(5) VOUTCLAMP 400 500 600 mV
Frequency Set Resistor Range RFREQ 9.0 -108 kΩ
Supply Current measured with no load
RFREQ = 108kΩ
RFREQ = 9kΩ
ICC
-
-
4.5
17
8
23
mA
Supply Current in Shutdown Mode (EN = 0.0V) ICCSHUTDOWN -0.12 5.0 μA
Output Short-circuit Current (Output shorted to VCC or ground for <1s) ISC -100 -mA
Input Leakage Current (VINP = 1.0V) IINP -2.0 5.0 μA
Line-Time Distortion (100 IRE, 18μs) HDIST -0.1 0.2 %
Field-Time Distortion (100 IRE, 18μs, field lines) VDIST -0.2 0.4 %
Logic Low Input Voltage VIL - - 0.3(VCC) V
Logic High Input Voltage VIH 0.7(VCC) - - V
Logic Level Input Current (source and sink) IILH - - |1.0| μA
Notes
4. Referenced to input. Input clamp not active for signals C, Pb, Pr, U, and V.
5. Establishes output sync level.
Analog Integrated Circuit Device Data
6Freescale Semiconductor
34830
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
Plots are taken under conditions VCC = 4.0V, RFREQ = 9.0kΩ, RL =150Ω, TA = 27°C, unless otherwise noted.
Figure 4. Frequency Response Magnitude
Figure 5. -1dB Bandwidth vs. RFREQ (kΩ)
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions VCC = 3.0V to 5.5V, TA = -40°C to 85°C, RFREQ = 9.0kΩ, CIN = 0.1μs, RL =150Ω, CL
= 5.0pF. Typical values are at TA = 27°C, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
Low Frequency Gain (@100kHz) A1.9 2.0 2.1 V/V
Small-signal 1.0 dB Bandwidth
RFREQ = 108kΩ
RFREQ = 9kΩ)
BW1SS
25
85
37
130
MHz
Differential Gain (3-step measurement, RFREQ = 108kΩ, f = 4.0MHz)dG -0.3 1.0 %
Differential Phase (3-step measurement, RFREQ = 108kΩ, f = 4.0MHz)dθ-0.3 1.0 deg
Total Harmonic Distortion (VIN = 0.65V + 700mVP-P , 60MHz sine wave) THD -0.65 - %
DC Group Delay (at 100kHz) tG-2.8 -ns
Group Delay Deviation (f = 100kHz to 60 MHz) ΔtG-0.5 -ns
Slew Rate (VOUT = 2V step) SR -450 -V/μs
Settling Time to 10% (VOUT = 2VPP)tS-4.0 -ns
Peak Signal to Noise Ratio (VOUT = 2.0Vp-p, f=100Hz to 200 MHz) SNR 58 65 -dB
Power Supply Rejection (Measured at 100kHz with 100mVpp sinewave ripple
on VCC.)
PSR -40 -dB
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
0.1 1 10 100 1000
FREQUENCY (M Hz)
FREQUENCY RESPONSE MAGNITUDE (dB
RFREQ=9kΩ
RFREQ=108kΩ
FREQUENCY (MHz)
FREQUENCY RESPONSE MAGNITUDE (dB)
25
35
45
55
65
75
85
95
105
115
125
135
145
0 102030405060708090100110120
RFREQ, BANDWIDTH SETTING RESISTOR (k)
-1dB BANDWIDTH (MHz)
RFREQ, BANDWIDTH SETTING RESISTOR (kΩ)
-1dB BANDWIDTH (MHz)
Analog Integrated Circuit Device Data
Freescale Semiconductor 7
34830
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
Figure 6. Supply Current vs. RFREQ (kΩ)
Figure 7. DC Output Voltage vs. Input Voltage
Figure 8. Supply Current vs. Temperature
Figure 9. No Load Supply Current vs. Supply Voltage
Figure 10. Channel DC Shift vs. Temperature
Figure 11. Sinusoidal Wave Response (External
resistors setting clamp level to 0.5V, VCC= 3V, RFREQ =
108kΩ for 5MHz sine input.)
4
6
8
10
12
14
16
18
20
0 2040 6080100120
RFR E Q , BANDWIDTH SETTING RESISTOR (k )
RFREQ, BANDWIDTH SETTING RESISTOR (kΩ)
ICC, SUPPLY CURRENT (mA)
0
0.5
1
1.5
2
2.5
3
3.5
4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
VIN, INPUT VOLTAGE (V)
VOUT, OUTPUT VOLTAGE (V)
RFREQ=9kΩ
RFREQ=108k Ω
VIN, INPUT VOLTAGE (V)
VOUT, OUTPUT VOLTAGE (V)
0
2
4
6
8
10
12
14
16
18
20
-40 -27.5 -15 -2.5 10 22.5 35 47.5 60 72.5 85
T, TEM PERATURE (°C)
ICC, NO LOAD SUPPLY CURRENT (mA
)
RFREQ = 108kΩ
RFREQ = 9kΩ
T, TEMPERATURE (°C)
ICC, NO LOAD SUPPLY CURRENT (mA)
0
2
4
6
8
10
12
14
16
18
20
33.5 44.5 55.5
VCC, SUPPLY VOLTAGE (V)
ICC, SUPPLY CURRENT (mA)
RFREQ = 9kΩ
RFREQ = 108kΩ
VCC, SUPPLY VOLTAGE (V)
0.5
0.503
0.506
0.509
0.512
0.515
0.518
0.521
0.524
0.527
0.53
-40 -27.5 -15 -2.5 10 22.5 35 47.5 60 72.5 85
T, TEM PERATURE (C)
VOS, CHANNEL DC SHIFT (V)
RFREQ = 108kΩ
RFREQ = 9kΩ
T, TEMPERATURE (°C)
VOS, CHANNEL DC SHIFT (V)
Time (80ns/div)
Voltage (500mV/div)
Inp ut
Output
gnd
gnd
Set to 0.5V by key clamp
Set to 1.5V
TIME (80ns/DIV)
VOLTAGE (500mV/DIV)
Analog Integrated Circuit Device Data
8Freescale Semiconductor
34830
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
Figure 12. 480i Signal (RFREQ = 108kΩ)
Figure 13. 480i 2T and Modulated 12.5T Response
(RFREQ = 108kΩ)
Figure 14. 480i Vertical/Horizontal Sync Levels (RFREQ =
108kΩ)
Figure 15. 1080i Signal
Figure 16. 1080i 2T Response
Figure 17. 1080i Vertical/Horizontal Sync Levels
Time (95μs/div)
Voltage (500mV/div)
gnd
Input
Output
Set to 0 V by Sync tip clamp
Set to 0.5 V
gnd
TIME (9.5μs/DIV)
VOLTAGE (500mV/DIV)
Time (700ns/div)
Voltage (500mV/div)
gnd
gnd
Input
Output
TIME (700ns/DIV)
VOLTAGE (500mV/DIV)
TIME (0.6ms/div)
VOLTAGE (200mV/div
)
INPUT
OUTPUT
gnd
gnd
TIME (0.6ms/DIV)
VOLTAGE (200mV/DIV)
Time (34μs/div)
Voltage (500mV/div)
gnd
gnd
Input
Output
Set to 0.5 V
Set to 0 V by Sync tip clamp
TIME (3.4μs/DIV)
VOLTAGE (500mV/DIV)
Time (25ns/div)
Voltage (500mV/div)
gnd
gnd
Input
Output
VOLTAGE (500mV/DIV)
TIME (25ns/DIV)
TIME (0.8ms/div)
VOLTAGE (200mV/div
)
INPUT
OUTPUT
gnd
gnd
VOLTAGE (200mV/DIV)
TIME (0.8ms/DIV)
Analog Integrated Circuit Device Data
Freescale Semiconductor 9
34830
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
Figure 18. Differential Gain (RFREQ = 108kΩ, measured
at 4.0MHz)
Figure 19. Differential Phase (RFREQ = 108kΩ, measured
at 4MHz)
Figure 20. Group Delay Response
Figure 21. DC PSR vs. Supply Voltage
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0123456
STEPS FROM 0.3V TO 1V (140mV/STEP)
dG, DIFFERENTIAL GAIN (%
)
dG, DIFFERENTIAL GAIN (%)
STEPS FROM 0.3 to 1.0V (140mV/STEP)
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0123456
STEPS FROM 0.3V TO 1V (140mV/STEP)
d, DIFFERENTIAL PHASE (deg)
dθ, DIFFERENTIAL PHASE (DEG)
STEPS FROM 0.3 to 1.0V (140mV/STEP)
1
2
3
4
5
6
7
8
0.1 1 10 100 1000
Frequency (MHz)
Group Delay (ns)
RFREQ = 108kΩ
GROUP DELAY (ns)
FREQUENCY (MHz)
-70
-60
-50
-40
-30
-20
-10
0
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
VCC, SUPPLY VOLTAGE (V)
DC PSR (dB)
RFREQ = 9kΩ
RFREQ = 108k Ω
DC PSR (dB)
VCC, SUPPLY VOLTAGE (V)
Analog Integrated Circuit Device Data
10 Freescale Semiconductor
34830
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
VCC
VCC is the power input terminal for the IC. A 0.1μF bypass
capacitor in series with a 4.7Ω resistor to ground should be
connected as close as possible to this pin to provide noise
immunity.
IN
IN is the video signal input terminal.
GND
GND is the ground terminal for the IC.
RFREQ
The operating bandwidth of the IC is set by the value of the
resistor between this terminal and ground. By selecting a
value for the RFREQ resistor between 9.0kΩ and 108kΩ,the
bandwidth can be set for video applications ranging from
1080p to 480i.
OUT
OUT is the video signal output terminal.
EN
EN is a logic level enable input for the IC. EN = 1 turns the
IC on, and EN = 0 turns it off.
Analog Integrated Circuit Device Data
Freescale Semiconductor 11
34830
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Figure 22. Functional Internal Block Diagram
SIGNAL PATH/SIGNAL CHANNEL
INPUT CLAMP
This sets the DC level of the signal at the input if the input
is AC-coupled.
LEVELSHIFTER
The Level Shifter provides +250mV DC shift to the input
signal. This positions the signal within the input compliance
of the output buffer.
OUTPUT BUFFER
It provides gain of two as well as the current to drive the
load.
BIAS CIRCUITRY
The Bias Circuitry sets the operating points for the internal
blocks of the 34830. It consists of a bandgap voltage
reference, a PTAT current generator and a constant current
generator.
BANDWIDTH ADJUST
It consists of a variable PTAT current generator whose
current is set by an external resistor. Bias current variation is
inversely proportional to the external resistor value. By
varying the bias current for the level shifter and output buffer
we can adjust the channel bandwidth.
SHUTDOWN
Shutdown enables/disables internal blocks of the 34830
based on the state of the enable input (EN).
PTAT Current Generator
MC34830 - Functional Block Diagram
BiasSignal Path Bandwidth Adjust
Constant Current Generator
Voltage Bandgap
Bias Bandwidth Adjust
Signal Path/ Signal Channel
Output Buffer
Level Shifter
Input Clamp
Shutdown
Shutdown
Analog Integrated Circuit Device Data
12 Freescale Semiconductor
34830
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL DEVICE OPERATION
INTRODUCTION
The 34830 is a very high performance video buffer
designed for high-definition (HD) video applications. The
device features an innovative adjustable bandwidth circuitry
that allows the user to set the bandwidth of the device
through an external resistor connected to RFREQ. This
feature allows the 34830 to fit in a variety of video
applications giving it the flexibility to reduce power
consumption when full bandwidth is not required. In this way
the 34830 can support all video bandwidths, from standard
definition (SD) to high definition (HD), including the 1080i as
well as 1080p formats.
The 34830 also features an internal input clamp that works
with all sync formats and types of video signals. The clamp
can work in three different modes and allows both AC- and
DC-coupled input signals.
The 34830 is optimized to drive a single standard video
load while maintaining exceptional performance
characteristics. Two video loads can also be supported by the
device with a minimum tradeoff in performance
specifications. The 34830 supports both AC- and DC-
coupled outputs.
The 34830 can be disabled with an ultra-low current
consumption of 0.12μA, by driving the EN input to ground.
The 34830 operates using a single supply from 3V to 5.5V,
and is designed to work in the extended temperature range
from -40°C to 85°C. The device is offered in a small UDFN
package ideal to fit into space-critical applications.
The signal path of the 34830 begins with the input clamp
that DC-restores the input. The signal is then shifted up by a
level shifter which brings it to the appropriate levels required
for the output buffer. The level shifter also provides isolation
between the very sensitive input clamp circuit and the input
stage of the output buffer. The signal is then channeled to the
output buffer which amplifies it with a gain of two and drives
the output loads. Both the level shifter and output buffer
blocks are biased through the bandwidth adjust circuitry
which allows the user to set the bandwidth and quiescent
power consumption according to the application at hand.
INPUT CLAMP
The function of the input clamp is to set the DC level of the
signal at the input. The clamp can be operated in three
modes.
Sync Tip Clamp
The clamp works in this mode for Y,CV, R, G, and B
signals that are AC-coupled to the 34830. In this mode, the
clamp senses the most negative level of the input signal and
clamps it to ground. The clamp circuit does this by injecting
current into the AC-coupling capacitor to make the voltage at
the input rise. The current is disabled once the voltage has
risen to the appropriate level. The clamp circuitry includes a
small (2.0μA) pull-down current to guarantee operation of the
clamp.
Key Clamp
The clamp works in this mode for C, Pb, Pr, U, and V
signals that are AC-coupled to the 34830 while DC bias is set
externally. In this configuration, ensure that the DC bias at the
input is such that the most negative level of the signal never
goes below 50mV, to avoid interference with the clamp. The
DC bias at the input can be set through a resistive voltage
divider after the AC-coupling capacitor (Figure 23). In order to
maximize the input signal swing, it is recommended to set the
input DC bias to 0.5V. This will also maximize the swing at the
output of the 34830.
Transparent Clamp
The clamp works in this mode for all DC-biased signals.
Ensure that the most negative level of the signal is above
50mV from ground. If this requirement is not met, the signal
source and clamp both try to set the level at the input,
resulting in signal distortion. The input clamp becomes
transparent for signals above 50mV and the signal passes
through unaffected.
BIAS CIRCUITRY
The bias circuit sets the operating bias for 34830’s internal
blocks. It includes a bandgap voltage reference, a PTAT
current generator, as well as a constant current generator.
These reference currents and voltages are then distributed to
34830’s internal blocks to set their respective operating
points.
BANDWIDTH ADJUST
The 34830 features a bandwidth adjust circuit that sets the
bandwidth of the channel by adjusting quiescent supply
current. It consists of a PTAT current generator whose
current varies with the value of an external resistor (RFREQ).
This PTAT current is used to set the operating bias for the
level shifter and output buffer blocks. Increasing the external
resistor (RFREQ) lowers the bias current, and hence reduces
both supply current and bandwidth. Decreasing the value of
RFREQ increases both supply current and bandwidth. Select
a value for RFREQ in the range between 9kΩ and 108kΩ, to
set the bandwidth between the upper and lower limits. Refer
to Figure 5.
LEVEL-SHIFTER
After passing through the input clamp, which restores its
DC level to a known value, the signal is level-shifted up by
250mV. The level-shifting operation is done for two reasons.
The first is to isolate the input of the output buffer from the
sensitive clamp circuitry to prevent distortion. In this sense,
Analog Integrated Circuit Device Data
Freescale Semiconductor 13
34830
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
the level-shifter acts simply as a buffer of gain one. The
second reason, is to bring the input signal into the proper
operating range of the output buffer. Shifting the signal up
allows the output buffer to work in its sweet spot. This also
prevents the output devices of the output buffer from going
into saturation.
Since the level-shifter needs to pass the signal without
affecting it, it really is a high-speed amplifier. The current that
biases this block comes from the bandwidth adjust section,
which allows for the power consumption to be decreased if
lower bandwidths are required. Refer to Figure 6.
OUTPUT BUFFER
The output buffer is a high-speed (800MHz open-loop
bandwidth), operational amplifier used in a non-inverting gain
of two configuration through resistive feedback. The amplifier
uses a class AB topology with a rail-to-rail output that
incorporates saturation protection as well as current-limiting.
In this way the 34830 is protected against excessive loads or
short-circuit conditions to both supply and ground and will
resume its normal operation as soon as the short-circuit or
overload condition is removed.
The output buffer also uses PTAT current biasing that
varies with RFREQ. By increasing RFREQ, the buffer
bandwidth can be decreased, resulting in power consumption
savings.
The output buffer has been optimized to drive a standard
video load (150Ω) with up to 5pF of load capacitance, while
meeting all of the specifications listed in the electrical
characteristics table. The output buffer can also support two
standard video loads with a slight relaxation in the
specifications.
SHUTDOWN
The 34830 features an enable input (EN) that allows the
device to be placed in a low-supply-current shutdown state
when not required to pass a video signal. Driving EN high
puts the 34830 in its active mode. Driving EN low puts the
34830 in shutdown. In shutdown, the device has a supply
current of 120nA and its output becomes high impedance.
The shutdown feature makes the 34830 ideal for portable
applications where power consumption is critical.
SETTING KEY CLAMP BIAS
For C, Pb, Pr, U, and V signals, use a resistor divider to set
the DC bias (VCLAMP) at the input of the 34830, as shown in
Figure 23. In this configuration.
Ensure that VCLAMP is set to a value such that the most
negative value of the signal at the input to the 34830 is above
50mV. This prevents the internal clamp from turning on. To
maximize signal swing, set VCLAMP = 0.5V. The general
procedure for selecting the resistor values for RC1 and RC2,
is to first select a value for VCLAMP and RC1, and then solve
for RC2 using the formula:
The values selected for RC1 should not be too small, The
bias current that flows through the resistor divider network
comes directly from VCC, and hence adds to power
consumption. A typical value for RC1 is 10kΩ.
The general relationship between input and output voltage
of the channel is given by the formula:
Where the 250mV term is the offset provided by the
internal level shifter. The 100mV term that is added to the
equation represents the worst case errors and offsets that
can be expected from the signal path, due to process and
temperature variations. The DC bias at the output is given by
the same formula substituting VCLAMP for VIN. Thus the DC
bias at the output for VCLAMP = 0.5V is around 1.5V.
Figure 23. Key Clamp DC Bias Configuration
SETTING BANDWIDTH
The bandwidth of the 34830 is set through an external
resistor connected from input RFREQ to ground. Increasing
the value of the resistor causes the quiescent current of the
device to decrease, which in turn decreases its bandwidth.
Decreasing the value of RFERQ has the opposite effect,
mainly to increase quiescent supply current and thus
bandwidth. Select the value of RFREQ in the range between
9kΩ and 108kΩ. Refer to Figure 5 for a relationship between
the value of RFREQ and the corresponding bandwidth of the
34830. To ensure that the channel bandwidth is greater than
the one needed for the application, after taking into account
process and temperature variation, multiply the value of
RFREQ obtained from the graph by 0.6. Use this number as
the value of the external resistor.
It is recommended to place a small capacitor (100pF) in
parallel with the external resistor at RFREQ. This capacitor
helps to filter any noise or signal that couples into the RFREQ
input, which may disturb the bias conditions of the device.
VCLAMP
RC1 VCC
×
RC1 RC2
+
---------------------------
=
RC2
RC1 VCC VCLAMP
–()×
VCLAMP
--------------------------------------------------------------------
=
VOUT 2V
IN 250mV+()×100mV±=
MC34830
IN
AC coupling
capacitor
VCC
RC2
VCLAMP
RC1
Analog Integrated Circuit Device Data
14 Freescale Semiconductor
34830
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
INPUT CONSIDERATIONS
As explained in the Input Clamp section, the 34830
features an internal clamp that allows the device to work with
both AC as well as DC-coupled input signals. To AC-couple
the input signal, use a 0.1μF capacitor following the video
signal source. If the signal being AC-coupled has sync, then
the 34830’s clamp circuit ensures that the sync tip is detected
and positioned near ground (Sync Tip Clamp). If the signal
that is being AC-coupled does not have sync (Key Clamp),
care must be taken to ensure that its most negative portions
are not confused as being sync tips and clamped, resulting in
signal distortion. In order to prevent this from happening, the
user must set the DC bias at the input correctly. See the
SETTING KEY CLAMP BIAS section.
When the input to the 34830 goes above 50mV, the clamp
circuit becomes transparent and does not have any effect on
the signal being passed. This allows the 34830 to work with
DC-coupled signals. To DC-couple the input signal, simply
connect the video source directly to the input of the 34830.
OUTPUT CONISDERATIONS
The relationship between input and output for the 34830
follows the equation:
Where the 250mV term is the offset provided by the
internal level shifter. The 100mV term that is added to the
equation represents the worst case errors and offsets that
can be expected from the signal path, due to process and
temperature variations.
The 34830 has been optimized to drive a single standard
video load. A standard video load typically consists of a 75Ω
back-termination resistor, followed by a matched video cable
and a 75Ω load resistor. The 34830 can drive up to 5pF of
load capacitance in parallel with the video cable and load
resistor. Two video loads can be supported by the 34830 with
a minimum tradeoff in performance parameters.
The output of the 34830 can be both AC or DC-coupled.
When the output is AC-coupled the AC-coupling capacitor
forms a high-pass filter with the load resistor. Ensure that the
value of the AC-coupling capacitor is such that the lowest
frequencies of the video signal are passed without
attenuation from this filter. A typical value for the output AC-
coupling capacitor is 220μF.
Place the output termination resistor as close to the output
as possible to minimize parasitic inductance and capacitance
effects that tend to deteriorate signal quality.
VOUT 2V
IN 250mV+()×100mV±=
Analog Integrated Circuit Device Data
Freescale Semiconductor 15
34830
TYPICAL APPLICATIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
TYPICAL APPLICATIONS
Figure 24. Composite Video Signal
Figure 25. S-Video Application
Figure 26. Component Video Application
0.1μF
0.1μF
CVIN
VCC
AC coupling
capacitor
75Ω75Ω
Video Cable
CVOUT
EN
IN
GND RFREQ
OUT
EN
VCC
34830
100pF
4.7Ω
0.1μF
0.1μF
YIN
VCC
AC coupling
capacitor
75Ω75Ω
Video Cable
YOUT
0.1μF
0.1μF
CIN
VCC
AC coupling
capacitor
75Ω75Ω
Video Cable
COUT
EN
EN
IN GND RFREQ
OUT
EN
VCC
34830
IN
GND RFREQ
OUT
EN
VCC
34830
100pF
100pF
Rc2
Rc1
4.7Ω
4.7Ω
IN GND RFREQ
OUT
EN
VCC
34830
0.1μF
0.1μF
YIN/GIN
VCC
AC coupling
capacitor
75Ω75Ω
Video Cable
YOUT/GOUT
0.1μF
0.1μF
PbIN/BIN
VCC
AC coupling
capacitor
75Ω75Ω
Video Cable
PbOUT/BOUT
EN
EN
IN GND RFREQ
OUT
EN
VCC
34830
0.1μF
0.1μF
PrIN/RIN
VCC
AC coupling
capacitor
75Ω75Ω
Video Cable
PrOUT/ROUT
EN
IN GND RFREQ
OUT
EN
VCC
34830
100pF
100pF
100pF
Rc2
Rc1
Rc2
Rc1
PbIN only
PrIN only
4.7Ω
4.7Ω
4.7Ω
Analog Integrated Circuit Device Data
16 Freescale Semiconductor
34830
TYPICAL APPLICATIONS
BILL OF MATERIAL
Figure 27. 34830 Evaluation Board Schematic
BILL OF MATERIAL
Table 5. 34830 Bill of Material
Item Qty Part Description Value / Rating Part Number / Manufacturer Install
C1, C3 2Capacitor 220μF, 10V UVZ1A221MED, Nichicon, radial,
electrolytic
Y
C2 1Capacitor .1μF, 25V 0603, ceramic, 03CER Y
C4 1Capacitor .1μF, 6.3V 0204, ceramic, Murata,
LLL153C80J104ME01B
Y
C6 1Capacitor 10μF, 25V 1206, ceramic
C7 1Capacitor 100pF, 50V 0603, metal film chip Y
X1-2 2FIDICUAL_40 N
JP1-3, JP5-6, JP8-9, JP12,
3.0V, 5.5V 10 1x2 Male header strip HDR1X2, .1 Pitch straight for .062 BD. Y
D1 1LED HSMx-c670 HP 0805 N
U1 1MC34830 MC34830 Y
R1 1Resistor 1.0kΩ, 1/10W, 1% 0603, metal flip chip Y
R2 1Resistor 180Ω, 1/10W, 1% 0603, metal flip chip N
R3, R6 - R9 5Resistor 75Ω, 1/10W, 1% 0603, metal flip chip, Speer Electronics Y
R4 1Resistor 10kΩ, 1/10W, 1% 0603, metal flip chip Y
R5 1Potentiometer 150kΩBourns 3299Y-1-154L, trrimpot, 25 turn Y
R10 1Resistor 49.9kΩ, 1/10W, 1% Speer Electronics, 0603, metal flip chip Y
R11 1Resistor 100kΩ, 1/10W, 1% 0603, metal flip chip Y
R12 1Resistor 4.7Ω, 1/0W, 1% 0603, metal flip chip Y
NOPOP 1Resistor 49.9Ω, 1/10W, 1% 0603, metal flip chip, TTI
CRCW060349R9FT
N
Input, Output 1-2 3SMA Jack SMA-PCB_EDGE_E Johnson, 142-0711-826, Edge Mount Y
VCC
IN
GND
EN
OUT
RFREQ
34830
C1
C2
C3
C4
R1
R3 R4
R5
R6
R7
R8
R9
R10 R11
NOPOP
VCC
EN
Output1
Output2
Input
VCC
1
2
34
5
6
1
2
3
JP1 JP2 JP3
JP5 JP6
JP8 JP9
JP12
75 10k
.1μF
.1μF
49.9k 100k
3V 5.5V
150k
1k
75 220μF
75
75
220μF
75
R2
180
D1
C6
10μF
C7
100pF
12
3
VCC
GND
X1-2
49.9
R12
4.7
Analog Integrated Circuit Device Data
Freescale Semiconductor 17
34830
TYPICAL APPLICATIONS
PCB LAYOUT CONSIDERATIONS
The 34830 is a high-speed amplifier, and as such requires
careful attention to be paid to the way in which boards are laid
out, in order to guarantee best performance. All high-speed
layout techniques should be followed including the following
points.
1. Minimize all trace inductances by reducing trace
lengths. This is especially critical for the supply and
ground lines as well as for the output line. Boards with
multiple layers should have enough vias from the
ground plane to the chip ground connection to further
reduce inductance.
2. Make sure that a solid ground plane is available and
run all traces above it.
3. Avoid traces with 90 degree bends.
4. Use a 0.1μF bypass capacitor in series with a 4.7Ω
resistor as close to the VCC and GND pins of the 34830
as possible. Include a 10μF bypass capacitor at the
location on the board where VCC and GND are
connected to the external world.
5. Try to refer all ground connections to the same point as
in a star ground configuration. Usually this point is the
middle point of the ground plane.
THERMAL CONSIDERATIONS
Make sure that the thermal dissipation ratings for the
34830 package are not violated in the application at hand.
The 34830 comes in a package with an exposed pad (EP).
The primary function of the EP is to serve as an effective way
to dissipate heat away from the inside of the package. Take
full advantage of this feature and connect the EP to a surface
or plane that can act as a heat sink. The EP is electrically
connected to ground. Make sure that the heat sink is also
connected to the same potential. If multiple heat generating
components are used in the application, distribute these
evenly throughout the board, so as not to create hot spots
with large temperature gradients that could violate power and
heat dissipation ratings.
POWER DISSIPATION
Care must be taken not to exceed the maximum die
junction temperature of the 34830. The die junction
temperature can be calculated through the formula:
Where PDISS is the average power dissipation of the
device which can be calculated as PDISS = VCC*(ICC +
VOUT(RMS)2/RLOAD).
EN 1E-Switch Switch SPDT SPDT, EG1218 Y
VCC
1
2POL254 Phoenix
Connector
Termblock2_MKD MKDSN1.5/2, 2 pin Terminal block 2 Diga-
key, 5.0mm, 90 deg wire to pin, Stock
number - 277-1236-ND
Y
Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or
tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
Table 5. 34830 Bill of Material
Item Qty Part Description Value / Rating Part Number / Manufacturer Install
TJTAPDISS θJA
×+=
Analog Integrated Circuit Device Data
Freescale Semiconductor 19
34830
PACKAGING
PACKAGE DIMENSIONS
EP SUFFIX (PB-FREE)
6-PIN
98ASA10819D
ISSUE A
Analog Integrated Circuit Device Data
20 Freescale Semiconductor
34830
PACKAGING
PACKAGE DIMENSIONS
EP SUFFIX (PB-FREE)
6-PIN
98ASA10819D
ISSUE A
Analog Integrated Circuit Device Data
Freescale Semiconductor 21
34830
REVISION HISTORY
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES
1.0 9/2008 • Initial Release
MC34830
Rev. 1.0
9/2008
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