ADC102S101CIMMX - National Semiconductor

ADC102S101

ADC102S101 2 Channel, 500 ksps to 1 Msps, 10-Bit A/D Converter

Literature Number: SNAS287F

ADC102S101

January 29, 2010

2 Channel, 500 ksps to 1 Msps, 10-Bit A/D Converter

General Description

The ADC102S101 is a low-power, two-channel CMOS 10-bit

analog-to-digital converter with a high-speed serial interface.

Unlike the conventional practice of specifying performance at

a single sample rate only, the ADC102S101 is fully specified

over a sample rate range of 500 ksps to 1 Msps. The con-

verter is based on a successive-approximation register archi-

tecture with an internal track-and-hold circuit. It can be

configured to accept one or two input signals at inputs IN1

and IN2.

The output serial data is straight binary, and is compatible with

several standards, such as SPI™, QSPI™, MICROWIRE,

and many common DSP serial interfaces.

The ADC102S101 operates with a single supply that can

range from +2.7V to +5.25V. Normal power consumption us-

ing a +3V or +5V supply is 3.9 mW and 11.4 mW, respectively.

The power-down feature reduces the power consumption to

just 0.12 µW using a +3.6V supply, or 0.47 µW using a +5.5V

supply.

The ADC102S101 is packaged in an 8-lead MSOP package.

Operation over the industrial temperature range of −40°C to

+85°C is guaranteed.

Features

■Specified over a range of sample rates.

■Two input channels

■Variable power management

■Single power supply with 2.7V - 5.25V range

Key Specifications

■DNL + 0.26/−0.16 LSB (typ)

■INL + 0.4/−0.1 LSB (typ)

■SNR 61.7 dB (typ)

■Power Consumption

■—3V Supply 3.9 mW (typ)

—5V Supply 11.4 mW (typ)

Applications

■Portable Systems

■Remote Data Acquisition

■Instrumentation and Control Systems

Pin-Compatible Alternatives by Resolution and Speed

All devices are fully pin and function compatible.

Resolution Specified for Sample Rates of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC122S021 ADC122S051 ADC122S101

10-bit ADC102S021 ADC102S051 ADC102S101

8-bit ADC082S021 ADC082S051 ADC082S101

Connection Diagram

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Ordering Information

Order Code Temperature Range Description Top Mark

ADC102S101CIMM −40°C to +85°C 8-Lead MSOP Package X23C

ADC102S101CIMMX −40°C to +85°C 8-Lead MSOP Package, Tape & Reel X23C

ADC102S101EVAL Evaluation Board

TRI-STATE® is a trademark of National Semiconductor Corporation

QSPI™ and SPI™ are trademarks of Motorola, Inc.

ADC102S101 2 Channel, 500 ksps to 1 Msps, 10-Bit A/D Converter

Block Diagram

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Pin Descriptions and Equivalent Circuits

Pin No. Symbol Description

ANALOG I/O

5,4 IN1 and IN2 Analog inputs. These signals can range from 0V to VA.

DIGITAL I/O

8 SCLK Digital clock input. This clock directly controls the conversion and readout processes.

7 DOUT Digital data output. The output samples are clocked out of this pin on falling edges of the

SCLK pin.

6 DIN Digital data input. The ADC102S101's Control Register is loaded through this pin on rising

edges of the SCLK pin.

1 CS Chip select. On the falling edge of CS, a conversion process begins. Conversions

continue as long as CS is held low.

POWER SUPPLY

2VA

Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and

bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within

1 cm of the power pin.

3 GND The ground return for the die.

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ADC102S101

Absolute Maximum Ratings (Note 1, Note

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Analog Supply Voltage VA−0.3V to 6.5V

Voltage on Any Pin to GND −0.3V to VA +0.3V

Input Current at Any Pin (Note 3) ±10 mA

Package Input Current (Note 3) ±20 mA

Power Consumption at TA = 25°C See (Note 4)

ESD Susceptibility (Note 5)

Human Body Model

Machine Model

2500V

250V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Operating Ratings (Note 1, Note 2)

Operating Temperature Range −40°C ≤ TA ≤ +85°C

VA Supply Voltage +2.7V to +5.25V

Digital Input Pins Voltage Range −0.3V to VA

Clock Frequency 50 kHz to 16 MHz

Analog Input Voltage 0V to VA

Package Thermal Resistance

Package θJA

8-lead MSOP 250°C / W

Soldering process must comply with National

Semiconductor's Reflow Temperature Profile specifications.

Refer to www.national.com/packaging. (Note 6)

ADC102S101 Converter Electrical Characteristics (Note 9)

The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 8 MHz to 16 MHz,

fSAMPLE = 500 ksps to 1 Msps, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Symbol Parameter Conditions Typical Limits

(Note 7)Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 10 Bits

INL Integral Non-Linearity +0.4 +0.7 LSB (max)

−0.1 −0.5 LSB (min)

DNL Differential Non-Linearity +0.26 +0.6 LSB (max)

−0.16 −0.6 LSB (min)

VOFF Offset Error +0.19 ±0.6 LSB (max)

OEM Channel to Channel Offset Error Match 0.02 ±0.6 LSB (max)

FSE Full-Scale Error −0.15 ±0.7 LSB (max)

FSEM Channel to Channel Full-Scale Error Match 0.02 ±0.5 LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

SINAD Signal-to-Noise Plus Distortion Ratio VA = +2.7V to 5.25V

fIN = 40.3 kHz, −0.02 dBFS 61.6 61 dB (min)

SNR Signal-to-Noise Ratio VA = +2.7V to 5.25V

fIN = 40.3 kHz, −0.02 dBFS 61.7 61.3 dB (min)

THD Total Harmonic Distortion VA = +2.7V to 5.25V

fIN = 40.3 kHz, −0.02 dBFS −82 −72 dB (max)

SFDR Spurious-Free Dynamic Range VA = +2.7V to 5.25V

fIN = 40.3 kHz, −0.02 dBFS 83 75 dB (min)

ENOB Effective Number of Bits VA = +2.7V to 5.25V

fIN = 40.3 kHz, −0.02 dBFS 9.9 9.8 Bits (min)

Channel-to-Channel Crosstalk VA = +5.25V

fIN = 40.3 kHz −78 dB

IMD

Intermodulation Distortion, Second Order

Terms

VA = +5.25V

fa = 40.161 kHz, fb = 41.015 kHz −82 dB

Intermodulation Distortion, Third Order

Terms

VA = +5.25V

fa = 40.161 kHz, fb = 41.015 kHz −81 dB

FPBW -3 dB Full Power Bandwidth VA = +5V 11 MHz

VA = +3V 8 MHz

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ADC102S101

Symbol Parameter Conditions Typical Limits

(Note 7)Units

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VAV

IDCL DC Leakage Current ±1 µA (max)

CINA Input Capacitance Track Mode 33 pF

Hold Mode 3 pF

DIGITAL INPUT CHARACTERISTICS

VIH Input High Voltage VA = +5.25V 2.4 V (min)

VA = +3.6V 2.1 V (min)

VIL Input Low Voltage 0.8 V (max)

IIN Input Current VIN = 0V or VA±0.2 ±10 µA (max)

CIND Digital Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

VOH Output High Voltage ISOURCE = 200 µA VA − 0.03 VA − 0.5 V (min)

ISOURCE = 1mA VA − 0.1 V

VOL Output Low Voltage ISINK = 200 µA 0.03 0.4 V (max)

ISINK = 1 mA 0.1 V

IOZH, IOZL TRI-STATE® Leakage Current ±0.01 ±1 µA (max)

COUT TRI-STATE® Output Capacitance 2 4pF (max)

Output Coding Straight (Natural) Binary

POWER SUPPLY CHARACTERISTICS (CL = 10 pF)

VASupply Voltage 2.7 V (min)

5.25 V (max)

Supply Current, Normal Mode (Operational,

CS low)

VA = +5.25V,

fSAMPLE = 1 Msps, fIN = 40 kHz 2.18 2.7 mA (max)

VA = +3.6V,

fSAMPLE = 1 Msps, fIN = 40 kHz 1.08 1.3 mA (max)

Supply Current, Shutdown (CS high)

VA = +5.25V,

fSAMPLE = 0 ksps 90 nA

VA = +3.6V,

fSAMPLE = 0 ksps 33 nA

Power Consumption, Normal Mode

(Operational, CS low)

VA = +5.25V 11.4 14.2 mW (max)

VA = +3.6V 3.9 4.7 mW (max)

Power Consumption, Shutdown (CS high) VA = +5.25V 0.47 µW

VA = +3.6V 0.12 µW

AC ELECTRICAL CHARACTERISTICS

fSCLK Clock Frequency (Note 8) 8MHz (min)

16 MHz (max)

fSSample Rate (Note 8) 500 ksps (min)

1Msps (max)

tCONV Conversion Time 13 SCLK cycles

DC SCLK Duty Cycle fCLK = 16 MHz 50 30 % (min)

70 % (max)

tACQ Track/Hold Acquisition Time Full-Scale Step Input 3SCLK cycles

Throughput Time Acquisition Time + Conversion

Time 16 SCLK cycles

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ADC102S101

ADC102S101 Timing Specifications

The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, CL = 50 pF, fSCLK = 8 MHz to 16 MHz,

fSAMPLE = 500 ksps to 1 Msps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Symbol Parameter Conditions Typical Limits

(Note 7)Units

tCSU Setup Time SCLK High to CS Falling Edge (Note 10)VA = +3.0V −3.5 10 ns (min)

VA = +5.0V −0.5

tCLH Hold time SCLK Low to CS Falling Edge (Note 10)VA = +3.0V +4.5 10 ns (min)

VA = +5.0V +1.5

tEN Delay from CS Until DOUT active VA = +3.0V +4 30 ns (max)

VA = +5.0V +2

tACC Data Access Time after SCLK Falling Edge VA = +3.0V +16.5 30 ns (max)

VA = +5.0V +15

tSU Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min)

tHData Valid SCLK Hold Time +3 10 ns (min)

tCH SCLK High Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min)

tCL SCLK Low Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min)

tDIS CS Rising Edge to DOUT High-Impedance

Output Falling VA = +3.0V 1.7

20 ns (max)

VA = +5.0V 1.2

Output Rising VA = +3.0V 1

VA = +5.0V 1

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20

mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute

Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values

for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven

beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms

Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.

Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under

Operating Ratings.

Note 9: Min/max specification limits are guaranteed by design, test, or statistical analysis.

Note 10: Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.

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ADC102S101

Timing Diagrams

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ADC102S101 Operational Timing Diagram

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Timing Test Circuit

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ADC102S101 Serial Timing Diagram

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ADC102S101

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SCLK and CS Timing Parameters

Specification Definitions

ACQUISITION TIME is the time required to acquire the input

voltage. That is, it is time required for the hold capacitor to

charge up to the input voltage.

APERTURE DELAY is the time between the fourth falling

SCLK edge of a conversion and the time when the input signal

is acquired or held for conversion.

CONVERSION TIME is the time required, after the input volt-

age is acquired, for the ADC to convert the input voltage to a

digital word.

CROSSTALK is the coupling of energy from one channel into

the other channel, or the amount of signal energy from one

analog input that appears at the measured analog input.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital

waveform is high to the total time of one period. The specifi-

cation here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion or SINAD. ENOB is defined as

(SINAD − 1.76) / 6.02 and says that the converter is equiva-

lent to a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

FULL SCALE ERROR (FSE) is a measure of how far the last

code transition is from the ideal 1½ LSB below VREF+ and is

defined as:

VFSE = Vmax + 1.5 LSB – VREF+

where Vmax is the voltage at which the transition to the maxi-

mum code occurs. FSE can be expressed in Volts, LSB or

percent of full scale range.

GAIN ERROR is the deviation of the last code transition

(111...110) to (111...111) from the ideal (VREF − 1.5 LSB), af-

ter adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from negative

full scale (½ LSB below the first code transition) through pos-

itive full scale (½ LSB above the last code transition). The

deviation of any given code from this straight line is measured

from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to the ADC input at the same time.

It is defined as the ratio of the power in the second and third

order intermodulation products to the sum of the power in both

of the original frequencies. IMD is usually expressed in dB.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. These codes cannot be reached with

any input value. The ADC102S101 is guaranteed not to have

any missing codes.

OFFSET ERROR is the deviation of the first code transition

(000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB).

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal at the converter output

to the rms value of the sum of all other spectral components

below one-half the sampling frequency, not including d.c. or

harmonics included in the THD specification..

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below half the clock frequency, including harmonics

but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the rms values of the input

signal and the peak spurious signal where a spurious signal

is any signal present in the output spectrum that is not present

at the input, excluding d.c.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-

pressed in dB or dBc, of the rms total of the first five harmonic

components at the output to the rms level of the input signal

frequency as seen at the output. THD is calculated as

where Af1 is the RMS power of the input frequency at the out-

put and Af2 through Af6 are the RMS power in the first 5

harmonic frequencies. Accurate THD measurement requires

a spectrally pure sine wave (monotone) at the ADC input.

THROUGHPUT TIME is the minimum time required between

the start of two successive conversion. It is the acquisition

time plus the conversion time. In the case of the AD-

C102S101, this is 16 SCLK periods.

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ADC102S101

Typical Performance Characteristics TA = +25°C, fSAMPLE = 500 ksps to 1 Msps,

fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated.

DNL - VA = 3.0V

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INL - VA = 3.0V

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DNL - VA = 5.0V

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INL - VA = 5.0V

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DNL vs. Supply

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INL vs. Supply

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ADC102S101

DNL vs. Clock Frequency

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INL vs. Clock Frequency

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DNL vs. Clock Duty Cycle

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INL vs. Clock Duty Cycle

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DNL vs. Temperature

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INL vs. Temperature

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ADC102S101

SNR vs. Supply

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THD vs. Supply

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SNR vs. Clock Frequency

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THD vs. Clock Frequency

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SNR vs. Clock Duty Cycle

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THD vs. Clock Duty Cycle

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ADC102S101

SNR vs. Input Frequency

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THD vs. Input Frequency

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SNR vs. Temperature

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THD vs. Temperature

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SFDR vs. Supply

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SINAD vs. Supply

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ADC102S101

SFDR vs. Clock Frequency

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SINAD vs. Clock Frequency

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SFDR vs. Clock Duty Cycle

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SINAD vs. Clock Duty Cycle

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SFDR vs. Input Frequency

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SINAD vs. Input Frequency

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ADC102S101

SFDR vs. Temperature

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SINAD vs. Temperature

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ENOB vs. Supply

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ENOB vs. Clock Frequency

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ENOB vs. Clock Duty Cycle

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ENOB vs. Input Frequency

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ADC102S101

ENOB vs. Temperature

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Spectral Response - 3V, 500 ksps

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Spectral Response - 5V, 500 ksps

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Spectral Response - 3V, 1.0 Msps

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Spectral Response - 5V, 1.0 Msps

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Power Consumption vs. Throughput

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ADC102S101

Applications Information

1.0 ADC102S101 OPERATION

The ADC102S101 is a successive-approximation analog-to-

digital converter designed around a charge-redistribution dig-

ital-to-analog converter. Simplified schematics of the AD-

C102S101 in both track and hold modes are shown in

Figures 1, 2, respectively. In Figure 1, the ADC102S101 is in

track mode: switch SW1 connects the sampling capacitor to

one of two analog input channels through the multiplexer, and

SW2 balances the comparator inputs. The ADC102S101 is in

this state for the first three SCLK cycles after CS is brought

low.

Figure 2 shows the ADC102S101 in hold mode: switch SW1

connects the sampling capacitor to ground, maintaining the

sampled voltage, and switch SW2 unbalances the compara-

tor. The control logic then instructs the charge-redistribution

DAC to add fixed amounts of charge to the sampling capacitor

until the comparator is balanced. When the comparator is

balanced, the digital word supplied to the DAC is the digital

representation of the analog input voltage. The ADC102S101

is in this state for the fourth through sixteenth SCLK cycles

after CS is brought low.

The time when CS is low is considered a serial frame. Each

of these frames should contain an integer multiple of 16 SCLK

cycles, during which time a conversion is performed and

clocked out at the DOUT pin and data is clocked into the DIN

pin to indicate the multiplexer address for the next conversion.

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FIGURE 1. ADC102S101 in Track Mode

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FIGURE 2. ADC102S101 in Hold Mode

2.0 USING THE ADC102S101

An ADC102S101 timing diagram and a serial interface timing

diagram for the ADC102S101 are shown in the Timing Dia-

grams section. CS is chip select, which initiates conversions

and frames the serial data transfers. SCLK (serial clock) con-

trols both the conversion process and the timing of serial data.

DOUT is the serial data output pin, where a conversion result

is sent as a serial data stream, MSB first. Data to be written

to the ADC102S101's Control Register is placed at DIN, the

serial data input pin. New data is written to DIN with each

conversion.

A serial frame is initiated on the falling edge of CS and ends

on the rising edge of CS. Each frame must contain an integer

multiple of 16 rising SCLK edges. The ADC output data

(DOUT) is in a high impedance state when CS is high and is

active when CS is low. Thus, CS acts as an output enable.

Additionally, the device goes into a power down state when

CS is high and also between continuous conversion cycles.

During the first 3 cycles of SCLK, the ADC is in the track

mode, acquiring the input voltage. For the next 13 SCLK cy-

cles the conversion is accomplished and the data is clocked

out, MSB first, starting at the 5th clock. If there is more than

one conversion in a frame, the ADC will re-enter the track

mode on the falling edge of SCLK after the N*16th rising edge

of SCLK, and re-enter the hold/convert mode on the N*16+4th

falling edge of SCLK, where "N" is an integer.

When CS is brought high, SCLK is internally gated off. If SCLK

is stopped in the low state while CS is high, the subsequent

fall of CS will generate a falling edge of the internal version of

SCLK, putting the ADC into the track mode. This is seen by

the ADC as the first falling edge of SCLK. If SCLK is stopped

with SCLK high, the ADC enters the track mode on the first

falling edge of SCLK after the falling edge of CS.

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ADC102S101

During each conversion, data is clocked into the ADC at DIN

on the first 8 rising edges of SCLK after the fall of CS. For

each conversion, it is necessary to clock in the data indicating

the input that is selected for the conversion after the current

one. See Tables 1, 2 and Table 3.

If CS and SCLK go low within the times defined by tCSU and

tCLH, the rising edge of SCLK that begins clocking data in at

DIN may be one clock cycle later than expected. It is, there-

fore, best to strictly observe the minimum tCSU and tCLH times

given in the Timing Specifications.

There are no power-up delays or dummy conversions re-

quired with the ADC102S101. The ADC is able to sample and

convert an input to full conversion immediately following pow-

er up. The first conversion result after power-up will be that of

IN1.

TABLE 1. Control Register Bits

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

TABLE 2. Control Register Bit Descriptions

Bit #: Symbol: Description

7 - 6, 2 - 0 DONTC Don't care. The value of these bits do not affect the device.

3 ADD0 These bits determine which input channel will be sampled and converted in the

next track/hold cycle. The mapping between codes and channels is shown in

Table 3.

4 ADD1

5 ADD2

TABLE 3. Input Channel Selection

ADD2 ADD1 ADD0 Input Channel

x 0 0 IN1 (Default)

x 0 1 IN2

x 1 x Not allowed. The output signal at the DOUT pin

is indeterminate if ADD1 is high.

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ADC102S101

3.0 ADC102S101 TRANSFER FUNCTION

The output format of the ADC102S101 is straight binary. Code transitions occur midway between successive integer LSB values.

The LSB width for the ADC102S101 is VA/1024. The ideal transfer characteristic is shown in Figure 3. The transition from an output

code of 00 0000 0000 to a code of 00 0000 0001 is at 1/2 LSB, or a voltage of VA/2048. Other code transitions occur at steps of

one LSB.

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FIGURE 3. Ideal Transfer Characteristic

4.0 TYPICAL APPLICATION CIRCUIT

A typical application of the ADC102S101 is shown in Figure

4. Power is provided, in this example, by the National Semi-

conductor LP2950 low-dropout voltage regulator, available in

a variety of fixed and adjustable output voltages. The power

supply pin is bypassed with a capacitor network located close

to the ADC102S101. Because the reference for the AD-

C102S101 is the supply voltage, any noise on the supply will

degrade device noise performance. To keep noise off the

supply, use a dedicated linear regulator for this device, or

provide sufficient decoupling from other circuitry to keep noise

off the ADC102S101 supply pin. Because of the

ADC102S101's low power requirements, it is also possible to

use a precision reference as a power supply to maximize per-

formance. The four-wire interface is shown connected to a

microprocessor or DSP.

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FIGURE 4. Typical Application Circuit

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ADC102S101

5.0 ANALOG INPUTS

An equivalent circuit for one of the ADC102S101's input chan-

nels is shown in Figure 5. Diodes D1 and D2 provide ESD

protection for the analog inputs. At no time should any input

go beyond (VA + 300 mV) or (GND − 300 mV), as these ESD

diodes will begin conducting, which could result in erratic op-

eration. For this reason, these ESD diodes should NOT be

used to clamp the input signal.

The capacitor C1 in Figure 5 has a typical value of 3 pF, and

is mainly the package pin capacitance. Resistor R1 is the on

resistance of the multiplexer and track / hold switch, and is

typically 500 ohms. Capacitor C2 is the ADC102S101 sam-

pling capacitor and is typically 30 pF. The ADC102S101 will

deliver best performance when driven by a low-impedance

source to eliminate distortion caused by the charging of the

sampling capacitance. This is especially important when us-

ing the ADC102S101 to sample AC signals. Also important

when sampling dynamic signals is a band-pass or low-pass

filter to reduce harmonics and noise, improving dynamic per-

formance.

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FIGURE 5. Equivalent Input Circuit

6.0 DIGITAL INPUTS AND OUTPUTS

The ADC102S101's digital output DOUT is limited by, and

cannot exceed, the supply voltage, VA. The digital input pins

are not prone to latch-up and, and although not recommend-

ed, SCLK, CS and DIN may be asserted before VA without

any latchup risk.

7.0 POWER SUPPLY CONSIDERATIONS

The ADC102S101 is fully powered-up whenever CS is low,

and fully powered-down whenever CS is high, with one ex-

ception: the ADC102S101 automatically enters power-down

mode between the 16th falling edge of a conversion and the

1st falling edge of the subsequent conversion (see Timing

Diagrams).

The ADC102S101 can perform multiple conversions back to

back; each conversion requires 16 SCLK cycles. The AD-

C102S101 will perform conversions continuously as long as

CS is held low.

The user may trade off throughput for power consumption by

simply performing fewer conversions per unit time. The Power

Consumption vs. Sample Rate curve in the Typical Perfor-

mance Curves section shows the typical power consumption

of the ADC102S101 versus throughput. To calculate the pow-

er consumption, simply multiply the fraction of time spent in

the normal mode by the normal mode power consumption ,

and add the fraction of time spent in shutdown mode multi-

plied by the shutdown mode power dissipation.

7.1 Power Supply Noise Considerations

The charging of any output load capacitance requires current

from the power supply, VA. The current pulses required from

the supply to charge the output capacitance will cause voltage

variations on the supply. If these variations are large enough,

they could degrade SNR and SINAD performance of the ADC.

Furthermore, discharging the output capacitance when the

digital output goes from a logic high to a logic low will dump

current into the die substrate, which is resistive. Load dis-

charge currents will cause "ground bounce" noise in the sub-

strate that will degrade noise performance if that current is

large enough. The larger is the output capacitance, the more

current flows through the die substrate and the greater is the

noise coupled into the analog channel, degrading noise per-

formance.

To keep noise out of the power supply, keep the output load

capacitance as small as practical. If the load capacitance is

greater than 50 pF, use a 100 Ω series resistor at the ADC

output, located as close to the ADC output pin as practical.

This will limit the charge and discharge current of the output

capacitance and improve noise performance.

7.2 Power Supply Noise Considerations

The charging of any output load capacitance requires current

from the power supply, VA. The current pulses required from

the supply to charge the output capacitance will cause voltage

variations on the supply. If these variations are large enough,

they could degrade SNR and SINAD performance of the ADC.

Furthermore, discharging the output capacitance when the

digital output goes from a logic high to a logic low will dump

current into the die substrate, which is resistive. Load dis-

charge currents will cause "ground bounce" noise in the sub-

strate that will degrade noise performance if that current is

large enough. The larger is the output capacitance, the more

current flows through the die substrate and the greater is the

noise coupled into the analog channel, degrading noise per-

formance.

To keep noise out of the power supply, keep the output load

capacitance as small as practical. If the load capacitance is

greater than 50 pF, use a 100 Ω series resistor at the ADC

output, located as close to the ADC output pin as practical.

This will limit the charge and discharge current of the output

capacitance and improve noise performance.

www.national.com 18

ADC102S101

Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead MSOP

Order Number ADC102S101CIMM, ADC102S101CIMMX

NS Package Number P0MUA08A

19 www.national.com

ADC102S101

Notes

ADC102S101 2 Channel, 500 ksps to 1 Msps, 10-Bit A/D Converter

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