SST29EE512-70-4C-NHE - Microchip Technology, Inc.

S71060-09-000 9/05

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

SSF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to cha nge without notice.

Data Sheet

512 Kbit (64K x8) Page-Write EEPROM

SST29EE512

FEATURES:

• Single Voltage Read and Write Operations

– 4.5-5.5V for SST29EE512

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

– Active Current: 20 mA (typical)

– Standby Current: 10 µA (typical)

• Fast Page-Write Operation

– 128 Bytes per Page, 512 Pages

– Page-Write Cycle: 5 ms (typical)

– Complete Memory Rewrite: 2.5 sec (typical)

– Effective Byte-Write Cycle Time: 39 µs (typ ica l)

• Fast Read Access Time

– 4.5-5.5V operation: 70 ns

• Latched Address and Data

• Automatic Write Timing

– Internal VPP Generation

• End of Write Detection

– Toggle Bit

– Data# Polling

• Har dware and Sof tware Data Protection

• Product Identification can be accessed via

Software Operation

• TTL I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 20mm)

– 32-pin PDIP

• All non-Pb (lead-free) de vices are RoHS compliant

PRODUCT DESCRIPTION

The SST29EE512 is a 64K x8 CMOS, Page-Write

EEPROM manuf actured with SST’ s proprietary, high-per-

formance CMOS SuperFlash technology. The split-gate

cell design and thick-oxide tunneling injector attain better

reliability and manufacturability compared with alternate

approaches. The SST29EE512 writes with a single

power supply. Internal Erase/Program is transparent to

the user. The SST29EE512 conforms to JEDEC stan-

dard pin assignments for b yte-wide memories.

Featuring high performance Page-Write, the

SST29EE512 provides a typical Byte-Write time of 39

µsec. The entire memory, i.e., 64 KByte, can be written

page-by-page in as little as 2.5 seconds, when using

interface features such as Toggle Bit or Data# Polling to

indicate the completion of a Write cycle. To protect

against inadvertent write, the SST29EE512 hav e on-chip

hardware and Software Data Protection schemes.

Designed, manuf actured, and tested f or a wide spectrum

of applications, the SST29EE512 is offere d with a guar-

anteed Page-Write endurance of 10,000 cycles. Data

retention is rated at greater than 100 years.

The SST29EE512 is suited for applications that require

convenient and economical updating of program, config-

uration, or data memor y. For all system applications, the

SST29EE512 significantly improves performance and

reliability, while lowering power consumption. The

SST29EE512 improves flexibility while lowering the cost

f or program, data, and configuration storage applications.

To meet high density, surface mount requirements, the

SST29EE512 is offered in 32-lead PLCC and 32-lead

TSOP packages. A 600-mil, 32-pin PDIP package is also

av aila ble . See Figures 1 , 2, and 3 f o r pin assignments .

Device Operation

The SST Page-Write EEPROM offers in-circuit electrical

write capability. The SST29EE512 does not require sepa-

rate Erase and Program operations. The internally timed

Write cycle ex ecutes both erase and prog ram transparently

to the user. The SST29EE512 has industry standard

optional Software Data Protection, which SST recom-

mends always to be enabled. The SST29EE512 is com-

patible with industry standard EEPROM pinouts and

functionality.

SST29EE512512Kb (x8) Page-Write, Small-Sector flash memories

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

Read

The Read operations of the SST29EE512 is controlled by

CE# and OE#, both ha v e to be lo w f or the system to obtain

data from the outputs. CE# is used for device selection.

When CE# is high, the chip is de selected and only standb y

power is consumed. OE# is the output control and is used

to gate data from the output pins. The data bus is in high

impedance state when either CE# or OE# is high . Refer to

the Read cycle timing diagr am for further details (Figure 4).

Write

The Page-Write to the SST29EE512 should always use

the JEDEC Standard Software Data Protection (SDP)

three-byte command sequence. The SST29EE512 con-

tains the optional JEDEC approved Software Data Protec-

tion scheme. SST recommends that SDP always be

enabled, thus, the description of the Write operations will

be given using the SDP enabled format. The three-byte

SDP Enable and SDP Write commands are identical;

therefore, any time a SDP Write command is issued,

Software Data Pr otection is automatically assured. The

first time the three -byt e SDP command is giv en, the de vice

becomes SDP enab led. Subsequent issuance of the same

command b ypa sses the da ta pro tection for the page being

written. At the end of the desired Page-Write, the entire

device remains protected. For additional descriptions,

please see the application notes The Proper Use of

JEDEC Standard Soft ware Data Protection and Protecting

Against Unintentional Writes When Using Single Power

Supply Flash Memories .

The Write operation consists of three steps. Step 1 is the

three-byte load sequence for Software Data Protection.

Step 2 is the byte-load cycle to a page buffer of the

SST29EE512. Steps 1 and 2 u se the same t iming for both

operatio ns . Step 3 is an internally controlled Write cycle for

writing the data loaded in the page buffer into the memory

array for nonvolatile storage. During both the SDP three-

byt e load sequence and the byte- load cycle, the addresses

are latched by the falling edge of either CE# or WE#,

whichever occurs last. The data is latched by the rising

edge of either CE# or WE#, whichever occurs first. The

inter nal Write cy cle is initiated by the TBLCO timer after the

rising edge of WE# or CE#, whichever occurs first. The

Write cycle, once initiated, will continue to completion, typi-

cally within 5 ms. See Figures 5 and 6 for WE# and CE#

controlled Page-Write cycle timing diagrams and Figures

15 and 17 f or flowcharts.

The Write operation has three functional cycles: the Soft-

ware Data Protection load sequence, the page-load cycle,

and the internal Write cycle. The Software Data Protection

consists of a specific three-byte load sequence that allows

writing to the selected page and will leave the

SST29EE512 protected at the end of the Page-Wr ite. The

page-load cycle consists of loading 1 to 128 Bytes of data

into the page b uff er . The inte rnal Write cycle consists of the

TBLCO time-out and the write timer operation. During the

Write operation, the only valid reads are Data# Polling and

Toggle Bit.

The Page-Write operation allows the loading of up to 128

Bytes of data into the page buffer of the SST29EE512

before the initiation of the internal Write cycle. During the

internal Write cycle, all the data in the pag e b uff er is written

simultaneously into the memory array. Hence, the Page-

Write feature of SST29EE512 allows the entire memory to

be written in as little as 2.5 seconds. During the internal

Write cycle, the host is free to perform additional tasks,

such as to fetch data from other locations in the system to

set up the write to the ne xt page . In each Page-Write oper-

ation, all the b ytes that are loaded into the pag e buff er must

have the same page address, i.e. A7 through A16. Any byte

not loaded with user data will be written to FFH.

See Figures 5 and 6 for the Page-Write cycle timing dia-

grams. If after the completion of the three-byte SDP load

sequence or the initial byte-load cycle , the host loads a sec-

ond byte into the page buffer within a byte-load cycle time

(TBLC) of 100 µs, the SST29EE512 will stay in the page-

load cycle. Additional bytes are then loaded consecutively.

The page-load cycle will be terminated if no additional b yte

is loaded into the page buffer within 200 µs (TBLCO) from

the last byte-load cycle, i.e., no subsequent WE# or CE#

high-to-low transition after the last rising edge of WE# or

CE#. Data in the page buffer can be changed by a subse-

quent byte-load cycle. The page-load per iod can continue

indefinitely, as long as the host contin ues to load the de vice

within the byte-load cycle time of 100 µs. The page to be

loaded is determined by the page address of the last byte

loaded.

Software Chip-Erase

The SST29EE512 provides a Chip-Erase ope r ation, which

allows the user to simultaneously clear the entire memor y

array to the “1” state. This is useful when the entire device

must be quic kly erased.

The Software Chip-Erase operation is initiated by using a

specific six-byte load sequence. After the load sequence,

the de vice enters into an internally timed cycle similar to the

Write cycle. During the Erase operation , the only v alid read

is Toggle Bit. See Table 4 for the load sequence , Figure 10

f or timing diagram , and Figure 19 for the flowchart.

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

Write Operation Status Detection

The SST29EE512 provides two software means to detect

the completion of a Write cycle, in order to optimiz e the sys-

tem Write cycle time. The software detection includes two

status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The

end of write detection mode is enab led after the rising WE#

or CE# whichever occurs first, which initiates the internal

Write cycle.

The actual completion of the nonvolatile wr ite is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i. e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an err oneous result occurs , the softw are routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is v alid.

Data# Polling (DQ7)

When the SST29EE512 is in the internal Wr ite cycle, any

attempt to read DQ7 of the last byte load ed during the by te-

load cycle will receive the complement of the true data.

Once the Write cycle is completed, DQ7 will show true

data. Note that even though DQ7 may have valid data

immediately following the completion of an internal Write

operation, the remaining data outputs may still be invalid:

valid data on the entire data bus will appear in subsequent

successive Read cycles after an interval of 1 µs. See Fig-

ure 7 for Data# Polling timing diagram and Figure 16 for a

flowchart.

Toggle Bit (DQ6)

During the internal Write cycle, an y consecutive attempts to

read DQ6 will produce alternating ‘0’s and ‘1’s, i.e., toggling

between 0 and 1. When the Write cycle is completed, the

toggling will stop. The device is then ready for the next

operation. See Figure 8 for Toggle Bit timing diagram and

Figure 16 for a flowchart. The initial read of the Toggle Bit

will typically be a “1”.

Data Protection

The SST29EE512 provide both hardware and software

f eatures to protect non volatile data fro m inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 2.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Wr ite operation. This prevents inadvert-

ent writes during power-up or po wer-do wn.

Software Data Protection (SDP)

The SST29EE512 provides the JEDEC approved optional

Software Data Protection scheme for all data alteration

operations, i.e., Write and Chip-Erase. With this scheme,

any Write operation requires the inclusion of a series of

three byte-load operations to precede the data loading

operation. The three-byte load sequence is used to initiate

the Write cycle, providing optimal protection from inadvert-

ent Write operations, e.g., during the system power-up or

power-down. The SST29EE512 is shipped with the Soft-

ware Dat a Protection disab led.

The software protection scheme can be enabled by

applying a three-byte sequence to the device, during a

page-load cycle (Figures 5 and 6). The device will then

be automatically set into the data protect mode. Any

subsequent Write operation will require the preceding

three-byte sequence. See Table 4 for the specific soft-

ware command codes and Figures 5 and 6 for the tim-

ing diagrams. To set the device into the unprotected

mode, a six-byte sequence is required. See Table 4 for

the specific codes and Figure 9 for the timing diag ram. If

a Write is attempted while SDP is enabled the device

will be in a non-accessible state for ~ 300 µs. SST rec-

ommends Software Data Protection alw ays be enabled.

See Figure 17 for flowcharts.

The SST29EE512 Software Data Protection is a global

command, protecting (or unprotecting) all pages in the

entire memory array once enabled (or disabled) . Theref or e

using SDP for a single Page-Write will enable SDP for the

entire array. Single pages by themselves cannot be SDP

enabled or disabled, although the page addressed during

the SDP write will be written.

Single power supply reprogrammable nonvolatile memo-

ries may be unintentionally altered. SST strongly recom-

mends that Software Data Protection (SDP) always be

enabled. The SST29EE512 should be programmed using

the SDP command sequence . SST re commends th e SDP

Disable Command Sequence not be issued to the device

prior to writing.

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

Please refer to the following Application Notes for more

inf ormation on using SDP:

•Protecting Against Unintentional Writes When

Using Single Power Supply Flash Memories

•The Proper Use of JEDEC St andard Software

Data Protection

Product Identification

The Product Ident ification mode identifies the de vice as the

SST29EE512 and manufacturer as SST. This mode is

accessed via software. For details, see Table 4, Figure 11

f or the software ID entry, and Read timing diagram and Fig-

ure 18 f or the ID entry command sequence flo wchart.

Product Identification Mode Exit

In order to return to the standard Read mode , the Softw are

Product Identification mode must be exited. Exiting is

accomplished by issuing the Software ID Exit (reset) opera-

tion, which returns the device to the Read operation. The

Reset operation ma y also be used to reset the device to the

Read mode after an inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. See Table 4 for software command

codes, Figure 12 for timing waveform, and Figure 18 for a

flowchart.

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’ s ID 0000H BFH

Device ID

SST29EE512 0001H 5DH

T1.3 1060

Y-Decoder and Page Latches

I/O Buffers and Data Latches

1060 B1.1

Address Buffer & Latches

X-Decoder

DQ7 - DQ0

15 - A0

WE#

OE#

CE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP

FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

32-lead PLCC

Top View

1060 32-plcc NH P1

14 15 16 17 18 19 20

1060 32-tsop EH P2

A11

A13

A14

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

Standard Pinout

Top View

Die Up

32-pin

PDIP

Top View

1060 32-pdip PH P3

A15

A12

VDD

WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

A15-A7Row Address Inputs To provide memory addresses. Row addresses define a page for a Write cycle.

A6-A0Column Address Inputs Column Addresses are toggled to load page data

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is inter nally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide: 5.0V supply (4.5-5.5V) for SST29EE512

VSS Ground

NC No Connection Unconnected pins.

T2.3 1060

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Page-Write VIL VIH VIL DIN AIN

Standby VIH X1

1. X can be VIL or VIH, but no other value.

X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Software Chip-Erase VIL VIH VIL DIN AIN, See Table 4

Product Identification

Software Mode VIL VIH VIL Manufacturer’s ID (BFH)

Device ID2

2. Device ID = 5DH for SST29EE512

See Table 4

SDP Enable Mode VIL VIH VIL See Table 4

SDP Disable Mode VIL VIH VIL See Table 4

T3.4 1060

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

Note: This product supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code

sequence. For new designs, SST recommends that the three-byte command code sequence be used.

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence 1st Bus

Write Cycle 2nd Bus

Write Cycle 3rd Bus

Write Cyc le 4th Bus

Write Cyc le 5th Bus

Write Cycle 6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Software

Data Protect Enable

& Page-Write

5555H AAH 2AAAH 55H 5555H A0H Addr2Data

Software Chip-Erase 35555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit 5555H AAH 2AAAH 55H 5555H F0 H

Alternate

Software ID Entry65555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H

T4.4 1060

1. Address format A14-A0 (Hex), Address A15 can be VIL or VIH, but no other value.”

2. Page-Write consists of loading up to 128 Bytes (A6-A0)

3. The software Chip-Erase function is not supported by the industrial temperature part.

Please contact SST if you require this function for an industrial temperature part.

4. The device does not remain in Software Product ID mode if powered down.

5. With A14-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,

SST29EE512 Device ID = 5DH, is read with A0 = 1

6. Alternate six-byte Software Product ID Command Code

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions ma y affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hole Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Solder Reflo w Temperat ure1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST29EE512

Range Ambient Temp VDD

Commercial 0°C to +70°C 4.5-5.5V

Industrial -40°C to +85°C 4.5-5.5V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns

Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF

See Figures 13 and 14

TABLE 5: DC OPERATING CHARACTERISTICS VDD = 4.5-5.5V FOR SST29EE512

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=1/TRC Min,

VDD=VDD Max

Read 30 mA CE#=OE#=VIL, WE#=VIH, all I/Os open

Program and Erase 50 mA CE#=WE#=VIL, OE#=VIH, VDD=VDD Max

ISB1 Standby VDD Current

(TTL input) 3 mA CE#=OE#=WE#=VIH, VDD=VDD Max

ISB2 Standby VDD Current

(CMOS input) 50 µA CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 2.0 V VDD=VDD Max

VOL Output Lo w Voltage 0.4 V IOL=2.1 mA, VDD=VDD Min

VOH Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

T5.2 1060

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Write Operation 5 ms

T6.0 1060

1. This parameter is measured only for initial qualification and after a design or process change t hat could affect this parameter.

TABLE 7: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change t hat could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T7.0 1060

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change t hat could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 mA JEDEC Standard 78

T8.5 1060

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

AC CHARACTERISTICS

TABLE 9: READ CYCLE TIMING PARAMETERS FOR SST29EE512

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 30 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change t hat could affect this parameter.

CE# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1CE# High to High-Z Output 20 ns

TOHZ1OE# High to High-Z Output 20 ns

TOH1Output Hold from Address Change 0 ns

T9.3 1060

TABLE 10: PAGE-WRITE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TWC Write Cycle (Erase and Program) 10 ms

TAS Address Setup Time 0 ns

TAH Address Hold Time 50 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 0 ns

TCP CE# Pulse Width 70 ns

TWP WE# Pulse Width 70 ns

TDS Data Setup Time 35 ns

TDH1

1. This parameter is measured only for initial qualification and after a design or process change t hat could affect this parameter.

Data Hold Time 0 ns

TBLC1Byte Load Cycle Time 0.05 100 µs

TBLCO1Byte Load Cycle Time 200 µs

TIDA1Software ID Access and Exit Time 10 µs

TSCE Software Chip-Er ase 20 ms

T10.6 1060

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

FIGURE 4: READ CYCLE TIMING DIAGRAM

FIGURE 5: WE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM

1060 F04.0

CE#

DDRESS A15-0

OE#

WE#

DQ 7-0

VIH

TCLZ TOH

D ATA VALID

TOLZ

TOE

HIGH-Z

TCE

TCHZ

TOHZ

TRC TAA

1060 F05.0

CE#

OE#

WE#

DDRESS A15-0

DQ 7-0

SW0

AA 55 A0

D ATA VALID

SW1 SW2

BYTE 0 BYTE 1 BYTE 127

TDS

TDH

TBLC TBLCO

TWC

TWP

TOEH

TOES

TCH

TCS

TAH

TAS

5555

Three-Byte Sequence for

Enabling SDP

2AAA 5555

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

FIGURE 6: CE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM

FIGURE 7: DATA# POLLING TIMING DIAGRAM

1060 F06.0

CE#

OE#

WE#

DDRESS A15-0

DQ 7-0

SW0

AA 55 A0

D ATA VALID

SW1 SW2

BYTE 0 BYTE 1 BYTE 127

TDS

TDH

TBLC TBLCO

TWC

TCP

TOEH

TOES

TCH

TCS

TAH

TAS

5555

Three-Byte Sequence for

Enabling SDP

2AAA 5555

1060 F07.0

CE#

OE#

WE#

TWC + TBLCO

TOE

TOEH

TCE

TOES

D# D

DDRESS A15-0

DQ 7D

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

FIGURE 8: TOGGLE BIT TIMING DIAGRAM

FIGURE 9: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM

1060 F08.0

CE#

OE#

WE#

TWC + TBLCO

TWO READ CYCLES

WITH SAME OUTPUTS

TOEH TOE TOES

TCE

DDRESS A15-0

DQ6

1060 F09.0

CE#

OE#

WE#

DDRESS A14-0

DQ 7-0

SW0 SW1 SW2 SW3 SW4 SW5

TBLCO

TBLC

TWC

TWP

55555555

55AA 55 20AA80

Six-Byte Sequence for Disabling

Software Data Protection

2AAA2AAA 55555555

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

FIGURE 10: SOFTWARE CHIP-ERASE TIMING DIAGRAM

FIGURE 11: SOFTWARE ID ENTRY AND READ

1060 F10.0

CE#

OE#

WE#

DDRESS A14-0

DQ 7-0

SW0 SW1 SW2 SW3 SW4 SW5

TBLCO

TBLC

TSCE

TWP

55555555

55AA 55 10AA80

Six-Byte Code for Software Chip-Erase

2AAA2AAA 55555555

1060 F11.0

CE#

OE#

WE#

DDRESS A14-0

DQ 7-0

SW0 SW1 SW2

TIDA

TAA

TBLC

TWP

5555

55AA BF 5D90

Three-Byte Sequence

for Software ID Entry

00002AAA 00015555

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

FIGURE 12: SOFTWARE ID EXIT AND RESET

1060 F12.0

CE#

OE#

WE#

DDRESS A14-0

DQ 7-0

SW0 SW1 SW2

TIDA

TBLC

TWP

5555

55AA F0

Three-Byte Sequence

for Software ID Exit and Reset

2AAA5555

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 14: A TEST LOAD EXAMPLE

1060 F13.0

REFERENCE POINTS OUTPUTINPUT

VHT

VLT

VHT

VLT

IHT

VILT

AC test inputs are driven at VIHT (2.4V) for a logic “1 ” and VILT (0.4 V) for a logic “0”. Measurement reference points for

inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and f all times (10% ↔ 90%) are <10 ns.

Note: VHT - VHIGH Test

VLT - VLOW Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1060 F14.0

T O TESTER

O DUT

CLRL LOW

RL HIG

VDD

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

FIGURE 15: WRITE ALGORITHM

1060 F15

Load Byte

Data

Yes

Byte

Address =

128?

Write

Completed

Increment

Byte Address

By 1

W ait TBLCO

Wait for end of

Write (TWC,

Data# Polling bit

or Toggle bit

operation)

Set Byte

Address = 0

Set Page

Address

Software Data

Protect Write

Command

Start

See Figure 17

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

FIGURE 16: WAIT OPTIONS

1060 F16.0

Read a byte

from page

Yes

Does DQ6

match?

Write

Completed

Read same

byte

Page-Write

Initiated

Toggle Bit

W ait TWC

Write

Completed

Page-Write

Initiated

Internal Timer

Read DQ7

(Data for last

byte loaded)

Is DQ7 =

true data?

Write

Completed

Page-Write

Initiated

Data# Polling

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

FIGURE 17: SOFTWARE DATA PROTECTION FLOWCHARTS

1060 F17.0

Write data: AAH

Address: 5555H

oftware Data Protect Enable

Command Sequence

Write data: 55H

Address: 2AAAH

Write data: A0H

Address: 5555H

Wait TWC

Wait TBLCO

SDP Enabled

Load 0 to

128 Bytes of

page data

Optional Page Load

Operation

Write data: AAH

Address: 5555H

Software Data Protect

Disable Command Sequence

Write data: 55H

Address: 2AAAH

Write data: 80H

Address: 5555H

Write data: AAH

Address: 5555H

Wait TWC

Wait TBLCO

SDP Disabled

Write data: 55H

Address: 2AAAH

Write data: 20H

Address: 5555H

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS

1060 F18

Write data: AAH

Address: 5555H

oftware Product ID Entry

Command Sequence

Write data: 55H

Address: 2AAAH

Pause 10 µs

Write data: 90H

Address: 5555H

Read Software ID

Write data: AAH

Address: 5555H

Software Product ID Exit &

Reset Command Sequence

Write data: 55H

Address: 2AAAH

Pause 10 µs

Write data: F0H

Address: 5555H

Return to normal

operation

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

FIGURE 19: SOFTWARE CHIP-ERASE COMMAND CODES

1060 F19

Write data: AAH

Address: 5555H

oftware Chip-Erase

ommand Sequence

Write data: 55H

Address: 2AAAH

Write data: AAH

Address: 5555H

Write data: 55H

Address: 2AAAH

Write data: 10H

Address: 5555H

W ait TSCE

Chip-Erase

to FFH

Write data: 80H

Address: 5555H

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

PRODUCT ORDERING INFORMATION

Valid combinations for SST29EE512

SST29EE512-70-4C-NH SST29EE512-70-4C-EH SST29EE512-70-4C-PH

SST29EE512-70-4C-NHE SST29EE512-70-4C-EHE

SST29EE512-70-4I-NH SST29EE512-70-4I-EH

SST29EE512-70-4I-NHE SST29EE512-70-4I-EHE

Note: Valid combination s are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to deter m ine availabi lity of new combinations.

Note: The software Chip-Erase function is not supported by the industrial temperature part.

Please contact SST if this function is required in an industrial temperature part.

Environmental Attribute

E1 = non-Pb

Package Modifier

H = 32 leads or pins

Package Type

E = TSOP (type 1, die up, 8mm x 20mm)

N = PLCC

P = PDIP

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Device Density

512 = 512 Kbit

Function

E = Page-Write

Voltage

E = 4.5-5.5V

Product Series

29 = Page -Write F l ash

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

SST 29 EE 512 - 70 - 4C - NH E

XX XX XXXX -XXX -XX- XXX X

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

PACKAGING DIAGRAMS

32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)

SST PACKAGE C ODE: NH

.040

.030

.021

.013 .530

.490

.095

.075

.140

.125

.032

.026

.032

.026

.029

.023

.453

.447

.553

.547

.595

.585

.495

.485 .112

.106

.042

.048

.042

.015 Min.

T OP VIEW SIDE VIEW BO TT OM VIEW

1232

.400

BSC

32-plcc-NH-

ote: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC

.050

BSC

Optional

Pin #1

dentifier .020 R.

MAX. R.

x 30˚

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM

SST PACKAGE C ODE: EH

0.15

0.05

20.20

19.80

18.50

18.30

0.70

0.50

8.10

7.90 0.27

0.17

1.05

0.95

32-tsop-EH-7

ote: 1.Complies with JEDEC publication 95 MO-142 BD dimensions,

although some dimensions may be more stringent.

2.All linear dimensions are in millimeters (max/min).

3.Coplanarity: 0.1 mm

4.Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25mm between leads.

Pin # 1 Identifier

0.50

BSC

1mm

1.20

max.

DETAIL

0.70

0.50

0˚-

5˚

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

32-PIN PLASTIC DUAL IN-LINE PINS (PDIP)

SST PACKAGE C ODE: PH

32-pdip-PH-3

Pin #1 Identifier

Base

Plane

eating

Plane

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.200

.170

7˚

4 PLCS.

.600 BSC

.100 BSC .150

.120

.022

.016

.065

.045

.080

.070

.050

.015

.075

.065 1.655

1.645

.012

.008

5˚

.625

.600

.550

.530

Data Sheet

512 Kbit Page-Write EEPROM

SST29EE512

TABLE 11: REVISION HISTORY

Number Description Date

06 •2002 Data Book May 2002

07 •WH package is no longer offered

•Removed the SST29EE512 90 ns Read Access Time

•Removed the SST29LE512 200 ns Read Access Time

•Removed the SST29VE512 250 ns Read Access Time

•Clarified IDD Write to be Program and Erase in Table 6 on page 9

Mar 2003

08 •2004 Data Book

•Added non-Pb MPNs and removed footnote (See page 22) Nov 2003

09 •Removed 2.7V and 3V devices and associated MPNs

refer to EOL Product Data Sheet S71060(01).

•Added RoHS compliance information on page 1 and in the

“Product Ordering Infor mation” on page 22

•Clarified the Solder Temperature Profile under “Absolute Maximum Stress Ratings”

on page 8

Sep 2005

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-91 10 • Fax 408-735-9036