July 2010 Rev 9 1/67
1
M29F 200FT, 400FT, 800FT, 160FT
M29F 200FB, 400FB, 800FB, 160FB
Top / Bottom Boot Block
5 V Supply Flash Memory
Features
Supply voltage
–V
CC = 5 V
Access time: 55 ns
Program / Erase controller
– Embedded byte/word program algorithms
Erase Suspend and Resume modes
Low power consumption
– Standby and Automatic Standby
100,000 Program/Erase cycles per block
Electronic signature
– Manufacturer code: 0x01
– Top Device codes:
– M29F200FT: 0x2251
– M29F400FT: 0x2223
– M29F800FT: 0x22D6
– M29F160FT: 0x22D2
– Bottom Device codes:
– M29F200FB: 0x2257
– M29F400FB: 0x22AB
– M29F800FB: 0x2258
– M29F160FB: 0x22D8
RoHS packages available
–SO44
– TSOP48
– TFBGA
Automotive device grade 3:
– Temperature: –40 to 125 °C
Automotive device grade 6:
– Temperatu re : – 40 to 85 °C
Automotive grad e ce rtif ied (AEC-Q1 0 0)
FBGA
TSOP48 (N)
12 x 20 mm
SO44 (M)
TFBGA48 (ZA)
6 x 8 mm
www.numonyx.com
Contents M29FxxxFT, M29FxxxFB
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Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1 Address Inputs (A0-A19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Data Input/Output or Address Input (DQ15A-1) . . . . . . . . . . . . . . . . . . . . 20
2.5 Chip Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6 Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.7 Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.8 Reset/Block Temporary Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.9 Ready/Busy Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.10 Byte/Word Organization Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.11 VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.12 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8 Block Protection and Block Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Auto Select Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4 Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.5 Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
M29FxxxFT, M29FxxxFB Contents
3/67
4.6 Unlock Bypass Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.7 Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.8 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.9 Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.10 Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.11 Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1 Data Polling Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2 Toggle Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3 Error Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.4 Erase Timer Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.5 Alternative Toggle Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6 Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 DC and AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8 Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Appendix A Block Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Appendix C Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
C.1 Programmer Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
C.2 In-System Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Appendix D Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
List of tables M29FxxxFT, M29FxxxFB
4/67
List of tables
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Bus Operations, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 3. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4. Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5. Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Pr ogram/Erase Times and Program/Erase Endurance Cycles, M29F160F. . . . . . . . . . . . 32
Table 7. Pr ogram/Erase Times and Program/Erase Endurance Cycles, M29F800F. . . . . . . . . . . . 32
Table 8. Pr ogram/Erase Times and Program/Erase Endurance Cycles, M29F400F. . . . . . . . . . . . 33
Table 9. Pr ogram/Erase Times and Program/Erase Endurance Cycles, M29F200F. . . . . . . . . . . . 33
Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 12. Operatin g an d AC Me as ur em e nt Con ditio n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 13. Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 14. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 15. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 16. Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 18. Reset/Block Temporary Unprotect AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 19. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data. . . 45
Table 20. SO44 - 44 lead Plastic Small Outline, 500 mils body width, package mechanical data . . . 46
Table 21. TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package mechanical data . . . . . . . 47
Table 22. Information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 23. Top Boot Block Addresses, M29F160FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 24. Bottom Boot Block Addresses, M29F160FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 25. Top Boot Block Addresses, M29F800FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 26. Bottom Boot Block Addresses, M29F800FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 27. Top Boot Block Addresses, M29F400FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 28. Bottom Boot Block Addresses, M29F400FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 29. Top Boot Block Addresses, M29F200FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 30. Bottom Boot Block Addresses, M29F200FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 31. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 32. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 33. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 34. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 35. Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 36. Security Co de Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 37. Programmer Technique Bus Operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . 61
Table 38. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
M29FxxxFT, M29FxxxFB List of figures
5/67
List of figures
Figure 1. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. TSOP Connections, M29F160F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. TSOP Connections, M29F800F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. TSOP Connections, M29F400F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. TSOP Connections, M29F200F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. SO Connections, M29F800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. SO Connections, M29F400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. SO Connections, M29F200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Block Addresses, M29F160 (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Block Addresses, M29F160 (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Block Addresses, M29F800 (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Block Addresses, M29F800 (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Block Addresses, M29F400 (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Block Addresses, M29F400 (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. Block Addresses, M29F200 (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Block Addresses, M29F200 (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 21. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 22. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 23. Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 24. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline, top view. . . 45
Figure 25. SO44 – 44 lead plastic small outline, 500 mils body width, package outline . . . . . . . . . . . 46
Figure 26. TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package outline . . . . . . . . . . . . . . . 47
Figure 27. Programmer Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 28. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 29. In-System Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 30. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Description M29FxxxFT, M29FxxxFB
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1 Description
The following overview of the Numonyx® Axcell™ M29F 5 V Flash Memory device
(M29W160F) refers to the 1 6-Mbit d evice. However, th e inform ation can also ap ply to lo we r
densities of the M29F device.
The M29F160F is a 16 Mbit (2 Mbit x8 or 1 Mbit x16) non- volatile memor y that can be read,
erased and reprogrammed. These operations can be performed using a single low voltage
(4.5 to 5.5 V) supply. On power-up the memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Each block can be protected independently to
prevent accide n tal Program or Erase com m and s f rom mo d ifyin g the me m or y. Program and
Erase commands are written to th e Command Interface of the memory. An on-chip
Program/Erase Controller sim plifies the pro cess of programming or erasing the memory by
taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.
The blocks in the memory are asymmetrically arranged, as shown in Figure 10.: Block
Addresses, M2 9F160 (x8) and Figure 11.: Block Addresses, M29F160 (x16) . The first or last
64 KBytes have been divided into fo ur additional blocks. The 16 KByte Boot Block can be
used for small initialization code to start the microprocessor, the two 8 KByte Parameter
Blocks can be used for parameter storage and the remaining 32K is a small Main Block
where the applic at ion may be sto red .
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The memory is offered in TSOP48 (12 x 20mm), SO44 , and TFBGA48 ( 0.8 mm pitch)
packages. The memory is supplied with all the bits erased (set to ’1’).
M29FxxxFT, M29FxxxFB Description
7/67
Figure 1. Logic Dia gram
Table 1. Signal Names
A0-A19 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
EChip Enable
GOutput Enable
WWrite Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Select
VCC Supply Voltage
VSS Ground
NC Not Connected Internally
AI06849B
20
A0-A19
W
DQ0-DQ07
DQ8-DQ15
VCC
E
VSS
15
G
RP
DQ15A–1
RB
BYTE
Description M29FxxxFT, M29FxxxFB
8/67
Figure 2. TSOP Connections, M29F160F
DQ3
DQ9
DQ2
A6 DQ0
W
A3
RB
DQ6
A8
A9 DQ13
A
17
A
10 DQ14
A2
DQ12
DQ10
DQ15A–
1
VCC
DQ4
DQ5
A7
DQ7
NC
NC
AI06850_160
12
1
13
24 25
36
37
48
DQ8
NC
A
19
A1
A
18
A4
A5
DQ1
DQ11
G
A
12
A
13
A16
A
11
BYTE
A
15
A
14 VSS
E
A0
RP
VSS
M29FxxxFT, M29FxxxFB Description
9/67
Figure 3. TSOP Connections, M29F800F
DQ3
DQ9
DQ2
A6 DQ0
W
A3
RB
DQ6
A8
A9 DQ13
A
17
A
10 DQ14
A2
DQ12
DQ10
DQ15A–
1
VCC
DQ4
DQ5
A7
DQ7
NC
NC
AI06850_800
12
1
13
24 25
36
37
48
DQ8
NC
A1
A
18
A4
A5
DQ1
DQ11
G
A
12
A
13
A16
A
11
BYTE
A
15
A
14 VSS
E
A0
RP
VSS
NC
Description M29FxxxFT, M29FxxxFB
10/67
Figure 4. TSOP Connections, M29F400F
DQ3
DQ9
DQ2
A6 DQ0
W
A3
RB
DQ6
A8
A9 DQ13
A
17
A
10 DQ14
A2
DQ12
DQ10
DQ15A–
1
VCC
DQ4
DQ5
A7
DQ7
NC
NC
AI06850_400
12
1
13
24 25
36
37
48
DQ8
NC
A1
A4
A5
DQ1
DQ11
G
A
12
A
13
A16
A
11
BYTE
A
15
A
14 VSS
E
A0
RP
VSS
NC
NC
M29FxxxFT, M29FxxxFB Description
11/67
Figure 5. TSOP Connections, M29F200F
DQ3
DQ9
DQ2
A6 DQ0
W
A3
RB
DQ6
A8
A9 DQ13
A
10 DQ14
A2
DQ12
DQ10
DQ15A–
1
VCC
DQ4
DQ5
A7
DQ7
NC
NC
AI06850_400
12
1
13
24 25
36
37
48
DQ8
NC
A1
A4
A5
DQ1
DQ11
G
A
12
A
13
A16
A
11
BYTE
A
15
A
14 VSS
E
A0
RP
VSS
NC
NC
NC
Description M29FxxxFT, M29FxxxFB
12/67
Figure 6. SO Connections, M29F800
DQ3
DQ9
DQ2
DQ0
A8
A9
DQ6
DQ13
A17
DQ12
D
Q10
DQ15A–
1
VCC
DQ4
DQ5
DQ14
DQ7
AI02906_400
1
11
12
22 23
33
34
44
DQ8
A6
A3
A2
A7
A1
A4
A5
DQ1
DQ11
G
W
BYTE
A10
A16
A12
A13
A11
A15
A14
VSS
A0
RP
RB
VSS
E
A18
M29FxxxFT, M29FxxxFB Description
13/67
Figure 7. SO Connections, M29F400
DQ3
DQ9
DQ2
DQ0
A8
A9
DQ6
DQ13
A17
DQ12
D
Q10
DQ15A–
1
VCC
DQ4
DQ5
DQ14
DQ7
AI02906_400
1
11
12
22 23
33
34
44
DQ8
A6
A3
A2
A7
A1
A4
A5
DQ1
DQ11
G
W
BYTE
A10
A16
A12
A13
A11
A15
A14
VSS
A0
RP
RB
VSS
E
NC
Description M29FxxxFT, M29FxxxFB
14/67
Figure 8. SO Connections, M29F200
DQ3
DQ9
DQ2
DQ0
A8
A9
DQ6
DQ13
DQ12
D
Q10
DQ15A–
1
VCC
DQ4
DQ5
DQ14
DQ7
AI02906_400
1
11
12
22 23
33
34
44
DQ8
A6
A3
A2
A7
A1
A4
A5
DQ1
DQ11
G
W
BYTE
A10
A16
A12
A13
A11
A15
A14
VSS
A0
RP
RB
VSS
E
NC
NC
M29FxxxFT, M29FxxxFB Description
15/67
Figure 9. TFBGA connections (top view through package)
1. On the M29F800FT/B, A19 is NC (no connect); on the M29F400FT/B, A19-A18 are NC; on M29F200FT/B,
A19-A18-A17 are NC.
AI02985c
654321
VSS
DQ15
A–1
A15
A14
A12
A13
DQ3
DQ11
DQ10
A18 /
NC
NC
RB
DQ1
DQ9
DQ8
DQ0
A6
A17 /
NC
A7
G
E
A0
A4
A3
DQ2
DQ6
DQ13
DQ14
A10
A8
A9
DQ4
VCC
DQ12
DQ5
A19 /
NC
NC
RP
W
A11
DQ7
A1
A2
VSS
A5 NC
A16
BYTE
G
F
E
B
A
D
C
H
Description M29FxxxFT, M29FxxxFB
16/67
Figure 10. Block Addresses, M2 9F160 (x8)
Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses.
Figure 11. Block Addresses, M2 9F160 (x16)
Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses.
AI06851_x8_160
16 K B yte
1FFFFFh
1FC000h
64 K B yte
01FFFFh
010000h
64 K B yte
00FFFFh
000000h
Top B oot Block Addre s s e s (x 8)
32 K B yte
1F7FFFh
1F0000h
64 K B yte
1E0000h
1EFFFFh
Total of 31
64 KByte Blocks
16 K B yte
1FFFFFh
1F0000h 64 K B yte
64 K B yte
003FFFh
000000h
Bottom Boot Block Addresses (x8)
32 K B yte
1EFFFFh
01FFFFh 64 K B yte
1E0000h
010000h
Total of 31
64 KByte Blocks
00FFFFh
008000h
8 KByte
8 KByte
1FBFFFh
1FA000h
1F9FFFh
1F8000h
8 KByte
8 KByte
007FFFh
006000h
005FFFh
004000h
AI06852_x16_160
8 K W ord
FFFFFh
FE000h
32 K W ord
0FFFFh
0
8000h
32 K W ord
07FFFh
0
0000h
Top B oot B loc k A ddress e s ( x1 6)
16 K W ord
FBFFFh
F8000h
32 K W ord
F0000h
F7FFFh
Total of 31
32 KWord Blocks
8 K W ord
FFFFFh
F8000h 32 K W ord
32 K W ord
01FFFh
00000h
Bott om Boot Block Addresses (x16)
16 K W ord
F7FFFh
0FFFFh 32 KW ord
F0000h
08000h
Total of 31
32 KWord Bloc
ks
07FFFh
04000h
4 K W ord
4 K W ord
F
DFFFh
F
D000h
F
CFFFh
FC000h
4 K W ord
4 K W ord
03FFFh
03000h
02FFFh
02000h
M29FxxxFT, M29FxxxFB Description
17/67
Figure 12. Block Addresses, M2 9F800 (x8)
Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses.
Figure 13. Block Addresses, M2 9F800 (x16)
Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses.
AI05463_x8_800
16 K B yte
FFFFFh
FC000h
64 K B yte
1FFFFh
10000h
64 K B yte
0FFFFh
00000h
Top B oot Block Address e s ( x8 )
32 K B yte
F7FFFh
F0000h
64 K B yte
E0000h
EFFFFh
Total of 15
64 KByte Blocks
16 K B yte
FFFFFh
F0000h 64 K B yte
64 K B yte
03FFFh
00000h
Bottom Boot Block Addresses (x8)
32 K B yte
EFFFFh
1FFFFh 64 KB yte
E0000h
10000h
Total of 15
64 KByte Blocks
0FFFFh
08000h
8 KByte
8 KByte
FBFFFh
FA000h
F9FFFh
F8000h
8 KByte
8 KByte
07FFFh
06000h
05FFFh
04000h
AI05464_x16_800
8 K W ord
7FFFFh
7E000h
32 K W ord
0FFFFh
0
8000h
32 K W ord
07FFFh
0
0000h
Top B oot B loc k A ddress e s ( x1 6)
16 K W ord
7BFFFh
78000h
32 K W ord
70000h
77FFFh
Total of 15
32 KWord Blocks
8 K W ord
7FFFFh
78000h 32 K W ord
32 K W ord
01FFFh
00000h
Bottom Boot Block Addresses (x16)
16 K W ord
77FFFh
0FFFFh 32 KW ord
70000h
08000h
Total of 15
32 KWord Bloc
ks
07FFFh
04000h
4 K W ord
4 K W ord
7
DFFFh
7
D000h
7
CFFFh
7C000h
4 K W ord
4 K W ord
03FFFh
03000h
02FFFh
02000h
Description M29FxxxFT, M29FxxxFB
18/67
Figure 14. Block Addresses, M2 9F400 (x8)
Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses.
Figure 15. Block Addresses, M2 9F400 (x16)
Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses.
AI05463_x8_400
16 K B yte
7FFFFh
7C000h
64 K B yte
1FFFFh
10000h
64 K B yte
0FFFFh
00000h
Top B oot Block Addre s s e s (x 8)
32 K B yte
77FFFh
70000h
64 K B yte
60000h
6FFFFh
Total of 7
64 KByte Blocks
16 K B yte
7FFFFh
70000h 64 K B yte
64 K B yte
03FFFh
00000h
Bottom Boot Block Addresses (x8)
32 K B yte
6FFFFh
1FFFFh 64 KB yte
60000h
10000h
Total of 7
64 KByte Blocks
0FFFFh
08000h
8 KByte
8 KByte
FBFFFh
7A000h
79FFFh
78000h
8 KByte
8 KByte
07FFFh
06000h
05FFFh
04000h
AI5464_x16_400
8 K W ord
3FFFFh
3E000h
32 K W ord
0FFFFh
0
8000h
32 K W ord
07FFFh
0
0000h
Top B oot B loc k A ddress e s ( x1 6)
16 K W ord
3BFFFh
38000h
32 K W ord
30000h
37FFFh
Total of 7
32 KWord Blocks
8 K W ord
3FFFFh
38000h 32 K W ord
32 K W ord
01FFFh
00000h
Bottom Boot Block Addresses (x16)
16 K W ord
37FFFh
0FFFFh 32 KW ord
30000h
08000h
Total of 7
32 KWord Bloc
ks
07FFFh
04000h
4 K W ord
4 K W ord
3
DFFFh
3
D000h
3
CFFFh
3C000h
4 K W ord
4 K W ord
03FFFh
03000h
02FFFh
02000h
M29FxxxFT, M29FxxxFB Description
19/67
Figure 16. Block Addresses, M2 9F200 (x8)
Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses.
Figure 17. Block Addresses, M2 9F200 (x16)
Also see Appendix Appendix A: Block Address Table for a full listing of the Block Addresses.
AI05463_x8_200
16 K B yte
3FFFFh
3C000h
64 K B yte
1FFFFh
10000h
64 K B yte
0FFFFh
00000h
Top B oot Block Addre s s e s (x 8)
32 K B yte
37FFFh
30000h
64 K B yte
20000h
3FFFFh
Total of 3
64 KByte Blocks
16 K B yte
2FFFFh
20000h 64 K B yte
64 K B yte
03FFFh
00000h
Bottom Boot Block Addresses (x8)
32 K B yte
2FFFFh
1FFFFh 64 KB yte
20000h
10000h
Total of 3
64 KByte Blocks
0FFFFh
08000h
8 KByte
8 KByte
3BFFFh
3A000h
39FFFh
38000h
8 KByte
8 KByte
07FFFh
06000h
05FFFh
04000h
AI05464_x16_200
8 K W ord
1FFFFh
1E000h
32 K W ord
0FFFFh
0
8000h
32 K W ord
07FFFh
0
0000h
Top B oot Block Addre s se s ( x1 6)
16 K W ord
3BFFFh
18000h
32 K W ord
10000h
17FFFh
Total of 3
32 KWord Blocks
8 K W ord
1FFFFh
18000h 32 K W ord
32 K W ord
01FFFh
00000h
Bottom Boot Block Addresses (x16)
16 K W ord
17FFFh
0FFFFh 32 KW ord
10000h
08000h
Total of 3
32 KWord Bloc
ks
07FFFh
04000h
4 K W ord
4 K W ord
1
DFFFh
1
D000h
3
CFFFh
1C000h
4 K W ord
4 K W ord
03FFFh
03000h
02FFFh
02000h
Signal Descriptions M29FxxxFT, M29FxxxFB
20/67
2 Signal Descriptions
See Figure 1.: Logic Diagram and Table 1.: Signal Names, for a brief overview of the signals
connected to this device.
2.1 Address Inputs (A0-A19)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller.
2.2 Data Inputs/Outputs (DQ0-DQ7)
The Data Inputs/Outputs output the da ta stored at the selected address during a Bus Read
operation. During Bus W rite operations th ey represent the comma nds sent to the Command
Interface of the Program/Erase Controller.
2.3 Data Inputs/Outputs (DQ8-DQ14)
The Data Inputs/Outputs output the da ta stored at the selected address during a Bus Read
operation when BYTE is High, VIH. When BYTE is Low, VIL, these p ins are not used and are
high impedance. During Bus Write operations the Command Reg ister does not use these
bits. When reading the Status Register these bits should be ignored.
2.4 Data Input/Output or Address Input (DQ15A-1)
When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the
LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout
the text consider references to the Data Input/Output to include this pin when BYTE is High
and references to the Address Inputs to include this pin when BYTE is Low except when
stated explicitly otherwise.
2.5 Chip Enable
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, VIH, all other pin s ar e ign or ed.
2.6 Output Enable
The Output Enable, G, controls the Bus Read operation of the memory.
M29FxxxFT, M29FxxxFB Signal Descriptions
21/67
2.7 Write Enable
The Wr ite Enable, W, controls the Bus Write operation of the m emory’s Command Interface.
2.8 Reset/Block Temporary Unpr otect
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.
A Hardware Reset is achieved by hold ing Reset/Block Temporary Unprotect Low, VIL, for at
least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be
ready for Bus Read and Bus Write opera tion s after tPHEL or tRHEL, whichever occurs last.
See the Ready/Busy Output section, Table 18.: Reset/Block Temporary Unprotect AC
Characteristics and Figure 23.: Reset/Block Temporary Unprotect AC Waveforms.
Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program
and Erase operations on all blocks will be possible. The transition from VIH to VID must be
slower than tPHPHH.
2.9 Ready/Busy Output
The Ready/Busy pin is an open-drain outpu t tha t can be used to identify when the de vice is
performing a Program or Erase operation. During Pro gram or Erase operatio ns Ready/Busy
is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and
Erase Suspend mode.
After a Ha rdware Reset, Bus Read and Bus W rite operations cannot b egin until Ready/Busy
becomes high-impedance. See Table 18.: Reset/Block Temporary Unprotect AC
Characteristics and Figure 23.: Reset/Block Temporary Unprotect AC Waveforms.
The use of an open-drain outp ut allows the Ready/Busy pins from se veral memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.10 Byte/Word Organization Select
The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus
modes of the memory. When Byte/Word Organization Se lect is Low, VIL, the memory is in 8-
bit mode, when it is High, VIH, the memory is in 16-bit mode.
2.11 VCC Supply Voltage
The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disa bled when the VCC Supply Voltage is less than the Lockout
Voltage, VLKO. This prevents Bus Write operations from accidentally da maging the data
during power up, power down an d power surges. If the Program/Erase Controller is
programming or e rasing during th is time then the oper ation aborts a nd the memory conten ts
being altered will be invalid.
Signal Descriptions M29FxxxFT, M29FxxxFB
22/67
A 0.1µF capacitor should be connected between the VCC Supply Vo ltage pin and th e VSS
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during program and erase operations, ICC3.
2.12 VSS Ground
The VSS Ground is the reference for all voltage measurements. The two VSS pins of the
device must be connected to the system ground.
M29FxxxFT, M29FxxxFB Bus Operations
23/67
3 Bus Operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See Table 2.: Bus Operations,
BYTE = VIL and Table 3.: Bus Operations, BYTE = VIH for a summary. Typically glitches of
less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect
bus operation s.
3.1 Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desir ed address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write
Enable High, VIH. The Data Inputs/Output s will output the value, see Figure 20.: Read Mode
AC Waveforms and Table 15.: Read AC Characteristics, for details of when the output
becomes valid.
3.2 Bus Write
Bus Write oper ations write to the Command Interface. A valid Bus Write operat ion begins by
setting the desired address on the Address Inputs. The Address Inputs ar e latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole Bus Write operation. See the following figures and tables:
Figure 21.: Write AC Waveforms, Write Enable Controlled
Figure 22.: Write AC Waveforms, Chip Enable Controlled,
Table 16.: Write AC Characteristics, Write Enable Controlled
Table 17.: Write AC Characteristics, Chip Enable Controlled.
3.3 Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4 Standby
When Chip Enable is High, VIH, the memory ent er s Stan dby mo d e an d th e Da ta
Inputs/Outpu ts pins are placed in the high -impedance st ate. To reduce th e Supply Current to
the Standby Supply Curre nt, ICC2, Chip Enable should be held within VCC ± 0. 2V. For the
Standby current level see Table 14.: DC Characteristics.
During program or erase operations the memory wil l continue to use the Program/Erase
Supply Current, ICC3, for Program or Er ase operations until the operation completes.
Bus Operations M29FxxxFT, M29FxxxFB
24/67
3.5 Automatic Standby
If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or
more the memory ente rs Automatic S tand by where the internal Supply Cu rrent is reduced to
the Standby Supply Curre nt, ICC2. The Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
3.6 Special Bus Operations
Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require VID to be
applied to some pins.
3.7 Electronic Signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Table 2.:
Bus Operations, BYTE = VIL and Table 3.: Bus Operations, BYTE = VIH.
3.8 Block Protection and Block Unprotection
Each block can be separately pr ot ec ted ag ain st ac cid en tal Program or Eras e. Prote ct ed
blocks can be unprotected to allow data to be changed.
There are two methods available for protecting and unprotecting the blocks, one for use on
programming equipment and the other for in-system use. Block Protect and Blocks
Unprotect operations are describ ed in Appendix C: Block protection.
M29FxxxFT, M29FxxxFB Bus Operations
25/67
Table 2. Bus Operations, BYTE = VIL
X = VIL or VIH.
Table 3. Bus Operations, BYTE = VIH
X = VIL or VIH.
Operation E G W Address Inputs
DQ15A–1, A0-A19
Data Inp uts/Outpu ts
DQ14-DQ8 DQ7-DQ0
Bus Read VIL VIL VIH Cell Address Hi-Z Data Output
Bus Write VIL VIH VIL Command Address Hi-Z Data Input
Output Disable X VIH VIH X Hi-Z Hi-Z
Standby VIH X X X Hi-Z Hi-Z
Read
Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH Hi-Z 0x01
Read Device
Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH Hi-Z
0x51 (M29F200FT)
0x57 (M29F200FB)
0x23 (M29F400FT)
0xAB (M29F400FB)
0xD6 (M29F800FT)
0x58 (M29F800FB)
0xD2 (M29F160FT)
0xD8 (M29F160FB)
Operation E G W Address Inputs
A0-A19 Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Bus Read VIL VIL VIH Cell Address Data Output
Bus Write VIL VIH VIL Command Address Data Input
Output Disable X VIH VIH XHi-Z
Standby VIH XXX Hi-Z
Read
Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 =
VID, Others VIL or VIH 0x01
Read Device
Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 =
VID, Others VIL or VIH
0x2251 (M29F200FT)
0x2257 (M29F200FB)
0x2223 (M29F400FT)
0x22AB (M29F400FB)
0x22D6 (M29F800FT)
0x2258 (M29F800FB)
0x22D2 (M29F160FT)
0x22D8 (M29F160FB)
Command Interface M29FxxxFT, M29FxxxFB
26/67
4 Command Interface
All Bus Write operations to the memory are interpreted by the Command Interf ace.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-
bit or 8-bit mode. See either Table 4.: Commands, 16-bit mode, BYTE = VIH, or Table 5.:
Commands, 8-bit mode, BYTE = VIL, depending on the configur ation that is being used, for
a summary of the commands.
4.1 Read/Reset Command
The Read/Reset command returns the memory to its Read mode where it behaves like a
ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register.
Either one or three Bus Write operations can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to read mode. Once the progr am or erase
operation has started the Read/Reset command is no longer accepted. The Read/Reset
command will not abort an Erase operation when issued while in Erase Suspend.
4.2 Auto Select Command
The Auto Select comma nd is used to read the Man ufacturer Code, the Device Code and the
Block Protection Status. Three consecutive Bus Write operations are required to issue the
Auto Select command. Once the Auto Select command is issued the memory remains in
Auto Select mode until a Read/Reset command is issu ed. Read CFI Query and Read/Reset
commands are accepted in Auto Select mode, all other commands are ignored.
From the Auto Select mode the Manufacturer Code can be read using a Bus Read
operation with A0 = VIL and A1 = V IL. The ot her addr ess bit s may b e set to either VIL or VIH.
The Manufacturer Code for Numonyx is 0001h.
The Device Code can be read using a Bu s Read ope ratio n with A0 = VIH and A1 = VIL. Th e
other addre ss bits may be set to eith er VIL or VIH.
The Block Protection Status of each block can be read using a Bus Read operation with A0
= VIL, A1 = VIH, and A12-A19 specifying the address of the block. The other address bi ts
may be set to either VIL or VIH. If the addressed block is protected then 01h is output on
Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.
4.3 Program Command
The Program command can be used to program a value to one address in the memory
array at a time. The com m an d req uir es four Bus Write opera tion s, the fin al writ e op era tion
latches the add ress an d da ta, and starts the Program/Erase Controller.
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error conditio n is given.
M29FxxxFT, M29FxxxFB Command Interface
27/67
During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. Typical program times are given in
Table 6.: Program/Erase Times and Program/Erase Endurance Cycles, M29F160F. Bus
Read operations during the program operation will output the Status Register on the Data
Inputs/Outputs. See the section on the Status Register for more details.
After the program operation has completed the memory returns to the Read mode, unless
an error has occurred. When an error occurs the memory continues to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read mode.
Note that the Program co mmand canno t chang e a bit set at ’0’ b ack to ’1’. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
4.4 Unlock Bypass Command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memor y. When the access time to the device is long (as with
some EPROM programmers) considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in Read mode.
4.5 Unlock Bypass Program Command
The Unlock Bypass Prog ram command can be used to program one address in memory at
a time. The command requires two Bus W rite operations, the final write operation latches
the address and data, and starts the Program/Erase Controller.
The Program operation u sing the Unlock Bypass Program command behaves identically to
the Program operation using the Program command. A protected block cannot be
programmed; the ope ration cannot be aborted and the Status Register is read. Errors must
be reset using the Read/Reset command, which leaves the device in Unlock Byp ass Mode.
See the Program co mmand for details on the behavior.
4.6 Unlock Bypass Reset Command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass Mode.
4.7 Chip Erase Command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase Command and start the Program/Erase Controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
Command Interface M29FxxxFT, M29FxxxFB
28/67
within about 10 0µs, leaving the d ata unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands. It is not possible to issue
any command to abort the operation. Typical chip erase times are given in Table 6.:
Program/Erase Times and Program/Erase Endurance Cycles, M29F160F. All Bus Read
operations during the Chip Erase operation will output the Status Register on the Data
Inputs/Outputs. See the section on the Status Register for more details.
After the Chip Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read Mode.
The Chip Erase Command set s all of the bi ts in unprotected blocks of the memory to ’1’. All
previous data is lost.
4.8 Block Erase Command
The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write
operations are requir ed to select the first block in the list. Each ad ditional block in the list can
be selected by repeating the sixth Bus Write operation using the address of the additional
block. The Block Erase operation starts the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Prog ra m/Er ase Controller starts it is not possible to
select any more blocks. Each additional block must therefore be sele cted within 50 µs of the
last block. The 50 µs timer rest art s when an ad ditional block is selected . The Status Register
can be read after the sixth Bus Write operation. See the Status Register section for details
on how to identify if the Program/Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are igno red and all the othe r selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100µs, leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command. Typical block erase times are given in Table 6.: Program/Erase Times
and Program/Erase Endurance Cycles, M29F160F. All Bus Read operations during the
Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the
section on the Status Register for more details.
After the Block Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the select ed bl oc ks is lost.
4.9 Erase Suspend Command
The Erase Suspend Command may be used to tempora rily suspend a Block Erase
operation and return the memor y to Read mode. The command requires one Bus Write
operation.
M29FxxxFT, M29FxxxFB Command Interface
29/67
The Program/Erase Controller will suspend within the Erase Suspend Latency Time (refer to
Table 6.: Program/Erase Times and Program/Erase Endurance Cycles, M29F160F for
value) of the Erase Suspend Command being issued. Once the Program/Erase Controller
has stopped the memory will be set to Read mode and the Erase will be suspended. If the
Erase Suspend command is issued during the period when the memory is waiting for an
additional block (before the Program/Erase Controller starts) then the Erase is suspended
immediately and will start immediately when the Erase Resume Command is issued. It is
not possible to select any further blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any
attempt is made to program in a protected block or in the suspended block then the Program
command is ignored and the data remains unchanged. The Status Register is not read and
no error condition is given. Reading from blocks that are being erased will output the S t atus
Register.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypa ss co mmands
during an Erase Suspend. The Read/Reset command must be issued to return the device to
Read Array mode before the Resume command will be accepted.
4.10 Erase Resume Command
The Erase Resume command must be used to restart the Program/Erase Controller from
Erase Suspend. An erase can be suspended and resumed more than once.
4.11 Read CFI Query Command
The Read CFI Query Command is used to read data from the Common Flash Interface
(CFI) Memory Area. This command is valid when the device is in the Read Array mode, or
when the device is in Auto Select mode.
One Bus Write cycle is required to issue the Read CFI Query Command. Once the
command is issued subsequent Bus Read operations read from the Common Flash
Interface Memory Area.
The Read/Reset command must be issued to return the device to the previous mode (the
Read Array mode o r Auto Sele ct mode). A secon d Read/Reset command would b e needed
if the device is to be put in the Read Array mode from Auto Select mode.
See Appendix B: Common Flash Interface (CFI) and the following tables for details on the
information contained in the Common Flash Interface (CFI) memory area.
Tab le 31 .: Que ry Structure Overview ,
Table 32.: CFI Query Identification String,
Table 33.: CFI Query System Interface Information,
Table 34.: Device Geometry Definition,
Table 35.: Primary Algorithm-Specific Extended Query Table
Table 36.: Security Code Area
Command Interface M29FxxxFT, M29FxxxFB
30/67
Table 4. Commands, 16-bit mode, BYTE = VIH
X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
Command Interface: only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Read/Reset: After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select: After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase: After these commands read the Status Register until the
Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks dur ing Block Erase
Command with additional Bus Write Operations until Timeout Bit is set.
Unlock Bypass: After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset: After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend: After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and
Program commands on non-erasing blocks as normal.
Erase Resume: After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the
Program/Erase Controller completes and the memory returns to Read Mode.
CFI Query: Command is valid when device is ready to read array data or when device is in Auto Select mode.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Addr Addr Addr Addr Addr Addr Addr Addr Addr Addr Addr
Read/Reset 1X F0
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program 2 X A0 PA PD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 55 98
M29FxxxFT, M29FxxxFB Command Interface
31/67
Table 5. Commands, 8-bit mode, BYTE = VIL
X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
Command Interface: only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Read/Reset: After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select: After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase: After these commands read the Status Register until the
Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks dur ing Block Erase
Command with additional Bus Write Operations until Timeout Bit is set.
Unlock Bypass: After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset: After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend: After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and
Program commands on non-erasing blocks as normal.
Erase Resume: After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the
Program/Erase Controller completes and the memory returns to Read Mode.
CFI Query: Command is valid when device is ready to read array data or when device is in Auto Select mode.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1X F0
3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass
Program 2 X A0 PA PD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 AA 98
Command Interface M29FxxxFT, M29FxxxFB
32/67
Table 6. Program/Erase Times and Program/Erase Endurance Cycles, M29F160F
Typical values are measured at room temperature and nominal voltages; typical and maximum values are samples, not 100%
tested.
Chip Erase, Program, and Chip Program parameters: Maximum value measured at worst case conditions for both temperature
and VCC after 100,000 program/erase cycles.
Block Erase and Erase Suspend Latency parameters: Maximum value measured at worst case conditions for both temperature
and VCC.
Table 7. Program/Erase Times and Program/Erase Endurance Cycles, M29F800F
Typical values are measured at room temperature and nominal voltages; typical and maximum values are samples, not 100%
tested.
Chip Erase, Program, and Chip Program parameters: Maximum value measured at worst case conditions for both temperature
and VCC after 100,000 program/erase cycles.
Block Erase and Erase Suspend Latency parameter: Maximum value measured at worst case conditions for both temperature
and VCC.
Parameter Min Typical Max Unit
Chip Erase — 25 120 s
Block Erase (64 KBytes) — 0.8 6 s
Erase Suspend Latency Time — 20 25 µs
Program (Byte or Word) — 11 200 µs
Chip Program (Byte by Byte) — 24 120 s
Chip Program (Word by Word) — 12 60 s
Program/Erase Cycles (per Block) 100,000 — — cycles
Data Retention 20 — — years
Parameter Min Typical Max Unit
Chip Erase — 12 60 s
Block Erase (64 KBytes) — 0.8 6 s
Erase Suspend Latency Time — 20 25 µs
Program (Byte or Word) — 11 200 µs
Chip Program (Byte by Byte) — 12 — s
Chip Program (Word by Word) — 6 30 s
Program/Erase Cycles (per Block) 100,000 — — cycles
Data Retention 20 — — years
M29FxxxFT, M29FxxxFB Command Interface
33/67
Table 8. Program/Erase Times and Program/Erase Endurance Cycles, M29F400F
Typical values are measured at room temperature and nominal voltages; typical and maximum values are samples, not 100%
tested.
Chip Erase, Program, and Chip Program parameters: Maximum value measured at worst case conditions for both temperature
and VCC after 100,000 program/erase cycles.
Block Erase and Erase Suspend Latency parameter: Maximum value measured at worst case conditions for both temperature
and VCC.
Table 9. Program/Erase Times and Program/Erase Endurance Cycles, M29F200F
Typical values are measured at room temperature and nominal voltages; typical and maximum values are samples, not 100%
tested.
Chip Erase, Program, and Chip Program parameters: Maximum value measured at worst case conditions for both temperature
and VCC after 100,000 program/erase cycles.
Block Erase and Erase Suspend Latency parameter: Maximum value measured at worst case conditions for both temperature
and VCC.
Parameter Min Typical Max Unit
Chip Erase — 6 30 s
Block Erase (64 KBytes) — 0.8 6 s
Erase Suspend Latency Time — 20 25 µs
Program (Byte or Word) — 11 200 µs
Chip Program (Byte by Byte) — 6 — s
Chip Program (Word by Word) — 3 15 s
Program/Erase Cycles (per Block) 100,000 — — cycles
Data Retention 20 — — years
Parameter Min Typical Max Unit
Chip Erase — 3 15 s
Block Erase (64 KBytes) — 0.8 6 s
Erase Suspend Latency Time — 20 25 µs
Program (Byte or Word) — 11 200 µs
Chip Program (Byte by Byte) — 4 — s
Chip Program (Word by Word) — 2 8 s
Program/Erase Cycles (per Block) 100,000 — — cycles
Data Retention 20 — — years
Status Register M29FxxxFT, M29FxxxFB
34/67
5 Status Register
Bus Read operations from any address always read the Status Register during Program
and Erase operations. It is also read du ring Erase Suspe nd when an add ress within a block
being erased is accessed.
The bits in the Status Register are summarized in Table 10.: Status Register Bits.
5.1 Data Polling Bit
The Data Polling Bit (DQ7) can be used to identify whether the Program/Erase Controller
has successfully completed its operation or if it has responded to an Erase Suspend. The
Data Polling Bit is output on DQ7 when the Status Register is read.
During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.
During Erase operations the Dat a Polling Bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
Mode.
In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase operation.
Figure 1. Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A
Valid Address is the address being programmed or an address within the block being
erased.
5.2 Toggle Bit
The Toggle Bit (DQ6) can be used to identify whether the Program/Er ase Controller has
successfully completed its operation or if it has respon ded to an Erase Suspend. The Toggle
Bit is output on DQ6 when the Status Register is read.
During Program and Erase op erations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After succe ssf ul com p let ion of the
operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block
being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.
If any attempt is made to erase a protected block, the operation is aborted, no error is
signalled and DQ6 toggles for approximately 100µs. If any attempt is made to program a
protected block or a suspended block, the operation is aborted, no error is signalled and
DQ6 toggles for ap p ro xim at ely 1µs .
Figure 2. Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.
M29FxxxFT, M29FxxxFB Status Register
35/67
5.3 Error Bit
The Error Bit (DQ5) can be used to identify errors detected by the Program/Erase Controller .
The Error Bit is set to ’1’ when a Progr am, Block Erase or Chip Erase operation fails to write
the correct data to the memory. If the Error Bit is set a Read/Reset command must be
issued before other commands are issued. The Error bit is output on DQ5 when the Status
Register is read.
Note that the Prog ra m command cann ot cha nge a b it se t to ’0’ b ack to ’1’ and attemp tin g to
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’
5.4 Erase Timer Bit
The Erase Timer Bit (DQ3) can be used to identify the start of Program/Erase Controller
operation during a Block Erase command. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the
Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the
Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is
read.
5.5 Alternative Toggle Bit
The Alternative Toggle Bit (DQ2) can be used to monitor the Program/Erase controller
during Erase ope rations. The Alternative Toggle Bit is output on DQ2 when the Status
Register is read.
During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations from addresses within the blocks being erased.
A protected block is treated the sa me as a block not being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.
After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle Bit does not change if
the addresse d blo ck has er as ed cor re ctly.
Status Register M29FxxxFT, M29FxxxFB
36/67
Table 10. Status Register Bits
Unspecified data bits should be ignored.
Figure 1. Data Polling Flowchart
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle 0 – – 0
Program During
Erase Suspend Any Address DQ7 Toggle 0 – – 0
Program Error Any Address DQ7 Toggle 1 – – 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout
Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No
Toggle 0
Block Erase Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No
Toggle 0
Erase Suspend Erasing Block 1 No
Toggle 0 – Toggle 1
Non-Erasing Block Data read as normal 1
Erase Error
Good Block
Address 0 Toggle 1 1 No
Toggle 0
Faulty Block
Address 0 Toggle 1 1 Toggle 0
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
at VALID ADDRESS
FAIL PASS
AI03598
DQ7
=
DATA YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA YES
NO
M29FxxxFT, M29FxxxFB Status Register
37/67
Figure 2. Data Toggle Flowchart
READ DQ6
START
READ DQ6
TWICE
FAIL PASS
AI01370C
DQ6
=
TOGGLE NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 & DQ6
Maximum Rating M29FxxxFT, M29FxxxFB
38/67
6 Maximum Rating
Stressing the device above t he rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the de vice at th ese or an y ot he r con d itio ns abo ve thos e ind i ca te d in th e
Operating sections of this specification is not implied. Refer als o to the Numony x SURE
Program and other relevant quality docum ents.
Table 11. Absolute Maximum Ratings
Input or Output Voltage parameter: Minimum voltage may undershoot to –2V during transition and for less than
20ns during transitions.
Input or Output Voltage parameter: Maximum voltage may overshoot to VCC +2V during transition and for less
than 20ns during transitions.
Symbol Parameter Min Max Unit
TBIAS Temperature Under Bias –50 125 °C
TSTG Storage Temperature –65 150 °C
VIO Input or Output Voltage –0.6 VCC +0.6 V
VCC Supply Voltage –0.6 6 V
VID Identification Voltage –0.6 13.5 V
M29FxxxFT, M29FxxxFB DC and AC Parameters
39/67
7 DC and AC Para meters
This section summa riz es th e op e ratin g me as ur em e nt condit ion s, an d the DC an d AC
characterist ics of th e de vice. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions shown here.
Designers should check that the operating conditions in their circui t match the operating
conditions when relying on the quoted parameters.
Table 12. Operating and AC Measurement Conditions
Figure 18. AC Measurement I/O Waveform
Figure 19. AC Measurement Load Circuit
Parameter Min Max Unit
VCC Supply Voltage 4.5 5.5 V
Ambient Operating Temperature –40 125 °C
Load Capacitance (CL) 3030pF
Input Rise and Fall Times — 5 ns
Input Pulse Voltages 0 to VCC 0 to VCC V
Input and Output Ti ming Ref. Voltages VCC/2 VCC/2 V
AI04498
VCC
0V
VCC/2
AI0449
9
CL
CL includes JIG capacitance
DEVICE
UNDER
TEST
25kΩ
VCC
25kΩ
VCC
0.1µF
DC and AC Parameters M29FxxxFT, M29FxxxFB
40/67
Table 13. Device Capacitance
Sampled only, not 100% tested.
Table 14. DC Characteristics
Supply Current (Program/Erase) parameter: Sampled only, not 100% tested.
Figure 20. Read Mode AC Waveforms
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacit ance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 12 pF
Symbol Parameter Test Condition Min Typ Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ——±1µA
ILO Output Leakage
Current 0V ≤ VOUT ≤ VCC ——±1µA
ICC1 Supply Current (Read) E = VIL, G = VIH,
f = 6MHz —7 20mA
ICC2 Supply Current
(Standby) E = VCC ±0.2V,
RP = VCC ±0.2V — 60 120 µA
ICC3 Supply Current
(Program/Erase) Program/Erase
Controller active ——30mA
VIL Input Low Voltage — –0.5 — 0.8 V
VIH Input High Voltage — 0.7VCC —V
CC +0.3 V
VOL Output Low Voltage IOL = 1.8mA — — 0.45 V
VOH Output High Voltage IOH = –100µAV
CC –0.4 — — V
VID Identification Voltage 11.5 — 12.5 V
IID Identification Current A9 = VID — — 100 µA
VLKO
Program/Erase
Lockout Supply
Voltage — 1.8 — 2.3 V
AI02922
tAVAV
tAVQV tAXQX
tELQX tEHQZ
tGLQV
tGLQX tGHQX
VALID
A0-A19/
A–1
G
DQ0-DQ7/
DQ8-DQ15
E
tELQV tEHQX
tGHQZ
VALID
tBHQV
tELBL/tELBH tBLQZ
BYTE
M29FxxxFT, M29FxxxFB DC and AC Parameters
41/67
Table 15. Read AC Characteristics
tELQX tGLQX tEHQZ and tGHQZ parameters: Sampled only, not 100% tested.
Figure 21. Write AC Waveforms, Write Enable Controlled
Symbol Alt Parameter Test Cond ition M29F160F Unit
55/5A
tAVAV tRC Address Valid to Next Address
Valid E = VIL,
G = VIL Min 55 ns
tAVQV tACC Address Valid to Output Valid E = VIL,
G = VIL Max 55 ns
tELQX tLZ Chip Enable Low to Output
Transition G = VIL Min 0 ns
tELQV tCE Chip Enable Low to Output Valid G = VIL Max 55 ns
tGLQX tOLZ Output Enable Low to Output
Transition E = VIL Min 0 ns
tGLQV tOE Output Enable Low to Output Valid E = VIL Max 20 ns
tEHQZ tHZ Chip Enable High to Output Hi-Z G = VIL Max 15 ns
tGHQZ tDF Output Enable High to Output Hi-Z E = VIL Max 15 ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or
Address Transition to Output
Transition —Min0 ns
tELBL
tELBH
tELFL
tELFH Chip Enable to BYTE Low or High — Max 3 ns
tBLQZ tFLQZ BYTE Low to Output Hi-Z — Max 15 ns
tBHQV tFHQV BYTE High to Output Va lid — Max 20 ns
AI02923
E
G
W
A0-A19/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHEL
tWHEH
tWHWL
tELWL
tAVWL
tWHGL
tWLAX
tWHDX
tAVAV
tDVWH
tWLWHtGHWL
RB
tWHRL
DC and AC Parameters M29FxxxFT, M29FxxxFB
42/67
Table 16. Write AC Characteristics, Write Enable Controlled
tWHRL parameter: Sampled only, not 100% tested.
Figure 22. Write AC Waveforms, Chip Enable Controlled
Symbol Alt Parameter M29F160F Unit
55/5A
tAVAV tWC Address Valid to Next Address Valid Min 55 ns
tELWL tCS Chip Enable Low to Write Enable Low Min 0 ns
tWLWH tWP Write Enable Low to Write Enable High Min 30 ns
tDVWH tDS Input Valid to Write Enable High Min 20 ns
tWHDX tDH Write Enable High to Input Transition Min 0 ns
tWHEH tCH Write Enable High to Chip Enable High Min 0 ns
tWHWL tWPH Write Enable High to Write Enable Low Min 15 ns
tAVWL tAS Address Valid to Write Enable Low Min 0 ns
tWLAX tAH Write Enable Low to Address Transition Min 30 ns
tGHWL Output Enable High to Write Enable Low Min 0 ns
tWHGL tOEH Write Enable High to Output Enable Low Min 0 ns
tWHRL tBUSY Program/Erase Va lid to RB Low Max 20 ns
tVCHEL tVCS VCC High to Chip Enable Low Min 50 µs
AI02924
E
G
W
A0-A19/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHWL
tEHWH
tEHEL
tWLEL
tAVEL
tEHGL
tELAX
tEHDX
tAVAV
tDVEH
tELEHtGHEL
RB
tEHRL
M29FxxxFT, M29FxxxFB DC and AC Parameters
43/67
Table 17. Write AC Characteristics, Chip Enable Controlled
tEHRL parameter: Sampled only, not 100% tested.
Figure 23. Reset/Block Temporary Unprotect AC Waveforms
Symbol Alt Parameter M29F160F Unit
55/5A
tAVAV tWC Address Valid to Next Address Valid Min 55 ns
tWLEL tWS Write Enable Low to Chip Enable Low Min 0 ns
tELEH tCP Chip Enable Low to Chip Enable High Min 30 ns
tDVEH tDS Input Valid to Chip Enable High Min 20 ns
tEHDX tDH Chip Enable High to Input Transition Min 0 ns
tEHWH tWH Chip Enable High to Write Enable High Min 0 ns
tEHEL tCPH Chip Enable High to Chip Enable Low Min 15 ns
tAVEL tAS Ad dress Valid to Chip Enable Low Min 0 ns
tELAX tAH Chip Enable Low to Address Transition Min 30 ns
tGHEL Output Enable High Chip Enable Low Min 0 ns
tEHGL tOEH Chip Enable High to Output Enable Low Min 0 ns
tEHRL tBUSY Program/Erase Valid to RB Low Max 20 ns
tVCHWL tVCS VCC High to Write Enable Low Min 50 µs
AI02931B
RB
W,
RP tPLPX
tPHWL, tPHEL, tPHGL
tPLYH
tPHPHH
E, G
tRHWL, tRHEL, tRHGL
DC and AC Parameters M29FxxxFT, M29FxxxFB
44/67
Table 18. Reset/Block Temporary Unprotect AC Characterist ics
tPHWL tPHGL tRHWL tRHEL tRHGL tPLYH and tPHPHH parameters: Sampled only, not 100% tested.
Symbol Alt Parameter M29F160F Unit
55/5A
tPHWL
tPHEL
tPHGL
tRH RP High to Write Enable Low, Chip Enable
Low, Output Enable Low Min 50 ns
tRHWL
tRHEL
tRHGL
tRB RB High to Write Enable Low, Chip Enable
Low, Output Enable Low Min 0 ns
tPLPX tRP RP Pulse Width Min 500 ns
tPLYH tREADY RP Low to Read Mode Max 10 µs
tPHPHH tVIDR RP Rise Time to VID Min 500 ns
M29FxxxFT, M29FxxxFB Package Mechanical
45/67
8 Package Mechanical
Figure 24. TSOP48 – 48 lead Plastic Thin Small Outlin e, 12 x 20mm, Package
Outline, top view
Drawing is not to scale.
Table 19. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package
Mechanical Data
Symbol millimeters
Typ Min Max
A1.200
A1 0.100 0.050 0.150
A2 1.000 0.950 1.050
B 0.220 0.170 0.270
C 0.100 0.210
CP 0.080
D1 12.000 11.900 12.100
E 20.000 19.800 20.200
E1 18.400 18.300 18.500
e0.500 – –
L 0.600 0.500 0.700
L1 0.800
a3 0 5
TSOP-G
B
e
DIE
C
LA1 α
E1
E
A
A2
1
24
48
25
D1
L1
CP
Package Mechanical M29FxxxFT, M29Fxxx FB
46/67
Figure 25. SO44 – 44 lead plastic small outline, 500 mils bod y wid th, package outline
Table 20. SO44 - 44 lead Plastic Small Outline, 500 mils body width, package
mechanical data
Symbol millimeters
Typ Min Max
A3.00
A1 0.10
A2 2.69 2.56 2.79
b 0.35 0.50
c 0.18 0.28
D 28.50 28.37 28.63
ddd 0.10
E 16.03 15.77 16.28
E1 12.60 12.47 12.73
e1.27––
L0.79
L1 1.73
Θ8°
N44
E1
44
e
D
c
E
122
23
b
SO-F
LA1
A
ddd
A2
θ
L1
M29FxxxFT, M29FxxxFB Package Mechanical
47/67
Figure 26. TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package outline
Table 21. TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package mechanical
data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.260 0.0102
A2 0.900 0.0354
b 0.350 0.450 0.0138 0.0177
D 6.000 5.900 6.100 0.2362 0.2323 0.2402
D1 4.000 – – 0.1575 – –
ddd 0.100 0.0039
E 8.000 7.900 8.100 0.3150 0.3110 0.3189
E1 5.600 – – 0.2205 – –
e 0.800 – – 0.0315 – –
FD 1.000 – – 0.0394 – –
FE 1.200 – – 0.0472 – –
SD 0.400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –
E1E
D1
D
eb
A2
A1
A
BGA-Z32
ddd
FD
FE SD
SE
e
BALL "A1"
Part Numbering M29FxxxFT, M29FxxxFB
48/67
9 Part Numbering
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (S peed, Package, etc.) or for further information on any aspect
of this device, pleas e contact the Numony x Sales Office nearest to you.
Table 22. Information scheme
Example: M29F200F T 5A M 6 - 2
Device type
M29F = 5 V
Density
200 = 2-Mbit
400 = 4-Mbit
800 = 8-Mbit
160 = 16-Mbit (not available in SO44 package)
Technology
F = 110 nm
Configuration
T = Top Boot
B = Bottom Boot
Speed
55 = 55 ns device speed in conjunction with
temperature range = 3 denotes Auto Grade –40 to
125 °C parts
5A = 55 ns Access time (Auto Grade) only in
conjunction with the Grade 6 option
Package
M = SO 44.525 INCH CU
N = TSOP-1 48 12 x 20 AL 4
ZA(1) = TFBGA48, 6 x 8 mm, 0.80 mm pitch
1. THis package is available only in the 8-Mbit, bottom boot configuration.
Temperature range
6 = –40 to 85 °C
3 = –40 to 125 °C
Packing option
<blank> = standard packing (Tra y)
T = Tape & Reel 24 mm packing
E = RoHS package, standar d p acking (Tray)
F = RoHS package, Tape & Reel 24 mm packing
Fab location
2 = Numonyx Fab.2 (Singapore)
M29FxxxFT, M29FxxxFB Block Address Table
49/67
Appendix A Block Address Table
Table 23. Top Boot Block Addresses, M29F160FT
#Size
(KBytes) Address Range
(x8) Address Range
(x16)
34 16 1FC000h-1FFFFFh FE000h-FFFFFh
33 8 1FA000h-1FBFFFh FD000h-FDFFFh
32 8 1F8000h-1F9FFFh FC000h-FCFFFh
31 32 1F0000h-1F7FFFh F8000h-FBFFFh
30 64 1E0000h-1EFFFFh F0000h-F7FFFh
29 64 1D0000h-1DFFFFh E8000h-EFFFFh
28 64 1C0000h-1CFFFFh E0000h-E7FFFh
27 64 1B0000h-1BFFFFh D8000h-DFFFFh
26 64 1A0000h-1AFFFFh D0000h-D7FFFh
25 64 190000h-19FFFFh C8000h-CFFFFh
24 64 180000h-18FFFFh C0000h-C7FFFh
23 64 170000h-17FFFFh B8000h-BFFFFh
22 64 160000h-16FFFFh B0000h-B7FFFh
21 64 150000h-15FFFFh A8000h-AFFFFh
20 64 140000h-14FFFFh A0000h-A7FFFh
19 64 130000h-13FFFFh 98000h-9FFFFh
18 64 120000h-12FFFFh 90000h-97FFFh
17 64 110000h-11FFFFh 88000h-8FFFFh
16 64 100000h-10FFFFh 80000h-87FFFh
15 64 0F0000h-0FFFFFh 78000h-7FFFFh
14 64 0E0000h-0EFFFFh 70000h-77FFFh
13 64 0D0000h-0DFFFFh 68000h-6FFFFh
12 64 0C0000h-0CFFFFh 60000h-67FFFh
11 64 0B0000h-0BFFFFh 58000h-5FFFFh
10 64 0A0000h-0AFFFFh 50000h-57FFFh
9 64 090000h-09FFFFh 48000h-4FFFFh
8 64 080000h-08FFFFh 40000h-47FFFh
7 64 070000h-07FFFFh 38000h-3FFFFh
6 64 060000h-06FFFFh 30000h-37FFFh
5 64 050000h-05FFFFh 28000h-2FFFFh
4 64 040000h-04FFFFh 20000h-27FFFh
3 64 030000h-03FFFFh 18000h-1FFFFh
2 64 020000h-02FFFFh 10000h-17FFFh
1 64 010000h-01FFFFh 08000h-0FFFFh
0 64 000000h-00FFFFh 00000h-07FFFh
Block Address Table M29FxxxFT, M29FxxxFB
50/67
Table 24. Bottom Boot Block Addresses, M29F160FB
#Size
(KBytes) Address Range
(x8) Address Range
(x16)
34 64 1F0000h-1FFFFFh F8000h-FFFFFh
33 64 1E0000h-1EFFFFh F0000h-F7FFFh
32 64 1D0000h-1DFFFFh E8000h-EFFFFh
31 64 1C0000h-1CFFFFh E0000h-E7FFFh
30 64 1B0000h-1BFFFFh D8000h-DFFFFh
29 64 1A0000h-1AFFFFh D0000h-D7FFFh
28 64 190000h-19FFFFh C8000h-CFFFFh
27 64 180000h-18FFFFh C0000h-C7FFFh
26 64 170000h-17FFFFh B8000h-BFFFFh
25 64 160000h-16FFFFh B0000h-B7FFFh
24 64 150000h-15FFFFh A8000h-AFFFFh
23 64 140000h-14FFFFh A0000h-A7FFFh
22 64 130000h-13FFFFh 98000h-9FFFFh
21 64 120000h-12FFFFh 90000h-97FFFh
20 64 110000h-11FFFFh 88000h-8FFFFh
19 64 100000h-10FFFFh 80000h-87FFFh
18 64 0F0000h-0FFFFFh 78000h-7FFFFh
17 64 0E0000h-0EFFFFh 70000h-77FFFh
16 64 0D0000h-0DFFFFh 68000h-6FFFFh
15 64 0C0000h-0CFFFFh 60000h-67FFFh
14 64 0B0000h-0BFFFFh 58000h-5FFFFh
13 64 0A0000h-0AFFFFh 50000h-57FFFh
12 64 090000h-09FFFFh 48000h-4FFFFh
11 64 080000h-08FFFFh 40000h-47FFFh
10 64 070000h-07FFFFh 38000h-3FFFFh
9 64 060000h-06FFFFh 30000h-37FFFh
8 64 050000h-05FFFFh 28000h-2FFFFh
7 64 040000h-04FFFFh 20000h-27FFFh
6 64 030000h-03FFFFh 18000h-1FFFFh
5 64 020000h-02FFFFh 10000h-17FFFh
4 64 010000h-01FFFFh 08000h-0FFFFh
3 32 008000h-00FFFFh 04000h-07FFFh
2 8 006000h-007FFFh 03000h-03FFFh
1 8 004000h-005FFFh 02000h-02FFFh
0 16 000000h-003FFFh 00000h-01FFFh
M29FxxxFT, M29FxxxFB Block Address Table
51/67
Table 25. Top Boot Block Addresses, M29F800FT
#Size
(KBytes) Address Ran ge
(x8) Address Range
(x16)
18 16 FC000h-FFFFFh 7E000h-7FFFFh
17 8 FA000h-FBFFFh 7D000h-7DFFFh
16 8 F8000h-F9FFFh 7C000h-7CFFFh
15 32 F0000h-F7FFFh 78000h-7BFFFh
14 64 E0000h-EFFFFh 70000h-77FFFh
13 64 D0000h-DFFFFh 68000h-6FFFFh
12 64 C0000h-CFFFFh 60000h-67FFFh
11 64 B0000h-BFFFFh 58000h-5FFFFh
10 64 A0000h-AFFFFh 50000h-57FFFh
9 64 90000h-9FFFFh 48000h-4FFFFh
8 64 80000h-8FFFFh 40000h-47FFFh
7 64 70000h-7FFFFh 38000h-3FFFFh
6 64 60000h-6FFFFh 30000h-37FFFh
5 64 50000h-5FFFFh 28000h-2FFFFh
4 64 40000h-4FFFFh 20000h-27FFFh
3 64 30000h-3FFFFh 18000h-1FFFFh
2 64 20000h-2FFFFh 10000h-17FFFh
1 64 10000h-1FFFFh 08000h-0FFFFh
0 64 00000h-0FFFFh 00000h-07FFFh
Block Address Table M29FxxxFT, M29FxxxFB
52/67
Table 26. Bottom Boot Block Addresses, M29F800FB
#Size
(KBytes) Address Ran ge
(x8) Address Range
(x16)
18 64 F0000h-FFFFFh 78000h-7FFFFh
17 64 E0000h-EFFFFh 70000h-77FFFh
16 64 D0000h-DFFFFh 68000h-6FFFFh
15 64 C0000h-CFFFFh 60000h-67FFFh
14 64 B0000h-BFFFFh 58000h-5FFFFh
13 64 A0000h-AFFFFh 50000h-57FFFh
12 64 90000h-9FFFFh 48000h-4FFFFh
11 64 80000h-8FFFFh 40000h-47FFFh
10 64 70000h-7FFFFh 38000h-3FFFFh
9 64 60000h-6FFFFh 30000h-37FFFh
8 64 50000h-5FFFFh 28000h-2FFFFh
7 64 40000h-4FFFFh 20000h-27FFFh
6 64 30000h-3FFFFh 18000h-1FFFFh
5 64 20000h-2FFFFh 10000h-17FFFh
4 64 10000h-1FFFFh 08000h-0FFFFh
3 32 08000h-0FFFFh 04000h-07FFFh
2 8 06000h-07FFFh 03000h-03FFFh
1 8 04000h-05FFFh 02000h-02FFFh
0 16 00000h-03FFFh 00000h-01FFFh
M29FxxxFT, M29FxxxFB Block Address Table
53/67
Table 27. Top Boot Block Addresses, M29F400FT
#Size
(KBytes) Address Ran ge
(x8) Address Range
(x16)
10 16 7C000h-7FFFFh 3E000h-3FFFFh
9 8 7A000h-7BFFFh 3D000h-3DFFFh
8 8 78000h-79FFFh 3C000h-3CFFFh
7 32 70000h-77FFFh 38000h-3BFFFh
6 64 60000h-6FFFFh 30000h-37FFFh
5 64 50000h-5FFFFh 28000h-2FFFFh
4 64 40000h-4FFFFh 20000h-27FFFh
3 64 30000h-3FFFFh 18000h-1FFFFh
2 64 20000h-2FFFFh 10000h-17FFFh
1 64 10000h-1FFFFh 08000h-0FFFFh
0 64 00000h-0FFFFh 00000h-07FFFh
Block Address Table M29FxxxFT, M29FxxxFB
54/67
Table 28. Bottom Boot Block Addresses, M29F400FB
#Size
(KBytes) Address Ran ge
(x8) Address Range
(x16)
10 64 70000h-7FFFFh 38000h-3FFFFh
9 64 70000h-6FFFFh 30000h-37FFFh
8 64 50000h-5FFFFh 28000h-2FFFFh
7 64 40000h-4FFFFh 20000h-27FFFh
6 64 30000h-3FFFFh 18000h-1FFFFh
5 64 20000h-2FFFFh 10000h-17FFFh
4 64 10000h-1FFFFh 08000h-0FFFFh
3 32 08000h-0FFFFh 04000h-07FFFh
2 8 06000h-07FFFh 03000h-03FFFh
1 8 04000h-05FFFh 02000h-02FFFh
0 16 00000h-03FFFh 00000h-01FFFh
M29FxxxFT, M29FxxxFB Block Address Table
55/67
Table 29. Top Boot Block Addresses, M29F200FT
Table 30. Bottom Boot Block Addresses, M29F200FB
#Size
(KBytes) Address Ran ge
(x8) Address Range
(x16)
6 16 3C000h-3FFFFh 1E000h-1FFFFh
5 8 3A000h-3BFFFh 1D000h-1DFFFh
4 8 38000h-39FFFh 1C000h-1CFFFh
3 32 30000h-37FFFh 18000h-1BFFFh
2 64 20000h-2FFFFh 10000h-17FFFh
1 64 10000h-1FFFFh 08000h-0FFFFh
0 64 00000h-0FFFFh 00000h-07FFFh
#Size
(KBytes) Address Ran ge
(x8) Address Range
(x16)
6 64 30000h-3FFFFh 18000h-1FFFFh
5 64 20000h-2FFFFh 10000h-17FFFh
4 64 10000h-1FFFFh 08000h-0FFFFh
3 32 08000h-0FFFFh 04000h-07FFFh
2 8 06000h-07FFFh 03000h-03FFFh
1 8 04000h-05FFFh 02000h-02FFFh
0 16 10000h-1FFFFh 00000h-01FFFh
Common Flash Interface (CFI) M29FxxxFT, M29Fxxx FB
56/67
Appendix B Common Flash Interface (CFI)
The Common Flash Interfa ce is a JEDEC approved, st andardized dat a structure that can be
read from the Flash memory device. It allows a system software to query the device t o
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the CFI Query Command is issued the device enters CFI Query mode and the data
structure is read from the memory. Addresses used to retrieve the data are shown in the
following tables:
Tab le 31 .: Que ry Structure Overview ,
Table 32.: CFI Query Identification String,
Table 33.: CFI Query System Interface Information,
Table 34.: Device Geometry Definition,
Table 35.: Primary Algorithm-Specific Extended Query Table
Table 36.: Security Code Area
The CFI data structure also contains a security area where a 64-bit unique security number
is written (see Table 36.: Security Code Area). This area can be accesse d on ly in Rea d
mode by the final user. It is impo ssib le to chan g e th e sec ur ity nu m be r after it has been
written by Numonyx. Issue a Read command to return to Read mode.
Table 31. Query Structure Overview
Query data are always presented on the lowest order data outputs.
Table 32. CFI Query Identification String
Address Sub-section Name Description
x16 x8
10h 20h CFI Query Identification String Command set ID and algorithm data offset
1Bh 36h System Interface Information Device timing & voltage information
27h 4Eh Device Geometry Definition Flash devi ce layout
40h 80h Primary Algorithm-specific Extended
Query table Additional information specific to the Primary Algorithm
(optional)
61h C2h Security Code Area 64 bit unique device number
Address Data Description Value
x16 x8
10h 20h 0051h "Q"
11h 22h 0052h Query Unique ASCII String "QRY" "R"
12h 24h 0059h "Y"
13h 26h 0002h Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm AMD
Compatible
14h 28h 0000h
15h 2Ah 0040h Address for Primary Algorithm extended Query table (see Tab le 34.) P = 40h
16h 2Ch 0000h
M29FxxxFT, M29FxxxFB Common Flash Interface (CFI)
57/67
Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
Table 33. CFI Query System Interface Information
Table 34. Device Geometry Definition
17h 2Eh 0000h Alternate Vendor Command Set and Control Interface ID Code
second vendor - specified algorithm supported NA
18h 30h 0000h
19h 32h 0000h Address for Alternate Algorithm extended Query table NA
1Ah 34h 0000h
Address Data Description Value
x16 x8
Address Data Description Value
x16 x8
1Bh 36h 0045h VCC Logic Supply Minimum Program/Erase vol tage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV 4.5 V
1Ch 38h 0055h VCC Logic Supply Maximum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV 5.5 V
1Dh 3Ah 0000h VPP [Programming] Supply Minimum Program/Erase voltage NA
1Eh 3Ch 0000h VPP [Programming] Supply Maximum Program/Erase voltage NA
1Fh 3Eh 0003h Typical timeout per single Byte/Word program = 2n µs 8 µs
20h 40h 0000h Typical timeout for minimum size write buffer program = 2n µs NA
21h 42h 000Ah Typical timeout per individual block er ase = 2 n ms 1 s
22h 44h 0000h Typical timeout for full chip erase = 2n ms NA
23h 46h 0004h Maximum timeout for Byte/Word program = 2n times typical 256 µs
24h 48h 0000h Maximum timeout for write buffer program = 2n times typical NA
25h 4Ah 0003h Maxi mu m timeou t per individual block erase = 2n times typical 8 s
26h 4Ch 0000h Maximum timeout for chip erase = 2n times typical NA
Address Data Description Value
x16 x8
27h 4Eh
0015h
Device Size = 2n in number of Bytes
2 MByte
0014h 1 MByte
0013h 512 KByte
0012h 256 KByte
28h
29h 50h
52h 0002h
0000h Flash Devi ce Interface Code description x8, x16
Async.
2Ah
2Bh 54h
56h 0000h
0000h Maximum number of Bytes in multi-Byte program or page = 2n NA
Common Flash Interface (CFI) M29FxxxFT, M29Fxxx FB
58/67
Table 35. Primary Algorithm-Specific Extended Query Table
2Ch 58h 0004h Number of Erase Block Regions within the device.
It specifies the number of regions within the device containing
contiguous Erase Blocks of the same size. 4
2Dh
2Eh 5Ah
5Ch 0000h
0000h Region 1 Information
Number of identical size erase block = 0000h+1 1
2Fh
30h 5Eh
60h 0040h
0000h Region 1 Information
Block size in Region 1 = 0040h * 256 Byte 16 KByte
31h
32h 62h
64h 0001h
0000h Region 2 Information
Number of identical size erase block = 0001h+1 2
33h
34h 66h
68h 0020h
0000h Region 2 Information
Block size in Region 2 = 0020h * 256 Byte 8 KByte
35h
36h 6Ah
6Ch 0000h
0000h Region 3 Information
Number of identical size erase block = 0000h+1 1
37h
38h 6Eh
70h 0080h
0000h Region 3 Information
Block size in Region 3 = 0080h * 256 Byte 32 KByte
39h
3Ah 72h
74h 001Eh
0000h Region 4 Information (2 MByte)
Number of identical-size er ase block = 001Eh+1 31
39h
3Ah 72h
74h 000Eh
0000h Region 4 Information (1 MByte)
Number of identical-size er ase block = 000Eh+1 15
39h
3Ah 72h
74h 0006h
0000h Region 4 Information (512 KByte)
Number of identical-size er ase block = 0006h+1 7
39h
3Ah 72h
74h 0002h
0000h Region 4 Information (256 KByte)
Number of identical-size er ase block = 0002h+1 3
3Bh
3Ch 76h
78h 0000h
0001h Region 4 Information
Block size in Region 4 = 0100h * 256 Byte 64 KByte
Address Data Description Value
x16 x8
Address Data Description Value
x16 x8
40h 80h 0050h
Primary Algorithm extended Query table unique ASCII string “PRI”
"P"
41h 82h 0052h "R"
42h 84h 0049h "I"
43h 86h 0031h Maj or version number, ASCII "1"
44h 88h 0030h Min or version number, ASCII "0"
45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2) Yes
46h 8Ch 0002h Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write 2
M29FxxxFT, M29FxxxFB Common Flash Interface (CFI)
59/67
Table 36. Security Code Area
47h 8Eh 0001h Block Protection
00 = not supported, x = number of blocks in per group 1
48h 90h 0001h Temporary Block Unprotect
00 = not supported, 01 = supported Yes
49h 92h
0002h
0004h
0008h
0160h
Block Protect /Unprotect
02 = M29F200
04 = M29F400
08 = M29F800
10 = M29F160
2
4
8
16
4Ah 94h 0000h Simultaneous Operations, 00 = not supported No
4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No
4Ch 98h 0000h Page Mode, 00 = not supp orted, 01 = 4 page Word, 02 = 8 page Word No
Address Data Description Value
x16 x8
Address Data Description
x16 x8
61h C3h, C2h XXXX
64 bit: unique device number
62h C5h, C4h XXXX
63h C7h, C6h XXXX
64h C9h, C8h XXXX
Block protection M29FxxxFT, M29FxxxFB
60/67
Appendix C Block protection
Block protection can be use d to prevent any ope ratio n from mod ifying the dat a stored in the
Flash memory. Each Block can be protected individually. Once protected, Program and
Erase operations on the block fail to change the data.
There are three techniques that can be used to control Block Protection, these are the
Programmer technique, the In-System technique and Temporary Unprotection. Temporary
Unprotection is con tro lle d by the Reset/Block Tempor a ry Unpr otection pin, RP ; this is
described in the Signal Descriptions section.
Unlike the Command Interface of the Program/Erase Controller, the techniques for
protecting and unpr otecti ng blocks coul d cha nge betwee n different Flash memory supplie rs.
C.1 Programmer Technique
The Programmer technique uses high (VID) voltage levels on some of the bus pins. These
cannot be achieved using a standard microprocessor bus, therefore the technique is
recommended only for use in Programm ing Equipment.
To protect a block follow the flowchart in Figure 27.: Programmer Equipment Block Protect
Flowchart. Du ring the Block Protect algorithm, the A19-A12 Addres s Inputs indicate the
address of the block to be protected. The block will be correctly protected only if A19-A12
remain valid and stable, and if Chip Enable is kept Low, VIL, all along the Protect and Verify
phases.
The Chip Unprotect algorithm is used to unprotect all the memory blocks at the same time.
This algorithm can only be used if all of the blocks are protected firs t. To unprotect the chip
follow Figure 28.: Programmer Equipment Chip Unprotect Flowchart and Table 37.:
Programmer Technique Bus Operations, BYTE = VIH or VIL, which give a summar y of each
operation.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not abort the proced ure before
reaching the end. Chip Unprotect can take several seconds and a user message should be
provided to show that the operation is progressing.
C.2 In-System Technique
The In-System technique requires a high voltage level on the Reset/Blocks Temporary
Unprotect pin, RP. This can be achieved without violating the maximum ratings of the
component s on the microprocesso r bus, therefore this technique is suitable for use af ter the
Flash memory has been fitted to the system.
To protect a block follow the flowchart in Figure 29.: In-System Equipment Block Protect
Flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then
all the blocks can be unprotected at the same time. To unprotect the chip follow Figure 30.:
In-System Equipment Chip Unprotect Flowchart.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not allow the microprocessor to
service interrupts that will upset the timing and do not abort the procedure before reaching
M29FxxxFT, M29FxxxFB Block protection
61/67
the end. Chip Unprotect can take several seconds and a user messag e should be provided
to show that the operation is progressing.
Table 37. Programmer Technique Bus Operations, BYTE = VIH or VIL
Operation E G W Address Inputs
A0-A19 Data Inputs/Out puts
DQ15A–1, DQ14-DQ0
Block Protect VIL VID VIL Pulse A9 = VID, A12-A19 Block Address
Others = X X
Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH
Others = X X
Block Protection
Verify VIL VIL VIH
A0 = VIL, A1 = VIH, A6 = VIL,
A9 = VID, A12-A19 Block Address
Others = X
Pass = XX01h
Retry = XX00h
Block Unprotection
Verify VIL VIL VIH
A0 = VIL, A1 = VIH, A6 = VIH,
A9 = VID, A12-A19 Block Address
Others = X
Retry = XX01h
Pass = XX00h
Block protection M29FxxxFT, M29FxxxFB
62/67
Figure 27. Programmer Equipment Block Protect Flowchart
Address Inputs A19-A12 give the address of the block that is to be protected. It is imperative that they remain
stable during the operation.
During the Protect and Verify phases of the algorithm, Chip Enable E must be kept Low, VIL.
ADDRES S = B L OCK ADDRE SS
AI03469b
G, A9 = VID,
E = VIL
n = 0
Wait 4µs
W ait 100µs
W = VIL
W = VIH
E, G = VIH,
A0, A6 = VIL,
A1 = VIH
A9 = VIH
E, G = VIH
++n
= 2 5
START
FAIL
PASS
YES
NO
DATA
=
01hYES
NO
W = VIH
E = VIL
Wait 4µs
G = VIL
W ait 60ns
Read DATA
Verify Protect Set-upEnd
A9 = VIH
E, G = VIH
M29FxxxFT, M29FxxxFB Block protection
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Figure 28. Programmer Equipment Chip Unprotect Flowchart
P R OTEC T ALL BLOC K S
AI0347
0
A6, A 12, A15 = VIH
E, G , A9 = VID
DATA
W = VIH
E, G = VIH
ADDRES S = CURRENT B LO C K ADDRES S
A0 = VIL, A1, A6 = V IH
W ait 10ms
=
00h
INCREMENT
CURRENT BLOCK
n = 0
CURR E NT BLOCK = 0
Wait 4µs
W = VIL
++n
= 1000
START
YES
YESNO
NO LAST
BLOCK
YES
NO
E = VIL
Wait 4µs
G = VIL
W ait 60ns
Read DATA
FAIL PASS
Verify Unprotect Set-upEnd
A9 = VIH
E, G = VIH A9 = VIH
E, G = VIH
Block protection M29FxxxFT, M29FxxxFB
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Figure 29. In-System Equipment Block Protect Flowchart
AI03471
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
n = 0
Wait 100µs
WRITE 40h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
RP = VIH ++n
= 25
START
FAIL
PASS
YES
NO
DATA
=
01hYES
NO
RP = VIH
Wait 4µs
Verify Protect Set-upEnd
READ DATA
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
RP = VID
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
M29FxxxFT, M29FxxxFB Block protection
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Figure 30. In-System Equipment Chip Unprotect Flowchart
AI03472
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
n = 0
CURRENT BLOCK = 0
Wait 10ms
WRITE 40h
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
RP = VIH
++n
= 1000
START
FAIL PASS
YES
NO
DATA
=
00h
YESNO
RP = VIH
Wait 4µs
READ DATA
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
RP = VID
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PROTECT ALL BLOCKS
INCREMENT
CURRENT BLOCK
LAST
BLOCK
YES
NO
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Verify Unprotect Set-upEnd
Revision History M29FxxxFT, M29FxxxFB
66/67
Appendix D Revision History
Table 38. Document Revision History
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (S peed, Package, etc.) or for further information on any aspect
of this device, pleas e contact the Numony x Sales Office nearest to you.
Date Version Revision Details
30-March-2009 1 Initial release.
1-April-2009 2 Corrected block diagram err ors;
Changed read manufacture r code and read device code to TBD.
Added 55 ns option to speed option in Ordering Information table.
22-April-2009 3
Updated manufacturer code and device ID codes in the following locations:
– cover page,
–Table 2.: Bus Operations, BYTE = VIL
–Table 3.: Bus Operations, BYTE = VIH
–Table 34.: Device Geometry Definition
–Table 35.: Primary Algorithm-Specific Extended Query Tabl e
Removed the fo llowing:
– “preliminary” and delivery date from cover page;
– 70 ns columns from all AC characteristics tables;
– “inches” from package manufacturing tables.
27-May-2009 4
Removed the Note in the introduction to the Appendix B: Common Flash Interface
(CFI).
Corrected the Description and Value informaiton for Address 49h (x16) and 92h (x8)
Table 35.: Primary Algorithm-Specific Extended Query Table;
Added additional speed and packing information to Ordering Information.
13-Aug-2009 5 TFBGA48 6 x 8 mm package added.
14-Oct-2009 6
Revised as follows:
– Added / revised details in Order Information table.
– Removed device code detail in 4.2: Auto Select Command
–In Table 14.: DC Characteristics, changed ICC1 Max value from 10 to 20; changed
ICC3 Max value from 20 to 30; changed VIL value from 0.5 °C to –0.5 °C
– Removed “preliminary data” statement throughout the document.
–In Figure 9.: TFBGA connections (top view through package), changed VPP/WP
to NC.
21-Oct-2009 7 Revised the following:
In Table 14.: DC Characteristics, changed VIH from 0.8 V to 0.7 V.
8-Feb-2010 8 Minor text edits.
19-July-2010 9 Made minor text edits, and changed manufacturer code from 0020h to 0001h in
Section 4.2: Auto Select Command on page 26.
M29FxxxFT, M29FxxxFB
67/67
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