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1-MBIT (128K x 8)

BOOT BLOCK FLASH MEMORY

28F001BX-T/28F001BX-B/28F001BN-T/28F001BN-B

YHigh-Integration Blocked Architecture

Ð One 8 KB Boot Block w/Lock Out

Ð Two 4 KB Parameter Blocks

Ð One 112 KB Main Block

Y100,000 Erase/Program Cycles Per

Block

YSimplified Program and Erase

Ð Automated Algorithms via On-Chip

Write State Machine (WSM)

YSRAM-Compatible Write Interface

YDeep Power-Down Mode

Ð 0.05 mAI

CC Typical

Ð 0.8 mAI

PP Typical

Y12.0V g5% VPP

YHigh-Performance Read

Ð 70/75 ns, 90 ns, 120 ns, 150 ns

Maximum Access Time

Ð 5.0V g10% VCC

YHardware Data Protection Feature

Ð Erase/Write Lockout during Power

Transitions

YAdvanced Packaging, JEDEC Pinouts

Ð 32-Pin PDIP

Ð 32-Lead PLCC, TSOP

YETOXTM II Nonvolatile Flash

Technology

Ð EPROM-Compatible Process Base

Ð High-Volume Manufacturing

Experience

YExtended Temperature Options

Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with

features that simplify write and allow block erase. These devices aid the system designer by combining the

functions of several components into one, making boot block flash an innovative alternative to EPROM and

EEPROM or battery-backed static RAM. Many new and existing designs can take advantage of the

28F001BX’s integration of blocked architecture, automated electrical reprogramming, and standard processor

interface.

The 28F001BX-B and 28F001BX-T are 1,048,576 bit nonvolatile memories organized as 131,072 bytes of

8 bits. They are offered in 32-pin plastic DIP, 32-lead PLCC and 32-lead TSOP packages. Pin assignment

conform to JEDEC standards for byte-wide EPROMs. These devices use an integrated command port and

state machine for simplified block erasure and byte reprogramming. The 28F001BX-T’s block locations pro-

vide compatibility with microprocessors and microcontrollers that boot from high memory, such as Intel’s

MCSÉ-186 family, 80286, i386TM, i486TM, i860TM and 80960CA. With exactly the same memory segmentation,

the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory,

such as Intel’s MCS-51, MCS-196, 80960KX and 80960SX families. All other features are identical, and unless

otherwise noted, the term 28F001BX can refer to either device throughout the remainder of this document.

The boot block section includes a reprogramming write lock out feature to guarantee data integrity. It is

designed to contain secure code which will bring up the system minimally and download code to the other

locations of the 28F001BX. Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring high-

performance access speeds, low power consumption, and immunity to noise. Its access time provides

no-WAIT-state performance for a wide range of microprocessors and microcontrollers. A deep-powerdown

mode lowers power consumption to 0.25 mW typical through VCC, crucial in laptop computer, handheld instru-

mentation and other low-power applications. The RPÝpower control input also provides absolute data protec-

tion during system powerup or power loss.

Manufactured on Intel’s ETOX process base, the 28F001BX builds on years of EPROM experience to yield the

highest levels of quality, reliability, and cost-effectiveness.

NOTE: The 28F001BN is equivalent to the 28F001BX.

28F001BX-T/28F001BX-B

290406–1

Figure 1. 28F001BX Block Diagram

Table 1. Pin Description

Symbol Type Name and Function

A0–A16 INPUT ADDRESS INPUTS for memory addresses. Addresses are internally latched during

a write cycle.

DQ0–DQ7INPUT/ DATA INPUTS/OUTPUTS: Inputs data and commands during memory write

cycles; outputs data during memory, Status Register and Identifier read cycles. The

OUTPUT

data pins are active high and float to tri-state off when the chip is deselected or the

outputs are disabled. Data is internally latched during a write cycle.

CEÝINPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

sense amplifiers. CEÝis active low; CEÝhigh deselects the memory device and

reduces power consumption to standby levels.

RPÝINPUT POWERDOWN: Puts the device in deep powerdown mode. RPÝis active low;

RPÝhigh gates normal operation. RPÝeVHH allows programming of the boot

block. RPÝalso locks out erase or write operations when active low, providing data

protection during power transitions. RPÝactive resets internal automation. Exit

from deep powerdown sets device to Read Array mode.

OEÝINPUT OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a

read cycle. OEÝis active low. OEÝeVHH (pulsed) allows programming of the

boot block.

WEÝINPUT WRITE ENABLE: Controls writes to the Command Register and array blocks. WEÝ

is active low. Addresses and data are latched on the rising edge of the WEÝpulse.

VPP ERASE/PROGRAM POWER SUPPLY for erasing blocks of the array or

programming bytes of each block. Note: With VPP kVPPL max, memory contents

cannot be altered.

VCC DEVICE POWER SUPPLY: (5V g10%)

GND GROUND

28F001BX-T/28F001BX-B

28F010

VPP

A16

A15

A12

DQ0

DQ1

DQ2

GND

290406–2

28F010

VCC

WEÝ

A14

A13

A11

OEÝ

A10

CEÝ

DQ7

DQ6

DQ5

DQ4

DQ3

Figure 2. DIP Pin Configuration

28F010

A11

A13

A14

WEÝ

VCC

VPP

A16

A15

A12

290406–3

28F010

OEÝ

A10

CEÝ

DQ7

DQ6

DQ5

DQ4

DQ3

GND

DQ2

DQ1

DQ0

Figure 3. TSOP Lead Configuration

28F001BX-T/28F001BX-B

290406–4

Figure 4. PLCC Lead Configuration

APPLICATIONS

The 28F001BX flash ‘boot block’ memory augments

the non-volatility, in-system electrical erasure and

reprogrammability of Intel’s standard flash memory

by offering four separately erasable blocks and inte-

grating a state machine to control erase and pro-

gram functions. The specialized blocking architec-

ture and automated programming of the 28F001BX

provide a full-function, non-volatile flash memory

ideal for a wide range of applications, including PC

boot/BIOS memory, minimum-chip embedded pro-

gram memory and parametric data storage. The

28F001BX combines the safety of a hardware-pro-

tected 8-KByte boot block with the flexibility of three

separately reprogrammable blocks (two 4-KByte pa-

rameter blocks and one 112-KByte code block) into

one versatile, cost-effective flash memory. Addition-

ally, reprogramming one block does not affect code

stored in another block, ensuring data integrity.

The flexibility of flash memory reduces costs

throughout the life cycle of a design. During the early

stages of a system’s life, flash memory reduces pro-

totype development and testing time, allowing the

system designer to modify in-system software elec-

trically versus manual removal of components. Dur-

ing production, flash memory provides flexible firm-

ware for just-in-time configuration, reducing system

inventory and eliminating unnecessary handling and

less reliable socketed connections. Late in the life

cycle, when software updates or code ‘‘bugs’’ are

often unpredictable and costly, flash memory reduc-

es update costs by allowing the manufacturers to

send floppy updates versus a technician. Alterna-

tively, remote updates over a communication link are

possible at speeds up to 9600 baud due to flash

memory’s fast programming time.

28F001BX-T/28F001BX-B

Reprogrammable environments, such as the per-

sonal computer, are ideal applications for the

28F001BX. The internal state machine provides

SRAM-like timings for program and erasure, using

the Command and Status Registers. The blocking

scheme allows BIOS update in the main and param-

eter blocks, while still providing recovery code in the

boot block in the unlikely event a power failure oc-

curs during an update, or where BIOS code is cor-

rupted. Parameter blocks also provide convenient

configuration storage, backing up SRAM and battery

configurations. EISA systems, for example, can

store hardware configurations in a flash parameter

block, reducing system SRAM.

Laptop BIOSs are becoming increasingly complex

with the addition of power management software

and extended system setup screens. BIOS code

complexity increases the potential for code updates

after the sale, but the compactness of laptop de-

signs makes hardware updates very costly. Boot

block flash memory provides an inexpensive update

solution for laptops, while reducing laptop obsoles-

cence. For portable PCs and hand-held equipment,

the deep powerdown mode dramatically lowers sys-

tem power requirements during periods of slow op-

eration or sleep modes.

The 28F001BX gives the embedded system design-

er several desired features. The internal state ma-

chine reduces the size of external code dedicated to

the erase and program algorithms, as well as freeing

the microcontroller or microprocessor to respond to

other system requests during program and erasure.

The four blocks allow logical segmentation of the

entire embedded software: the 8-KByte block for the

boot code, the 112-KByte block for the main pro-

gram code and the two 4-KByte blocks for updatable

parametric data storage, diagnostic messages and

data, or extensions of either the boot code or pro-

gram code. The boot block is hardware protected

against unauthorized write or erase of its vital code

in the field. Further, the powerdown mode also locks

out erase or write operations, providing absolute

data protection during system powerup or power

loss. This hardware protection provides obvious ad-

vantages for safety related applications such as

transportation, military, and medical. The 28F001BX

is well suited for minimum-chip embedded applica-

tions ranging from communications to automotive.

290406–5

Figure 5. 28F001BX-T in a 80C188 System 290406–6

Figure 6. 28F001BX-B in a 80C51 System

28F001BX-T/28F001BX-B

PRINCIPLES OF OPERATION

The 28F001BX introduces on-chip write automation

to manage write and erase functions. The write state

machine allows for 100% TTL-level control inputs,

fixed power supplies during erasure and program-

ming, minimal processor overhead with RAM-like

write timings, and maximum EPROM compatiblity.

After initial device powerup, or after return from

deep powerdown mode (see Bus Operations), the

28F001BX functions as a read-only memory. Manip-

ulation of external memory-control pins yield stan-

dard EPROM read, standby, output disable or Intelli-

gent Identifier operations. Both Status Register and

Intelligent Identifiers can be accessed through the

Command Register when VPP eVPPL.

This same subset of operations is also available

when high voltage is applied to the VPP pin. In addi-

tion, high voltage on VPP enables successful erasure

and programming of the device. All functions associ-

ated with altering memory contentsÐprogram,

erase, status, and inteligent IdentifierÐare accessed

via the Command Register and verified through the

Status Register.

Commands are written using standard microproces-

sor write timings. Register contents serve as input to

the WSM, which controls the erase and program-

ming circuitry. Write cycles also internally latch ad-

dresses and data needed for programming or erase

operations. With the appropriate command written to

the register, standard microprocessor read timings

output array data, access the intelligent identifier

codes, or output program and erase status for verifi-

cation.

Interface software to initiate and poll progress of in-

ternal program and erase can be stored in any of the

28F001BX blocks. This code is copied to, and exe-

cuted from, system RAM during actual flash memory

update. After successful completion of program

and/or erase, code execution out of the 28F001BX

is again possible via the Read Array command.

Erase suspend/resume capability allows system

software to suspend block erase and read data/exe-

cute code from any other block.

Command Register and Write

Automation

An on-chip state machine controls block erase and

byte program, freeing the system processor for other

tasks. After receiving the erase setup and erase

confirm commands, the state machine controls

block pre-conditioning and erase, returning progress

via the Status Register. Programming is similarly

controlled, after destination address and expected

data are supplied. The program algorithm of past In-

tel Flash Memories is now regulated by the state

machine, including program pulse repetition where

required and internal verification and margining of

data.

Data Protection

Depending on the application, the system designer

may choose to make the VPP power supply switcha-

ble (available only when memory updates are re-

quired) or hardwired to VPPH. When VPP eVPPL,

memory contents cannot be altered. The 28F001BX

Command Register architecture provides protection

from unwanted program or erase operations even

when high voltage is applied to VPP. Additionally, all

functions are disabled whenever VCC is below the

write lockout voltage VLKO, or when RPÝis at VIL.

The 28F001BX accommodates either design prac-

tice and encourages optimization of the processor-

memory interface.

The two-step program/erase write sequence to the

Command Register provides additional software

write protection.

1FFFF

8-KByte BOOT BLOCK

1DFFF

1E000

4-KByte PARAMETER BLOCK

1CFFF

1D000

4-KByte PARAMETER BLOCK

1BFFF

1C000

112-KByte MAIN BLOCK

00000

Figure 7. 28F001BX-T Memory Map

1FFFF

112-KByte MAIN BLOCK

03FFF

04000

4-KByte PARAMETER BLOCK

02FFF

03000

4-KByte PARAMETER BLOCK

01FFF

02000

8-KByte BOOT BLOCK

00000

Figure 8. 28F001BX-B Memory Map

28F001BX-T/28F001BX-B

BUS OPERATION

Flash memory reads, erases and writes in-system

via the local CPU. All bus cycles to or from the flash

memory conform to standard microprocessor bus

cycles.

Read

The 28F001BX has three read modes. The memory

can be read from any of its blocks, and information

can be read from the Intelligent Identifier or the

Status Register. VPP can be at either VPPL or VPPH.

The first task is to write the appropriate read mode

command to the Command Register (array, Intelli-

gent Identifier, or Status Register). The 28F001BX

automatically resets to Read Array mode upon initial

device powerup or after exit from deep powerdown.

The 28F001BX has four control pins, two of which

must be logically active to obtain data at the outputs.

Chip Enable (CEÝ) is the device selection control,

and when active enables the selected memory de-

vice. Output Enable (OEÝ) is the data input/output

(DQ0–DQ7) direction control, and when active

drives data from the selected memory onto the I/O

bus. RPÝand WEÝmust also be at VIH. Figure 12

illustrates read bus cycle waveforms.

Output Disable

With OEÝat a logic-high level (VIH), the device out-

puts are disabled. Output pins (DQ0–DQ7) are

placed in a high-impedance state.

Standby

CEÝat a logic-high level (VIH) places the 28F001BX

in standby mode. Standby operation disables much

of the 28F001BX’s circuitry and substantially reduc-

es device power consumption. The outputs (DQ0–

DQ7) are placed in a high-impedance state indepen-

dent of the status of OEÝ. If the 28F001BX is dese-

lected during erase or program, the device will

continue functioning and consuming normal active

power until the operation is completed.

Deep Power-Down

The 28F001BX offers a 0.25 mWV

CC power-down

feature, entered when RPÝis at VIL. During read

modes, RPÝlow deselects the memory, places out-

put drivers in a high-impedance state and turns off

all internal circuits. The 28F001BX requires time

tPHQV (see AC Characteristics-Read Only Opera-

tions) after return from power-down until initial mem-

ory access outputs are valid. After this wakeup inter-

val, normal operation is restored. The Command

ister is cleared to value 80H, upon return to normal

operation.

During erase or program modes, RPÝlow will abort

either operation. Memory contents of the block be-

ing altered are no longer valid as the data will be

partially programmed or erased. Time tPHWL after

RPÝgoes to logic-high (VIH) is required before an-

other command can be written.

Table 2. 28F001BX Bus Operations

Mode Notes RPÝCEÝOEÝWEÝA9A0VPP DQ0–7

Read 1, 2, 3 VIH VIL VIL VIH XX X D

OUT

Output Disable 2 VIH VIL VIH VIH X X X High Z

Standby 2 VIH VIH X X X X X High Z

Deep Power Down 2 VIL X X X X X X High Z

Intelligent Identifier (Mfr) 2, 3, 4 VIH VIL VIL VIH VID VIL X 89H

Intelligent Identifier (Device) 2, 3, 4, 5 VIH VIL VIL VIH VID VIH X 94H, 95H

Write 2, 6, 7, 8 VIH VIL VIH VIL XX X D

NOTES:

1. Refer to DC Characteristics. When VPP eVPPL, memory contents can be read but not programmed or erased.

2. X can be VIL or VIH for control pins and addresses, and VPPL or VPPH for VPP.

3. See DC Characteristics for VPPL,V

PPH,V

HH and VID voltages.

4. Manufacturer and device codes may also be accessed via a Command Register write sequence. Refer to Table 3. A1–A8,

A10–A16 eVIL.

5. Device ID e94H for the 28F001BX-T and 95H for the 28F001BX-B.

6. Command writes involving block erase or byte program are successfully executed only when VPP eVPPH.

7. Refer to Table 3 for valid DIN during a write operation.

8. Program or erase the boot block by holding RPÝat VHH or toggling OEÝto VHH. See AC Waveforms for program/erase

operations.

28F001BX-T/28F001BX-B

The use of RPÝduring system reset is important

with automated write/erase devices. When the sys-

tem comes out of reset it expects to read from the

flash memory. Automated flash memories provide

status information when accessed during write/

erase modes. If a CPU reset occurs with no flash

memory reset, proper CPU initialization would not

occur because the flash memory would be providing

the status information instead of array data. Intel’s

Flash Memories allow proper CPU initialization fol-

lowing a system reset through the use of the RPÝ

input. In this application RPÝis controlled by the

same RESETÝsignal that resets the system CPU.

Intelligent Identifier Operation

The Intelligent Identifier operation outputs the manu-

facturer code, 89H; and the device code, 94H for the

28F001BX-T and 95H for the 28F001BX-B. Pro-

gramming equipment or the system CPU can then

automatically match the device with its proper erase

and programming algorithms.

PROGRAMMING EQUIPMENT

CEÝand OEÝat a logic low level (VIL), with A9at

high voltage VID (see DC Characteristics) activates

this operation. Data read from locations 00000H and

00001H represent the manufacturer’s code and the

device code respectively.

IN-SYSTEM PROGRAMMING

The manufacturer- and device-codes can also be

read via the Command Register. Following a write of

90H to the Command Register, a read from address

location 00000H outputs the manufacturer code

(89H). A read from address 00001H outputs the de-

vice code (94H for the 28F001BX-T and 95H for the

28F001BX-B). It is not necessary to have high volt-

age applied to VPP to read the Intelligent Identifiers

from the Command Register.

Write

Writes to the Command Register allow read of de-

vice data and Intelligent Identifiers. They also con-

trol inspection and clearing of the Status Register.

Additionally, when VPP eVPPH, the Command Reg-

ister controls device erasure and programming. The

contents of the register serve as input to the internal

state machine.

The Command Register itself does not occupy an

addressable memory location. The register is a latch

used to store the command and address and data

information needed to execute the command. Erase

Setup and Erase Confirm commands require both

appropriate command data and an address within

the block to be erased. The Program Setup Com-

mand requires both appropriate command data and

the address of the location to be programmed, while

the Program command consists of the data to be

written and the address of the location to be pro-

grammed.

The Command Register is written by bringing WEÝ

to a logic-low level (VIL) while CEÝis low. Address-

es and data are latched on the rising edge of WEÝ.

Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the AC Wave-

form for Write Operations, Figure 13, for specific tim-

ing parameters.

COMMAND DEFINITIONS

When VPPL is applied to the VPP pin, read opera-

tions from the Status Register, intelligent identifiers,

or array blocks are enabled. Placing VPPH on VPP

enables successful program and erase operations

as well.

Device operations are selected by writing specific

commands into the Command Register. Table 3 de-

fines these 28F001BX commands.

Read Array Command

Upon initial device powerup and after exit from

deep-powerdown mode, the 28F001BX defaults to

Read Array mode. This operation is also initiated by

writing FFH into the Command Register. Microproc-

essor read cycles retrieve array data. The device re-

mains enabled for reads until the Command Regis-

ter contents are altered. Once the internal write

state machine has started an erase or program op-

eration, the device will not recognize the Read Array

command, until the WSM has completed its opera-

tion. The Read Array command is functional when

VPP eVPPL or VPPH.

Intelligent Identifier Command for

In-System Programming

The 28F001BX contains an Intelligent Identifier op-

eration to supplement traditional PROM-program-

ming methodology. The operation is initiated by writ-

ing 90H into the Command Register. Following the

command write, a read cycle from address 00000H

retrieves the manufacturer code of 89H. A read cy-

cle from address 00001H returns the device code of

94H (28F001BX-T) or 95H (28F001BX-B). To termi-

nate the operation, it is necessary to write another

valid command into the register. Like the Read Array

command, the Intelligent Identifier command is func-

tional when VPP eVPPL or VPPH.

28F001BX-T/28F001BX-B

Table 3. 28F001BX Command Definitions

Command Cycles

Req’d

Bus

Notes First Bus Cycle Second Bus Cycle

Operation Address Data Operation Address Data

Read Array/Reset 1 1 Write X FFH

Intelligent Identifier 3 2, 3, 4 Write X 90H Read IA IID

Read Status Register 2 3 Write X 70H Read X SRD

Clear Status Register 1 Write X 50H

Erase Setup/Erase Confirm 2 2 Write BA 20H Write BA D0H

Erase Suspend/Erase Resume 2 Write X B0H Write X D0H

Program Setup/Program 2 2, 3 Write PA 40H Write PA PD

NOTES:

1. Bus operations are defined in Table 2.

2. IA eIdentifier Address: 00H for manufacturer code, 01H for device code.

BA eAddress within the block being erased.

PA eAddress of memory location to be programmed.

3. SRD eData read from Status Register. See Table 4 for a description of the Status Register bits.

PD eData to be programmed at location PA. Data is latched on the rising edge of WEÝ.

IID eData read from Intelligent Identifiers.

4. Following the Intelligent Identifier command, two read operations access manufacture and device codes.

5. Commands other than those shown above are reserved by Intel for future device implementations and should not be

used.

Read Status Register Command

The 28F001BX contains a Status Register which

may be read to determine when a program or erase

operation is complete, and whether that operation

completed successfully. The Status Register may be

read at any time by writing the Read Status Register

command (70H) to the Command Register. After

writing this command, all subsequent read opera-

tions output data from the Status Register, until an-

other valid command is written to the Command

latched on the falling edge of OEÝor CEÝ, which-

ever occurs last in the read cycle. OEÝor CEÝ

must be toggled to VIH before further reads to up-

date the Status Register latch. The Read Status

VPPH.

Clear Status Register Command

The Erase Status and Program Status bits are set to

‘‘1’’ by the Write State Machine and can only be

reset by the Clear Status Register command. These

bits indicate various failure conditions (see Table 4).

By allowing system software to control the resetting

of these bits, several operations may be performed

(such as cumulatively programming several bytes or

erasing multiple blocks in sequence). The Status

occurred during that series. This adds flexibility to

the way the device may be used.

Additionally, the VPP Status bit (SR.3), when set to

‘‘1’’, MUST be reset by system software before fur-

ther byte programs or block erases are attempted.

To clear the Status Register, the Clear Status Regis-

ter command (50H) is written to the Command Reg-

ister. The Clear Status Register command is func-

tional when VPP eVPPL or VPPH.

28F001BX-T/28F001BX-B

Table 4. 28F001BX Status Register Definitions

WSMS ESS ES PS VPPS R R R

76543210

SR.7 eWRITE STATE MACHINE STATUS

1eReady

0eBusy

SR.6 eERASE SUSPEND STATUS

1eErase Suspended

0eErase In Progress/Completed

SR.5 eERASE STATUS

1eError in Block Erasure

0eSuccessful Block Erase

SR.4 ePROGRAM STATUS

1eError in Byte Program

0eSuccessful Byte Program

SR.3 eVPP STATUS

1eVPP Low Detect; Operation Abort

0eVPP OK

SR.2–SR.0 eRESERVED FOR FUTURE ENHANCE-

MENTS

These bits are reserved for future use and should be

masked out when polling the Status Register.

NOTES:

The Write State Machine Status Bit must first be checked

to determine program or erase completion, before the

Program or Erase Status bits are checked for success.

If the Program AND Erase Status bits are set to ‘‘1s’’ dur-

ing an erase attempt, an improper command sequence

was entered. Attempt the operation again.

If VPP low status is detected, the Status Register must be

cleared before another program or erase operation is at-

tempted.

The VPP Status bit, unlike an A/D converter, does not

provide continuous indication of VPP level. The WSM in-

terrogates the VPP level only after the program or erase

command sequences have been entered and informs the

system if VPP has not been switched on. The VPP Status

bit is not guaranteed to report accurate feedback be-

tween VPPL and VPPH.

Erase Setup/Erase Confirm

Commands

Erase is executed one block at a time, initiated by a

two-cycle command sequence. An Erase Setup

command (20H) is first written to the Command

(D0H). These commands require both appropriate

command data and an address within the block to

be erased. Block preconditioning, erase and verify

are all handled internally by the Write State Machine,

invisible to the system. After receiving the two-com-

mand erase sequence, the 28F001BX automatically

outputs Status Register data when read (see Figure

10; Block Erase Flowchart). The CPU can detect the

completion of the erase event by checking the WSM

Status bit of the Status Register (SR.7).

When the Status Register indicates that erase is

complete, the Erase Status bit should be checked. If

erase error is detected, the Status Register should

be cleared. The Command Register remains in Read

Status Register Mode until further commands are is-

sued to it.

This two-step sequence of set-up followed by execu-

tion ensures that memory contents are not acciden-

tally erased. Also, block erasure can only occur

when VPP eVPPH. In the absence of this high volt-

age, memory contents are protected against era-

sure. If block erase is attempted while VPP eVPPL,

the VPP Status bit will be set to ‘‘1’’. Erase attempts

while VPPL kVPP kVPPH produce spurious results

and should not be attempted.

Erase Suspend/Erase Resume

Commands

The Erase Suspend Command allows erase se-

quence interruption in order to read data from anoth-

er block of memory. Once the erase sequence is

started, writing the Erase Suspend command (B0H)

to the Command Register requests that the WSM

suspend the erase sequence at a predetermined

point in the erase algorithm. The 28F001BX contin-

ues to output Status Register data when read, after

the Erase Suspend command is written to it. Polling

the WSM Status and Erase Suspend Status bits will

determine when the erase operation has been sus-

pended (both will be set to ‘‘1s’’).

At this point, a Read Array command can be written

to the Command Register to read data from blocks

other than that which is suspended. The only oth-

er valid commands at this time are Read Status Reg-

ister (70H) and Erase Resume (D0H), at which time

the WSM will continue with the erase sequence. The

Erase Suspend Status and WSM Status bits of the

Status Register will be cleared. After the Erase Re-

sume command is written to it, the 28F001BX auto-

matically outputs Status Register data when read

(see Figure 11; Erase Suspend/Resume Flowchart).

28F001BX-T/28F001BX-B

Program Setup/Program Commands

Programming is executed by a two-write sequence.

The program Setup command (40H) is written to the

Command Register, followed by a second write

specifying the address and data (latched on the ris-

ing edge of WEÝ) to be programmed. The WSM

then takes over, controlling the program and verify

algorithms internally. After the two-command pro-

gram sequence is written to it, the 28F001BX auto-

matically outputs Status Register data when read

(see Figure 9; Byte Program Flowchart). The CPU

can detect the completion of the program event by

analyzing the WSM Status bit of the Status Register.

Only the Read Status Register command is valid

while programming is active.

When the Status Register indicates that program-

ming is complete, the Program Status bit should be

checked. If program error is detected, the Status

only detects errors for ‘‘1s’’ that do not successfully

program to ‘‘0s’’. The Command Register remains in

Read Status Register mode until further commands

are issued to it. If byte program is attempted while

VPP eVPPL, the VPP Status bit will be set to ‘‘1’’.

Program attempts while VPPL kVPP kVPPH pro-

duce spurious results and should not be attempted.

EXTENDED ERASE/PROGRAM

CYCLING

EEPROM cycling failures have always concerned

users. The high electrical field required by thin oxide

EEPROMs for tunneling can literally tear apart the

oxide at defect regions. To combat this, some sup-

pliers have implemented redundancy schemes, re-

ducing cycling failures to insignificant levels. Howev-

er, redundancy requires that cell size be doubled; an

expensive solution.

Intel has designed extended cycling capability into

its ETOX flash memory technology. Resulting im-

provements in cycling reliability come without in-

creasing memory cell size or complexity. First, an

advanced tunnel oxide increases the charge carry-

ing ability ten-fold. Second, the oxide area per cell

subjected to the tunneling electrical field is one-

tenth that of common EEPROMs, minimizing the

probability of oxide defects in the region. Finally, the

peak electric field during erasure is approximately 2

Mv/cm lower than EEPROM. The lower electric field

greatly reduces oxide stress and the probability of

failure.

The 28F001BX-B and 28F001BX-T are capable of

100,000 program/erase cycles on each parameter

block, main block and boot block.

ON-CHIP PROGRAMMING

ALGORITHM

The 28F001BX integrates the Quick Pulse program-

ming algorithm of prior Intel Flash Memory devices

on-chip, using the Command Register, Status Regis-

ter and Write State Machine (WSM). On-chip inte-

gration dramatically simplifies system software and

provides processor-like interface timings to the

Command and Status Registers. WSM operation, in-

ternal program verify and VPP high voltage presence

are monitored and reported via appropriate Status

flowchart for device programming. The entire se-

quence is performed with VPP at VPPH. Program

abort occurs when RPÝtransitions to VIL,orV

drops to VPPL. Although the WSM is halted, byte

data is partially programmed at the location where

programming was aborted. Block erasure or a re-

peat of byte programming will initialize this data to a

known value.

ON-CHIP ERASE ALGORITHM

As above, the Quick Erase algorithm of prior Intel

Flash Memory devices is now implemented internal-

ly, including all preconditioning of block data. WSM

operation, erase success and VPP high voltage pres-

ence are monitored and reported through the Status

Erase Confirm is written to the device after Erase

Setup has been written, both the Erase Status and

Program Status bits will be set to ‘‘1’’. When issuing

the Erase Setup and Erase Confirm commands, they

should be written to an address within the address

range of the block to be erased. Figure 10 shows a

system software flowchart for block erase.

Erase typically takes 1–4 seconds per block. The

Erase Suspend/Erase Resume command sequence

allows interrupt of this erase operation to read data

from a block other than that in which erase is

being performed. A system software flowchart is

shown in Figure 11.

The entire sequence is performed with VPP at VPPH.

Abort occurs when RPÝtransitions to VIL or VPP

falls to VPPL, while erase is in progress. Block data is

partially erased by this operation, and a repeat of

erase is required to obtain a fully erased block.

28F001BX-T/28F001BX-B

BOOT BLOCK PROGRAM AND

ERASE

The boot block is intended to contain secure code

which will minimally bring up a system and control

programming and erase of other blocks of the de-

vice, if needed. Therefore, additional ‘‘lockout’’ pro-

tection is provided to guarantee data integrity. Boot

block program and erase operations are enabled

through high voltage VHH on either RPÝor OEÝ,

and the normal program and erase command se-

quences are used. Reference the AC Waveforms for

Program/Erase.

If boot block program or erase is attempted while

RPÝis at VIH, either the Program Status or Erase

Status bit will be set to ‘‘1’’, reflective of the opera-

tion being attempted and indicating boot block lock.

Program/erase attempts while VIH kRPÝkVHH

produce spurious results and should not be attempt-

ed.

In-System Operation

For on-board programming, the RPÝpin is the most

convenient means of altering the boot block. Before

issuing Program or Erase confirms commands, RPÝ

must transition to VHH. Hold RPÝat this high volt-

age throughout the program or erase interval (until

after Status Register confirm of successful comple-

tion). At this time, it can return to VIH or VIL.

290406–7

Bus Command Comments

Operation

Write Program Data e40H

Setup Address eByte to be

Programmed

Write Program Data to be programmed

Address eByte to be

Programmed

Read Status Register Data.

Toggle OEÝor CEÝto

update Status Register

Standby Check SR.7

1eReady, 0 eBusy

Repeat for subsequent bytes.

Full status check can be done after each byte or after a

sequence of bytes.

Write FFH after the last byte programming operation to

reset the device to Read Array Mode.

Bus Command Comments

Operation

Standby Check SR.3

1eVPP Low Detect

Standby Check SR.4

1eByte Program Error

SR.3 MUST be cleared, if set during a program attempt,

before further attempts are allowed by the Write State

Machine.

SR.4 is only cleared by the Clear Status Register

Command, in cases where multiple bytes are

programmed before full status is checked.

If error is detected, clear the Status Register before

attempting retry or other error recovery.

Figure 9. 28F001BX Byte Programming Flowchart

28F001BX-T/28F001BX-B

290406–8

Bus Command Comments

Operation

Write Erase Data e20H

Setup Address eWithin Block to be erased

Write Erase Data eD0H

Address eWithin Block to be erased

Read Status Register Data.

Toggle OEÝor CEÝto update Status

Standby Check SR.7

1eReady, 0 eBusy

Repeat for subsequent blocks.

Full status check can be done after each block or after a sequence of

blocks.

Write FFH after the last block erase operation to reset the device to

Read Array Mode.

Bus Command Comments

Operation

Standby Check SR.3

1eVPP Low Detect

Standby Check SR.4, 5

Both 1 eCommand Sequence Error

Standby Check SR.5

1eBlock Erase Error

SR.3 MUST be cleared, if set during an erase attempt, before further

attempts are allowed by the Write State Machine.

SR.5 is only cleared by the Clear Status Register Command, in cases

where multiple blocks are erased before full status is checked.

If error is detected, clear the Status Register before attempting retry or

other error recovery.

Figure 10. 28F001BX Block Erase Flowchart

28F001BX-T/28F001BX-B

290406–9

Bus Command Comments

Operation

Write Erase Data eB0H

Suspend

Write Erase Data e70H

Status Register

Standby/ Read Status Register

Read Check SR.7

1eReady, 0 eBusy

Toggle OEÝor CEÝto

Update Status Register

Standby Check SR.6

1eSuspended

Write Read Array Data eFFH

Read Read array data from

block other than that

being erased.

Write Erase Resume Data eD0H

Figure 11. 28F001BX Erase Suspend/Resume Flowchart

Programming Equipment

For PROM programming equipment that cannot

bring RPÝto high voltage, OEÝprovides an alter-

nate boot block access mechanism. OEÝmust tran-

sition to VHH a minimum of 480 ns before the initial

program/erase setup command and held at VHH at

least 480 ns after program or erase confirm com-

mands are issued to the device. After this interval,

OEÝcan return to normal TTL levels.

DESIGN CONSIDERATIONS

Three-Line Output Control

Flash memories are often used in larger memory ar-

rays. Intel provides three control inputs to accommo-

date multiple memory connections. Three-line con-

trol provides for:

a) lowest possible memory power dissipation

b) complete assurance that data bus contention will

not occur

To efficiently use these control inputs, an address

decoder should enable CEÝ, while OEÝshould be

connected to all memory devices and the system’s

READÝcontrol line. This assures that only selected

memory devices have active outputs while deselect-

ed memory devices are in Standby Mode. RPÝ

should be connected to the system POWERGOOD

signal to prevent unintended writes during system

power transitions. POWERGOOD should also toggle

during system reset.

28F001BX-T/28F001BX-B

Power Supply Decoupling

Flash memory power switching characteristics re-

quire careful device coupling. System designers are

interested in 3 supply current issues; standby current

levels (ISB), active current levels (ICC) and transient

peaks producted by falling and rising edges of CEÝ.

Transient current magnitudes depend on the device

outputs’ capacitive and inductive loading. Two-line

control and proper decoupling capacitor selection

will suppress transient voltage peaks. Each device

should have a 0.1 mF ceramic capacitor connected

between its VCC and GND, and between its VPP and

GND. These high frequency, low inherent-induc-

tance capacitors should be placed as close as pos-

sible to the device. Additionally, for every 8 devices,

a 4.7 mF electrolytic capacitor should be placed at

the array’s power supply connection between VCC

and GND. The bulk capacitor will overcome voltage

slumps caused by PC board trace inductances.

VPP Trace on Printed Circuit Boards

Programming flash memories, while they reside in

the target system, requires that the printed circuit

board designer pay attention to the VPP power sup-

ply trace. The VPP pin supplies the memory cell cur-

rent for programming. Use similar trace widths and

layout considerations given to the VCC power bus.

Adequate VPP supply traces and decoupling will de-

crease VPP voltage spikes and overshoots.

VCC,V

PP,RP

ÝTransitions and the

Command/Status Registers

Programming and erase completion are not guaran-

teed if VPP drops below VPPH. If the VPP Status bit of

the Status Register (SR.3) is set to ‘‘1’’, a Clear

Status Register command MUST be issued before

further program/erase attempts are allowed by the

WSM. Otherwise, the Program (SR.4) or Erase

(SR.5) Status bits of the Status Register will be set

to ‘‘1’’ if error is detected. RPÝtransitions to VIL

during program and erase also abort the operations.

Data is partially altered in either case, and the com-

mand sequence must be repeated after normal op-

eration is restored. Device poweroff, or RPÝtran-

sitions to VIL, clear the Status Register to initial val-

ue 80H.

The Command Register latches commands as is-

sued by system software and is not altered by VPP

or CEÝtransitions or WSM actions. Its state upon

powerup, after exit from Deep-Powerdown or after

VCC transitions below VLKO, is FFH, or Read Array

Mode.

After program or erase is complete, even after VPP

transitions down to VPPL, the Command Register

must be reset to read array mode via the Read Array

command if access to the memory array is desired.

Power Up/Down Protection

The 28F001BX is designed to offer protection

against accidental erasure or programming during

power transitions. Upon power-up, the 28F001BX is

indifferent as to which power supply, VPP or VCC,

powers up first. Power supply sequencing is not re-

quired. Internal circuitry in the 28F001BX ensures

that the Command Register is reset to Read Array

mode on power up.

A system designer must guard against spurious

writes for VCC voltages above VLKO when VPP is

active. Since both WEÝand CEÝmust be low for a

command write, driving either to VIH will inhibit

writes. The Command Register architecture provides

an added level of protection since alteration of mem-

ory contents only occurs after successful completion

of the two-step command sequences.

Finally, the device is disabled, until RPÝis brought

to VIH, regardless of the state of its control inputs.

This provides an additional level of protection.

28F001BX Power Dissipation

When designing portable systems, designers must

consider battery power consumption not only during

device operation, but also for data retention during

system idle time. Flash nonvolatility increases us-

able battery life because the 28F001BX does not

consume any power to retain code or data when the

system is off.

In addition, the 28F001BX’s Deep-Powerdown mode

ensures extremely low power dissipation even when

system power is applied. For example, laptop and

other PC applications, after copying BIOS to DRAM,

can lower RPÝto VIL, producing negligible power

consumption. If access to the boot code is again

needed, as in case of a system RESETÝ, the part

can again be accessed, following the tPHAV wakeup

cycle required after RPÝis first raised back to VIH.

The first address presented to the device while in

powerdown requires time tPHAV, after RPÝtran-

sitions high, before outputs are valid. Further ac-

cesses follow normal timing. See AC Characteris-

ticsÐRead-Only Operations and Figure 12 for more

information.

28F001BX-T/28F001BX-B

ABSOLUTE MAXIMUM RATINGS*

Operating Temperature

During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0§Cto70

(1)

During Erase/Program ÀÀÀÀÀÀÀÀÀÀÀ0§Cto70

(1)

Operating Temperature

During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀb40§Ctoa

85§C(2)

During Erase/Program ÀÀÀÀÀÀb40§Ctoa

85§C(2)

Temperature under Bias ÀÀÀÀÀÀÀÀÀb10§Cto80

(1)

Temperature under Bias ÀÀÀÀÀÀÀb20§Ctoa

90§C(2)

Storage TemperatureÀÀÀÀÀÀÀÀÀÀÀÀÀb65§Cto125

Voltage on Any Pin

(except A9,RP

,OE

CC and VPP)

with Respect to GND ÀÀÀÀÀÀÀÀÀÀb2.0V to 7.0V(3)

Voltage on A9,RP

, and OEÝ

with Respect to GND ÀÀÀÀÀÀÀb2.0V to 13.5V(3, 4)

VPP Program Voltage

with Respect to GND

During Erase/Program ÀÀÀÀÀÀb2.0V to 14.0V(3, 4)

VCC Supply Voltage

with Respect to GND ÀÀÀÀÀÀÀÀÀÀb2.0V to 7.0V(3)

Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA(5)

NOTICE: This is a production data sheet. The specifi-

cations are subject to change without notice.

WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

OPERATING CONDITIONS

Symbol Parameter Min Max Unit

TAOperating Temperature(1) 070

AOperating Temperature(2) b40 85 §C

VCC Supply Voltage 4.50 5.50 V

NOTES:

1. Operating temperature is for commercial product defined by this specification.

2. Operating temperature is for extended temperature product defined by this specification.

3. Minimum DC voltage is b0.5V on input/output pins. During transitions, this level may undershoot to b2.0V for periods

k20 ns. Maximum DC voltage on input/output pins is VCC a0.5V which, during transitions, may overshoot to VCC a2.0V

for periods k20 ns.

4. Maximum DC voltage on A9or VPP may overshoot to a14.0V for periods k20 ns.

5. Output shorted for no more than one second. No more than one output shorted at a time.

DC CHARACTERISTICS

VCC e5.0V g10%, TAe0§Ctoa

70§C

Symbol Parameter Notes Min Typ Max Unit Test Conditions

IIL Input Load Current 1 g1.0 mAV

CC eVCC Max

VIN eVCC or GND

ILO Output Leakage Current 1 g10 mAV

CC eVCC Max

VOUT eVCC or GND

ICCS VCC Standby Current 1.2 2.0 mA VCC eVCC Max

CEÝeRPÝeVIH

30 100 mAV

CC eVCC Max

CEÝeRPÝeVCC g0.2V

ICCD VCC Deep Power-Down Current 1 0.05 1.0 mARP

GND g0.2V

28F001BX-T/28F001BX-B

DC CHARACTERISTICS (Continued)

VCC e5.0V g10%, TAe0§Ctoa

70§C

Symbol Parameter Notes Min Typ Max Unit Test Conditions

ICCR VCC Read Current 1 13 30 mA VCC eVCC Max, CEÝeVIL

fe8 MHz, IOUT e0mA

CCP VCC Programming Current 1 5 20 mA Programming in Progress

ICCE VCC Erase Current 1 6 20 mA Erase in Progress

ICCES VCC Erase Suspend Current 1, 2 5 10 mA Erase Suspended

CEÝeVIH

IPPS VPP Standby Current 1 g1g10 mAV

PP sVCC

90 200 mAV

PP lVCC

IPPD VPP Deep Power-Down Current 1 0.80 1.0 mARP

GND g0.2V

IPPP VPP Programming Current 1 6 30 mA VPP eVPPH

Programming in Progress

IPPE VPP Erase Current 1 6 30 mA VPP eVPPH

Erase in Progress

IPPES VPP Erase Suspend Current 1 90 300 mAV

PP eVPPH

Erase Suspended

IID A9Intelligent Identifier Current 1 90 500 mAA

VIL Input Low Voltage b0.5 0.8 V

VIH Input High Voltage 2.0 VCC a0.5 V

VOL Output Low Voltage 0.45 V VCC eVCC Min

IOL e5.8 mA

VOH Output High Voltage 2.4 V VCC eVCC Min

IOH e2.5 mA

VID A9Intelligent Identifier Voltage 11.5 13.0 V

VPPL VPP during Normal Operations 3 0.0 6.5 V

VPPH VPP during Prog/Erase Operations 11.4 12.0 12.6 V

VLKO VCC Erase/Write Lock Voltage 2.5 V

VHH RPÝ,OE

ÝUnlock Voltage 11.4 12.6 V Boot Block Prog/Erase

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC e5.0V, VPP e12.0V, TAe25§C. These currents

are valid for all product versions (packages and speeds).

2. ICCES is specified with the device deselected. If the 28F001BX is read while in Erase Suspend mode, current draw is the

sum of ICCES and ICCR.

3. Erase/Programs are inhibited when VPP eVPPL and not guaranteed in the range between VPPH and VPPL.

28F001BX-T/28F001BX-B

DC CHARACTERISTICS

VCC e5.0V g10%, TAeb

40§Ctoa

85§C

Symbol Parameter Notes Min Typ Max Unit Test Conditions

IIL Input Load Current 1 g1.0 mAV

CC eVCC Max

VIN eVCC or GND

ILO Output Leakage Current 1 g10 mAV

CC eVCC Max

VOUT eVCC or GND

ICCS VCC Standby Current 1.2 2.0 mA VCC eVCC Max

CEÝeRPÝeVIH

30 150 mAV

CC eVCC Max

CEÝeRPÝeVCC g0.2V

ICCD VCC Deep Power-Down Current 1 0.05 2.0 mARP

GND g0.2V

ICCR VCC Read Current 1 13 35 mA VCC eVCC Max, CEÝeVIL

fe8 MHz, IOUT e0mA

CCP VCC Programming Current 1 5 20 mA Programming in Progress

ICCE VCC Erase Current 1 6 20 mA Erase in Progress

ICCES VCC Erase Suspend Current 1, 2 5 10 mA Erase Suspended

CEÝeVIH

IPPS VPP Standby Current 1 g1g15 mAV

PP sVCC

90 400 mAV

PP lVCC

IPPD VPP Deep Power-Down Current 1 0.80 1.0 mARP

GND g0.2V

IPPP VPP Programming Current 1 6 30 mAV

PP eVPPH

Programming in Progress

IPPE VPP Erase Current 1 6 30 mA VPP eVPPH

Erase in Progress

IPPES VPP Erase Suspend Current 1 90 400 mAV

PP eVPPH

Erase Suspended

IID A9Intelligent Identifier Current 1 90 500 mAA

VIL Input Low Voltage b0.5 0.8 V

VIH Input High Voltage 2.0 VCCa0.5 V

VOL Output Low Voltage 0.45 V VCC eVCC Min

IOL e5.8 mA

VOH1 Output High Voltage (TTL) 2.4 V VCC eVCC Min

IOH e2.5 mA

VOH2 Output High Voltage (CMOS) 0.85 VCC VV

CC eVCC Min

IOH eb

2.5 mA

VCCb0.4 VCC eVCC Min

IOH eb

100 mA

VID A9Intelligent Identifier Voltage 11.5 13.0 V

VPPL VPP during Normal Operations 3 0.0 6.5 V

VPPH VPP during Prog/Erase Operations 11.4 12.0 12.6 V

VLKO VCC Erase/Write Lock Voltage 2.5 V

VHH RPÝ,OE

ÝUnlock Voltage 11.4 12.6 V Boot Block Prog/Erase

28F001BX-T/28F001BX-B

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC e5.0V, VPP e12.0V, TAe25§C. These currents

are valid for all product versions (packages and speeds).

2. ICCES is specified with the device deselected. If the 28F001BX is read while in Erase Suspend mode, current draw is the

sum of ICCES and ICCR.

3. Erase/Programs are inhibited when VPP eVPPL and not guaranteed in the range between VPPH and VPPL.

CAPACITANCE(1) TAe25§C, f e1 MHz

Symbol Parameter Max Unit Conditions

CIN Input Capacitance 8 pF VIN e0V

COUT Output Capacitance 12 pF VOUT e0V

NOTE:

1. Sampled, not 100% tested.

AC INPUT/OUTPUT REFERENCE WAVEFORM

290406–10

A.C. test inputs are driven at VOH (2.4 VTTL) for a Logic ‘‘1’’ and VOL (0.45 VTTL) for a Logic ‘‘0’’. Input timing begins at

VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) k10 ns.

STANDARD TEST CONFIGURATION

AC TESTING LOAD CIRCUIT

290406–11

CLe100 pF

CLIncludes Jig Capacitance

RLe3.3 kX

HIGH SPEED TEST CONFIGURATION

AC TESTING LOAD CIRCUIT

290406–23

CLe30 pF

CLIncludes Jig Capacitance

RLe3.3 kX

28F001BX-T/28F001BX-B

AC CHARACTERISTICSÐRead-Only Operations(1)

Symbol Parameter Notes

28F001BX-70 28F001BX-90

Units

VCC e5V VCC e5V VCC e5V

g5% g10% g10%

30 pF 100 pF 100 pF

Min Max Min Max Min Max

tAVAV tRC Read Cycle Time 70 75 90 ns

tAVQV tACC Address to Output Delay 70 75 90 ns

tELQV tCE CEÝto Output Delay 2 70 75 90 ns

tPHQV tPWH RPÝto Output Delay 600 600 600 ns

tGLQV tOE OEÝto Output Delay 2 27 30 35 ns

tELQX tLZ CEÝto Output in Low Z 3 0 0 0 ns

tEHQZ tHZ CEÝto Output in High Z 3 55 55 35 ns

tGLQX tOLZ OEÝto Output in Low Z 3 0 0 0 ns

tGHQZ tDF OEÝto Output in High Z 3 30 30 30 ns

tOH Output Hold from 3 0 0 0 ns

Address CEÝ,orOE

Change, Whichever

Occurs First

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OEÝmay be delayed up to tCE –tOE after the falling edge of CEÝwithout impact on tCE.

3. Sampled, but not 100% tested.

4. See High Speed Test Configuration.

5. See Standard Test Configuration.

28F001BX-T/28F001BX-B

AC CHARACTERISTICSÐRead-Only Operations(1)

E28F001BX-150

Unit

E28F001BX-120 TE28F001BX-150

Versions(2) VCC g10% N28F001BX-120 N28F001BX-150

P28F001BX-120 TN28F001BX-150

P28F001BX-150

Symbol Parameter Notes Min Max Min Max

tAVAV tRC Read Cycle Time 120 150 ns

tAVQV tACC Address to Output Delay 120 150 ns

tELQV tCE CEÝto Output Delay 3 120 150 ns

tPHQV tPWH RPÝHigh to Output Delay 600 600 ns

tGLQV tOE OEÝto Output Delay 3 50 55 ns

tELQX tLZ CEÝto Output Low Z 4 0 0 ns

tEHQZ tHZ CEÝHigh to Output High Z 4 55 55 ns

tGLQX tOLZ OEÝto Output Low Z 4 0 0 ns

tGHQZ tDF OEÝHigh to Output High Z 4 30 30 ns

tOH Output Hold from 4 0 0 ns

Addresses, CEÝor OEÝ

Change, Whichever is First

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. Model Number Prefixes: E eTSOP (Standard Pinout), N ePLCC, P ePDIP, T eExtended Temperature. Refer to

standard test configuration.

3. OEÝmay be delayed up to tCE –tOE after the falling edge of CEÝwithout impact on tCE.

4. Sampled, not 100% tested.

28F001BX-T/28F001BX-B

Figure 12. AC Waveform for Read Operations

290406–12

28F001BX-T/28F001BX-B

AC CHARACTERISTICSÐWrite/Erase/Program Operations(1, 9)

Symbol Parameter Notes

28F001BX-70 28F001BX-90

Units

VCC e5V VCC e5V VCC e5V

g5%(10) g10%(11) g10%(11)

30 pF 100 pF 100 pF

Min Max Min Max Min Max

tAVAV tWC Write Cycle Time 70 75 90 ns

tPHWL tPS RPÝHigh Recovery to WEÝ2 480 480 480 ns

Going Low

tELWL tCS CEÝSetup to WEÝGoing Low 10 10 10 ns

tWLWH tWP WEÝPulse Width 35 40 40 ns

tPHHWH tPHS RPÝVHH Setup to WEÝGoing 2 100 100 100 ns

High

tVPWH tVPS VPP Setup to WEÝGoing High 2 100 100 100 ns

tAVWH tAS Address Setup to WEÝGoing 3 35 40 40 ns

High

tDVWH tDS Data Setup to WEÝGoing High 4 35 40 40 ns

tWHDX tDH Data Hold from WEÝHigh 10 10 10 ns

tWHAX tAH Address Hold from WEÝHigh 10 10 10 ns

tWHEH tCH CEÝHold from WEÝHigh 10 10 10 ns

tWHWL tWPH WEÝPulse Width High 35 35 35 ns

tWHQV1 Duration of Programming 5, 6, 7 15 15 15 ms

Operation

tWHQV2 Duration of Erase Operation 5, 6, 7 1.3 1.3 1.3 sec

(Boot)

tWHQV3 Duration of Erase Operation 5, 6, 7 1.3 1.3 1.3 sec

(Parameter)

tWHQV4 Duration of Erase Operation 5, 6, 7 3.0 3.0 3.0 sec

(Main)

tWHGL Write Recovery before Read 0 0 0 ms

tQVVL tVPH VPP Hold from Valid SRD 2, 6 0 0 0 ns

tQVPH tPHH RPÝVHH Hold from Valid SRD 2, 7 0 0 0 ns

tPHBR Boot-Block Relock Delay 2 100 100 100 ns

NOTES:

1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to

AC Characteristics for Read-Only Operations.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid AIN for byte programming or block erasure.

4. Refer to Table 3 for valid DIN for byte programming or block erasure.

5. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel

Flash Memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase

verify (erasing).

6. Program and erase durations are measured to completion (SR.7 e1). VPP should be held at VPPH until determination of

program/erase success (SR.3/4/5 e0).

7. For boot block programming and erasure, RPÝshould be held at VHH until determination of program/erase success

(SR.3/4/5 e0).

8. Alternate boot block access method.

9. Erase/Program Cycles on extended temperature products is 10,000 cycles.

10. See high speed test configuration.

11. See standard test configuration.

28F001BX-T/28F001BX-B

AC CHARACTERISTICSÐWrite/Erase/Program Operations(1, 9)

Versions VCC g10%(10) 28F001BX-120 28F001BX-150 Unit

Symbol Parameter Notes Min Max Min Max

tAVAV tWC Write Cycle Time 120 150 ns

tPHWL tPS RPÝHigh Recovery to WEÝGoing Low 2 480 480 ns

tELWL tCS CEÝSetup to WEÝGoing Low 10 10 ns

tWLWH tWP WEÝPulse Width 50 50 ns

tPHHWH tPHS RPÝVHH Setup to WEÝGoing High 2 100 100 ns

tVPWH tVPS VPP Setup to WEÝGoing High 2 100 100 ns

tAVWH tAS Address Setup to WEÝGoing High 3 50 50 ns

tDVWH tDS Data Setup to WEÝGoing High 4 50 50 ns

tWHDX tDH Data Hold from WEÝHigh 10 10 ns

tWHAX tAH Address Hold from WEÝHigh 10 10 ns

tWHEH tCH CEÝHold from WEÝHigh 10 10 ns

tWHWL tWPH WEÝPulse Width High 50 50 ns

tWHQV1 Duration of Programming Operation 5, 6, 7 15 15 ms

tWHQV2 Duration of Erase Operation (Boot) 5, 6, 7 1.3 1.3 sec

tWHQV3 Duration of Erase Operation (Parameter) 5, 6, 7 1.3 1.3 sec

tWHQV4 Duration of Erase Operation (Main) 5, 6, 7 3.0 3.0 sec

tWHGL Write Recovery before Read 0 0 ms

tQVVL tVPH VPP Hold from Valid SRD 2, 6 0 0 ns

tQVPH tPHH RPÝVHH Hold from Valid SRD 2, 7 0 0 ns

tPHBR Boot-Block Relock Delay 2 100 100 ns

PROM Programmer Specifications

Versions VCC g10% 28F001BX-120 28F001BX-150 Unit

Symbol Parameter Notes Min Max Min Max

tGHHWL OEÝVHH Setup to WEÝGoing Low 2, 8 480 480 ns

tWHGH OEÝVHH Hold from WEÝHigh 2, 8 480 480 ns

NOTES:

1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to

AC Characteristics for Read-Only Operations.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid AIN for byte programming or block erasure.

4. Refer to Table 3 for valid DIN for byte programming or block erasure.

5. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel

Flash Memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase

verify (erasing).

6. Program and erase durations are measured to completion (SR.7 e1). VPP should be held at VPPH until determination of

program/erase success (SR.3/4/5 e0).

7. For boot block programming and erasure, RPÝshould be held at VHH until determination of program/erase success

(SR.3/4/5 e0).

8. Alternate boot block access method.

9. Erase/Program Cycles on extended temperature products is 10,000 cycles.

10. See standard test configuration.

28F001BX-T/28F001BX-B

ERASE AND PROGRAMMING PERFORMANCE

Parameter Notes 28F001BX-120 28F001BX-150 Unit

Min Typ(1) Max Min Typ(1) Max

Boot Block Erase Time 2 2.10 14.9 2.10 14.9 Sec

Boot Block Program Time 2 0.15 0.52 0.15 0.52 Sec

Parameter Block Erase Time 2 2.10 14.6 2.10 14.6 Sec

Parameter Block Program Time 2 0.07 0.26 0.07 0.26 Sec

Main Block Erase Time 2 3.80 20.9 3.80 20.9 Sec

Main Block Program Time 2 2.10 7.34 2.10 7.34 Sec

Chip Erase Time 2 10.10 65 10.10 65 Sec

Chip Program Time 2 2.39 8.38 2.39 8.38 Sec

NOTES:

1. 25§C, 12.0 VPP.

2. Excludes System-Level Overhead.

28F001BX-T/28F001BX-B

290406–19

Figure 13. 28F001BX Typical

Programming Capability

290406–20

Figure 14. 28F001BX Typical

Programming Time at 12V

290406–21

Figure 15. 28F001BX Typical Erase Capability

290406–22

Figure 16. 28F001BX Typical Erase Time at 12V

28F001BX-T/28F001BX-B

Figure 17. AC Waveform for Write Operations

290406–13

28F001BX-T/28F001BX-B

290406–15

Figure 18. Alternate Boot Block Access Method Using OEÝ

28F001BX-T/28F001BX-B

AC CHARACTERISTICS FOR CEÝ-CONTROLLED WRITES(1)

Symbol Parameter Notes

28F001BX-70 28F001BX-90

Units

VCC e5V VCC e5V VCC e5V

g5%(8) g10%(9) g10%(9)

30 pF 100 pF 100 pF

Min Max Min Max Min Max

tAVAV tWC Write Cycle Time 70 75 90 ns

tPHEL tPS RPÝHigh Recovery to CEÝ2 480 480 480 ns

Going Low

tWLEL tWS WEÝSetup to CEÝGoing Low 0 0 0 ns

tELEH tCP CEÝPulse Width 50 55 55 ns

tPHHEH tPHS RPÝVHH Setup to CEÝGoing 2 100 100 100 ns

High

tVPEH tVPS VPP Setup to CEÝGoing High 2 100 100 100 ns

tAVEH tAS Address Setup to CEÝGoing 3 35 40 40 ns

High

tDVEH tDS Data Setup to CEÝGoing High 4 35 40 40 ns

tEHDX tDH Data Hold from CEÝHigh 10 10 10 ns

tEHAX tAH Address Hold from CEÝHigh 10 10 10 ns

tEHWH tWH WEÝHold from CEÝHigh 0 0 0 ns

tEHEL tEPH CEÝPulse Width High 20 20 20 ns

tEHQV1 Duration of Programming 5, 6 15 15 15 ms

Operation

tEHQV2 Duration of Erase Operation 5, 6 1.3 1.3 1.3 sec

(Boot)

tEHQV3 Duration of Erase Operation 5, 6 1.3 1.3 1.3 sec

(Parameter)

tEHQV4 Duration of Erase Operation 5, 6 3.0 3.0 3.0 sec

(Main)

tEHGL Write Recovery before Read 0 0 0 ms

tQVVL tVPH VPP Hold from Valid SRD 2, 5 0 0 0 ns

tQVPH tPHH RPÝVHH Hold from Valid SRD 2, 6 0 0 0 ns

tPHBR Boot-Block Relock Delay 2 100 100 100 ns

NOTES:

1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CEÝand WEÝ. In systems where

CEÝdefines the write pulse width (within a longer WEÝtiming waveform), all set-up, hold and inactive WEÝtimes should

be measured relative to the CEÝwaveform.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid AIN for byte programming or block erasure.

4. Refer to Table 3 for valid DIN for byte programming or block erasure.

5. Program and erase durations are measured to completion (SR.7 e1). VPP should be held at VPPH until determination of

program/erase success (SR.3/4/5 e0).

6. For boot block programming and erasure, RPÝshould be held at VHH until determination of program/erase success

(SR.3/4/5 e0).

7. Alternate boot block access method.

8. See high speed test configuration.

9. See standard text configuration.

28F001BX-T/28F001BX-B

AC CHARACTERISTICS FOR CEÝ-CONTROLLED WRITES(1)

Versions VCC g10% 28F001BX-120 28F001BX-150 Unit

Symbol Parameter Notes Min Max Min Max

tAVAV tWC Write Cycle Time 120 150 ns

tPHEL tPS RPÝHigh Recovery to CEÝGoing Low 2 480 480 ns

tWLEL tWS WEÝSetup to CEÝGoing Low 0 0 ns

tELEH tCP CEÝPulse Width 70 70 ns

tPHHEH tPHS RPÝVHH Setup to CEÝGoing High 2 100 100 ns

tVPEH tVPS VPP Setup to CEÝGoing High 2 100 100 ns

tAVEH tAS Address Setup to CEÝGoing High 3 50 50 ns

tDVEH tDS Data Setup to CEÝGoing High 4 50 50 ns

tEHDX tDH Data Hold from CEÝHigh 10 10 ns

tEHAX tAH Address Hold from CEÝHigh 15 15 ns

tEHWH tWH WEÝHold from CEÝHigh 0 0 ns

tEHEL tEPH CEÝPulse Width High 25 25 ns

tEHQV1 Duration of Programming Operation 5, 6 15 15 ms

tEHQV2 Duration of Erase Operation (Boot) 5, 6 1.3 1.3 sec

tEHQV3 Duration of Erase Operation (Parameter) 5, 6 1.3 1.3 sec

tEHQV4 Duration of Erase Operation (Main) 5, 6 3.0 3.0 sec

tEHGL Write Recovery before Read 0 0 ms

tQVVL tVPH VPP Hold from Valid SRD 2, 5 0 0 ns

tQVPH tPHH RPÝVHH Hold from Valid SRD 2, 6 0 0 ns

tPHBR Boot-Block Relock Delay 2 100 100 ns

PROM Programmer Specifications

Versions VCC g10% 28F001BX-120 28F001BX-150 Unit

Symbol Parameter Notes Min Max Min Max

tGHHEL OEÝVHH Setup to CEÝGoing Low 2, 7 480 480 ns

tEHGH OEÝVHH Hold from CEÝHigh 2, 7 480 480 ns

NOTES:

1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CEÝand WEÝ. In systems where

CEÝdefines the write pulse width (within a longer WEÝtiming waveform), all set-up, hold and inactive WEÝtimes should

be measured relative to the CEÝwaveform.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid AIN for byte programming or block erasure.

4. Refer to Table 3 for valid DIN for byte programming or block erasure.

5. Program and erase durations are measured to completion (SR.7 e1). VPP should be held at VPPH until determination of

program/erase success (SR.3/4/5 e0).

6. For boot block programming and erasure, RPÝshould be held at VHH until determination of program/erase success

(SR.3/4/5 e0).

7. Alternate boot block access method.

28F001BX-T/28F001BX-B

Figure 19. Alternate AC Waveform for Write Operations

290406–16

28F001BX-T/28F001BX-B

ORDERING INFORMATION

290406–18

VALID COMBINATIONS:

32-Lead TSOP 32-Lead PLCC 32-Pin PDIP

Commercial E28F001BX-T70 N28F001BX-T70 P28F001BX-T70

E28F001BX-T90 N28F001BX-T90 P28F001BX-T90

E28F001BX-T120 N28F001BX-T120 P28F001BX-T120

E28F001BX-T150 N28F001BX-T150 P28F001BX-T150

E28F001BX-B70 N28F001BX-B70 P28F001BX-B70

E28F001BX-B90 N28F001BX-B90 P28F001BX-B90

E28F001BX-B120 N28F001BX-B120 P28F001BX-B120

E28F001BX-B150 N28F001BX-B150 P28F001BX-B150

Extended TE28F001BX-T90 TN28F001BX-T90 TP28F001BX-T90

TE28F001BX-T150 TN28F001BX-T150 TP28F001BX-B90

TE28F001BX-B90 TN28F001BX-B90

TE28F001BX-B150 TN28F001BX-B150

ADDITIONAL INFORMATION

References

Order Number Document

292046 AP-316 ‘‘Using Flash Memory for In-System Reprogrammable Nonvolatile Storage’’

292077 AP-341 ‘‘Designing an Updateable BIOS Using Flash Memory’’

292161 AP-608 ‘‘Implementing a Plug and Play BIOS Using Intel’s Boot Block Flash Memory’’

292178 AP-623 ‘‘Multi-Site Layout Planning Using Intel’s Boot Block Flash Memory’’

294005 ER-20 ‘‘ETOX II Flash Memory Technology’’

28F001BX-T/28F001BX-B

Revision History

Number Description

-004 Removed Preliminary classification.

Latched address A16 in Figure 5.

Updated Boot Block Program and Erase section: ‘‘If boot block program or erase is attempted

while RPÝis at VIH,either the Program Status or Erase Status bit will be set to ‘‘1’’,

reflective of the operation being attempted and indicating boot block lock.’’

Updated Figure 11, 28F001BX Erase Suspend/Resume Flowchart

Added DC Characteristics typical current values

Combined VPP Standby current and VPP Read current into one VPP Standby current spec with

two test conditions (DC Characteristics table)

Added maximum program/erase times to Erase and Programming Performance table.

Added Figures 13–16

Added Extended Temperature proliferations

-005 PWD changed to RPÝfor JEDEC standardization compatibility

Revised symbols, i.e.; CE,OE, etc. to CEÝ,OE

, etc.

-006 Added specifications for -90 and -70 product versions.

Added VOH CMOS Specification.

-007 Added reference to 28F001BN.