1
®
FN3976.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1997, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP4020
Half Amp Full Bridge Power Driver for
Small 3V, 5V and 12V DC Motors
In the Functional Block Diagram of the HIP4020, the four
switches and a load are arranged in an H-Configuration so
that the drive voltage from terminals OUTA and OUTB can
be cross-switched to change the direction of current flow in
the load. This is commonly known as 4-quadrant load
control. As shown in the Block Diagram, switches Q1 and Q4
are conducting or in an ON state when current flows from
VDD through Q1 to the load, and then through Q4 to terminal
VSSB; where load terminal OUTA is at a positive potential
with respect to OUTB. Switches Q1 and Q4 are operated
synchronously by the control logic. The control logic
switches Q3 and Q2 to an open or OFF state when Q1 and
Q4 are switched ON. To reverse the current flow in the load,
the switch states are reversed where Q1 and Q4 are OFF
while Q2 and Q3 are ON. Consequently, current then flows
from VDD through Q3, through the load, and through Q2 to
terminal VSSA, and load terminal OUTB is then at a positive
potential with respect to OUTA.
Terminals ENA and ENB are ENABLE Inputs for the Logic A
and B Input Controls. The ILF output is an Overcurrent Limit
Fault Flag Output and indicates a fault condition for either
Output A or B or both. The VDD and VSS are the Power
Supply reference terminals for the A and B Control Logic
Inputs and ILF Output. While the VDD positive power supply
terminal is internally connected to each bridge driver, the
VSSA and VSSB Power Supply terminals are separate and
independent from VSS and may be more negative than the
VSS ground reference terminal. The use of level shifters in
the gate drive circuitry to the NMOS (low-side) output stages
allows controlled level shifting of the output drive relative to
ground.
Features
• Two Independent Controlled Complementary MOS Power
Output Half H-Drivers (Full-Bridge) for Nominal 3V to 12V
Power Supply Operation
• Split ±Voltage Power Supply Option for Output Drivers
• Load Switching Capabilities to 0.5A
• Single Supply Range +2.5V to +15V
• Low Standby Current
• CMOS/TTL Compatible Input Logic
• Over-Temperature Shutdown Protection
• Overcurrent Limit Protection
• Overcurrent Fault Flag Output
• Direction, Braking and PWM Control
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• DC Motor Driver
• Relay and Solenoid Drivers
• Stepper Motor Controller
• Air Core Gauge Instrument Driver
• Speedometer Displays
• Tachometer Displays
• Remote Power Switch
• Battery Operated Switch Circuits
• Logic and Microcontroller Operated Switch
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE (°C) PACKAGE
PKG.
DWG. #
HIP4020IB HIP4020IB -40 to 85 20 Ld SOIC M20.3
HIP4020IBZ
(Note)
HIP4020IBZ -40 to 85 20 Ld SOIC
(Pb-free)
M20.3
HIP4020IBZT
(Note)
HIP4020IBZ -40 to 85 20 Ld SOIC
Tape and Reel
(Pb-free)
M20.3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Data Sheet December 20, 2005
2FN3976.3
December 20, 2005
Pinout
HIP4020 (SOIC)
TOP VIEW
Block Diagram
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
NC
ILF
B2
ENB
B1
VSS
A1
ENA
A2
NC
NC
NC
OUTB
VSSB
VDD
VSSA
OUTA
NC
VDD
NC
VSSB
VDD
OUTB
LOAD
OUTA
B1
B2
ENB
A1
A2
ENA
ILF
VSS VSSA
Q1
Q3
Q2
Q4
CONTROL
LOGIC B
CONTROL
LOGIC A
ISENSE
TSENSE
ISENSE
ISENSE
ISENSE
OVER TEMP. AND CURRENT LIMIT,
LEVEL SHIFT, DRIVE CONTROL
HIP4020
3FN3976.3
December 20, 2005
Absolute Maximum Ratings Thermal Information
Supply Voltage; VDD to VSS or VSSA or VSSB . . . . . . . . . . . . .+15V
Neg. Output Supply Voltage, (VSSA, VSSB) . . . . . . . . . . . . (Note 1)
DC Logic Input Voltage (Each Input) . . . (VSS -0.5V) to (VDD +0.5V)
DC Logic Input Current (Each Input) . . . . . . . . . . . . . . . . . . . . .±15mA
ILF Fault Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±15mA
Output Load Current, (Self Limiting, See Elec. Spec.). . . . ±IO(LIMIT)
Operating Conditions TA = 25°C
Typical Operating Supply Voltage Range, VDD . . . . . . . +3 to +12V
Low Voltage Logic Retention, Min. VDD. . . . . . . . . . . . . . . . . . . .+2V
Idle Supply Current; No Load, VDD = +5V. . . . . . . . . . . . . . . .0.8mA
Typical P+N Channel rDS(ON), VDD = +5V, 0.5A Load . . . . . . . . 2Ω
Thermal Resistance (Typical, Note 2) θJA (°C/W)
Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . . 105
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. VSS is the required common ground reference for the logic input switching. The load currents may be switched positive and negative in reference
to the VSS common ground by using a split supply for VDD (positive) to VSSA and VSSB (negative). For an uneven split in the supply voltage,
the Maximum Negative Output Supply Voltage for VSSA and VSSB is limited by the Maximum VDD to VSSA or VSSB ratings. Since the VDD pins
are internally tied together, the voltage on each VDD pins must be equal and common.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
3. Refer to the Truth Table and the VEN to VOUT Switching Waveforms. Current, IO refers to IOUTA or IOUTB as the Output Load current. Note that
ENA controls OUTA and ENB controls OUTB. Each Half H-Switch has independent control from the respective A1, A2, ENA or B1, B2, ENB
inputs. Refer to the Terminal Information Table for external pin connections to establish mode control switching. Figure 1 shows a typical
application circuit used to control a DC Motor.
Electrical Specifications TA = 25°C, VDD = +5V, VSSA = VSSB = VSS = 0V, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Input Leakage Current ILEAK VDD = +15V - - 25 nA
Low Level Input Voltage VIL VSS -0.8V
High Level Input Voltage VIH 2-V
DD V
ILF Output Low, Sink Current IOH VOUT = 0.4V, VDD = +12V 15 - - mA
ILF Output High, Source Current IOL VOUT = 11.6V, VDD = +12V - - -15 mA
Input Capacitance CIN -2-pF
P-Channel rDS(ON), Low Supply Voltage rDS(ON) VDD = +3V, ISOURCE = 250mA - 1.6 2.1 Ω
N-Channel rDS(ON), Low Supply Voltage rDS(ON) VDD = +3V, ISINK = 250mA - 1 1.5 Ω
P-Channel rDS(ON), High Supply Voltage rDS(ON) VDD = +12V, ISOURCE = 400mA - 0.6 1.2 Ω
N-Channel rDS(ON), High Supply Voltage rDS(ON) VDD = +12V, ISINK = 400mA - 0.5 1.1 Ω
OUTA, OUTB Source Current Limiting IO(LIMIT) VDD = +6V, VSS = 0V, VSSA = VSSB = -6V 480 625 1500 mA
OUTA, OUTB Sink Current Limiting -IO(LIMIT) VDD = +6V, VSS = 0V, VSSA = VSSB = -6V 480 800 1500 mA
Idle Supply Current; No Load IDD -0.81.5mA
OUTA, OUTB Voltage High VOH ISOURCE = 450mA 4.2 4.5 - V
OUTA, OUTB Voltage Low VOL ISINK = 450mA - 0.4 0.6 V
OUTA, OUTB Voltage High VOH VDD = +3V, ISOURCE = 250mA 2.415 2.6 - V
OUTA, OUTB Voltage Low VOL VDD = +3V, ISINK = 250mA - 0.25 0.375 V
OUTA, OUTB Source Current Limiting IO(LIMIT) VDD = +12V 480 625 1500 mA
OUTA, OUTB Sink Current Limiting -IO(LIMIT) VDD = +12V 480 800 1500 mA
OUTA, OUTB Source Current Limiting IO(LIMIT) VDD = +3V 480 625 1500 mA
OUTA, OUTB Sink Current Limiting -IO(LIMIT) VDD = +3V 480 800 1500 mA
HIP4020
4FN3976.3
December 20, 2005
Thermal Shutdown TSD - 145 - °C
Response Time: VEN to VOUT
Turn-On: Prop Delay
tPLH IO = 0.5A (Note 3) - 2.5 - µs
Rise Time tr-4-µs
Turn-Off: Prop Delay tPHL -0.1- µs
Fall Time tf-0.1- µs
Electrical Specifications TA = 25°C, VDD = +5V, VSSA = VSSB = VSS = 0V, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Pin Descriptions
PIN NUMBER SYMBOL DESCRIPTION
12, 19 VDD Positive Power Supply pins; internally common and externally connect to the same Positive Supply (V+).
15 VSSA Negative Power Supply pin; Negative or Ground return for Switch Driver A; externally connect to the Supply
(V-).
16 VSSB Negative Power Supply pin; Negative or Ground return for Switch Driver B; externally connect to the Supply
(V-).
6V
SS Common Ground pin for the Input Logic Control circuits. May be used as a common ground with VSSA and
VSSB.
8, 5 A1, B1 Input pins used to control the direction of output load current to/from OUTA and OUTB, respectively. When
connected, A1 and B1 can be controlled from the same logic signal to change the directional rotation of a
motor.
9, 3 A2, B2 Input pins used to force a low state on OUTA and OUTB, respectively. When connected, A2 and B2 can be
controlled from the same logic signal to activate Dynamic Braking of a motor.
7, 4 ENA, ENB Input pins used to Enable Switch Driver A and Switch Driver B, respectively. When Low, the respective
output is in a high impedance (Z) off-state. Since each Switch Driver is independently controlled, OUTA and
OUTB may be a separately PWM controlled as Half H-Switch Drivers.
14, 17 OUTA, OUTB Respectively, Switch Driver A and Switch Driver B Output pins.
2 ILF Current Limiting Fault Output Flag pin; when in a high logic state, signifies that Switch Driver A or B or both
are in a Current Limiting Fault Mode.
HIP4020
5FN3976.3
December 20, 2005
Application
The HIP4020 is designed to detect load current feedback
from sampling resistors of low value in the source
connections of the output drivers to VDD, VSSA and VSSB
(See Figure 1). When the sink or source current at OUTA or
OUTB exceeds the preset OC (Overcurrent) limiting value of
550mA typical, the current is held at the limiting value. If the
OT (Over-Temperature) Shutdown Protection limit is
exceeded, temperature sensing BiMOS circuits limit the
junction temperature to 150°C typical.
The circuit of Figure 1 shows the Full H-Switch in a small motor-
drive application. The left (A) and right (B) H-Switch’s are
controlled from the A and B inputs via the A and B CONTROL
LOGIC to the MOS output transistors Q1, Q2, Q3 and Q4. The
circuit is intended to safely start, stop, and control rotational
direction for a motor requiring no more than 0.5A of supply
current. The stop function includes a Dynamic Braking feature.
With the ENABLE Inputs Low, the MOS transistors Q1 and Q3
are OFF; which cuts-off supply current to OUTA and OUTB.
With the BRAKE terminal Low and ENABLE Inputs High, either
Q1 and Q4 or Q3 and Q2 will be driven into conduction by the
FIGURE 1. TYPICAL MOTOR CONTROL APPLICATION CIRCUIT SHOWING DIRECTIONAL AND BRAKING CONTROL
B1
B2
ENB
A1
A2
ENA
VDD
VSS VSSB
VSSA
V+
OUTA OUTB
BRAKE
ON
OFF
DIRECTION
ENABLE
(LOGIC
GROUND) LOAD
ILF
Q1 Q3
Q2 Q4
D1 D3
D4
D2
CONTROL
LOGIC A
V-
LEVEL SHIFTER
AND OC/OT LIMITER
LEVEL SHIFTER
AND OC/OT LIMITER
OVER-TEMP LIMIT
CONTROL
LOGIC B
SWITCHING WAVEFORMS
FIGURE 2.
TRUTH TABLE
SWITCH DRIVER A SWITCH DRIVER B
INPUTS OUTPUT INPUTS OUTPUT
A1 A2 ENA OUTA B1 B2 ENB OUTB
HL H OH LL H OH
LL H OL HL H OL
HH H OL LH H OL
LH H OL HH H OL
XX L Z XX L Z
L = Low logic level; H = High logic level
Z = High Impedance (off state)
OH = Output High (sourcing current to the output terminal)
OL = Output Low (sinking current from the output terminal)
X = Don’t Care
tPLH
50%
50%
VEN
VOUT
tPHL
50%
50%
VEN
VOUT
tr
tf
10%
90%
10%
90%
HIP4020
6FN3976.3
December 20, 2005
DIRECTION Input Control terminal. The MOS output transistor
pair chosen for conduction is determined by the logic level
applied to the DIRECTION control; resulting in either clockwise
(CW) or counter-clockwise (CCW) shaft rotation.
When the BRAKE terminal is switched high (while holding
the ENABLE input high), the gates of both Q2 and Q4 are
driven high. Current flowing through Q2 (from the motor
terminal OUTA) at the moment of Dynamic Braking will
continue to flow through Q2 to the VSSA and VSSB external
connection, and then continue through diode D4 to the motor
terminal OUTB. As such, the resistance of the motor winding
(and the series-connected path) dissipates the kinetic
energy stored in the system. Reversing rotation, current
flowing through Q4 (from the motor terminal OUTB), at the
moment of Dynamic Braking, would continue to flow through
Q4 to the VSSB and VSSA tie, and then continue through
diode D2 to the motor terminal OUTA, to dissipate the stored
kinetic energy as previously described.
Where VDD to VSS are the Power Supply reference
terminals for the Control Logic, the lowest practical supply
voltage for proper logic control should be no less than 2.0V.
The VSSA and VSSB terminals are separate and
independent from VSS and may be more negative than the
VSS ground reference terminal. However, the maximum
supply level from VDD to VSSA or VSSB must not be greater
than the Absolute Maximum Supply Voltage rating.
Terminals A1, B1, A2, B2, ENA and ENB are internally
connected to protection circuits intended to guard the CMOS
gate-oxides against damage due to electrostatic discharge.
(See Figure 3) Inputs ENA, ENB, A1, B1 A2 and B2 have
CD74HCT4000 Logic Interface Protection and Level
Converters for TTL or CMOS Input Logic. These inputs are
designed to typically provide ESD protection up to 2kV.
However, these devices are sensitive to electrostatic
discharge. Proper I.C. handling procedures should be
followed.
INPUT LEVEL
CONV.
VDD
FIGURE 3. LOGIC INPUT ESD INTERFACE PROTECTION
A1
A2
ENA
(DIR)
(BRAKE)
(ENABLE)
OT AND OC
PROTECT
N-DR
LIMIT
P-DR
LIMIT
Q2
D2
Q1
D1
VDD
VSSA
OUTA
B1
B2
ENB
(DIR)
(BRAKE)
(ENABLE)
OT AND OC
PROTECT
N-DR
LIMIT
P-DR
LIMIT
Q4
D4
Q3
D3
VDD
VSSB
OUTB
FIGURE 4. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS
HIP4020
7FN3976.3
December 20, 2005
Typical Performance Curves
FIGURE 5. TYPICAL CHARACTERISTIC OF THE P-MOSFET OUTPUT DRIVER DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE,
TAMBIENT = 25°C
FIGURE 6. TYPICAL CHARACTERISTIC OF THE N-MOSFET OUTPUT DRIVER DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE,
TAMBIENT = 25°C
FIGURE 7. TYPICAL CHARACTERISTIC OF THE P AND N OUTPUT DRIVER SHORT CIRCUIT CURRENT vs SUPPLY VOLTAGE,
TAMBIENT = 25°C
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
DRAIN-TO-SOURCE VOLTAGE (V)
VDD = 3V
VDD = 5V
VDD = 12V
P-CHANNEL DRAIN CURRENT (mA)
TYPICAL CURRENT
LIMITING
1Ω0.5Ω2Ω
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
1Ω0.5Ω2Ω
DRAIN-TO-SOURCE VOLTAGE (V)
N-CHANNEL DRAIN CURRENT (mA)
VDD = 3V
VDD = 5V
VDD = 12V
TYPICAL CURRENT
LIMITING
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
SHORT CIRCUIT CURRENT (mA)
VDD SUPPLY VOLTAGE (V)
N-CHANNEL
P-CHANNEL
HIP4020
8FN3976.3
December 20, 2005
FIGURE 8. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A +5V SUPPLY, TAMBIENT = 25°C
FIGURE 9. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A ±3V SPLIT SUPPLY, OUTPUT
REFERENCE EQUAL LOGIC GROUND, TAMBIENT = 25°C
FIGURE 10. TYPICAL CHARACTERISTIC OF SATURATION VOLTAGE vs OUTPUT CURRENT USING A ±6V SPLIT SUPPLY, OUTPUT
REFERENCE EQUAL LOGIC GROUND, TAMBIENT = 25°C
Typical Performance Curves (Continued)
OUTPUT CURRENT, IO (A)
SATURATION VOLTAGE, VDD - VOUT (V)
HIGH
LOW
VDD = +5V
VSS = VSSA = VSSB = GND
0100 200 300 400 500
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65 HIP4020 SPLIT 5V COMMON GROUND
VSAT(P)
VSAT(N)
VSAT vs LOAD CURRENT
OUTPUT CURRENT, IO (A)
SATURATION VOLTAGE, VDD - VOUT (V)
HIGH
LOW
VDD = +3V
VSS = GND
VSSA = VSSB = -3V
0100 200 300 400 500 600 700
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70 HIP4020 SPLIT ±3V
VSAT(P)
VSAT(N)
VSAT vs LOAD CURRENT
OUTPUT CURRENT, IO (A)
SATURATION VOLTAGE, VDD - VOUT (V)
VDD = +6V
VSS = GND
VSSA = VSSB = -6V
0100 200 300 400 500 600
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
HIP4020 SPLIT ±6V
VSAT(P)
VSAT(N)
VSAT vs LOAD CURRENT
HIGH
LOW
HIP4020
9
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3976.3
December 20, 2005
HIP4020
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C A
MBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) B
MM
α
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.014 0.019 0.35 0.49 9
C 0.0091 0.0125 0.23 0.32 -
D 0.4961 0.5118 12.60 13.00 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N20 207
α0° 8° 0° 8° -
Rev. 2 6/05
