HCMS-2902 - Hewlett-Packard / Agilent

3-109

High Performance CMOS 5 x 7

Alphanumeric Displays

Technical Data

HCMS-29XX Series

Features

• Easy to Use

• Interfaces Directly with

Microprocessors

• 0.15" Character Height in 4,

8, and 16 (2x8) Character

Packages

• 0.20" Character Height in 4

and 8 Character Packages

• Rugged X- and Y-Stackable

Package

• Serial Input

• Convenient Brightness

Controls

• Wave Solderable

• Offered in Five Colors

• Low Power CMOS

Technology

• TTL Compatible

Applications

• Telecommunications

Equipment

• Portable Data Entry Devices

• Computer Peripherals

• Medical Equipment

• Test Equipment

• Business Machines

• Avionics

• Industrial Controls

Device Selection Guide

AlGaAs HER Orange Yellow Green Package

Description HCMS- HCMS- HCMS- HCMS- HCMS- Drawing

1 x 4 0.15" Character 2905 2902 2904 2901 2903 A

1 x 8 0.15" Character 2915 2912 2914 2911 2913 B

2 x 8 0.15" Character 2925 2922 2924 2921 2923 C

1 x 4 0.20" Character 2965 2962 2964 2961 2963 D

1 x 8 0.20" Character 2975 2972 2974 2971 2973 E

Description

The HCMS-29XX series are high

performance, easy to use dot

matrix displays driven by on-board

CMOS ICs. Each display can be

directly interfaced with a

microprocessor, thus eliminating

the need for cumbersome interface

components. The serial IC

interface allows higher character

count information displays with a

minimum of data lines. A variety of

colors, font heights, and character

counts gives designers a wide

range of product choices for their

specific applications and the easy

to read 5 x 7 pixel format allows

the display of uppercase, lower

case, Katakana, and custom user-

defined characters. These displays

are stackable in the x- and y-

directions, making them ideal for

high character count displays.

ESD WARNING: STANDARD CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVED TO

AVOID STATIC DISCHARGE.

5964-6376E

3-110

HCMS-291X

NOTES:

1. DIMENSIONS ARE IN mm (INCHES).

2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).

3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.

2.54 ± 0.13

(0.100 ± 0.005)

(NON ACCUM.)

TYP.

35.56 (1.400) MAX.

76543210

0.25

(0.010)

7.62

(0.300)

PIN # 1 IDENTIFIER

COO

INTENSITY CATEGORY

DATE CODE (YEAR, WEEK)

COLOR BIN

COUNTRY OF ORIGIN

PART NUMBER

5.08 (0.200)

2.54

(0.100) SYM.

0.51

(0.020)

TYP.

0.51 ± 0.13

(0.020 ± 0.005)

2.22 (0.087) SYM.

10.16 (0.400) MAX.

2.11 (0.083) TYP.

4.32

(0.170)TYP.

1.27

(0.050)SYM.

4.45

(0.175)TYP.

3.71

(0.146)

TYP. NO PIN

NO PIN

V LED

NO PIN

GND LED

NO PIN

V LED

NO PIN

DATA IN

NO PIN

CLOCK

BLANK

GND LOGIC

SEL

V LOGIC

NO PIN

RESET

OSC

DATA OUT

PIN FUNCTION

ASSIGNMENT TABLE

PIN # FUNCTION

HCMS-291X

YYWW

NOTES:

1. DIMENSIONS ARE IN mm (INCHES).

2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).

3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.

X Z

COO

2.11 (0.083) TYP.

0.25

(0.010)

7.62

(0.300)

PIN # 1 IDENTIFIER

4321

17.78 (0.700) MAX.

3.71 (0.146) TYP.

4.45 (0.175) TYP.

2.22 (0.087) SYM.

10.16 (0.400) MAX.

PIN # 1

LIGHT INTENSITY CATEGORY

DATE CODE

COLOR BIN

COUNTRY OF ORIGIN

PART NUMBER

5.08

(0.200)

2.54

(0.100) SYM.

TYP.

0.51 ± 0.13

(0.020 ± 0.005)

2.54 ± 0.13

(0.100 ± 0.005)

(NON ACCUM.)

TYP.

4.32

(0.170)TYP.

1.27

(0.050)SYM.

0.51 (0.020)

DATA OUT

OSC

V LED

DATA IN

CLK

BLANK

GND

SEL

V LOGIC

RESET

PIN FUNCTION

ASSIGNMENT TABLE

PIN # FUNCTION

HCMS-290X

YYWW

HCMS-290X

3-111

HCMS-292X

NO PIN

V LED

NO PIN

GND LED

NO PIN

V LED

NO PIN

DATA IN

NO PIN

CLOCK

BLANK

GND LOGIC

SEL

V LOGIC

NO PIN

RESET

OSC

DATA OUT

PIN FUNCTION ASSIGNMENT TABLE

NO PIN

V LED

NO PIN

GND LED

NO PIN

V LED

NO PIN

DATA IN

NO PIN

CLOCK

BLANK

GND LOGIC

SEL

V LOGIC

NO PIN

RESET

OSC

DATA OUT

10A

11A

12A

13A

14A

15A

16A

17A

18A

19A

20A

21A

22A

23A

24A

25A

26A

PIN # FUNCTION

NOTES:

1. DIMENSIONS ARE IN mm (INCHES).

2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).

3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.

15141312111098

76543210

1.27

(0.050)

0.25

(0.010)

7.62

(0.300)

2.03

(0.080)

4.83

(0.190)

PIN # 1 IDENTIFIER

ROW A

ROW B

35.56 (1.400) MAX.

3.71 (0.146) TYP.

2.22 (0.088) SYM.

4.45 (0.175) MAX.

19.81 (0.780) MAX.

9.65 (0.380)

COO

INTENSITY CATEGORY

DATE CODE (YEAR, WEEK)

COLOR BIN

COUNTRY OF ORIGIN

PART NUMBER

5.08 (0.200)

2.54

(0.100) SYM.

0.51

(0.020)

0.51 ± 0.13

(0.020 ± 0.005)TYP.

2.54 ± 0.13

(0.100 ± 0.005)

(NON ACCUM.)

TYP.

26A

26B

2.11 (0.083) TYP.

10B

11B

12B

13B

14B

15B

16B

17B

18B

19B

20B

21B

22B

23B

24B

25B

26B

PIN # FUNCTION

HCMS-292X

YYWW

HCMS-296X

NOTES:

1. DIMENSIONS ARE IN mm (INCHES).

2. UNLESS OTHERWISE SPECIFIED, THE TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).

3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.

3210

PIN # 1 IDENTIFIER

PART NUMBER

5.31

(0.209)

0.169

(4.28) SYM.

TYP.

0.51 ± 0.13

(0.020 ± 0.005)

2.54 ± 0.13

(0.100 ± 0.005)TYP.

2.67 (0.105) SYM.

2.54 (0.100) TYP.

11.43 (0.450) MAX.

5.36 (0.211) TYP.

0.25

(0.010)

7.62

(0.300)

3.71

(0.146)TYP.

0.072

(1.83)SYM.

4.57

(0.180)TYP.

COO

INTENSITY CATEGORY

DATE CODE (YEAR, WEEK)

COLOR BIN

COUNTRY OF ORIGIN

21.46 (0.845) MAX.

0.50

(0.020)

DATA OUT

OSC

V LED

DATA IN

CLK

BLANK

GND

SEL

V LOGIC

RESET

PIN FUNCTION

ASSIGNMENT TABLE

PIN # FUNCTION

HCMS-296X

YYWW

3-112

Absolute Maximum Ratings

Logic Supply Voltage, VLOGIC to GNDLOGIC ....................... -0.3 V to 7.0 V

LED Supply Voltage, VLED to GNDLED .............................. -0.3 V to 5.5 V

Input Voltage, Any Pin to GND ......................... -0.3 V to VLOGIC +0.3 V

Free Air Operating Temperature Range T

A[1] ................. -40°C to +85°C

Relative Humidity (non-condensing)................................................ 85%

Storage Temperature, TS................................................. -55°C to 100°C

Maximum Solder Temperature

1.59 mm (0.063 in.) Below Seating Plane, t< 5 sec.................. 260°C

ESD Protection @ 1.5 kΩ, 100 pF (each pin) ................................ 2 KV

TOTAL Package Power Dissipation at T

A = 25°C[2]

4 character ....................................................................... 1.2 W

8 character ....................................................................... 2.4 W

16 character....................................................................... 4.8 W

Notes:

1. For operation in high ambient temperatures, see Appendix A, Thermal Considerations.

HCMS-297X

NOTES:

1. DIMENSIONS ARE IN mm (INCHES).

2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).

3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.

87654321

COO

PIN # 1 IDENTIFIER

INTENSITY CATEGORY

DATE CODE (YEAR, WEEK)

COLOR BIN

COUNTRY OF ORIGIN

PART NUMBER

5.31

(0.209)

6.22

(0.245)SYM.

0.51

(0.020)

TYP.

0.51 ± 0.13

(0.020 ± 0.005)

2.54 ± 0.13

(0.100 ± 0.005)

(NON ACCUM.)

TYP.

42.93 (1.690) MAX.

2.67 (0.105) SYM.

5.36 (0.211) TYP.

11.43 (0.450) MAX.

2.54 (0.100) TYP.

0.25

(0.010)

7.62

(0.300)

3.71

(0.146)TYP.

1.90

(0.075)SYM.

NO PIN

V LED

NO PIN

GND LED

NO PIN

V LED

NO PIN

DATA IN

NO PIN

CLOCK

BLANK

GND LOGIC

SEL

V LOGIC

NO PIN

RESET

OSC

DATA OUT

PIN # FUNCTION

4.57

(0.180)TYP.

HCMS-297X

YYWW

Recommended Operating Conditions over Temperature Range

(-40°C to +85°C)

Parameter Symbol Min. Typ. Max. Units

Logic Supply Voltage VLOGIC 3.0 5.0 5.5 V

LED Supply Voltage VLED 4.0 5.0 5.5 V

GNDLED to GNDLOGIC – -0.3 0 +0.3 V

3-113

Electrical Characteristics over Operating Temperature Range (-40°C to +85°C)

TA = 25°C -40°C < TA < 85°C

VLOGIC = 5.0 V 3.0 V < VLOGIC < 5.5 V

Parameter Symbol Typ. Max. Min. Max. Units Test Conditions

Input Leakage Current IIµAV

IN = 0 V to VLOGIC

HCMS-290X/296X (4 char) +7.5 -2.5 +50

HCMS-291X/297X (8 char) +15 -5.0 +100

HCMS-292X (16 char) +15 -5.0 +100

ILOGIC OPERATING ILOGIC(OPT) mA V

IN = V

LOGIC

HCMS-290X/296X (4 char) 0.4 2.5 5

HCMS-291X/297X (8 char) 0.8 5 10

HCMS-292X (16 char) 0.8 5 10

ILOGIC SLEEP[1] ILOGIC(SLP) µAV

IN = V

LOGIC

HCMS-290X/296X (4 char) 5 15 25

HCMS-291X/297X (8 char) 10 30 50

HCMS-292X (16 char) 10 30 50

ILED BLANK ILED(BL) mA BL = 0 V

HMCS-290X/296X (4 char) 0.4 1.8 2.5

HCMS-291X/297X (8 char) 0.8 3.5 5

HCMS-292X (16 char) 0.8 3.5 5

ILED SLEEP[1] ILED(SLP) µA

HCMS-290X/296X (4 char) 1 3 50

HCMS 291X/297X (8 char) 2 6 100

HCMS-292X (16 char) 2 6 100

Peak Pixel Current[2] IPIXEL VLED = 5.5 V

HCMS-29X5 (AlGaAs) 15.4 17.1 18.7 mA All pixels ON,

HCMS-29XX (Other Colors) 14.0 15.9 17.1 mA Average value per

pixel

HIGH level input voltage V

ih 2.0 V 4.5 V < VLOGIC < 5.5 V

0.8 VLOGIC V 3.0 V < VLOGIC < 4.5 V

LOW level input voltage V

il 1.1 V 4.5 V < VLOGIC < 5.5 V

0.2 VLOGIC V 3.0 V < VLOGIC < 4.5 V

HIGH level output voltage V

oh 2.4 V V

LOGIC = 4.5 V,

Ioh = -40 µA

0.8 VLOGIC V 3.0 V < VLOGIC < 4.5 V

LOW level output voltage V

ol 0.4 V V

LOGIC = 5.5 V,

Iol = 1.6 mA[3]

0.2 VLOGIC V 3.0 V < VLOGIC < 4.5 V

Thermal Resistance RθJ-P 70 °C/W IC junction to pin

Notes:

1. In SLEEP mode, the internal oscillator and reference current for LED drivers are off.

2. Average peak pixel current is measured at the maximum drive current set by Control Register 0. Individual pixels may exceed this

value.

3. For the Oscillator Output, Iol = 40 µA.

3-114

Optical Characteristics at 25°C[1]

VLED = 5.0 V, 50% Peak Current, 100% Pulse Width

Luminous Intensity Peak Dominant

per LED[2] Wavelength Wavelength

Character Average (µcd) λPeak (nm) λd[3] (nm)

Display Color Part Number Min. Typ. Typ. Typ.

AlGaAs Red HCMS-29X595 230 645 637

High Efficiency Red HCMS-29X229 64 635 626

Orange HCMS-29X429 64 600 602

Yellow HCMS-29X129 64 583 585

Green HCMS-29X357 114 568 574

Notes:

1. Refers to the initial case temperature of the device immediately prior to measurement.

2. Measured with all LEDs illuminated.

3. Dominant wavelength, λd, is derived from the CIE chromaticity diagram and represents the single wavelength which defines the

perceived LED color.

Electrical Description

Pin Function Description

RESET (RST) Sets Control Register bits to logic low. The Dot Register contents are

unaffected by the Reset pin. (logic low = reset; logic high = normal

operation).

DATA IN (DIN) Serial Data input for Dot or Control Register data. Data is entered on the

rising edge of the Clock input.

DATA OUT (DOUT) Serial Data output for Dot or Control Register data. This pin is used for

cascading multiple displays.

CLOCK (CLK) Clock input for writing Dot or Control Register data. When Chip Enable is

logic low, data is entered on the rising Clock edge.

as the destination for serial data entry. The logic level of RS is latched on

the falling edge of the Chip Enable input.

CHIP ENABLE (CE) This input must be a logic low to write data to the display. When CE

returns to logic high and CLK is logic low, data is latched to either the LED

output drivers or a Control Register.

OSCILLATOR SELECT Selects either an internal or external display oscillator source.

(SEL) (logic low = External Display Oscillator; logic high = Internal Display

Oscillator).

OSCILLATOR (OSC) Output for the Internal Display Oscillator (SEL = logic high) or input for an

External Display Oscillator (SEL = logic low).

BLANK (BL) Blanks the display when logic high. May be modulated for brightness

control.

GNDLED Ground for LED drivers.

GNDLOGIC Ground for logic.

VLED Positive supply for LED drivers.

VLOGIC Positive supply for logic.

3-115

AC Timing Characteristics over Temperature Range (-40°C to +85°C)

Timing

Diagram

Ref. 4.5 V < VLOGIC <5.5 V VLOGIC = 3 V

Number Description Symbol Min. Max. Min. Max. Units

1 Register Select Setup Time to trss 10 10 ns

Chip Enable

2 Register Select Hold Time to trsh 10 10 ns

Chip Enable

3 Rising Clock Edge to Falling tclkce 20 20 ns

Chip Enable Edge

4 Chip Enable Setup Time to tces 35 55 ns

Rising Clock Edge

5 Chip Enable Hold Time to tceh 20 20 ns

Rising Clock Edge

6 Data Setup Time to Rising tds 10 10 ns

Clock Edge

7 Data Hold Time after Rising tdh 10 10 ns

Clock Edge

8 Rising Clock Edge to DOUT[1] tdout 10 40 10 65 ns

9 Propagation Delay DIN to DOUT tdoutp 18 30 ns

Simultaneous Mode for

one IC[1,2]

10 CE Falling Edge to DOUT Valid tcedo 25 45 ns

11 Clock High Time tclkh 80 100 ns

12 Clock Low Time tclkl 80 100 ns

Reset Low Time trstl 50 50 ns

Clock Frequency F

cyc 5 4 MHz

Internal Display Oscillator F

inosc 80 210 80 210 KHz

Frequency

Internal Refresh Frequency F

rf 150 410 150 400 Hz

External Display Oscillator F

exosc

Frequency

Prescaler = 1 51.2 1000 51.2 1000 KHz

Prescaler = 8 410 8000 410 8000 KHz

Notes:

1. Timing specifications increase 0.3 ns per pf of capacitive loading above 15 pF.

2. This parameter is valid for Simultaneous Mode data entry of the Control Register.

3-116

Reset

Reset initializes the Control

Registers (sets all Control

places the display in the sleep

mode. The Reset pin should be

connected to the system power-on

reset circuit. The Dot Registers

are not cleared upon power-on or

by Reset. After power-on, the Dot

however, Reset will put the

display in sleep mode, thereby

blanking the LEDs. The Control

are cleared to all zeros by Reset.

To operate the display after being

Reset, load the Dot Register with

logic lows. Then load Control

Word 0 with the desired bright-

ness level and set the sleep mode

bit to logic high.

Dot Register

The Dot Register holds the

pattern to be displayed by the

Display Overview

The HCMS-29XX series is a family

of LED displays driven by

on-board CMOS ICs. The LEDs

are configured as 5 x 7 font

characters and are driven in

groups of 4 characters per IC.

Each IC consists of a 160-bit shift

7-bit Control Words, and refresh

circuitry. The Dot Register

contents are mapped on a

one-to-one basis to the display.

Thus, an individual Dot Register

bit uniquely controls a single

LED.

8-character displays have two ICs

that are cascaded. The Data Out

line of the first IC is internally

connected to the Data In line of

the second IC forming a 320-bit

Dot Register. The display’s other

control and power lines are

connected directly to both ICs. In

16-character displays, each row

functions as an independent

8-character display with its own

320-bit Dot Register.

LEDs. Data is loaded into the Dot

procedure shown in Table 1 and

the Write Cycle Timing Diagram.

First RS is brought low, then CE

is brought low. Next, each

successive rising CLK edge will

shift in the data at the DIN pin.

Loading a logic high will turn the

corresponding LED on; a logic

low turns the LED off. When all

160 bits have been loaded (or 320

bits in an 8-digit display), CE is

brought to logic high.

When CLK is next brought to

logic low, new data is latched into

the display dot drivers. Loading

data into the Dot Register takes

place while the previous data is

displayed and eliminates the need

to blank the display while loading

data.

Pixel Map

In a 4-character display, the

160-bits are arranged as 20

Table 1. Register Truth Table

Function CLK CE RS

Select Dot Register Not Rising ↓L

Load Dot Register

DIN = HIGH LED = "ON" ↑LX

IN = LOW LED = "OFF"

Copy Data from Dot Register to Dot Latch L H X

Select Control Register Not Rising ↓H

Load Control Register[1] ↑LX

Latch Data to Control Word 1[2] LHX

Notes:

1. BIT D0 of Control Word 1 must have been previously set to Low for serial mode or High for simultaneous mode.

2. Selection of Control Word 1 or Control Word 0 is set by D7 of the Control Shift Register. The unselected control word retains its

previous value.

3-117

and then CE is brought to logic

low. Next, each successive rising

CLK edge will shift in the data on

the DIN pin. Finally, when 8 bits

have been loaded, the CE line is

brought to logic high. When CLK

goes to logic low, new data is

copied into the selected control

word. Loading data into the

Control Register takes place while

the previous control word

configures the display.

Control Word 0

Loading the Control Register with

D7 = Logic low selects Control

Word 0 (see Table 2). Bits D0-D3

adjust the display brightness by

pulse width modulating the LED

on-time, while Bits D4-D5 adjust

the display brightness by

changing the peak pixel current.

Bit D6 selects normal operation or

sleep mode.

Control Register

The Control Register allows

software modification of the IC’s

operation and consists of two

independent 7-bit control words.

Bit D7 in the shift register selects

one of the two 7-bit control

words. Control Word 0 performs

pulse width modulation

brightness control, peak pixel

current brightness control, and

sleep mode. Control Word 1 sets

serial/simultaneous data out

mode, and external oscillator

prescaler. Each function is

independent of the others.

Control Register Data

Data is loaded into the Control

dure shown in Table 1 and the

Write Cycle Timing Diagram.

First, RS is brought to logic high

columns by 8 rows. This array can

be conceptualized as four 5 x 8

dot matrix character locations,

but only 7 of the 8 rows have

LEDs (see Figures 1 & 2). The

bottom row (row 0) is not used.

Thus, latch location 0 is never

displayed. Column 0 controls the

left-most column. Data from Dot

Latch locations 0-7 determine

whether or not pixels in Column 0

are turned-on or turned-off.

Therefore, the lower left pixel is

turned-on when a logic high is

stored in Dot Latch location 1.

Characters are loaded in serially,

with the left-most character being

loaded first and the right-most

character being loaded last. By

loading one character at a time

and latching the data before

loading the next character, the

figures will appear to scroll from

right to left.

HCMS-29XX Write Cycle Diagram

NOTE:

1. DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.

RSS RSH

CLKCE CES

CLKH

CLKL

CEH

CEDO

DOUT

DOUTP

PREVIOUS DATA NEW DATA

121143 5

10 8

NEW DATA LATCHED HERE

[1]

CLK

LED OUTPUTS,

CONTROL

REGISTERS

(SIMULTANEOUS)

OUT

D (SERIAL)

OUT

3-118

Figure 2.

ROW 0

(NOT USED)

DATA TO

CHARACTER

PIXEL

DATA FROM

CHARACTER

ROW 7

ROW 6

ROW 5

ROW 4

ROW 3

ROW 2

ROW 1

40 BIT

S.R.

DATA IN

OSCILLATOR

÷8

CLOCK

CHIP

ENABLE

SELECT

RESET

OSC

SELECT

BLANK

DATA IN

CLR DATA

OUT

CONTROL

REFRESH

CONTROL

RST

PRESCALE

VALUE

D Q RS

(LATCHED)

CURRENT

REFERENCE

PWM BRIGHT

CONTROL

RS (LATCHED)

SER/PAR

MODE

3:8 DECODER

CATHODE

FIELD DRIVERS

40 BIT

S.R.

DI 40 BIT

S.R.

DI 40 BIT

S.R.

ANODE CURRENT SOURCES

V LED +

GND (LED)

CHAR 0

COLUMN 0 COLUMN 19

CHAR 1 CHAR 2 CHAR 3

ROW 7

DOT

BIT # 159

ROW 1

ROW 0 (NO LEDS)

DOT

REGISTERS

AND

LATCHES

DATA OUT

Figure 1.

3-119

Registers are connected in series

to form a 320-bit dot shift

has not changed. However, Dot

Shift Register bit 0 of IC2

becomes bit 160 of the 320-bit

dot shift register.

The Control Registers of the two

ICs are independent of each

other. This means that to adjust

the display brightness the same

control word must be entered into

both ICs, unless the Control

Registers are set to simultaneous

mode.

Longer character string systems

can be built by cascading multiple

displays together. This is

accomplished by creating a five

line bus. This bus consists of CE,

RS, BL, Reset, and CLK. The

display pins are connected to the

corresponding bus line. Thus, all

CE pins are connected to the CE

bus line. Similarly, bus lines for

RS, BL, Reset, and CLK are

created. Then DIN is connected to

the right-most display. DOUT from

this display is connected to the

next display. The left-most display

receives its DIN from the DOUT of

the display to its right. DOUT from

the left-most display is not used.

Each display may be set to use its

internal oscillator, or the displays

may be synchronized by setting

up one display as the master and

the others as slaves. The slaves

are set to receive their oscillator

input from the master’s oscillator

output.

Sleep mode (Control Word 0, bit

D6 = Low) turns off the Internal

Display Oscillator and the LED

pixel drivers. This mode is used

when the IC needs to be powered

up, but does not need to be

active. Current draw in sleep

mode is nearly zero. Data in the

Dot Register and Control Words

are retained during sleep mode.

Control Word 1

Loading the Control Register with

D7 = logic high selects Control

Word 1. This Control Word

performs two functions: serial/

simultaneous data out mode and

external oscillator prescale select

(see Table 2).

Serial/Simultaneous Data

Output D0

Bit D0 of control word 1 is used to

switch the mode of DOUT between

serial and simultaneous data entry

during Control Register writes.

The default mode (logic low) is

the serial DOUT mode. In serial

mode, DOUT is connected to the

last bit (D7) of the Control Shift

Storing a logic high to bit D0

changes DOUT to simultaneous

mode which affects the Control

mode, DOUT is logically connected

to DIN. This arrangement allows

multiple ICs to have their Control

Registers written to simul-

taneously. For example, for N ICs

in the serial mode, N * 8 clock

pulses are needed to load the

same data in all Control Registers.

In the simultaneous mode, N ICs

only need 8 clock pulses to load

the same data in all Control

Registers. The propagation delay

from the first IC to the last is

N*t

DOUTP.

External Oscillator

Prescaler Bit D1

Bit D1 of Control Word 1 is used

to scale the frequency of an

external Display Oscillator. When

this bit is logic low, the external

Display Oscillator directly sets the

internal display clock rate. When

this bit is a logic high, the

external oscillator is divided by 8.

This scaled frequency then sets

the internal display clock rate. It

takes 512 cycles of the display

clock (or 8 x 512 = 4096 cycles

of an external clock with the

divide by 8 prescaler) to com-

pletely refresh the display once.

Using the prescaler bit allows the

designer to use a higher external

oscillator frequency without extra

circuitry.

This bit has no affect on the

internal Display Oscillator

Frequency.

Bits D2-D6

These bits must always be pro-

grammed to logic low.

Cascaded ICs

Figure 3 shows how two ICs are

connected within an HCMS-29XX

display. The first IC controls the

four left-most characters and the

second IC controls the four

right-most characters. The Dot

3-120

↑

Bit D7On-Time Duty Relative

Set Low PWM Brightness Oscillator Factor Brightness

to Select Control Cycles (%) (%)

Control

Word 0 LLLL 0 0 0

L L L H 1 0.2 1.7

L L H L 2 0.4 3.3

L L H H 3 0.6 5.0

L H L L 4 0.8 6.7

L H L H 5 1.0 8.3

L H H L 7 1.4 11.7

LHHH 9 1.8 15

H L L L 11 2.1 18

H L L H 14 2.7 23

HLHL 18 3.5 30

H L H H 22 4.3 37

H H L L 28 5.5 47

H H L H 36 7.0 60

HHHL 48 9.4 80

HHHH 60 11.7 100

Table 2. Control Shift Register

CONTROL WORD 0

Peak Current Typical Peak Relative Full

Brightness Pixel Current Scale Current

Control (mA) (Relative Brightness, %)

H L 4.0 31

L H 6.4 50

L L 9.3 73 (Default at Power Up)

H H 12.8 100

SLEEP MODE L – DISABLES INTERNAL OSCILLATOR-DISPLAY BLANK

H – NORMAL OPERATION

Serial/Simultaneous Data Out

L – Dout holds contents of Bit D7

H – Dout is functionally tied to Din

External Display Oscillator Prescaler

L – Oscillator Freq ÷ 1

H – Oscillator Freq ÷ 8

↑

Bit D7

Set High

to Select

Control

Word 1

Reserved for Future

Use (Bits D2-D6

must be set Low)

CONTROL WORD 1

HLLLLLD

3-121

Figure 3. Cascaded ICs.

IC2

BITS 160-319

CHARACTERS 4-7

SEL

OSC

CLK

OUT

IC1

BITS 0-159

CHARACTERS 0-3

SEL

OSC

CLK

OUT

RESET

SEL

OSC

CLK

OUT

RESET

3-122

PD can be calculated as Equation

2 below.

Figure 4 shows how to derate the

power of one IC versus ambient

temperature. Operation at high

ambient temperatures may

require the power per IC to be

reduced. The power consumption

can be reduced by changing

either the N, IPIXEL, Osc cyc or

VLED. Changing VLOGIC has very

little impact on the power

consumption.

Appendix A. Thermal

Considerations

The display IC has a maximum

junction temperature of 150°C.

The IC junction temperature can

be calculated with Equation 1

below.

A typical value for RθJA is 100°C/

W. This value is typical for a

display mounted in a socket and

covered with a plastic filter. The

socket is soldered to a .062 in.

thick PCB with .020 inch wide,

one ounce copper traces.

Equation 1:

TJMAX = TA + PD * RθJA

Where:

TJMAX = maximum IC junction temperature

TA= ambient temperature surrounding the display

RθJA = thermal resistance from the IC junction to ambient

PD= power dissipated by the IC

Equation 2:

PD = (N * IPIXEL * Duty Factor * VLED) + ILOGIC * VLOGIC

Where:

PD= total power dissipation

N = number of pixels on (maximum 4 char * 5 * 7 = 140)

IPIXEL = peak pixel current.

Duty Factor = 1/8 * Osccyc/64

Osc cyc = number of ON oscillator cycles per row

ILOGIC = IC logic current

VLOGIC = logic supply voltage

Equation 3:

IPEAK = M * 20 * IPIXEL

Where:

IPEAK = maximum instantaneous peak current for the display

M = number of ICs in the system

20 = maximum number of LEDs on per IC

IPIXEL = peak current for one LED

Equation 4:

ILED(AVG) = N * IPIXEL * 1/8 * (oscillator cycles)/64

(see Variable Definitions above)

Appendix B. Electrical

Considerations

Current Calculations

The peak and average display

current requirements have a

significant impact on power

supply selection. The maximum

peak current is calculated with

Equation 3 below.

The average current required by

the display can be calculated with

Equation 4 below.

The power supply has to be able

to supply IPEAK transients and

supply ILED(AVG) continuously.

The range on VLED allows noise on

this supply without significantly

changing the display brightness.

VLOGIC and VLED Considerations

The display uses two independent

electrical systems. One system is

used to power the display’s logic

and the other to power the

display’s LEDs. These two

systems keep the logic supply

clean.

Separate electrical systems allow

the voltage applied to VLED and

VLOGIC to be varied independently.

Thus, VLED can vary from 0 to 5.5

V without affecting either the Dot

or the Control Registers. VLED can

P MAX – MAXIMUM POWER

DISSIPATION PER IC – W

025

T – AMBIENT TEMPERATURE – °C

0.7

0.6

0.5

0.4

0.3

0.2

0.1

60555045403530

0.8

0.9

1.0

1.1

1.2

8580757065

R = 100°C/W

J-A

1.3

Figure 4.

3-123

be varied between 4.0 to 5.5 V

without any noticeable variation

in light output. However, operat-

ing VLED below 4.0 V may cause

objectionable mismatch between

the pixels and is not

recommended. Dimming the

display by pulse width modulating

VLED is also not recommended.

VLOGIC can vary from 3.0 to 5.5 V

without affecting either the

displayed message or the display

intensity. However, operation

below 4.5 V will change the

timing and logic levels and

operation below 3 V may cause

the Dot and Control Registers to

be altered.

The logic ground is internally

connected to the LED ground by a

substrate diode. This diode

becomes forward biased and

conducts when the logic ground is

0.4 V greater then the LED

ground. The LED ground and the

logic ground should be connected

to a common ground which can

withstand the current introduced

by the switching LED drivers.

When separate ground

connections are used, the LED

ground can vary from -0.3 V to

+0.3 V with respect to the logic

ground. Voltages below -0.3 V can

cause all the dots to be ON.

Voltage above +0.3 V can cause

dimming and dot mismatch. The

LED ground for the LED drivers

can be routed separately from the

logic ground until an appropriate

ground plane is available. On long

interconnections between the

display and the host system,

voltage drops on the analog

ground can be kept from affecting

the display logic levels by

isolating the two grounds.

Electrostatic Discharge

The inputs to the ICs are pro-

tected against static discharge

and input current latchup. How-

ever, for best results, standard

CMOS handling precautions

should be used. Before use, the

HCMS-29XX should be stored in

antistatic tubes or in conductive

material. During assembly, a

grounded conductive work area

should be used and assembly

personnel should wear conductive

wrist straps. Lab coats made of

synthetic material should be

avoided since they are prone to

static buildup. Input current

latchup is caused when the CMOS

inputs are subjected to either a

voltage below ground (VIN <

ground) or to a voltage higher

then VLOGIC (VIN > VLOGIC) and

when a high current is forced into

the input. To prevent input

current latchup and ESD damage,

unused inputs should be con-

nected to either ground or VLOGIC.

Voltages should not be applied to

the inputs until VLOGIC has been

applied to the display.

Appendix C. Oscillator

The oscillator provides the

internal refresh circuitry with a

signal that is used to synchronize

the columns and rows. This

ensures that the right data is in

the dot drivers for that row. This

signal can be supplied from either

an external source or the internal

source.

A display refresh rate of 100 Hz

or faster ensures flicker-free

operation. Thus for an external

oscillator the frequency should be

greater than or equal to 512 x

100 Hz = 51.2 kHz. Operation

above 1 MHz without the

prescaler or 8 MHz with the

prescaler may cause noticeable

pixel to pixel mismatch.

Appendix D. Refresh

Circuitry

This display driver consists of 20

one-of-eight column decoders and

20 constant current sources, 1

one-of-eight row decoder and

eight row sinks, a pulse width

modulation control block, a peak

current control block, and the

circuit to refresh the LEDs. The

refresh counters and oscillator are

used to synchronize the columns

and rows.

The 160 bits are organized as 20

columns by 8 rows. The IC

illuminates the display by

sequentially turning ON each of

the 8 row drivers. To refresh the

display once takes 512 oscillator

cycles. Because there are eight

row drivers, each row driver is

selected for 64 (512/8) oscillator

cycles. Four cycles are used to

briefly blank the display before

the following row is switched on.

Thus, each row is ON for 60

oscillator cycles out of a possible

64. This corresponds to the

maximum LED on time.

Appendix E. Display

Brightness

Two ways have been shown to

control the brightness of this LED

display: setting the peak current

and setting the duty factor. Both

values are set in Control Word 0.

To compute the resulting display

brightness when both PWM and

peak current control are used,

simply multiply the two relative

brightness factors. For example,

if Control Register 0 holds the

word 1001101, the peak current

3-124

is 73% of full scale (BIT D5 = L,

BIT D4 = L) and the PWM is set

to 60% duty factor (BIT D3 = H,

BIT D2 = H, BIT D1 = L, BIT D0

= H). The resulting brightness is

44% (.73 x .60 = .44) of full

scale.

The temperature of the display

will also affect the LED brightness

as shown in Figure 5.

Appendix F. Reference

Material

Application Note 1027: Soldering

LED Components

Application Note 1015: Contrast

Enhancement Techniques for

LED Displays

Figure 5.

RELATIVE LUMINOUS INTENSITY

(NORMALIZED TO 1 AT 25°C)

YELLOW

HER/ORANGE

0.2-55

T – AMBIENT TEMPERATURE – °C

3.0

2.6

2.2

1.8

1.4

1.0

0.6

856545255-15-35

GREEN

AlGaAs