Silego Technology, Inc. Rev 0.57
000-0046110-057 Revised September 3, 2014
GreenPAK
Programmable Mixed Signal Array
SLG46110
Preliminary
Preliminary
Block Diagram
Features
• Logic & Mixed Signal Circuits
• Highly Versatile Macro Cells
• 1.8 V (±5%) to 5 V (±10%) Supply
• Operating Temperature Range: -40°C to 85°C
• RoHS Compliant / Halogen-Free
• Pb-Free 12-pin STQFN: 1.6 x 1.6 x 0.55 mm, 0.4 mm pitch
Applications
• Personal Computers and Servers
• PC Peripherals
• Consumer Electronics
• Data Communications Equipment
• Handheld and Portable Electronics
Pin Configuration
GND
GPIO
GPIO
GPIO
GPIO
GPIO
2
3
47
8
9
10
GPI
VDD 1
STQFN-12
(Top View)
GPIO
NC
56
GPIO
NC
11
12
3-bit
LUT3_4 or
Pipe Delay
VrefRC Oscillator
Pin 1
VDD
Pin 2
GPI
Pin 3
GPIO
Pin 4
GPIO
Pin 12
GPIO Pin 11
NC
Pin 5
NC Pin 6
GPIO
Pin 8
GPIO
Pin 7
GND
Pin 10
GPIO
Pin 9
GPIO
ACMP0
ACMP1
Look Up Tables (LUTs)
Counters/Delay Generators
CNT0 CNT3CNT1 2-bit
LUT2_2
3-bit
LUT3_3
2-bit
LUT2_3
3-bit
LUT3_2
Combination Function Macrocells
2-bit
LUT2_0
or DFF0
2-bit
LUT2_1
or DFF1
3-bit
LUT3_1
or DFF3
3bit
LUT3_0
or DFF2
4-bit
LUT4_0
or CNT2
FILTER_0/Prog. Delay
Additional
Combination Functions
PORBandgap
000-0046110-057 Page 1 of 65
SLG46110
Preliminary
1.0 Overview
The SLG46110 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit
design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macro
cells of the SL G46110. This highly versatile device allo ws a wi de variety of mixed-signal functions to be designed withi n a very
small, low power single integrated circu it. The macro cells in the device include the following:
• Two Analog Comparators (ACMP)
• Four Combinatorial Look Up Tables (LUTs)
• Two 2-bit LUTs
• Two 3-bit LUTs
• Six Combination Function Macro cell
• Two Selectable FF/Latch or 2-bit LUTs
• Two Selectable FF/Latch or 3-bit LUTs
• One Selectable Pipe Delay or 3-bit LUT
• Pipe Delay – 8 stage / 2 output
• One Selectable Counter/Delay or 4-bit LUT
• One Programmable Delay / Deglitch Filter
• Three Counter / Delay Generators (CNT/DLY)
• Three 8-bit counter/delays with external clock/rese t
• Four D Flip-Flop / Latches (DFF) (Part of Combination Function Macrocell)
• Pipe Delay – 8 stage/2 output (Part of Combination Function Macrocell)
• One Bandgap
• RC Oscillator (RC OSC)
000-0046110-057 Page 2 of 65
SLG46110
Preliminary
2.0 Pin Description
2.1 Functional and Programming Pin Description
Pin # Pin Name Function Programming Function
1 VDD Power Supply Power Supply
2 GPI General Purpose Input VPP (Programming Voltage)
3 GPIO General Purpose I/O or Analog Comparator 0 (+) Programming ID Pin
4 GPIO General Purpose I/O or Analog Comparator 0 (-) N/A
5 NC No Connect N/A
6 GPIO General Purpose I/O or Analog Comparator 1 (+) with OE N/A
7 GND Ground N/A
8 GPIO General Purpose I/O Programming Mode Control
9 GPIO General Purpose I/O or POR Output Programming SDIO Pin
10 GPIO General Purpose I/O with OE and Vref output Programming SRDWB Pin
11 NC No Connect N/A
12 GPIO General Purpose I/O or External Clock Input Programming SCL Pin
000-0046110-057 Page 3 of 65
SLG46110
Preliminary
3.0 User Programmability
The SLG461 10 is a user programmable device with One-Time-Programmable (OTP) memory elements that are able to construct
combinatorial logic elements. Three of the I/O Pins provide a connection for the bit patterns into the OTP on board memory. A
programming development kit allows the user the a bility to create initial device s. Once the design is finali zed, th e programmi ng
code (.gpx file) is forwarded to Silego to integrate into a production process.
Figure 1. Steps to create a custom Silego GreenPAK device
3URGXFW
'HILQLWLRQ
&XVWRPHU&UHDWHVWKHLURZQGHVLJQLQ
*UHHQ3$.'HVLJQHU
3URJUDP(QJLQHHULQJ6DPSOHVZLWK
*UHHQ3$.3URJUDPPHU
&XVWRPHUYHULILHV*UHHQ3$.
LQV\VWHPGHVLJQ
(PDLOJS[ILOHWR
*UHHQ3$.#VLOHJRFRP
(PDLO3URGXFW,GHD'HILQLWLRQ'UDZLQJRU
6FKHPDWLFWR*UHHQ3$.#VLOHJRFRP
6LOHJR$SSOLFDWLRQV(QJLQHHUVZLOOUHYLHZGHVLJQ
VSHFLILFDWLRQVZLWKFXVWRPHU
6DPSOHVDQG'HVLJQ&KDUDFWHUL]DWLRQ
5HSRUWVHQWWRFXVWRPHU
&XVWRPHUYHULILHV*UHHQ3$.GHVLJQ
&XVWRP*UHHQ3$.SDUW
HQWHUVSURGXFWLRQ
*UHHQ3$.'HVLJQ
DSSURYHGLQV\VWHPWHVW
*UHHQ3$.'HVLJQ
DSSURYHG
*UHHQ3$.'HVLJQ
DSSURYHG
000-0046110-057 Page 4 of 65
SLG46110
Preliminary
4.0 Ordering Information
Part Number Type
SLG46110V 12-pin STQFN
SLG46110VTR 12-pin STQFN - Tape and Reel (3k units)
000-0046110-057 Page 5 of 65
SLG46110
Preliminary
5.0 Electrical Specifications
5.1 Absolute Maximum Conditions
5.2 Electrical Characteristics (1.8V ±5% VDD)
Parameter Min. Max. Unit
VHIGH to GND -0.3 7 V
Voltage at Input Pin -0.3 7 V
Current at Input Pin -1.0 1.0 mA
Storage Temperature Range -65 150 °C
Junction Temperature -- 150 °C
ESD Protection (Human Body Model) 2000 -- V
ESD Protection (Charged Device Model) 1000 -- V
Moisture Sensitivity Level 1
Symbol Parameter Condition/Note Min. Typ. Max. Unit
VDD Supply Voltage 1.71 1.80 1.89 V
IQQuiescent Current Static Inputs and Outputs
(when ACMP, Vref and RC OSC are
powered down and non-operational) -- 0.5 -- μA
TAOperating Temperature -40 25 85 °C
VPP Programming Voltage 7.25 7.50 7.75 V
VAIR Analog Input Voltage Range ACMP with voltage gain divider 0 -- VDD V
ACMP without voltage gain divider 0 - - 1.1 V
VIH HIGH-Level Input Voltage Logic Input 1.100 -- VDD V
Logic Input with Schmitt Trigger 1.270 -- VDD V
Low-Level Logic Input 0.98 0 -- VDD V
VIL LOW-Level Input Voltage Logic Input -- -- 0.690 V
Logic Input with Schmitt Trigger -- -- 0.440 V
Low-Level Logic Input -- -- 0.520 V
IIH HIGH-Level Input Current Logic Input Pins; VIN = 1.8 V -1.0 -- 1.0 μA
IIL LOW-Level Input Current Logic Input Pins; VIN = 0 V -1.0 -- 1.0 μA
VOH HIGH-Level Outp ut Voltage
Push-Pull, IOH = 100 μA, 1X Driver 1.680 1.790 -- V
PMOS OD, IOH = 100 μA, 1X Driver 1 .68 0 1.790 -- V
Push-Pull, IOH = 100 μA, 2X Driver 1.702 1.795 -- V
PMOS OD, IOH = 100 μA, 2X Driver 1 .70 2 1.795 -- V
VOL LOW-Level Output Voltage
Push-Pull, IOL= 100 μA, 1X Driver -- 0.020 0.030 V
Push-Pull, IOL = 100 μA, 2X Driver -- 0.010 0.020 V
Open Drain, IOL = 100 μA, 1X Driver -- 0.010 0.020 V
Open Drain, IOL = 100 μA, 2X Driver -- 0.010 0.010 V
IOH HIGH-Level Outp ut Current
Push-Pull, VOH = VDD - 0.2, 1X Driver 1.043 1.400 -- mA
PMOS OD, VOH = VDD - 0.2, 1X Driver 1.036 1.407 -- mA
Push-Pull, VOH = VDD - 0.2, 2X Driver 2.150 2.707 -- mA
PMOS OD, VOH = VDD - 0.2, 2X Driver 2.200 2.719 -- mA
000-0046110-057 Page 6 of 65
SLG46110
Preliminary
IOL LOW-Level Output Current
Push-Pull, VOL = 0.15 V, 1X Driver 0.76 1.339 -- mA
Push-Pull, VOL = 0.15 V, 2X Driver 1.52 2.661 -- mA
Open Drain, VOL = 0.15 V, 1X Driver 1.53 2.669 -- mA
Open Drain, VOL = 0.15 V, 2X Driver 3.06 5.133 -- mA
TSU Startup Time from VDD rising past 1.6 V -- 1 -- ms
Symbol Parameter Condition/Note Min. Typ. Max. Unit
000-0046110-057 Page 7 of 65
SLG46110
Preliminary
5.3 Electrical Characteristics (3.3V ±10% VDD)
Symbol Parameter Condition/Note Min. Typ. Max. Unit
VDD Supply Voltage 3.0 3.3 3.6 V
IQQuiescent Current Static Inputs and Outputs
(when ACMP, Vref and RC OSC are
powered down and non-operational) -- 0.75 -- μA
TAOperating Temperature -40 25 85 °C
VPP Programming Voltage 7.25 7.50 7.75 V
VAIR Analog Input Voltage Range ACMP with voltage gain divider 0 -- VDD V
ACMP without voltage gain divider 0 - - 1.2 V
VIH HIGH-Level Input Voltage Logic Input 1.780 -- VDD V
Logic Input with Schmitt Trigger 2.130 -- VDD V
Low-Level Logic Input 1.13 0 -- VDD V
VIL LOW-Level Input Voltage Logic Input -- -- 1.210 V
Logic Input with Schmitt Trigger -- -- 0.950 V
Low-Level Logic Input -- -- 0.690 V
IIH HIGH-Level Input Current Logic Input Pins; VIN = 3.3 V -1.0 -- 1.0 μA
IIL LOW-Level Input Current Logic Input Pins; VIN = 0 V -1.0 -- 1.0 μA
VOH HIGH-Level Output Voltage
Push-Pull; IOH = 3 mA, 1X Driver 2.710 3.090 -- V
PMOS OD; IOH = 3 mA, 1X Driver 2.730 3.090 -- V
Push-Pull; IOH = 3 mA, 2X Driver 2.870 3.190 -- V
PMOS OD; IOH = 3 mA, 2X Driver 2.870 3.190 -- V
VOL LOW-Level Output Voltage
Push-Pull; IOL= 3 mA, 1X Driver -- 0.180 0.28 V
Push-Pull; IOL = 3 mA, 2X Driver -- 0.090 0.13 V
Open Drain; IOL = 3 mA, 1X Driver -- 0.090 0.13 V
Open Drain; IOL = 3 mA, 2X Driver -- 0.050 0.07 V
IOH HIGH-Level Output Current
Push-Pull; VOH = 2.4 V, 1X Driver 5.830 10.184 -- mA
PMOS OD; VOH = 2.4 V, 1X Driver 6.010 10.206 -- mA
Push-Pull; VOH = 2.4 V, 2X Driver 11 .264 19.655 -- mA
PMOS OD; VOH = 2.4 V, 2X Driver 12.010 19.703 -- mA
IOL LOW-Level Output Current
Push-Pull; VOL = 0.4 V, 1X Driver 4.06 6.440 -- mA
Push-Pull; VOL = 0.4 V, 2X Driver 8.13 12.358 -- mA
Open Drain; VOL = 0.4 V, 1X Driver 8.13 12.405 -- mA
Open Drain; VOL = 0.4 V, 2X Driver 16.26 22.897 -- mA
TSU Startup Time from VDD rising past 1.6 V -- 1 -- ms
000-0046110-057 Page 8 of 65
SLG46110
Preliminary
5.4 Electrical Characteristics (5V ±10% VDD)
Symbol Parameter Condition/Note Min. Typ. Max. Unit
VDD Supply Voltage 4.5 5.0 5.5 V
IQQuiescent Current Static Inputs and Outputs
(when ACMP, Vref and RC OSC are
powered down and non-operational) -- 1.0 -- μA
TAOperating Temperature -40 25 85 °C
VPP Programming Voltage 7.25 7.50 7.75 V
VAIR Analog Input Voltage Range ACMP with voltage gain divider 0 -- VDD V
ACMP without voltage gain divider 0 - - 1.2 V
VIH HIGH-Level Input Voltage Logic Input 2.640 -- VDD V
Logic Input with Schmitt Trigger 3.160 -- VDD V
Low-Level Logic Input 1.23 0 -- VDD V
VIL LOW-Level Input Voltage Logic Input -- -- 1.840 V
Logic Input with Schmitt Trigger -- -- 1.510 V
Low-Level Logic Input -- -- 0.780 V
IIH HIGH-Level Input Current Logic Input Pins; VIN = 5 V -1.0 -- 1.0 μA
IIL LOW-Level Input Current Logic Input Pins; VIN = 0 V -1.0 -- 1.0 μA
VOH HIGH-Level Outp ut Voltage
Push-Pull, IOH = 5 mA, 1X Driver 4.150 4.730 -- V
PMOS OD, IOH = 5 mA, 1X Driver 4.180 4.740 -- V
Push-Pull, IOH = 5 mA, 2X Driver 4.300 4.860 -- V
PMOS OD, IOH = 5 mA, 2X Driver 4.330 4.860 -- V
VOL LOW-Level Output Voltage
Push-Pull, IOL= 5 mA, 1X Driver -- 0.230 0.330 V
Push-Pull, IOL =5 mA, 2X Driver -- 0.120 0.160 V
Open Drain, IOL = 5 mA, 1X Driver -- 0.120 0.160 V
Open Drain, IOL = 5 mA, 2X Driver -- 0.070 0.090 V
IOH HIGH-Level Outp ut Current
Push-Pull, VOH = 2.4 V, 1X Driver 21.808 29.099 -- mA
PMOS OD, VOH = 2.4 V, 1X Driver 21.980 29.170 -- mA
Push-Pull, VOH = 2.4 V, 2X Driver 40.598 56.078 -- mA
PMOS OD, VOH = 2.4 V, 2X Driver 43.092 56.338 -- mA
IOL LOW-Level Output Current
Push-Pull, VOL = 0.4 V, 1X Driver 6.010 9.730 -- mA
Push-Pull, VOL = 0.4 V, 2X Driver 11.585 19.460 -- mA
Open Drain, VOL = 0.4 V, 1X Driver 11 .756 19.460 -- mA
Open Drain, VOL = 0.4 V, 2X Driver 19.120 35.621 -- mA
TSU Startup Time from VDD rising past 1.6 V -- 1 -- ms
000-0046110-057 Page 9 of 65
SLG46110
Preliminary
6.0 Summary of Macro Cell Function
6.1 I/O Pins
• Digital Input (low voltage or normal voltage, with or without Schmitt T rigger)
• Open Drain Outputs
• Push Pull Outputs
• Analog I/O
• 10 kΩ/100 kΩ/1 MΩ pull-up/pull-down resistors
6.2 Connection Matrix
• Digital matrix for circuit connections based on user design
6.3 Analog Comparators (2 total)
• Selectable hysteresis 0 mV/25 mV/50 mV/200 mV
6.4 Voltage Reference
• Used for references on Analog Comparators
• Can also be driven to external pin (Pin 10)
6.5 Combinational Logi c Lo ok Up Tables (LUTs – 4 total)
• Two 2-bit Lookup Tables
• Two 3-bit Lookup Tables
6.6 Combination Function Macrocells (7 total)
• Two Selectable FF/Latch or 2-bit LUTs
• Two Selectable FF/Latch or 3-bit LUTs
• One Selectable Pipe Delay or 3-bit LUT
• One Selectable CNT/DLY or 4-bit LUT
• One Programmable Delay or Deglitch Filter
6.7 Delays/Counters (3 total)
• Three 8-bit delays/counters with exte rnal clock/reset: Range 1-255 clock cycles
6.8 Pipe Delay (Part of Combination Function Macrocell)
• 8 stage / 2 output
• Two 1- 8 stage select ab l e ou tputs.
6.9 Programmable Delay
• 125 ns/250 ns/375 ns/500 ns @ 3.3 V
• Includes Edge Detection function
6.10 Additional Logic Functions (Part of Combination Function Macrocell)
• One Deglitch filter macro cell
6.11 RC Oscillator
• 25 kHz and 2 MHz selectable frequency
• First Stage Clock pre=divider (4): OSC/1, OSC/2, OSC/4, and OSC/8
• Second stage divider control with two outputs, OUT0 and OUT1 (8): selectable (OSC/1, OSC/2, OSC/3, OSC/4, OSC/8,
OSC/12, OSC/24, or OSC/64)
000-0046110-057 Page 10 of 65
SLG46110
Preliminary
7.0 I/O Pins
The SLG46110 has a total of 8 multi-function I/O pins which can function as either a user defined Input or Output, as well as
serving as a special function (such as outp utting the voltage reference), or serving as a signal for programming of the on-ch ip
Non Volatile Memory (NVM).
Normal Mode pin definitions are as follows:
•Pin 1: V
DD Power Supply
• Pin 2: General Purpose Input
• Pin 3: General Purpose I/O or Analog Comparator 0 (+)
• Pin 4: General Purpose I/O or Analog Comparator 0 (-)
• Pin 5: No Connect
• Pin 6: General Purpose I/O or Analog Comparator 1 (+) with OE
• Pin 7: Ground
• Pin 8: General Purpose I/O
• Pin 9: General Purpose I/O or POR Output
• Pin 10: General Purpose I/O with OE and Vref Output
• Pin 11: No Connect
• Pin 12: General Purpose I/O or External Clock Input
Programming Mode pin definitions are as follows:
•Pin 1: V
DD Power Supply
•Pin 2: V
PP Programming Voltage
• Pin 3: Programming ID Pin
• Pin 7: Ground
• Pin 8: Programming Mode Control
• Pin 9: Programming SDIO Pin
• Pin 10: Programming SRDWB Pin
• Pin 12: Programming SCL Pin
Of the 8 user defined I/O pins on the SLG46110, all but one of the pins (Pin 2) can serve as both digital input and digital output.
Pin 2 can only serve as a digital input pin.
7.1 Input Modes
Each I/O pin can be configured as a digital input pin with/without buffered Schmitt trigger, or can also be configured as a low
voltage digital input. Pins 3, 4, and 6 can also be configured to serve as analog inputs to the on-chip comparators.
7.2 Output Modes
Pins 3, 4, 6, 8, 9, 10, and 12 can all be configured as digital output pins.
7.3 Pull Up/Down Resistors
All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors
are 10 kΩ, 100 kΩ and 1 MΩ. In the case of Pin 2, the resistors are fixed to a pull-down configuration. In the case of all other I/O
pins, the internal resistors can be configur ed as either pull-up or pull-downs.
000-0046110-057 Page 1 1 of 65
SLG46110
Preliminary
7.4 I/O Register Settings
7.4.1 PIN 2 Register Settings
7.4.2 PIN 3 Register Settings
Table 1. PIN 2 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 2 Mode Control reg <380:379> 00: Digital Input without Schmitt trigger
01: Digital Input with Schmitt trigger
10: Low voltage digital input
11: Reserved
PIN 2 Pull Down
Resistor Value
Selection
reg <382:381> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
Table 2. PIN 3 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 3 Mode Control reg <385:383> 000: Digital Input without Schmitt trigger
001: Digital Input with Schmitt trigger
010: Low voltage digital input
011: Analog Input
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Analog Input & Open Drain NMOS
PIN 3 Pull Up/Down
Resistor Value
Selection
reg <387:386> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 3 Pull Up/Down
Resistor Selection reg <388> 0: Pull Down Resistor
1: Pull Up Resistor
PIN3 Driver
Strength Selection reg <389> 0: 1X
1: 2X
000-0046110-057 Page 12 of 65
SLG46110
Preliminary
7.4.3 PIN 4 Register Settings
7.4.4 PIN 6 Register Settings
Table 3. PIN 4 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 4 Mode Control reg <392:390> 000: Digital Input without Schmitt trigger
001: Digital Input with Schmitt trigger
010: Low voltage digital input
011: Analog Input
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Analog Input & Open Drain NMOS
PIN 4 Pull Up/Down
Resistor Value
Selection
reg <394:393> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 4 Pull Up/Down
Resistor Selection reg <395> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 4 Driver
Strength Selection reg <396> 0: 1X
1: 2X
Table 4. PIN 6 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 6 Mode Control
(sig_PIN6_oe=0) reg <398:397> 00: Digital Input without Schmitt trigger
01: Digital Input with Schmitt trigger
11: Low Voltage Digital Input
10: Analog Input
PIN 6 Mode Control
(sig_PIN6_oe =1) reg <400:399> 00: Push Pull 1X
01: Push Pull 2X
10: Open Drain NMOS 1X
11: Open Drain NMOS 2X
PIN 6 Pull Up/Down
Resistor Value
Selection
reg <402:401> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 6 Pull Up/Down
Resistor Selection reg <403> 0: Pull Down Resistor
1: Pull Up Resistor
000-0046110-057 Page 13 of 65
SLG46110
Preliminary
7.4.5 PIN 8 Register Settings
7.4.6 PIN 9 Register Settings
Table 5. PIN 8 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 8 Mode Control reg <406:404> 000: Digital Input without Schmitt trigger
001: Digital Input with Schmitt trigger
010: Low voltage digital input
011: Analog Input
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Analog Input & Open Drain NMOS
PIN 8 Pull Up/Down
Resistor Value
Selection
reg <408:407> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 8 Pull Up/Down
Resistor Selection reg <409> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 8 Driver
Strength Selection reg <410> 0: 1X
1: 2X
Table 6. PIN 9 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 9 Mode Control reg <413:411> 000: Digital Input without Schmitt trigger
001: Digital Input with Schmitt trigger
010: Low voltage digital input
011: Analog Input
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Analog Input & Open Drain NMOS
PIN 9 Pull Up/Down
Resistor Value
Selection
reg <415:414> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 9 Pull Up/Down
Resistor Selection reg <416> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 8 Driver
Strength Selection reg <417> 0: 1X
1: 2X
000-0046110-057 Page 14 of 65
SLG46110
Preliminary
7.4.7 PIN 10 Register Settings
7.4.8 PIN 12 Register Settings
Table 7. PIN 10 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 10 Mode
Control
(sig_PIN10_oe =0)
reg <419:418> 00: Digital Input without Schmitt trigger
01: Digital Input with Schmitt trigger
11: Low Voltage Digital Input
10: Analog Input / Output
PIN 10 Mode
Control
(sig_PIN10_oe =1)
reg <419:418> 00: Push Pull 1X
01: Push Pull 2X
10: Open Drain NMOS 1X
11: Open Drain NMOS 2X
PIN 10 Pull
Up/Down Resistor
Value Selection
reg <423:422> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 10 Pull
Up/Down Resistor
Selection
reg <424> 0: Pull Down Resistor
1: Pull Up Resistor
Table 8. PIN 12 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 12 Mode
Control reg <427:425> 000: Digital Input without Schmitt trigger
001: Digital Input with Schmitt trigger
010: Low voltage digital input
011: Analog Input
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Analog Input & Open Drain NMOS
PIN 12 Pull
Up/Down Resistor
Value Selection
reg <429:428> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 12 Pull
Up/Down Resistor
Selection
reg <430> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 12 Driver
Strength Selection reg <431> 0: 1X
1: 2X
000-0046110-057 Page 15 of 65
SLG46110
Preliminary
7.5 GPI IO Structure
7.5.1 GPI IO Structure (for Pin 2)
Figure 2. PIN 2 GPI IO Structure Diagram
PAD
Digital In
S0
S1
S2
S3
Floating
10 kΩ
90 kΩ
900 kΩ
Res_sel[1:0]
00: floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
wosmt_en
smt_en
lv_en Low Voltage
Input
Schmitt Trigger
Input
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en=1
01: Digital In with Schmitt Trigger, smt_en=1
10: Low Voltage Digital In mode, lv_en = 1
11: Reserved
000-0046110-057 Page 16 of 65
SLG46110
Preliminary
7.6 Matrix OE IO Structure
7.6.1 Matrix OE IO Structure (for Pin 6, 10)
Figure 3. Matrix OE IO Structure Diagram
PAD
Digital In
S0
S1
S2
S3
Floating
S0
S1
pull_up_en
10 kΩ
90 kΩ
900 kΩ
Res_sel[1:0]
00: floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
wosmt_en
smt_en
lv_en Low Voltage
Input
Schmitt Trigger
Input
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en=1
01: Digital In with Schmitt Trigger, smt_en=1
10: Low Voltage Digital In mode, lv_en = 1
11: analog IO mode
Output Mode [1:0]
00: 1x push-pull mode, pp1x_en=1
01: 2x push-pull mode, pp2x_en=1, pp1x_en=1
10: 1x NMOS open drain mode, od1x_en=1
11: 2x NMOS open drain mode, od2x_en=1, od1x_en=1
Analog IO
Digital Out
Digital Out
OE
od2x_en
OE
od1x_en
Digital Out
OE
pp2x_en
Digital Out
OE
pp1x_en
000-0046110-057 Page 17 of 65
SLG46110
Preliminary
7.7 Register OE IO Structure
7.7.1 Register OE IO Structure (for Pins 3, 4, 8, 9, 12)
Figure 4. Register OE IO Structure Diagram
PAD
Digital In
S0
S1
S2
S3
Floating
S0
S1
pull_up_en
10 kΩ
90 kΩ
900 kΩ
Res_sel[1:0]
00: floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
wosmt_en
smt_en
lv_en Low V oltage
Input
Schmitt Trigger
Input
Non-Schmitt
Trigger Input
Mode [2:0]
000: Digital In without Schmitt Trigger , wosmt_en=1
001: Digital In with Schmitt Trigger, smt_en=1
010: Low Voltage Digital In mode, lv_en = 1
011: analog IO mode
100: push-pull mode, pp_en=1
101: NMOS open drain mode, odn_en=1
110: PMOS open drain mode, odp_en=1
111: analog IO and NMOS open-drain mode, odn_en=1 and AIO_en=1
Analog IO
Digital Out
Digital Out
OE
odn_en
OE
odn_en
Digital Out
OE
2x_en
pp_en
2x_en
odp_en
Digital Out
OE
pp_en
2x_en
odp_en
000-0046110-057 Page 18 of 65
SLG46110
Preliminary
8.0 Connection Matrix
The Connection Matrix in the SLG46110 is used to create the internal routing for internal functions of the device once it is
programmed. The registers are programmed from the one-time NVM cell during Test Mode Operation. All of the connection point
for each logic cell within the SLG46110 has a specific digital bit code assigned to it that is either set to active “High” or inactive
“Low” based on the design that is created. Once the 512 register bits within the SLG46110 are programmed a fully custom circuit
will be created.
The Connection Matrix has 32 inputs and 44 outputs. Each of the 32 inputs to the Connection Matrix is hard-wired to a particular
source macrocell, including I/O pins, LUTs, analog comparators, other digital resources and VDD and VSS. Th e input to a digital
macrocell uses a 5-bit register to select one of these 32 input lines.
For a complete list of the SLG46110’s register table, see Section 15.0 Appendix A - SLG46110 Regi ster Definition.
Figure 5. Connection Matrix
VSS 0
Pin 2 Digital In 1
Pin 3 Digital In 2
Pin 4 Digital In 3
Matrix Input Signal
Functions N
PIN12 Digital In 30
VDD 31
N
Function
Registers
43
PIN12 Digital Output
Source
reg <219:215>
0
PIN3 Digital Output
Source
reg <4:0>
1
PIN4Digital Output
Source
reg <9:5>
2
PIN6 Digital Output
Source
reg <14:10>
Matrix Inputs
Matrix Outputs
000-0046110-057 Page 19 of 65
SLG46110
Preliminary
8.1 Matrix Input Table
Table 9. Matrix Input Table
NMatrix Input Signal Function Matrix Decode
43210
0 VSS 00000
1 pin2 digital Input 0 0 0 0 1
2 pin3 digital Input 0 0 0 1 0
3 pin4 digital Input 0 0 0 1 1
4 pin6 digital Input 0 0 1 0 0
5 LUT2_0 output (DFF/LATCH_0 output) 0 0 1 0 1
6 LUT2_1 output (DFF/LATCH_1 output) 0 0 1 1 0
7 LUT2_2 output 0 0 1 1 1
8 LUT2_3 output 0 1 0 0 0
9 LUT3_0 output (DFF/LATCH_2 output with resetb or seb) 0 1 0 0 1
10 LUT3_1 output (DFF/LATCH_3 output with resetb or seb) 0 1 0 1 0
11 LU T3_2 output 0 1 0 1 1
12 LUT3_3 output 0 1 1 0 0
13 LUT3_4 output(pipe delay ouput0) 0 1 1 0 1
14 pipe delay oupu t1 0 1 1 1 0
15 LUT4_0 output (CNT_DLY2 output (8 bit w/ ext CK,reset)) 0 1 1 1 1
16 CNT_DLY0 output (8 bit w/ ext CK (shared bottom delay/cnt),reset) 1 0 0 0 0
17 CNT_DLY1 output (8 bit w/ ext CK (from dedicated matrix out-
put),reset) 10001
18 CNT_DLY3 (8 bit) output 1 0 0 1 0
19 ACMP_0 output 1 0 0 1 1
20 ACMP_1 output 1 0 1 0 0
21 Edge detect output 1 0 1 0 1
22 Programmable delay with edge detector output (Deglitch filter out-
put) 10110
23 internal oscillator output1 (one of /1,/2,/3,/4,/8,12/,24/,64/ selected
by REG) 10111
24 internal oscillator output2 (one of /1,/2,/3,/4,/8,12/,24/,64/ selected
by REG) 11000
25 Bandgap OK signal 1 1 0 0 1
26 POR output to matrix 1 1 0 1 0
27 pin8 digital Input 1 1 0 1 1
28 pin9 digital Input 1 1 1 0 0
29 pin10 digital Input 1 1 1 0 1
30 pin12 digital Input 1 1 1 1 0
31 VDD 11111
000-0046110-057 Page 20 of 65
SLG46110
Preliminary
8.2 Matrix Output Table
Table 10. Matrix Output Table
Register Bit
Address Matrix Output Signal Function Matrix Output
Number
reg <4:0> Pin 3 digital out source 0
reg <9:5> Pin 4 digital out source 1
reg <14:10> Pin 6 digital out source 2
reg <19:15> Pin 6 output enable 3
reg <24:20> in0 of LUT2_0 (Clock Input of DFF0) 4
reg <29:25> in1 of LUT2 _0 (Da ta Input of DFF0) 5
reg <34:30> in0 of LUT2_1 (Clock Input of DFF1) 6
reg <39:35> in1 of LUT2 _1 (Da ta Input of DFF1) 7
reg <44:40> in0 of LUT2_2 8
reg <49:45> in1 of LUT2_2 9
reg <54:50> in0 of LUT2_3 10
reg <59:55> in1 of LUT2_3 11
reg <64:60> in0 of LUT3_0 (Clock Input of DFF2 with nReset/nSet) 12
reg <69:65> in1 of LUT3_0 (Data input of DFF2 with nReset/nSet) 13
reg <74:70> in2 of LUT3_0 (Resetb or Setb of DFF2 with nReset/nSet) 14
reg <79:75> in0 of LUT3_1 (Clock Input of DFF3 with nReset/nSet) 15
reg <84:80> in1 of LUT3_1 (Data input of DFF3 with nReset/nSet) 16
reg <89:85> in2 of LUT3_1 (Resetb or Setb of DFF3 with nReset/nSet) 17
reg <94:90> in0 of LUT3_2 18
reg <99:95> in1 of LUT3_2 19
reg <104:100> in2 of LUT3_2 20
reg <109:105> in0 of LUT3_3 21
reg <114:110> in1 of LUT3_3 22
reg <119:115> in2 of LUT3_3 23
reg <124:120> in0 of LUT3_4 (Input of pipe delay) 24
reg <129:125> in1 of LUT3_4 (Resetb of pipe delay) 25
reg <134:130> in2 of LUT3_4 (Clock of pipe delay) 26
reg <139:135> in0 of LUT4_0 (Input for Delay2 ext. clock or Counter2 external Clock) 27
reg <144:140> in1 of LUT4_0 (Input for delay2 or counter2 reset input) 28
reg <149:145> in2 of LUT4_0 29
reg <154:150> in3 of LUT4_0 30
reg <159:155> Input for delay0 or counter0 reset input 31
reg <164:160> Input for delay1 or counter1 reset input 32
reg <169:165> Input for Delay0/1 ext. clock or Counter1 external Clock 33
reg <174:170> Input for delay3 or counter3 reset input 34
reg <179:175> pdb for ACMP0 35
reg <184:180> pdb for ACMP1 36
reg <189:185> Input for programmable delay(deglitch filter input) 37
000-0046110-057 Page 21 of 65
SLG46110
Preliminary
reg <194:190> Power down for osc. (higher priority) (high = power down). 38
reg <199:195> Pin 8 digital out source 39
reg <204:200> Pin 9 digital out source 40
reg <209:205> Pin 10 digital out source 41
reg <214:210> Pin 10 output enable 42
reg <219:215> Pin 12 digital out source 43
Table 10. Matrix Output Table
Register Bit
Address Matrix Output Signal Function Matrix Output
Number
000-0046110-057 Page 22 of 65
SLG46110
Preliminary
9.0 Combinatorial Logic
Combinatorial logic is supported via four Lookup T ables (LUTs) within the SLG461 10. There are two 2-bit LUT s and two 3-bit LUTs.
The device also in cludes six Comb ination F unction Macroce lls tha t can be used as LUTs. For more details, please see Section
10.0 Combination Function Macro Cells.
Inputs/Outputs for the four LUTs are configured from the connection matrix with specific logic functions being defined by the state
of NVM bits. The outputs of the LUTs can be configured to any user defined function, including the following standard digital logic
devices (AND, NAND, OR, NOR, XOR, XNOR).
9.1 2-Bit LUT
The two 2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into
the connection matrix. ..
Each 2-bit LUT uses a 4-bit register signal to define their outpu t functions;
2-Bit LUT2 is defined by reg <23 5:232>
2-Bit LUT3 is defined by reg <23 9:236>
The table below shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be
created within each of the two 2-bit LUT logic cells.
Figure 6. 2-bit LUTs
Table 13. 2-bit LUT Standard Digital Functions.
Function MSB LSB
AND-2 1000
NAND-2 0 1 1 1
OR-2 1110
NOR-2 0 0 0 1
XOR-2 0110
XNOR-2 1001
2-bit LUT2 OUT
IN1
IN0
reg <235:232>
From Connection
Matrix Output <8>
From Connection
Matrix Output <9>
To Connection
Matrix Input <7> 2-bit LUT3 OUT
IN1
IN0
reg <239:236>
From Connection
Matrix Output <10>
From Connection
Matrix Output <11>
To Connection
Matrix Input <8>
Ta ble 11. 2-bit LU T2 Truth Table.
IN1 IN0 OUT
0 0 reg <232>
0 1 reg <233>
1 0 reg <234>
1 1 reg <235>
Table 12. 2-bit LUT3 Truth Table.
IN1 IN0 OUT
0 0 reg <236>
0 1 reg <237>
1 0 reg <238>
1 1 reg <239>
000-0046110-057 Page 23 of 65
SLG46110
Preliminary
9.2 3-Bit LUT
The two 3-bit LUTs each take in three input signals from the connection matrix and produce a single output, which goes back into
the connection matrix.
Each 3-bit LUT uses a 8-bit register signal to define their outpu t functions;
3-Bit LUT2 is defined by reg <26 5:258>
3-Bit LUT3 is defined by reg <27 3:266>
Figure 7. 3-bit LUTs
3-bit LUT2 OUT
IN1
IN0
reg <265:258>
From Connection
Matrix Output <18>
From Connection
Matrix Output <19> To Connection
Matrix Input <11> 3-bit LUT3 OUT
IN1
IN0
reg <273:266>
From Connection
Matrix Output <21>
From Connection
Matrix Output <22> To Connection
Matrix Input <12>
IN2
From Connection
Matrix Output <20> IN2
From Connection
Matrix Output <23>
Table 14. 3-bit LUT2 Truth Table.
IN2 IN1 IN0 OUT
0 0 0 reg <258>
0 0 1 reg <259>
0 1 0 reg <260>
0 1 1 reg <261>
1 0 0 reg <262>
1 0 1 reg <263>
1 1 0 reg <264>
1 1 1 reg <265>
Table 15. 3-bit LUT3 Truth Table.
IN2 IN1 IN0 OUT
0 0 0 reg <266>
0 0 1 reg <267>
0 1 0 reg <268>
0 1 1 reg <269>
1 0 0 reg <270>
1 0 1 reg <271>
1 1 0 reg <272>
1 1 1 reg <273>
000-0046110-057 Page 24 of 65
SLG46110
Preliminary
The table below shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be
created within each of the two 3-bit LUT logic cells.
Table 16. 3-bit LUT Standard Digital Functions.
Function MSB LSB
AND-3 10000000
NAND-3 01111111
OR-3 11111110
NOR-3 00000001
XOR-3 10010110
XNOR-3 01101001
000-0046110-057 Page 25 of 65
SLG46110
Preliminary
10.0 Combination Function Macro Cells
The SLG46110 has seven combination function macrocells that can serve more than one logic or timing function. In six of these
cases, they can serve as a Look Up Table (L UT), o r as another lo gic o r ti ming functi on. In the last case, it can serve as eithe r a
programmable delay or deglitch filter. See the list below for the functions that can be implemented in these macrocells ;
• Two macrocells that can serve as either 2-bit LUTs or as D Flip Flops.
• Two macrocells that can serve as either 3-bit LUTs or as D Flip Flops.
• One macrocell that can serve as either 3-bit LUT or as Pipe Delay
• One macrocells that can serve as either 4-bit LUTs or as 8-Bit Counter / Delays
• One macrocell that can serve as either a Programmable Delay or as a Deglitch Filter
Inputs/Outputs for the seven combination function macrocells are configured from the connection matrix with specific logic func-
tions being defined by the state of NVM bits.
When used as a LUT to implement combinatorial logic functi ons, the outpu ts of the LUTs can be configured to any user defined
function, includi ng the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
When used as a D Flip Flop / Latch, the source and destination of the inputs and outputs for the DFF/Latches are configured from
the connection matrix. All DFF/Latch macrocells have user sel ection for initia l state, and all have the option to connect both the
Q and Q Bar outputs to the connection matrix. The macrocells DFF2, DFF3 have an additional input from the matrix that can
serve as a nSet or nReset function to the macrocell.
The operation of the D Flip-Flo p and Latch will follow the functional descriptions below:
DFF: CLK is rising edge triggere d, then Q = D; otherwise Q will not change
Latch: if CLK = 0, then Q = D
10.1 2-Bit LUT or D Flip Flop Macrocells
There are two macrocells that can serve as either 2-bit LUTs or as D Flip Flops. When used to implement LUT functions, the 2-bit
LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the connection
matrix. When used to implement D Flip Flop function, the two input signals from the connection matrix go to the data (d) and clock
(clk) inputs for the Flip Flop, with the output going back to the connection matrix.
000-0046110-057 Page 26 of 65
SLG46110
Preliminary
Figure 8. 2-bit LUT0 or DFF0
Figure 9. 2-bit LUT1 or DFF1
DFF0
clk
D
2-bit LUT0 OUT
IN0
IN1
To Connection Matrix
Input <5>
4-bits NVM
From Connection Matrix Output <5>
1-bit NVM
reg <227:224>
reg <240>
From Connection Matrix Output <4> Q/nQ
reg <225> Output Se lect (Q or nQ)
DFF1
2-bit LUT1
From Connection Matrix Output <7>
reg <231:228>
reg <241>
From Connection Matrix Output <6>
To Connection Matrix
Input <6>
clk
D
OUT
IN0
IN1
4-bits NVM
1-bit NVM
Q/nQ
reg <229> Output Se lect (Q or nQ)
000-0046110-057 Page 27 of 65
SLG46110
Preliminary
10.1.1 2-Bit LUT or D Flip Flop Macrocells Used as 2-Bit LUTs
Each Macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-Bit LUT0 is defined by reg <22 7:224>
2-Bit LUT1 is defined by reg <23 1:228>
10.1.2 2-Bit LUT or D Flip Flop Macrocells Used as D Flip Flop Register Settings
Table 19. DFF0 Register Settings
Signal Function Register Bit
Address Register Definition
DFF0 or Latch
select reg <224> 0: DFF function
1: Latch function
DFF0 output select reg <225> 0: Q output
1: nQ output
DFF0 initial polarity
select reg <226> 0: Low
1: High
LUT2_0 data reg <235:232> LUT2_0 data
LUT2_0 or DFF0
select reg <240> 0: LUT2_0
1: DFF0
Table 20. DFF1Register Settings
Signal Function Register Bit
Address Register Definition
DFF1 or Latch
select reg <228> 0: DFF function
1: Latch function
DFF1 output select reg <229> 0: Q output
1: nQ output
DFF1 initial polarity
select reg <230> 0: Low
1: High
LUT2_1 data reg <239:236> LUT2_1 data
LUT2_1 or DFF1
select reg <241> 0: LUT2_1
1: DFF1
Table 17. 2-bit LUT0 Truth Table.
IN1 IN0 OUT
0 0 reg <224>
0 1 reg <225>
1 0 reg <226>
1 1 reg <227>
Table 18. 2-bit LUT1 Truth Table.
IN1 IN0 OUT
0 0 reg <228>
0 1 reg <229>
1 0 reg <230>
1 1 reg <231>
000-0046110-057 Page 28 of 65
SLG46110
Preliminary
10.2 3-Bit LUT or D Flip Flop with Set/Reset Macrocells
There are two macrocells that can serve as either 3-bit LUTs or as D Flip Flops. When used to implement LUT functions, the 3-bit
LUTs each take in three input signals from the connection matrix and produce a single output, which goes back into the connection
matrix. When used to implement D Flip Flop function, the three input signals from the connection matrix go to th e data (d) and
clock (clk) and Set/Reset (rRST/nSET) inputs for the Flip Flop, with the output going back to the connection matrix..
Figure 10. 3-bit LUT0 or DFF2
Figure 11. 3-bit LUT1 or DFF3
DFF2
clk
D
To Connection Matrix<
Input 9>
8-bits NVM
From Connection
Matrix Output <14>
1-bit NVM
3-bit LUT0 OUT
IN1
IN2
IN0
nRST/nSET
From Connection
Matrix Output <13>
From Connection
Matrix Output <12>
reg <249:242>
reg <282 >
Q/nQ
reg <243> Output Select (Q or nQ)
000-0046110-057 Page 29 of 65
SLG46110
Preliminary
10.2.1 3-Bit LUT or D Flip Flop Macrocells Used as 3-Bit LUTs
Each Macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT2 is defined by reg <24 9:242>
3-Bit LUT3 is defined by reg <25 7:250>
Table 21. 3-bit LUT0 Truth Table.
IN2 IN1 IN0 OUT
0 0 0 reg <242>
0 0 1 reg <243>
0 1 0 reg <244>
0 1 1 reg <245>
1 0 0 reg <246>
1 0 1 reg <247>
1 1 0 reg <248>
1 1 1 reg <249>
Ta ble 22. 3-bit LUT1 Truth Table.
IN2 IN1 IN0 OUT
0 0 0 reg <250>
0 0 1 reg <251>
0 1 0 reg <252>
0 1 1 reg <253>
1 0 0 reg <254>
1 0 1 reg <255>
1 1 0 reg <256>
1 1 1 reg <257>
000-0046110-057 Page 30 of 65
SLG46110
Preliminary
10.2.2 3-Bit LUT or D Flip Flop Macrocells Used as D Flip Flop Register Settings
Table 23. DFF2 Register Settings
Signal Function Register Bit
Address Register Definition
DFF2 or Latch
select reg <242> 0: DFF function
1: Latch function
DFF2 output select reg <243> 0: Q output
1: nQ output
DFF2 initial polarity
select reg <244> 0: Low
1: High
DFF2 rstb/setb
Select reg <245> 1: setb from matri x out
0: resetb from matrix out
LUT3_0 data reg <265:258> LUT3_0 data
LUT3_0 or DFF2
select reg <282> 0: LUT3_0
1: DFF2
Table 24. DFF3 Register Settings
Signal Function Register Bit
Address Register Definition
DFF3 or Latch
Select reg <250> 0: DFF function
1: Latch function
DFF3 Output Select reg <251> 0: Q output
1: nQ output
DFF3 rstb/setb
Select reg <252> 1: setb from matrix out
0: resetb from matrix out
DFF3 initial polarity
select reg <253> 0: Low
1: High
LUT3_1 data reg <273:266> LUT3_1 data
LUT3_1 or DFF3
select reg <283> 0: LUT3_1
1: DFF3
000-0046110-057 Page 31 of 65
SLG46110
Preliminary
10.3 3-Bit LUT or Pipe Delay Macrocell
There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay.
When used to implement LUT functions, the 3-bit LUT take in three input signals from the connection matrix and produces a single
output, which goes back into the connection matrix.
When used as an 8-stage pipe delay, there are three inp uts signals from the matrix, Input (IN), Clo ck (CK) and Reset (nRe set).
The pipe delay cell is built from D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The
DFF cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell. The two outputs (OUT0 and OUT1)
provide user selectable options for 1 to 8 stages of delay There are delay output points for each set of the OUT0 and OUT1 outputs
to a 3-input mux that is co ntrolle d by reg <6 66:663 > for OUT0 and reg <670:667> for OUT1 . The 3-inp ut mux is used to control
the selection of the amount of delay.
The overall time of the delay is based on the clock used in the SLG46110 design. Each DFF cell has a time delay of the inverse
of the clock time (either external cl ock or the RC Oscill ator within the SLG46110). The sum of the number of DFF cells used will
be the total time delay of the Pipe Delay logic cell.
Figure 12. 3-bit LUT4 or Pipe Delay
3-bit LUT4 OUT
IN1
IN0
reg <281:274>
From Connection
Matrix Output <24>
From Connection
Matrix Output <25>
IN2
From Connection
Matrix Output <26>
8 Flip flop Block
IN
nReset
CK
From Connection
Matrix Output <25>
From Connection
Matrix Output <24>
From Connection
Matrix Output <26>
reg <276:274>
reg <279:277>
To Connection
Matrix Input<14>
OUT1
OUT0
reg <432>
1
0
To Connection
Matrix Input<13>
reg <284>
0
1
000-0046110-057 Page 32 of 65
SLG46110
Preliminary
10.3.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUTs
Each Macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT4 is defined by reg <28 1:274>
10.3.2 3-Bit LUT or Pipe Dela y Macrocells Used as Pipe Delay Register Setting s
Table 26. Pipe Delay Register Settings
Signal Function Register Bit
Address Register Definition
OUT0 select reg <27 6:274> data (pipe number)
OUT1 select reg <27 9:277> data (pipe number)
LUT3_4 or pipe de-
lay output select reg <284> 0: LUT3_4
1: pipe delay
Table 25. 3-bit LUT4 Truth Table.
IN2 IN1 IN0 OUT
0 0 0 reg <274>
0 0 1 reg <275>
0 1 0 reg <276>
0 1 1 reg <277>
1 0 0 reg <278>
1 0 1 reg <279>
1 1 0 reg <280>
1 1 1 reg <281>
000-0046110-057 Page 33 of 65
SLG46110
Preliminary
10.4 4-Bit LUT or 8- Bit Counter / Delay Macrocells
There is one macrocell that can serve as either a 4-bit LUT or as a Counter / Delay. When used to implement LUT functions, the
4-bit LUT takes in four input signals from the connection matrix and produces a single output, which goes back into the connection
matrix. When used to implement 8-Bit Counter / Delay function, two of the four input signals from the connection matrix go to the
external clock (ext_clk) and reset (DL Y_n/CNT_Reset) for the counter/delay , with the output going back to the connection matrix.
Figure 13. 4-bit LUT0 or CNT/DLY2
CNT/DLY2 OUT
clk
DLY_n/CNT_Reset
4-bit LUT0
OUT
IN0
IN1
16-bits NVM
1-bit NVM
IN2
IN3
To Connection
Matrix Input <15>
From Connection Matrix Output <28>
reg <300:285>
reg <301>
From Connection
Matrix Output <27>
From Connection Matrix Output <30>
From Connection Matrix Output <29>
000-0046110-057 Page 34 of 65
SLG46110
Preliminary
10.4.1 4-Bit LUT or 8-B it Counter / Delay Macrocell Used as 4-Bit LUTs
Each Macrocell, when programmed for a LUT function, uses a 16-bit register to define their output function:
4-Bit LUT0 is defined by reg <30 0:285>
Table 28. 4-bit LUT Standard Digital Functions.
Function MSB LSB
AND-4 1000000000000000
NAND-40111111111111111
OR-4 1111111111111110
NOR-4 0000000000000001
XOR-4 0110100111001110
XNOR-41001011000110001
Table 27. 4-bit LUT0 Truth Table.
IN3 IN2 IN1 IN0 OUT
0000reg <285>
0001reg <286>
0010reg <287>
0011reg <288>
0100reg <289>
0101reg <290>
0110reg <291>
0111reg <292>
1000reg <293>
1001reg <294>
1010reg <295>
1011reg <296>
1100reg <297>
1101reg <298>
1110reg <299>
1111reg <300>
000-0046110-057 Page 35 of 65
SLG46110
Preliminary
10.4.2 4-Bit LUT or 8-Bit Counter / Delay Macroc ells Used as 8-Bit Counter / Delay Register Setting s
10.5 Programmable Delay / Edge Detector
The SLG46110 has a programma ble time de lay logi c cell ava ilab l e th at can generate a delay that is selectable from one of four
timings (time1) configured in the GreenP AK Designer. The programmable time delay cell can generate one of four different delay
patterns, rising edge detection, falling edge detection, both edge detection and both edge delay . These four patterns can be further
modified with the addition of delayed edge detection, which adds an extra unit of delay as well as glitch rejection during the delay
period. See the timing diagrams below for further information.
Table 29. CNT/DLY2 Register Settings
Signal Function Register Bit
Address Register Definition
Counter/delay2
Mode Selection reg <285> 0: Delay Mode
1: Counter Mode
Counter/delay2
Clock Source Select reg <288:286> 000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock
111: Counter1 Overflow
Counter/delay2
Control Data reg <296:289> 1 – 256 (delay time = (counter control data +1) /freq)
Delay2 Mode Select
or asynchronous
counter reset
reg <298:297> 00: Delay on both falling and rising edges(for delay & counter reset)
01: Delay on falling edge only (for delay & counter reset)
10: Delay on rising edge only (for delay & counter reset)
11: No delay on either falling or rising edges / high level reset for counter mode
LUT4_0 or
Counter2 select reg <301> 0: LUT4_0
1: Counter2
Figure 14. Programmable Delay
Programmable
Delay OUT
IN
reg <489:488>
From Connection
Matrix Output <37> To Connection
Matrix Input <22>
reg <487 :486>
Edge Mode Selection
Delay Value Selection
1
0
reg <485 >
Deglitch Filter Out
1
0
reg <485>
Deglitch Filter In
000-0046110-057 Page 36 of 65
SLG46110
Preliminary
10.5.1 Programmable Delay Timing Diagram - Edge Detector Output
10.5.2 Programmable Delay Register Settings
Figure 15. Edge Detector Output
Table 30. Programmable Delay Register Settings
Signal Function Register Bit
Address Register Definition
Programmable
delay or filter output
select
reg <485> 0: programmable delay output
1: filter output
Select the edge
mode of
programmable
delay & edge
detector
reg <487:486> 00: Rising Edge Detector
01: Falling Edge Detector
10: Both Edge Detector
11 : Both Edge Delay
Delay value select
for programmable
delay & edge
detector
(VDD = 3.3V , typical
condition)
reg <489:488> 00: 125 ns
01: 250 ns
10: 375 ns
11: 500 ns
time1
Edge Detector
Output
IN
Rising Edge Detector
Falling Edge Detector
Both Edge Detector
Both Edge Delay
time1
time1 can be set by register value
000-0046110-057 Page 37 of 65
SLG46110
Preliminary
10.6 Deglitch Filter
The SLG46110 has an additional logic function that is connected d irectly to the Connection Matrix inputs and outputs. There is
one deglitch filter.
Figure 16. Deglitch Filter
Deglich Filter In Deglitch Filter Out
Filter
reg <441 >
C
R
000-0046110-057 Page 38 of 65
SLG46110
Preliminary
11.0 Analog Comparators (ACMP)
There are two Analog Comparator (ACMP) macro cells in the SLG46110. In order for the ACMP cells to be used in a GreenPAK
design, the power up signals (ACMP0_pdb and ACMP1_pdb) need to be active. By connecting to signals coming from the
Connection Matrix, it is possible to ha ve each ACMP be on cont inuously, off continuously, or switched on peri odically based on
a digital signal coming from the Connection Matrix. When ACMP is powered down, output is low.
Each of the ACMP cells has a positive input signal that can be provided by a variety of external sources, and can also have a
selectable gain stage before connection to the analog comparator. Each of the ACMP cell s has a negative input signal that is
either created from an internal VREF or provided by way of the external sources.
Each of the ACMP cells has a selection for the bandwidth of the input signal, which can be used to save power when low bandwidth
signals are input into the analog comparator . Each cell also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV
or 200 mV.
11.1 ACMP0 Block Diagram
Figure 17. ACMP0 Block Diagram
11010
11001-
00000
Internal
Vref
PIN4: ACMP0(-)
10
01
PIN3: ACMP0(+)
External VDD 1.71 V ~ 5.5 V
Selectable
Gain
reg <364:363>
to ACMP1 MUX input
Vref
+
-
From Connection
Matrix Output <12>
pdb
LBW
Selection
ibias
reg <365>
Hysteresis
Selection
reg <362:361>
L/S
ON after
100 μs Delay
To Connection
Matrix Input< 19 >
reg <360:356>
*PIN3_aio_en; reg <366>
OFF after
1 μs Delay
*PIN3_aio_en:
if reg <385:383> = ’011’ then 1, otherwise: 0
000-0046110-057 Page 39 of 65
SLG46110
Preliminary
11.2 ACMP0 Register Settings
Table 31. ACMP0 Register Settings
Signal Function Register Bit
Address Register Definition
ACMP0 In Voltage
Select reg <360:356> 00000: 50 mV 00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: VDD/3 11001: VDD/4
11010: EXT_VREF (PIN4)
ACMP0 Hysteresis
Enable reg <362:361> 00: Disabled (0 mV)
01: Enabled (25 mV)
10: Enabled (50 mV)
11 : Enabled (200 mV)
ACMP0 Positive
Input Divider reg <364:363> 00: 1.00X
01: 0.50X
10: 0.33X
11 : 0.25X
ACMP0 Low
Bandwidth (Max: 1
MHz) Enable
reg <365> 0: Off
1: On
ACMP0 positive
input source select
PIN3 and VDD
reg <366> 0: Pin3
1: VDD
000-0046110-057 Page 40 of 65
SLG46110
Preliminary
11.3 ACMP1 Block Diagram
Figure 18. ACMP1 Block Diagram
11010
11001-
00000
Internal
Vref
PIN4: ACMP0(-)
10
01
PIN6: ACMP1(+)
From ACMP0’s MUX
Selectable
Gain
reg <375:374>
Vref
+
-
From Connection
Matrix Output <36>
pdb
LBW
Selection
ibias
reg <377>
Hysteresis
Selection
reg <373:372>
L/S
ON after
100 μs Delay
To Connection
Matrix Input< 20 >
reg <371:367>
*PIN6_aio_en; reg <378>
OFF after
1 μs Delay
*PIN6_aio_en:
if reg <19:15> = ’00000’ and reg <398:397> = ‘11’ then 1, otherwise: 0
000-0046110-057 Page 41 of 65
SLG46110
Preliminary
11.4 ACMP1 Register Settings
Table 32. ACMP1 Register Settings
Signal Function Register Bit
Address Register Definition
ACMP1 In Voltage
Select reg <371:367> 00000: 50 mV 00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: VDD/3 11001: VDD/4
11010: EXT_VREF (PIN4)
ACMP1 Hysteresis
Enable reg <373:372> 00: Disabled (0 mV)
01: Enabled (25 mV)
10: Enabled (50 mV)
11 : Enabled (200 mV)
ACMP1 Positive
Input Divider reg <375:374> 00: 1.00X
01: 0.50X
10: 0.33X
11 : 0.25X
ACMP1 Low
Bandwidth (Max: 1
MHz) Enable
reg <377> 1: On
0: Off
ACMP1 positive
input source select
PIN3 and Pin6
reg <378> 0: Pin6
1: Pin3
000-0046110-057 Page 42 of 65
SLG46110
Preliminary
12.0 Counters/Delay Generators (CNT/DLY)
There are three configura ble counters/d elay generators in the SLG46110. The three counters/delay generators (CNT /DLY 0, 1,
3) are 8-bit. For flexibility, each of th ese macrocells has a large selection of internal and external clock sources, as well as the
option to chain from the output of th e previous (N-1) CNT/DLY macrocell, to implement longer count / delay circuits.
Two of the counter/delay generator macrocells (CNT/DLY0 and CNT/DLY1) have two inputs from the connection matrix, one for
Delay Input/Reset Input (Delay_In/Re set_In), and one for an external counter/clock source. One of the coun ter/delay ge nerator
macrocells (CNT/DLY3) has one input from the connection matrix, which has a shared function of either a Delay Input or an
external clock input.
Note that there is al so one Combination F unction Macrocells that can impl ement either 4-bit LUTs or 8-bit counter / d elays, For
more information please see Section 10.4 4-Bit LUT or 8- Bit Counter / Delay Macroc ells.
Figure 19. CNT/DLY 0
CNT/DLY0
Counter_end
clk
To Connection
Matrix Input <16>
From Connection
Matrix Output <31>
Count_end_out_x-1
reg <314>
0
1
2
3
4
5
6
7
ext. clock from CM Out<33>
RC Osc/64
RC Osc/24
RC Osc/12
RC Osc/4
RC Osc
Counter Control Data
reg <325:318>
reg <317:315>
0
1
0
1
Delay_out
Delay_IN
CNT clock
000-0046110-057 Page 43 of 65
SLG46110
Preliminary
Figure 20. CNT/DLY 1
Figure 21. CNT/DLY 3
CNT/DLY1
Counter_end
clk
To Connection
Matrix Input <17>
From Connection
Matrix Output <32>
Count_end_out_x-1
reg <328>
0
1
2
3
4
5
6
7
ext. clock from CM Out<33>
RC Osc/64
RC Osc/24
RC Osc/12
RC Osc/4
RC Osc
Counter Control Data
reg <339:332>
reg <331:329>
0
1
0
1
Delay_out
Delay_IN
Reset_IN
Edge Detector
CNT/DLY3
Counter_end
clk
To Connection
Matrix Input <18>
From Connection
Matrix Output <34>
Count_end_out_x-1
reg <342>
0
1
2
3
4
5
6
7
ext. clock
RC Osc/64
RC Osc/24
RC Osc/12
RC Osc/4
RC Osc
Counter Control Data
reg <353:346>
reg <345:343>
0
1
0
1
Delay_out
Delay_IN/CNT_ext_clk
Delay_IN
CNT clock
Edge Detector
000-0046110-057 Page 44 of 65
SLG46110
Preliminary
12.1 CNT/DLY0 Register Settin gs
12.2 CNT/DLY1 Register Settin gs
Table 33. CNT/DLY0 Register Settings
Signal Function Register Bit
Address Register Definition
Counter/Delay0
Mode Select reg <314> 0: Delay Mode
1: Counter Mode
Counter/Delay0
Clock Source Select
(external clock is
only for counter
mode)
reg <317:315> 000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock
111: Counter3 Overflow
Counter0 Control
Data/Delay0 Time
Control
reg <325:318> 1-256: (delay time = (counter control data +1) /freq)
Delay0 Mode Select
or asynchronous
counter reset
reg <327:326> 00: Delay on both falling and rising edges(for delay & counter reset)
01: Delay on falling edge only (for delay & counter reset)
10: Delay on rising edge only (for delay & counter reset)
11: No delay on either falling or rising edges / high level reset for counter mode
Table 34. CNT/DLY1 Register Settings
Signal Function Register Bit
Address Register Definition
Counter/Delay1
Mode Select reg <328> 0: Delay Mode
1: Counter Mode
Counter/Delay1
Clock Source Select
(external clock is
only for counter
mode)
reg <331:329> 000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock
111: Counter0 Overflow
Counter1 Control
Data/Delay1 Time
Control
reg <339:332> 1-256: (delay time = (counter control data +1) /freq)
Delay1 Mode Select
or asynchronous
counter reset
reg <341:340> 00: Delay on both falling and rising edges(for delay & counter reset)
01: Delay on falling edge only (for delay & counter reset)
10: Delay on rising edge only (for delay & counter reset)
11: No delay on either falling or rising edges / high level reset for counter mode
000-0046110-057 Page 45 of 65
SLG46110
Preliminary
12.3 CNT/DLY3 Register Settin gs
Table 35. CNT/DLY3 Register Settings
Signal Function Register Bit
Address Register Definition
Counter/Delay3
Mode Select reg <342> 0: Delay Mode
1: Counter Mode
Counter/Delay3
Clock Source Select
(external clock is
only for counter
mode)
reg <345:343> 000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock
111: Counter2 Overflow
Counter3 Control
Data/Delay3 Time
Control
reg <353:346 1-256: (delay time = (counter control data +1) /freq)
Delay3 Mode Select reg <355:354> 00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
000-0046110-057 Page 46 of 65
SLG46110
Preliminary
13.0 Voltage Reference (VREF)
13.1 Vo ltage Reference Overview
The SLG46110 has a Voltage Reference Macrocell to provide references to the four analog comparators. This macrocell can
supply a user selection of fixed voltage references, /3 and /4 reference off of the VDD power supply to the device, and externally
supplied voltage references from pin 4. The macrocell also has the option to output reference voltages on pin 10. See table below
for the available selections for each analog comparator. Also see Figure 22 below, which shows the reference output structure.
13.2 VREF Selection Table
Table 36. VREF Selection Table.
SEL<4:0> CMP0_VREF CMP1_VREF
11010 ext. Vref (PIN4) ext. Vref (PIN4)
11001 VDD / 4 VDD / 4
11000 VDD / 3 VDD / 3
10111 1.20 V 1.20 V
10110 1.15 V 1.15 V
10101 1.10 V 1.10 V
10100 1.05 V 1.05 V
10011 1.00 V 1.00 V
10010 0.95 V 0.95 V
10001 0.90 V 0.90 V
10000 0.85 V 0.85 V
01111 0.80 V 0.80 V
01110 0.75 V 0.75 V
01101 0.70 V 0.70 V
01100 0.65 V 0.65 V
01011 0.60 V 0.60 V
01010 0.55 V 0.55 V
01001 0.50 V 0.50 V
01000 0.45 V 0.45 V
00111 0.40 V 0.40 V
00110 0.35 V 0.35 V
00101 0.30 V 0.30 V
00100 0.25 V 0.25 V
00011 0.20 V 0.20 V
00010 0.15 V 0.15 V
00001 0.10 V 0.10 V
00000 0.05 V 0.05 V
VDD Practial VREF Range Note
2.0 V - 5.5 V 50 mV ~1.2 V
1.7 V - 2.0V 50 mV ~1.1 V Higher than 1.1 V negative input, the comparator may show wrong result
000-0046110-057 Page 47 of 65
SLG46110
Preliminary
13.3 VREF Block Diagram
Figure 22. Voltage Reference Block Diagram
CMP0_VREF
CMP1_VREF
reg <360:356>
reg <371:367>
VDD / 3
VDD / 4
ext_vref_acmp0
(Pin4)
reg <445>
forced bg ON
000
001
100
101
110
reg <452 > VDD / 2
VDD / 3
VDD / 4
reg <449:447>
1
0
OP
reg <446>
Vref Out_1 (Pin10)
Pin10_aio_en
External VDD
2.7 V - 5.5 V
000-0046110-057 Page 48 of 65
SLG46110
Preliminary
14.0 RC Oscillator (RC OSC)
14.1 RC Oscillator Overview
The SLG46110 has two internal RC oscillators, one that runs at 25 kHz and one that runs at 2 MHz. The user can select one of
these fundamental frequencies for the RC OSC Macro cell, or the fundamental frequency can also come from an exte rnal clock
input (Pin 12). There are two divider stages that allow the user flexibility for introducing clock signals on various Connection Matrix
Input lines. The first stage divider (also known as the clock pre-divider) allows the selection of /1, /2, /4 or /8 divide down frequency
from the fundamental. There are two seco nd stage divide r controls (OUT0 and OUT1). Each has its own input of one frequency
from the first stage divider, and outputs five different frequencies on Connection Matrix Input lines <45>, <46>, <47>, <48>, and
<49>. See Figure 23 below for details of the frequencies for each of these five Connection Matrix Inputs.
If PWR DOWN input of oscillator is LOW, the oscillator will be turned on. If PWR DOWN input of oscillator is HIGH the oscillator
will be turned off. The PWR DOWN signal has the highest priority.
14.2 RC OSC Block Diagram
Figure 23. RC OSC Block Diagram
Internal RCO
reg <303>
0: 25 kHz
1: 2 MHz
/ 2
/ 3
/ 4
/ 8
/ 12
/ 24
/ 64
To Connection Matrix Input <23>
reg <308:306>
DIV /1/2/4/8
reg <305:304>
Clock Pre- Divider
Control
Second Stage
Divider
Pin 12 Ext. C l oc k
Ext. Clk Sel reg <312>
0
1
reg <311:309>
To Connection Matrix Input <24>
From Connection Matrix Output <38>
PWR DOWN
OUT0
OUT1
000-0046110-057 Page 49 of 65
SLG46110
Preliminary
15.0 Appendix A - SLG46110 Register Definition
Register Bit
Address Signal Functi on Register Bit Definition
reg <4:0> M atrix Out: PIN3 Digital Output Source
reg <9:5> M atrix Out: PIN4 Digital Output Source
reg <14:10> Matrix Out: PIN6 Digital Output Source
reg <19:15> Matrix Out: Output Enable of PIN6
reg <24:20> Matrix Out: In0 of LUT2 _0 or C lo ck In pu t o f DF F0
reg <29:25> Matrix Out: In1 of LUT2_0 or Data Input of DFF0
reg <34:30> Matrix Out: In0 of LUT2 _1 or C lo ck In pu t o f DF F1
reg <39:35> Matrix Out: In1 of LUT2_1 or Data Input of DFF1
reg <44:40> Matrix Out: In0 of LUT2_ 2
reg <49:45> Matrix Out: In1 of LUT2_ 2
reg <54:50> Matrix Out: In0 of LUT2_ 3
reg <59:55> Matrix Out: In1 of LUT2_ 3
reg <64:60> Matrix Out: In0 of LUT3 _0 or C lo ck In pu t o f DF F2
reg <69:65> Matrix Out: In1 of LUT3_0 or Data Input of DFF2
reg <74:70> Matrix Out: In2 of LU T3 _0 or R ese tb Input of DFF2
reg <79:75> Matrix Out: In0 of LUT3 _1 or C lo ck In pu t o f DF F3
reg <84:80> Matrix Out: In1 of LUT3_1 or Data Input of DFF3
reg <89:85> Matrix Out: In2 of LUT3_1 or Resetb(Setb) of DFF3
reg <94:90> Matrix Out: In0 of LUT3_ 2
reg <99:95> Matrix Out: In1 of LUT3_ 2
reg <104:100> Matrix Out: In2 of LUT3_2
reg <109:105> Matrix Out: In0 of LUT3_3
reg <114:110> Matrix Out: In1 of LUT3_ 3
reg <119:115> Matrix Out: In2 of LUT3_ 3
reg <124:120> Matrix Out: In0 of LUT3_ 4 or Input of Pipe delay
reg <129:125 > Matrix Out: In1 of LU T3 _4 or R ese tb of Pipe delay
reg <134:130 > Matrix Out: In2 of LUT3 _4 or Clock of Pipe delay
reg <139:135> Matrix Out: In0 of LUT4_0 or Input for delay2 (Counter2)
external clock
reg <144:140> Matrix Out: In1 of LUT4_0 or Input for delay2 data
(counter2 reset)
reg <149:145> Matrix Out: In2 of LUT4_0
reg <154:150> Matrix Out: In3 of LUT4_0
reg <159:155> Matrix Out: Input for delay0 data (counter0 reset)
reg <164:160> Matrix Out: Input for delay1 data (counter1 reset)
reg <169:165> Matrix Ou t: Input for delay0/1 (Counter0/1) external
clock
reg <174:170> Matrix Out: Input for delay3 (Counter3) external clock
reg <179:175> Matrix Out: pdb(power down) for ACMP0
reg <184:180> Matrix Out: pdb(power down) for ACMP1
reg <189:185> Matrix Out: Input for programmable delay (deglitch filter
input)
000-0046110-057 Page 50 of 65
SLG46110
Preliminary
reg <194:190> Matrix Out: Power down for osc
reg <199:195> Matrix Out: PIN8 Digital Output Source
reg <204:200> Matrix Out: PIN9 Digital Output Source
reg <209:205> Matrix Out: PIN10 Digital Output Source
reg <214:210> Matrix Out: Output Enable of PIN10
reg <219:215> Matrix Out: PIN12 Digital Output Source
reg <223:220> Reserved Reserved
DFF0/Latch
reg <227:224>
reg <224> DFF0 or Latch select 0: DFF function
1: Latch fu nct i on
reg <225> DFF0 output select 0: Q output
1: nQ output
reg <226> DFF0 initial polarity select 0: Low
1: High
reg <227> Unused if DFF/Latch selecte d Unused
DFF1/Latch
reg <231:228>
reg <228> DFF1 or Latch select 0: DFF function
1:Latch function
reg <229> DFF1 output select 0: Q output
1: nQ output
reg <230> DFF1 initial polarity select 0: Low
1:High
reg <231> Unused if DFF/Latch selecte d Unused
LUT2_0 data
reg <235:232> LUT2_0 data LUT2_0 data
LUT2_1 data
reg <239:236> LUT2_1 data LUT2_1 data
LUT2_0/DFF0
reg <240> LUT2_0 or DFF0 select 0: LUT2_0
1: DFF0
LUT2_1/DFF1
reg <241> LUT2_1 or DFF1 select 0: LUT2_1
1: DFF1
LUT3_0 or DFF2/Latch
reg <249:242>
reg <242> DFF2 or Latch select 0: DFF function
1: Latch fu nct i on
reg <243> DFF2 output select 0: Q output
1: nQ output
reg <244> DFF2 rstb/setb select 0: resetb from matrix output
1: setb from matrix output
reg <245> DFF2 initial polarity select 0: Low
1: High
reg <249:246> Unused if DFF/Latch selected Unused
Register Bit
Address Signal Functi on Register Bit Definition
000-0046110-057 Page 51 of 65
SLG46110
Preliminary
DFF3/Latch
reg <257:250>
reg <250> DFF3 or Latch select 0: DFF function
1: Latch fu nct i on
reg <251> DFF3 output select 0: Q output 1: nQ output 0: Q output
1: nQ output
reg <252> DFF3 rstb/setb select 0: resetb from matrix output
1: setb from matrix output
reg <253> DFF3 initial polarity select 0: Low
1: High
reg <257:254> Unused if DFF/Latch selected Unused
LUT3_0 data
reg <265:258> LUT3_0 data LUT3_0 data
LUT3_1 data
reg <273:266> LUT3_1 data LUT3_1 data
LUT3_4 or pipe number select
reg <281:274> reg <276:274>: OUT0 select data (pipe number)
reg <279:277>: OUT1 select data (pipe number)
reg <281:280>: Unused if Pipe Delay selected Unused
LUT3/DFF Select
reg <282> LUT3_0 or DFF2 select 0: LUT3_0
1: DFF2
reg <283> LUT3_1 or DFF3 select 0: LUT3_1
1: DFF3
reg <284> LUT3_4 or pipe dela y output select 0: lut3_4
1: pipe delay
LUT4_0 or Counter/delay2 mode selection
reg <300:285>
reg <285> Coun te r/ de l ay2 mode selection 0: Delay Mode
1: Counter Mode
reg <288:286> Counter/delay2 Clock Source select
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011 : OSC/24
100: OSC/64
101: External Clock
110 : Exte rnal Clock
111: Counter1 Overflow
reg <296:289> Counter/delay2 Control Data 1 – 256 (delay time = (counter control data +1) /freq)
reg <298:297> Delay2 Mode Select or asynchronous
counter reset
00: Delayon both falling and rising edges(for delay &
counter reset)
01: Delayon falling edge only (for delay & counter
reseDelayt)
10: on rising edge only (for delay & counter reset)
11: No dela y on either falling or rising edges / high
level reset for counter mode
reg <300:299> Unused is Counter/Delay2 selected Unused
reg <301> LUT4_0 or Counter2 select 0: LUT4_0, 1: Counter2 0: LUT4_0
1: Counter2
reg <302> Force RC oscillator on 0: Auto Power on
1: Force Power on
Register Bit
Address Signal Functi on Register Bit Definition
000-0046110-057 Page 52 of 65
SLG46110
Preliminary
reg <303> RC Oscillator frequency control 0: 25k
1: 2M
reg <305:304> Osc clock pre-divider 00: div1
01: div2
10: div4
11: div8
reg <308:306> Internal Oscillator frequency divider control 0 for Matrix
Input
000: OSC/1
001: OSC/2
010: OSC/3
011: OSC/4
100: OSC/8
101: OSC/12
110: OSC/24
111: OSC/64
reg <311:309> Internal Oscillator frequency divider control 1 for Matrix
Input
000: OSC/1
001: OSC/2
010: OSC/3
011: OSC/4
100: OSC/8
101: OSC/12
110: OSC/24
111: OSC/64
reg <312> External Clock Source Select 0: Internal Oscillator
1: External Clock from PIN12
reg <313> Reserved Reserved
Counter/Delay 0
reg <327:314>
reg <314>Counter/delay0 mode selection 0: Delay Mode
1: Counter Mode
reg <317:315> Counter/delay0 Clock Source select
(external clock is only for counter mode)
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011 : OSC/24
100: OSC/64
101: External Clock
110 : Exte rnal Clock
111: Counter3 Overflow
reg <325:318> Counter0 Control Data/Delay0 Time
Control 1-256: (delay time = (counter control data +1) /freq)
reg <327:326> Delay0 Mode Select or asynchronous
counter reset
00: Delayon both falling and rising edges(for delay &
counter reset)
01: Delayon falling edge only (for delay & counter
reset)
10: Delayon rising edge only (for delay & counter
reset)
11: No dela y on either falling or rising edges / high
level reset for counter mode
Register Bit
Address Signal Functi on Register Bit Definition
000-0046110-057 Page 53 of 65
SLG46110
Preliminary
Counter/Delay 1
reg <341:328>
reg <328> Coun te r/ de l ay1 mode selection 0: Delay Mode
1: Counter Mode
reg <331:329> Counter/delay1 Clock Source select
(external clock is only for counter mode)
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011 : OSC/24
100: OSC/64
101: External Clock
110 : External Clock
111: Counter0 Overflow
reg <339:332> Counter1 Control Data/Delay1 Time
Control 1-256: (delay time = (counter control data +1) /freq)
reg <341:340> Delay1 Mode Select or asynchronous
counter reset
00: Delay on both falling and rising edges(for delay
& counter reset)
01: Delay on falling edge only (for delay & counter
reset)
10: Delay on rising edge only (for delay & counter
reset)
11: No dela y on either falling or rising edges / high
level reset for counter mode
Counter/Delay 3
reg <355:342>
reg <342> Coun te r/ de l ay3 mode selection 0: Delay Mode
1: Counter Mode
reg <345:343> Counter/delay3 Clock Source select
(external clock is only for counter mode)
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011 : OSC/24
100: OSC/64
101: External Clock
110 : External Clock
111: Counter2 Overflow
reg <353:346> Counter3 Control Data/Delay4 Time
Control 1-256: (delay time = (counter control data +1) /freq)
reg <355:354> Delay3 Mode Select 00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No dela y on either fa lling or rising edges
Register Bit
Address Signal Functi on Register Bit Definition
000-0046110-057 Page 54 of 65
SLG46110
Preliminary
ACMP0
reg <366:356>
reg <360:356> ACMP0 IN voltage select
00000: 50 mV 00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: VDD/3 11001: VDD/4
11010: EXT_VREF(PIN4)
reg <362:361> ACMP0 hysteresis Enable 00: Disabled (0 mV)
01: Enabled (25 mV)
10: Enabled (50 mV)
11: En abled (200 mV)
reg <364:363> ACMP0 positive Input divider 00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
reg <365> ACMP0 low bandwidth (typ: Max.1Mhz) en-
able. 0: off
1: on
reg <366> ACMP0 positive input source select PIN3 and
VDD 0: PIN3
1: VDD
Register Bit
Address Signal Functi on Register Bit Definition
000-0046110-057 Page 55 of 65
SLG46110
Preliminary
ACMP1
reg <378:367>
reg <371:367> ACMP1 IN voltage select
00000: 50 mV 00001: 100 mV
00010: 150 mV 00011: 200 mV
00100: 250 mV 00101: 300 mV
00110: 350 mV 00111: 400 mV
01000: 450 mV 01001: 500 mV
01010: 550 mV 01011: 600 mV
01100: 650 mV 01101: 700 mV
01110: 750 mV 01111: 800 mV
10000: 850 mV 10001: 900 mV
10010: 950 mV 10011: 1 V
10100: 1.05 V 10101: 1.1 V
10110: 1.15 V 10111: 1.2 V
11000: VDD/3 11001: VDD/4
11010: EXT_VREF(PIN4)
reg <373:372> ACMP1 hysteresis Enable 00: Disabled (0 mV)
01: Enabled (25 mV)
10: Enabled (50 mV)
11: En abled (200 mV)
reg <375:374> ACMP1 positive Input divider 00: 1.0x
01: 0.5x
10: 0.33x
11: 0.25x
reg <376> ACMP1 100uA current source option 0: disable
1: enable
reg <377> ACMP1 low bandwidth (typ: Max.1 MHz) en-
able. 0: off
1: on
reg <378> ACMP1 positive input source select PIN6 and
PIN3 0: PIN6
1: PIN3
PIN 2
reg <382:379>
reg <380:379> PIN2 mode control 00: Digital Input without Schmitt trigger
01: Digital Input with Schmitt trigger
10: Low voltage digital input
11: Reserved
reg <382:381> PIN2 pull down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
Register Bit
Address Signal Functi on Register Bit Definition
000-0046110-057 Page 56 of 65
SLG46110
Preliminary
PIN 3
reg <389:383>
reg <385:383> PIN3 mode control
000: Digital Input without Schmitt trig ger
001: Digital Input with Schmitt trigger
010: Low voltage digital input
011: Analog Input / Output
100: Push Pull
101: Open Drain NMOS
110: Op en Drain PMOS
111: Analog Input / Output & Open drain
reg <387:386> PIN3 pull up/down resistor value selec-
tion
00: floating
01: 10K
10: 100K
11: 1M
reg <388> PIN3 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
reg <389> PIN3 driver strength selection 0: 1X
1: 2X
PIN 4
reg <396:390>
reg <392:390> PIN4 mode control
000: Digital Input without Schmitt trig ger
001: Digital Input with Schmitt trigger
010: Low voltage digital input
011: Analog Input / Output
100: Push Pull
101: Open Drain NMOS
110: Op en Drain PMOS
111: Analog Input / Output & Open drain
reg <394:393> PIN4 pull up/down resistor value selec-
tion
00: floating
01: 10K
10: 100K
11: 1M
reg <395> PIN4 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
reg <396> PIN4 driver strength selection 0: 1X
1: 2X
PIN6
reg <403:397>
reg <398:397> PIN6 mode control (sig_PIN6_oe =0) 00: Digital Input without Schmitt trigger
01: Digital Input with Schmitt trigger
11: Low Voltage Digital Input
10: Analog Input / Output
reg <400:399> PIN10 mode control (sig_PIN10_oe =1) 00: Push Pull 1X
01: Push Pull 2X
10: Open Drain NMOS 1X
11: Open Drain NMOS 2X
reg <402:401> PIN6 pull up/down resistor value selec-
tion
00: floating
01: 10K
10: 100K
11: 1M
reg <403> PIN6 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
Register Bit
Address Signal Functi on Register Bit Definition
000-0046110-057 Page 57 of 65
SLG46110
Preliminary
PIN8
reg <410:404>
reg <406:404> PIN8 mode control
000: Digital Input without Schmitt trig ger
001: Digital Input with Schmitt trigger
010: Low voltage digital input
011: Analog Input / Output
100: Push Pull
101: Open Drain NMOS
110: Op en Drain PMOS
111: Analog Input / Output & Open drain
reg <408:407> PIN8 pull up/down resistor value selec-
tion
00: floating
01: 10K
10: 100K
11: 1M
reg <409> PIN8 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
reg <410> PIN8 driver strength selection 0: 1X
1: 2X
PIN9
reg <417:411>
reg <413:411> PIN9 mode control
000: Digital Input without Schmitt trig ger
001: Digital Input with Schmitt trigger
010: Low voltage digital input
011: Analog Input / Output
100: Push Pull
101: Open Drain NMOS
110: Op en Drain PMOS
111: Analog Input / Output & Open drain
reg <415:414> PIN9 pull down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
reg <416> PIN9 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
reg <417> PIN9 driver strength selection 0: 1X
1: 2X
PIN10
reg <424:418>
reg <419:418> PIN10 mode control (sig_PIN10_oe =0) 00: Digital Input without Schmitt trigger
01: Digital Input with Schmitt trigger
11: Low Voltage Digital Input
10: Analog Input / Output
reg <421:420> PIN10 mode control (sig_PIN10_oe =1) 00: Push Pull 1X
01: Push Pull 2X
10: Open Drain NMOS 1X
11: Open Drain NMOS 2X
reg <423:422> PIN10 pull up/down resistor value selec-
tion
00: floating
01: 10K
10: 100K
11: 1M
reg <424> PIN10 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
Register Bit
Address Signal Functi on Register Bit Definition
000-0046110-057 Page 58 of 65
SLG46110
Preliminary
PIN12
reg <431:425>
reg <427:425> PIN12 mode control
000: Digital Input without Schmitt trig ger
001: Digital Input with Schmitt trigger
010: Low voltage digital input
011: Analog Input / Output
100: Push Pull
101: Open Drain NMOS
110: Op en Drain PMOS
111: Analog Input / Output & Open drain
reg <429:428> PIN12 pull up/down resistor value selec-
tion
00: floating
01: 10K
10: 100K
11: 1M
reg <430> PIN12 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
reg <431> PIN12 driver strength selection 0: 1X
1: 2X
reg <432> Pipe delay OUT1 polarity select bit 0: non-inverting
1: inverting
reg <440:433> 8-bit pattern id 8-bit pattern id
reg <441> filter0 output polarity select 0: non-inverting
1: inverting
reg <443:442> Reserved Reserved
reg <444> GPIO quick charge enable 0: Disable
1: Enable
reg <445> Force bandgap on 0: Auto-mode
1: Enable
reg <446> VREF1 Output Active Buffer Control 0: Disabled
1: Enabled
reg <449:447> VREF1 Output Source Select
000: ACMP0 reference voltage
001: ACMP1 reference voltage
100: VDD/2
101: VDD/3
110: VDD/4
101: Reserved
110: Reserved
111: Reserved
reg <450> NVM data read disable 0: Disable (read enable)
1: Enable (read disable)
reg <451> NVM power down (or NVM data programming disable) 0: None (or programming enable)
1: Power Down (or programming disable)
reg <452> Power Divider Powe r 0: Power down
1: Power On
reg <453> POR Auto Power detect 0: Enable
1: Disable
reg <454> Charge pump for an alog block enable (when VDD <=
2.7 V turn on) 0: Disable (automatic on/off control)
1: Enable (always on)
reg <455> VDD bypass enable 0: Regulator auto on
1: Regulator off (VDD bypass)"
reg <471:456> Reserved Reserved
reg <479:472> Reserved Reserved
Register Bit
Address Signal Functi on Register Bit Definition
000-0046110-057 Page 59 of 65
SLG46110
Preliminary
reg <481:480> Reserved Reserved
reg <482> PIN2 edge detect mode 0: rising edge
1: falling edge
reg <483> Bypass the PIN2 0: PIN2 edge active
1: PIN2 high active
reg <484> PIN2 reset enable 0: Disable
1: Enable
reg <485> programmable delay or filter output select 0: programmable delay output
1: filter output
reg <487:486> Select the edge mode of programmable delay & edge
detector
00: rising edge detector
01: falling edge detector
10: both edge detector
11: both edg e delay
reg <489:488> Delay value select for programmable delay & edge de-
tector (VDD = 3.3 V, typical condition)
00: 125 ns
01: 250 ns
10: 375 ns
11: 500 ns
reg <490> Reserved Reserved
reg <495:491> Reserved Reserved
reg <501:496> Reserved Reserved
reg <502> Reserved Reserved
reg <503> Reserved Reserved
reg <511:504> Reserved Reserved
Register Bit
Address Signal Functi on Register Bit Definition
000-0046110-057 Page 60 of 65
SLG46110
Preliminary
16.0 Package Top Marking System Definition
P P A Part Code + Assembly Code
Pin 1 Identifier WWR Date Code + Revision Code
NN Serial Number Code
000-0046110-057 Page 61 of 65
SLG46110
Preliminary
17.0 Package Drawing and Dimensions
12 Lead STQFN FC Package 1.6 x 1.6 mm
IC net weight: 0.0028 g
000-0046110-057 Page 62 of 65
SLG46110
Preliminary
18.0 Tape and Reel Specifications
18.1 Carrier Tape Drawing and Dimensions
Package
Type # of
Pins
Nominal
Package Size
[mm]
Max Units Reel &
Hub Size
[mm]
Leader (min) Trailer (min) Tape
Width
[mm]
Part
Pitch
[mm]
per Reel per Box Pockets Length
[mm] Pockets Length
[mm]
STQFN
12L FC
0.4P
Green 10 1.6x1.6x0.55 3000 3000 178/60 100 400 100 400 8 4
Package
Type
Pocket BTM
Length
[mm]
Pocket BTM
Width
[mm]
Pocket
Depth
[mm]
Index Hole
Pitch
[mm]
Pocket
Pitch
[mm]
Index Hole
Diameter
[mm]
Index Hole
to Tape
Edge
[mm]
Index Hole
to Pocket
Center
[mm]
Tape Width
[mm]
A0 B0 K0 P0 P1 D0 E F W
STQFN 12L
FC 0.4P
Green 1.9 1.9 0.8 4 4 1.5 1.75 3.5 8
000-0046110-057 Page 63 of 65
SLG46110
Preliminary
19.0 Recommended Land Pattern
20.0 Recommended Reflow Soldering Profile
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 1.408 mm3 (nominal). More
information can be found at www.jedec.org.
Units: μm
000-0046110-057 Page 64 of 65
SLG46110
Preliminary
21.0 Revision History
Date Version Change
9/3/2014 0.57 Up dated Electrical Characteristics VIH/VIL/VOH/VOL values
8/25/2014 0.56 Added Recommended Land Pattern
7/23/2014 0.55 Fixed ESD information
6/20/2014 0.54 Fixed typo on Electrical Spec
5/21/2014 0.53 Updated bl ock diagra m
Fixed typos
Moved Programmable Delay and Deglitch Filter to Combination Macrocells section
4/29/2014 0.52 Added ESD Ratings and MSL to Absolute Maximum Conditions
3/28/2014 0.5 Fixed typos
Preliminary Release
3/18/2014 0.42 Updated block diagrams and timing diagrams for clarity
2/12/2014 0.41 Fixed typos
12/2/2013 0.4 Updated VIH/VIL in Electrical Characteristics
Fixed typos
Added IC net weight to Package S pecification
11/25 /20 13 0.31 Added Block Diagram
11/11/2013 0.3 Added Diagrams
9/30/2013 0.2 Updated Electrical Characteristics
Added Register Table and Descriptions
9/16/2013 0.1 Initial release
000-0046110-057 Page 65 of 65
SLG46110
Preliminary
Silego Website & Support
Silego Technology Website
Silego Technology provides onlin e support via our w ebsite at http://www.silego.com/.This website is used as a means to make
files and information easily available to customers.
For more information regarding Silego Green products, please visit our website.
Our Green product lines feature:
GreenPAK1 / GreenPAK2 / GreenPAK3: Programmable Mixed Signal Matri x products
GreenFET1 / GreenFET2 / GreenFET3 : MOSFET Drivers and ultra-small, low RDSon Load Switches
GreenCLK1 / GreenCLK2 / GreenCLK3: Crystal replacement technology
Products are also available for purchase directly from Silego at the Silego Online Store at http://store.silego.com/.
Silego Technical Support
Datasheets and errata, application notes and example designs, user guides, and hardware support documents and the latest
software releases are available at the Silego website or can be requested di rectly at info@silego.com.
For specific GreenPAK design or applications questions and support please send e-mail requests to GreenPAK@silego.com
Users of Silego products can receive assistance through several channels:
Contact Your Loca l Sales Representative
Customers can contact their local sales representative or field application engineer (F AE) for support. Local sales offices are also
available to help customers. More information regarding your local representative is available at the Silego website or send a
request to info@silego.com
Contact Silego Directly
Silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following URL:
http://support.silego.com/
Other Information
The latest Silego Technology press releases, listing of seminars and events, listings of world wide Silego Technology offices and
representatives are all available at http://www.silego.com/
THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SY STEMS ARE NOT AUTHORIZED. SILEGO TECHNOLOGY DOES NOT ASSUME ANY LIAB ILITY ARISING OUT OF SUCH APPLICA-
TIONS OR USES OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY
WITHO UT NOTICE.
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Silego:
SLG46110V